阅读说明：本技术 存储器芯片 (Memory chip ) 是由 荒井健一 原田佳和 于 2019-08-06 设计创作，主要内容包括：根据实施方式,存储器芯片具备存储单元阵列、以及第1电路。所述第1电路对所述存储单元阵列的对象区域执行使用参数读取数据的第1处理。而且,所述第1电路在所述第1处理之后,执行改变所述参数的设定值并读取所述数据的第2处理。(According to one embodiment, a memory chip includes a memory cell array and a 1 st circuit. The 1 st circuit performs 1 st processing of reading data using a parameter on a target area of the memory cell array. Also, the 1 st circuit performs a 2 nd process of changing a set value of the parameter and reading the data after the 1 st process.)

1. A memory chip is provided with

An array of memory cells; and

a 1 st circuit that performs a 1 st process of reading data using a parameter on a target area of the memory cell array, and performs a 2 nd process of changing a set value of the parameter and reading the data after the 1 st process.

2. The memory chip according to claim 1, further comprising a 2 nd circuit connectable to an external device,

the 1 st circuit executes the 1 st process in accordance with an instruction from the external device, and executes the 2 nd process without further instruction from the external device after the 1 st process.

3. The memory chip of claim 1, wherein

The 1 st process includes a 3 rd process of comparing an expected value of the data with the read data,

the 1 st circuit determines whether to execute the 2 nd process based on a result of the 3 rd process.

4. The memory chip according to claim 3, further comprising a 2 nd circuit connectable to an external device,

the memory cell array is provided with a plurality of 1 st memory regions,

the 1 st circuit sets one 1 st storage area of the plurality of 1 st storage areas as the target area and executes the 1 st process, or the 1 st process and the 2 nd process in accordance with an instruction from the external device, and then sets another 1 st storage area different from the one 1 st storage area of the plurality of 1 st storage areas as the target area and executes the 1 st process, or the 1 st process and the 2 nd process without a further instruction from the external device.

5. The memory chip of claim 4, further provided with a 2 nd storage area,

the memory cell array is provided with a plurality of 3 rd memory regions,

the plurality of No. 3 storage areas are each provided with the plurality of No. 1 storage areas,

the 1 st circuit sequentially sets each of the 1 st storage areas included in a 4 th storage area, which is one of the 3 rd storage areas, as the target area, measures a 1 st number related to the 2 nd processing, determines whether or not the processing for the 4 th storage area is acceptable based on the 1 st number, and stores a result of the determination of whether or not the processing is acceptable in the 2 nd storage area.

6. The memory chip of claim 5, wherein

The 2 nd process includes a 4 th process which is the same process as the 3 rd process,

the 1 st circuit decides whether or not to execute the 2 nd process again based on a result of the 4 th process after the 2 nd process,

the 1 st number is the number of executions of the 2 nd process measured for each of the 1 st storage areas,

the 1 st circuit determines whether or not to pass based on a comparison of the 1 st number with a threshold.

7. The memory chip of claim 5, wherein

The 1 st number is the number of 1 st storage areas for executing the 2 nd processing among the 1 st storage areas included in the 4 th storage area,

the 1 st circuit determines whether or not to pass based on a comparison of the 1 st number with a threshold.

8. The memory chip according to claim 7, wherein the 1 st circuit stores a 2 nd number, does not add the 1 st number to the 2 nd number in a case where the processing to the 4 th storage area is determined to be ineligible, and adds the 1 st number to the 2 nd number in a case where the processing to the 4 th storage area is determined to be eligible.

9. The memory chip of claim 3, wherein

The 2 nd process includes a 4 th process which is the same process as the 3 rd process,

the 1 st circuit determines whether to execute the 2 nd process again based on a result of the 4 th process after the 2 nd process.

10. The memory chip of claim 4, wherein

The memory cell array is provided with a plurality of 2 nd memory regions,

the plurality of 2 nd storage areas are each provided with the plurality of 1 st storage areas,

the 1 st circuit sequentially sets each of the 1 st storage areas included in a 3 rd storage area, which is one of the 2 nd storage areas, as the target area, measures a 1 st number related to the 2 nd processing, and determines whether or not the processing for the 3 rd storage area is acceptable based on the 1 st number.

11. The memory chip of claim 1, wherein

The memory cell array includes a plurality of memory cell transistors each having a threshold voltage set to a state corresponding to data in a plurality of states,

the reading of the data is a process of determining the data by a comparison of a read level corresponding to an intersection of adjacent 2 states among the plurality of states with the threshold voltage,

the parameter includes a read level.

12. The memory chip of claim 6, wherein the threshold value is settable from an external device.

13. The memory chip of claim 7, wherein the threshold value is settable from an external device.

Technical Field

The present embodiments generally relate to a memory chip.

Background

Conventionally, a test of a memory chip of a NAND (Not-And) type flash memory is performed before the memory chip is shipped.

Disclosure of Invention

One embodiment provides a memory chip that can be easily tested.

According to the present embodiment, a memory chip includes a memory cell array and a 1 st circuit. The 1 st circuit performs 1 st processing of reading data using a parameter on a target area of the memory cell array. Also, the 1 st circuit performs a 2 nd process of changing a set value of the parameter and reading the data after the 1 st process.

Drawings

Fig. 1 is a schematic diagram showing an example of a usage form of a memory chip according to an embodiment.

Fig. 2 is a schematic diagram showing an example of the configuration of the memory chip according to the embodiment.

Fig. 3 is a circuit diagram showing an example of the configuration of 1 block B L K included in the memory cell array according to the embodiment.

Fig. 4 is a diagram showing an example of threshold voltages that can be obtained for the memory cell of the embodiment in the case of T L C.

Fig. 5 is a schematic diagram showing an example of the configuration of the sense amplifier according to the embodiment.

Fig. 6 is a schematic diagram showing an example of a state during a test of a memory chip according to the embodiment.

Fig. 7 is a schematic diagram showing an example of various parameters stored in the register REG according to the embodiment.

Fig. 8 is a schematic diagram showing a user ROM storing a plurality of parameter sets according to an embodiment.

Fig. 9 is a schematic diagram for explaining data stored in the memory cell array of the embodiment.

Fig. 10 is a sequence diagram for explaining an example of the procedure of testing the memory chip according to the embodiment.

Fig. 11 is a flowchart illustrating an example of a series of procedures of test operations performed by the memory chip according to the embodiment.

Detailed Description

Hereinafter, the memory chip of the embodiment will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiment.

(embodiment mode)