阅读说明：本技术 Ldpc软译码方法、存储器及电子设备 (L DPC soft decoding method, memory and electronic equipment ) 是由 王颀 姜一扬 李前辉 霍宗亮 于 2020-03-23 设计创作，主要内容包括：一种LDPC软译码方法、存储器及电子设备,该方法包括：对信息位已经编码过的存储单元进行读取,根据读取时当前存储单元对应的存储时间、阈值电压分区和综合分布态,并参照一预先建立的LLR表获得当前存储单元的LLR值；根据读取的当前存储单元的LLR值对信息位已经编码过的存储单元的码字进行软译码操作；其中,当前存储单元的综合分布态根据与该当前存储单元相邻的存储单元对于该当前存储单元分布态的影响确定；所述预先建立的LLR表的输入量为：存储时间、阈值电压分区和综合分布态,输出量为LLR值。基于综合分布态确定的LLR值进行译码的方式相较于现有的LDPC软译码方式降低了误码率,提升了纠错能力,同时还减少了迭代次数。(An L DPC soft decoding method, a memory and an electronic device are provided, the method includes reading a storage unit with an encoded information bit, obtaining a LL R value of the current storage unit according to a storage time, a threshold voltage partition and a comprehensive distribution state corresponding to the current storage unit when the storage unit is read, and referring to a pre-established LL R table, and performing soft decoding operation on a code word of the storage unit with the encoded information bit according to the read LL R value of the current storage unit, wherein the comprehensive distribution state of the current storage unit is determined according to the influence of a storage unit adjacent to the current storage unit on the distribution state of the current storage unit, the input quantity of the pre-established LL R table is the storage time, the threshold voltage partition and the comprehensive distribution state, and the output quantity is a LL R value, compared with an LL R value determined based on the comprehensive distribution state, a decoding mode reduces an error rate in an existing L DPC soft decoding mode, improves error correction capability, and reduces iteration times.)

1. An L DPC soft decoding method, used in a memory including a plurality of memory cells, the method comprising:

step S13, reading the memory cell with coded information bit, and obtaining LL R value of the current memory cell according to the corresponding storage time, threshold voltage partition and comprehensive distribution state of the current memory cell during reading and referring to a pre-established LL R table;

step S14, according to the read LL R value of the current memory cell, performing soft decoding operation on the code word of the memory cell with the coded information bits;

the comprehensive distribution state of the current storage unit is determined according to the influence of the storage unit adjacent to the current storage unit on the distribution state of the current storage unit, the input quantity of the pre-established LL R table is storage time, a threshold voltage partition and the comprehensive distribution state, and the output quantity is a LL R value.

2. The method according to claim 1, further comprising, before the step S13:

and step S12, coding the information bits to obtain code words and writing the code words into the storage units of the memory.

3. The method of claim 1, wherein the LL R table is pre-established by:

the method comprises the steps of carrying out reading test on a memory, obtaining threshold voltage distribution and distribution states of a current memory cell with known accurate codes and memory cells adjacent to the current memory cell in a certain memory time, determining a comprehensive distribution state of the current memory cell according to the influence of the memory cells adjacent to the current memory cell on the distribution state of the current memory cell, calculating LL R values of different threshold voltage partitions according to the comprehensive distribution state, obtaining the corresponding threshold voltage partitions and the comprehensive distribution states in different memory times, and obtaining a LL R table with input quantities of the memory time, the threshold voltage partitions and the comprehensive distribution states and output quantities of LL R values.

4. The method of claim 1, wherein the memory is a 3D NAND flash memory, the current cell has coordinates (m, n, k), k ≧ 1, and the cell adjacent to the current cell is selected by: and sequentially selecting a plurality of storage units with preset distances from the current storage unit along the z-axis upwards and/or downwards.

5. The method of claim 1, wherein when determining the global distribution of the current memory cell, at least two adjacent physical pages including the physical page of the current memory cell are read.

6. The method of claim 1, wherein when determining the comprehensive distribution state of the current memory cell, only two layers of physical pages are selected for reading, wherein a physical page at a lower layer is a physical page where the current memory cell is located, and a physical page at a higher layer is a physical page where a memory cell adjacent to the current memory cell is located, and the comprehensive distribution state of the current memory cell is determined by reading the distribution states of the memory cells on the two layers of physical pages.

7. The method of claim 1, wherein the LL R table comprises input values further including erase times.

8. A memory comprising a plurality of memory cells, the memory being configured to perform the method of any one of claims 1-7.

9. The memory of claim 8, wherein the memory comprises a flash memory.

10. An electronic device, comprising:

the coding unit is used for coding the information bits to obtain code words and writing the code words into a storage unit of a memory;

LL R memory cell, used for storing pre-established LL R table, the input quantity of the LL R table is storage time, threshold voltage subarea and comprehensive distribution state, the output quantity is LL R value, wherein, the comprehensive distribution state of the current memory cell is determined according to the influence of the memory cell adjacent to the current memory cell on the distribution state of the current memory cell;

a reading unit for reading the memory cell with the coded information bit, extracting the pre-established LL R table from the LL R memory cell according to the corresponding storage time, threshold voltage partition and comprehensive distribution state of the current memory cell during reading to obtain the LL R value of the current memory cell, and

the decoding unit is used for carrying out soft decoding operation on the code words of the storage units with the coded information bits according to the read LL R value of the current storage unit;

optionally, the electronic device includes: the system comprises a computer, a mobile phone, an intelligent sound box, wearable intelligent equipment and a robot;

optionally, the electronic device and the memory written and decoded are two independent entities; or the memory written and decoded is used as the component of the electronic equipment;

optionally, the LL R storage unit is located inside the memory, inside the electronic device, or on a server.

Optionally, in the LL R table, the input amount further includes the number of times of erasing.

Technical Field

The disclosure belongs to the technical field of coding and decoding of memories, and relates to an L DPC soft decoding method, a memory and electronic equipment, in particular to a L DPC soft decoding method, a memory and electronic equipment for a memory with an influence on the distribution state of a current memory cell by an adjacent memory cell.

Background

Non-volatile memories are of various types, such as: read-only Memory (ROM), programmable read-only Memory (PROM), electrically rewritable read-only Memory (EAROM), erasable programmable read-only Memory (EPROM), electrically erasable programmable read-only Memory (EEPROM), Flash Memory (Flash Memory), and the like. When the nonvolatile memory stores information, data needs to be encoded, the encoded data needs to be written into memory cells in the memory array, and when the nonvolatile memory reads the data, a decoding operation needs to be performed.

When the conventional nonvolatile memory adopts L DPC soft decoding, generally speaking, for a single-layer cell (S L C) flash memory, two distribution states are distributed along a threshold voltage, an overlap exists between the two distribution states, each overlap is read 3 times, the read data is divided into 4 areas along the distribution of the threshold voltage, different areas correspond to different LL R values, and the expression of LL R is LL R-L og (P is LL R)₀/P₁) Wherein P is₀Probability, P, expressed as logic 0₁The above L DPC soft decoding method is also applicable to two-level cell (M L C) and three-level cell (T L C) flash memories, except that M L C has 2 distributions along the threshold voltage²T L C has 2 distributions along the threshold voltage distribution³However, the existing L DPC soft decoding still has the need to improve the error correction capability of L DPC soft decoding and reduce the error rate and the number of iterations.

Disclosure of Invention

The present disclosure provides an L DPC soft decoding method, a memory and an electronic device, which at least partially solve the technical problems of reducing bit error rate, improving error correction capability and reducing iteration number when decoding the memory.

In order to solve at least one of the above technical problems, the present disclosure proposes an L DPC soft decoding method, a memory and an electronic device, in particular, a L DPC soft decoding method, a memory and an electronic device for a memory in which neighboring memory cells have an influence on the distribution status of current memory cells.

According to an aspect of the present disclosure, there is provided an L DPC soft decoding method for a memory including a plurality of memory cells, the method including:

step S13, reading the memory cell with coded information bit, and obtaining LL R value of the current memory cell according to the corresponding storage time, threshold voltage partition and comprehensive distribution state of the current memory cell during reading and referring to a pre-established LL R table;

step S14, according to the read LL R value of the current memory cell, performing soft decoding operation on the code word of the memory cell with the coded information bits;

the comprehensive distribution state of the current storage unit is determined according to the influence of the storage unit adjacent to the current storage unit on the distribution state of the current storage unit, the input quantity of the pre-established LL R table is storage time, a threshold voltage partition and the comprehensive distribution state, and the output quantity is a LL R value.

In an embodiment of the present disclosure, before the step S13, the method further includes: and step S12, coding the information bits to obtain code words and writing the code words into the storage units of the memory.

In an embodiment of the disclosure, the method for pre-establishing the LL R table includes the steps of performing a read test on a memory, obtaining threshold voltage distributions and distribution states of a current memory cell with known accurate codes and memory cells adjacent to the current memory cell in a certain storage time, determining a comprehensive distribution state of the current memory cell according to influences of memory cells adjacent to the current memory cell on the distribution state of the current memory cell, calculating LL R values of different threshold voltage partitions according to the comprehensive distribution state, and obtaining corresponding threshold voltage partitions and comprehensive distribution states in different storage times, so that a LL R table with input quantities of storage time, threshold voltage partitions and comprehensive distribution states and output quantities of LL R values is obtained.

In an embodiment of the present disclosure, the memory is a 3D NAND flash memory, the coordinate corresponding to the current storage unit is (m, n, k), k is greater than or equal to 1, and the way of selecting the storage unit adjacent to the storage unit is as follows: sequentially selecting a plurality of storage units with preset distances from the current storage unit along the z axis upwards and/or downwards;

in an embodiment of the present disclosure, when determining the comprehensive distribution state of the current storage unit, at least two adjacent physical pages including the physical page where the current storage unit is located are read.

In an embodiment of the present disclosure, when determining the comprehensive distribution state of the current storage unit, only two layers of physical pages are selected for performing a read operation, where a physical page at a lower layer is a physical page where the current storage unit is located, and a physical page at a higher layer is a physical page where a storage unit adjacent to the storage unit is located, and the comprehensive distribution state of the current storage unit is determined by reading the distribution states of the storage units on the two layers of physical pages.

In an embodiment of the present disclosure, the LL R table further includes an input amount of erasing times.

According to another aspect of the present disclosure, there is provided a memory comprising a plurality of memory cells, the memory being configured to perform any of the above-mentioned methods.

In an embodiment of the present disclosure, the memory comprises a flash memory.

According to still another aspect of the present disclosure, an electronic device is provided, which includes an encoding unit configured to encode information bits into codewords and write the codewords into memory cells of a memory, an LL R memory cell configured to store a pre-established LL R table, where the LL R table has input amounts of storage time, threshold voltage partition, and integrated distribution state, and an output amount of LL R value, where the integrated distribution state of a current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on the current memory cell distribution state, a reading unit configured to read a memory cell having encoded information bits, obtain an LL R value of the current memory cell according to the storage time, threshold voltage partition, and integrated distribution state corresponding to the current memory cell at the time of reading, and extract a pre-established LL R table from the LL R memory cell to obtain the codeword of the current memory cell, and a decoding unit configured to perform a soft decoding operation on the codewords of the memory cell having encoded information bits according to the LL R value of the read current memory cell.

In an embodiment of the present disclosure, the electronic device includes: computer, cell-phone, intelligent stereo set, wearable smart machine and robot.

In an embodiment of the present disclosure, the electronic device and the memory written and decoded are two independent entities; or a memory written and decoded as an integral part of the electronic device.

In an embodiment of the present disclosure, the LL R storage unit is located inside the memory, inside the electronic device, or on a server.

(III) advantageous effects

From the above technical solution, the L DPC soft decoding method, the memory and the electronic device provided by the present disclosure have the following beneficial effects:

a novel L DPC soft decoding method for configuring LL R is provided, considering that an adjacent storage unit has influence on the distribution state of a current storage unit, such as a lateral diffusion effect or a capacitive coupling effect, based on the influence effect of the adjacent storage unit, a comprehensive distribution state is provided to represent the form of the distribution state of the current storage unit, and a LL R value is determined in each partition based on the comprehensive distribution state for decoding, wherein compared with the existing L DPC soft decoding method, the method for decoding the LL R value determined based on the comprehensive distribution state reduces the error rate, improves the error correction capability, and reduces the iteration number.

Drawings

Fig. 1 shows an example of a calculation LL R for dividing a read data into regions by soft decoding using L DPC in the related art, where (a) is a schematic diagram of dividing a read data into regions and (b) is an example of calculating different regions LL R.

Fig. 2 is a flowchart illustrating an L DPC soft decoding method according to an embodiment of the disclosure.

Fig. 3 is a schematic diagram of a flash memory structure according to an example of the disclosure.

Fig. 4 is a schematic diagram illustrating an example of the distribution state influence of neighboring memory cells on the same channel on a current memory cell according to the embodiment of the disclosure.

Fig. 5 is a schematic diagram illustrating determination of a comprehensive distribution state after considering influence of adjacent memory cells on the current memory cell on the distribution state of the adjacent memory cell on the same channel according to an example of the disclosure.

Fig. 6 shows a correspondence relationship between states of a T L C flash memory and binary gray codes according to an example of the present disclosure.

Fig. 7 is a schematic diagram illustrating a comprehensive distribution state of a memory cell divided into three types according to an example of the present disclosure.

Fig. 8 is a schematic diagram of a partitioned area of a T L C flash memory according to an embodiment of the present disclosure, where (a) is a partitioned LL R area, and (b) is binary gray code corresponding to each LL R area for three adjacent physical pages.

Fig. 9 is a comparison graph of error correction capability of L DPC soft decoding method and the conventional decoding method according to the embodiment of the present disclosure.

Fig. 10 is a comparison graph of bit error rates of L DPC soft decoding method and the prior decoding method according to the embodiment of the disclosure.

Fig. 11 is a block diagram of an electronic device according to another embodiment of the present disclosure.

[ notation ] to show

An electronic device 3;

LL R storage unit 31, encoding unit 32;

a reading unit 33; and a decoding unit 34.

Detailed Description

The invention provides an L DPC soft decoding method and a memory, considering that an adjacent storage unit has influence on the distribution state of a current storage unit, such as a transverse diffusion effect or a capacitive coupling effect, and based on the influence effect of the adjacent storage unit, a comprehensive distribution state is provided to represent the form of the distribution state of the current storage unit, and a LL R value is determined in each partition based on the comprehensive distribution state for decoding.

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings. In this disclosure, the term "soft decoding" denotes a belief propagation algorithm. It is an iterative decoding algorithm based on Tanner graph. In the iteration process, reliability information, namely 'message' is transmitted back and forth in variable nodes and check nodes through edges on a Tanner graph, and tends to be stable after multiple iterations, and then optimal judgment is carried out according to the stable values.

Taking a flash memory as an example, fig. 1 is an example of dividing a read data into regions by calculating LL R by L DPC soft decoding in the prior art, wherein (a) is a schematic diagram of dividing a read data into regions, and (b) is an example of calculating different regions LL R, referring to fig. 1, in a conventional NAND flash memory, states of memory cells read by L DPC soft decoding, for example, for a single-layer cell (S L C), one physical page corresponds to one logical page, and for a certain memory cell, read data has two Distribution states (distributions) which are continuously distributed along with a threshold voltage, and are respectively calculated as E₁And P₀Represents, distribution state E₁Distribution state P corresponding to large probability of logic 1₀Corresponding to logic 0, L DPC is performed, and the two distribution states E₁And P₀The threshold voltage corresponding to the intersection point between them is used as a boundary R L2, and two other boundaries R L1 and R L3 can be obtained along the boundary R L2 and adjacent to each other by a predetermined distance, so that the read data can be divided into 4 regions corresponding to the three boundaries R L1, R L2 and R L3, as shown in (a) of fig. 1, and the 4 regions are represented by E _ H, E _ L, P _ L and P _ H, and as shown in (b) of fig. 1, LL R values can be calculated in each region, corresponding to the region E _ H and the probability P of logic 0₀Is 0.01, probability P of logic 1₁At 0.99, the LL R value for the region E _ H is calculated to be-6.63, indicating that a probability of 1 being read in the region E _ H approximately, the probability P of logic 0 corresponding to the region E _ L₀0.12, probability of logic 1P₁At 0.88, the LL R value of the region E _ L is calculated to be-2.87, indicating that 1 is likely to be read in the region E _ H, but the probability value of reading 1 in the region E _ L is less than the probability value of reading 1 in the region E _ H.Similarly, the LL R values corresponding to the areas P _ L and P _ H are 2 and 6.63, respectively, which indicate that 0 is read out in the areas P _ L and P _ H approximately, but the probability value of reading out 0 in the area P _ H is greater than that of reading out 0 in the area P _ L.

Considering that there is lateral diffusion effect in the 3D NAND flash memory, (L) overall spreading effect), that is, information stored by adjacent memory cells of the same channel has great influence on the storage characteristics of the current memory cell, the present disclosure proposes a form of representing the distribution state of the current memory cell by using an integrated distribution state, and configures LL R values according to the integrated distribution state considering the influence of the distribution state of the adjacent memory cells in each partition, and decodes according to the LL R values.

The present disclosure provides a new L DPC soft decoding configuration LL R method, which considers the influence of the storage units near the current storage unit on the distribution state of the current storage unit based on the consideration of the environment of the storage unit, obtains the comprehensive distribution state of the current storage unit, and determines the LL R value in each partition based on the comprehensive distribution state for decoding.

In a preferred embodiment, the storage units with the influence dominating the overall distribution state of the current storage unit are selected by considering the influence degree of the other storage units of the environment of the certain storage unit on the distribution state of the storage unit, so as to realize the balance between the accuracy and the cost (cost).

In some memory structures, such as a two-dimensional or three-dimensional (2D or 3D) flash memory, the memory has a plurality of memory cells, the plurality of memory cells form a two-dimensional or three-dimensional memory array, there are several memory cells around the memory cells in the two-dimensional or three-dimensional memory array or the memory cells at the edge, and the memory cells near the current memory cell affect the distribution state of the current memory cell. For example, in a 3D NAND flash memory, the distribution of one memory cell is affected by the lateral diffusion effect between the adjacent memory cells on the same channel. Or in some memory structures, there is capacitive coupling between adjacent memory cells. Of course, the method of the present disclosure is applicable to the case where the distribution state of the current memory cell is affected by the presence of other memory cells in the vicinity of the current memory cell, and the mechanism causing the effect may be a lateral diffusion effect or other effects.

Taking a flash memory as an example, because the flash memory adopts a design of sharing a charge storage space, information stored by adjacent memory cells of the same channel has a great influence on the storage characteristics of the current memory cell, and a value of LL R is configured in each partition according to a comprehensive distribution state considering the influence of the distribution state of the adjacent memory cells, and experiments prove that compared with the existing L DPC soft decoding method, a method for decoding the LL R value determined according to the comprehensive distribution state reduces the bit error rate, improves the error correction capability, and simultaneously reduces the iteration number.

In a first exemplary embodiment of the present disclosure, an L DPC soft decoding method is provided.

Fig. 2 is a flowchart illustrating an L DPC soft decoding method according to an embodiment of the disclosure.

Referring to fig. 2, the L DPC soft decoding method of the present embodiment includes step S11, step S13, and step S14.

In step S11, a LL R table is pre-established, wherein the input quantities of the LL R table are storage time, threshold voltage partition and integrated distribution state, and the output quantity is LL R value, wherein the integrated distribution state of the current memory cell is determined according to the influence of the memory cells adjacent to the current memory cell on the distribution state of the current memory cell.

The storage time is the time for storing data in the memory, and the storage time can be calculated by subtracting the time corresponding to the coding from the time corresponding to the decoding.

The threshold voltage partition and the comprehensive distribution state are functions of storage time, and the threshold voltage partition and the comprehensive distribution state can change along with the change of the storage time.

In an embodiment of the disclosure, the method for pre-establishing the LL R table includes the steps of performing a read test on a memory, obtaining threshold voltage distributions and distribution states of a current memory cell with known accurate codes and memory cells adjacent to the current memory cell in a certain storage time, determining a comprehensive distribution state of the current memory cell according to influences of memory cells adjacent to the current memory cell on the distribution state of the current memory cell, calculating LL R values of different threshold voltage partitions according to the comprehensive distribution state, and obtaining corresponding threshold voltage partitions and comprehensive distribution states in different storage times, so that a LL R table with input quantities of storage time, threshold voltage partitions and comprehensive distribution states and output quantities of LL R values is obtained.

In step S11, a LL R table may be established by way of pre-experiment, which includes, for example, selecting a random number a, storing the random number a in a flash memory, baking the random number a at regular intervals to obtain data (threshold voltage) such as a1 and a2, determining the comprehensive distribution state of each memory cell according to the data in a, classifying the memory cells according to the determination result, counting the threshold voltage of each comprehensive distribution state cell, and finally calculating LL R values corresponding to different distribution states at different times according to the partitions and recording the values in the table.

In an embodiment of the present disclosure, when determining the comprehensive distribution state of the current storage unit, at least two adjacent physical pages including the physical page where the current storage unit is located are read.

In an embodiment of the present disclosure, when determining the comprehensive distribution state of the current storage unit, only two layers of physical pages are selected for performing a read operation, where a physical page at a lower layer is a physical page where the current storage unit is located, and a physical page at a higher layer is a physical page where a storage unit adjacent to the storage unit is located, and the comprehensive distribution state of the current storage unit is determined by reading the distribution states of the storage units on the two layers of physical pages.

In an embodiment of the present disclosure, the LL R table further includes an input amount of erasing times.

In step S13, the memory cell with the encoded information bits is read, and the LL R value of the current memory cell is obtained according to the storage time, the threshold voltage partition and the integrated distribution state corresponding to the current memory cell at the time of reading, and by referring to the pre-established LL R table.

In step S14, a soft decoding operation is performed on the codeword of the memory cell whose information bits have been encoded according to the read LL R value of the current memory cell.

In an embodiment, the present disclosure may further include step S12, where step S12 is performed before step S13, and at step S12, the information bits are encoded into the codeword and written into the memory cells of the memory.

In one embodiment, for the 3D NAND flash memory, the step S11 of creating LL R table further includes the number of times of erasing (P/E cycle).

Embodiments of the above steps will be described in detail below with reference to the drawings.

The basic process of the non-volatile memory in the read operation is exemplarily described in a structure corresponding to the flash memory with reference to fig. 3.

Fig. 3 is a schematic diagram of a flash memory structure according to an example of the disclosure. Referring to FIG. 3, a three-dimensional charge trapping NAND flash memory is illustratedThe memory cell array corresponding to each layer of the 3D charge trap NAND Flash block is a physical page, the x and y coordinates of the adjacent memory cells on the same channel are the same and the z coordinate is different, namely the adjacent memory cells of the same channel are in different physical pages, in S L C, M L C and T L C, the physical page and the logical page have the following relations that the physical page is i × logical page, for S L C, i is 1, for M L C, i is 2, for T L C, i is 3, therefore, in the related art, when binary coding is adopted, S L C has 2¹2 distribution states, M L C has 2²T L C has 2 distribution states³In the adjacent three physical layers, the present disclosure is described as a lower physical Page (L lower Page), a Middle physical Page (Middle Page), and an Upper physical Page (Upper Page), respectively, in terms of a direction along which the word line extends (i.e., z direction).

In step S11, the integrated distribution state of the current memory cell is determined according to the influence of the memory cells adjacent to the current memory cell on the distribution state of the current memory cell. The meaning of "memory cell adjacent to the current memory cell" here is: with the current memory cell as a starting point, the memory cells in the radiated ambient environment include memory cells adjacent to the current memory cell (without spacing other memory cells), next adjacent memory cells, next adjacent memory cells, and the like.

For example, for a 3D NAND flash memory, the memory cells adjacent to the memory cells on a certain physical page are: and the memory cell on the physical page adjacent to the physical page is positioned in the same channel as the memory cell. Since the memory cells on the same physical page have better electrical isolation characteristics, it can be considered that other memory cells on the same physical page have no influence on the current memory cell, and here, when determining the comprehensive distribution state, the memory cell spatially adjacent to the current memory cell but having substantially no influence is not counted in, or the influence thereof is recorded as 0.

Referring to fig. 3, in the 3D NAND flash memory, a word line W L (n) corresponds to a physical page where a current memory cell is located, n is a positive integer, in the case where n ≧ 1, a word line corresponding to a physical page where a memory cell adjacent to the current memory cell is located may be W L (n +1), W L (n +2), … …, in the case where n ≧ 2, a word line corresponding to a physical page where a memory cell adjacent to the current memory cell is located may be W L (n-1), W L (n +1), W L (n +2) … …, in accordance with the location of the current memory cell, an adjacent memory cell may be obtained along a single direction or a plurality of directions (2 or more than 2), an adjacent distance (i.e., the number or level of adjacent memory cells selected) may be set according to actual calculated efficiency, cost, and accuracy, for example, in the case where n ═ 2, a memory cell corresponding to the current memory cell may be a physical page corresponding to W L (W) 3911), W638 (3), W5963) may be also a physical page corresponding to W5963 (396), W638), W5963 (3), and W638 (3) (also may be also a physical page).

In other illustrative examples, such as for 2D flash memory, the multiple memory monolayers are arranged in a grid array, the current memory cell is located at the center, and the adjacent memory cells may be 8 memory cells surrounding the memory cell at the center, or 4 memory cells in the same line with the center memory cell, or a larger range and a larger number of adjacent memory cells may be selected. In addition, the neighboring memory cells may be divided into, from the near to the far, the following according to the distance between the neighboring memory cells and the current memory cell: first adjacent memory cell, second adjacent memory cell, … … kth adjacent memory cell, k being a positive integer, have similar arrangements to the previously described adjacent (without spacing other memory cells), next adjacent memory cell, next adjacent memory cell.

Next, referring to fig. 6, a correspondence relationship between different memory states and Binary Gray codes (Binary Gray codes) is described by taking a three-level cell T L C as an example.

FIG. 6 is a diagram illustrating an exemplary correspondence between states of a T L C flash memory and binary Gray codes according to an embodiment of the disclosureAs shown, each physical page has 8 distribution states, and the 8 distribution states are respectively represented by E, P in FIG. 6₁、P₂、P₃、P₄、P₅、P₆And P₇It is shown that, in the lower physical page, the gray codes corresponding to the 8 distribution states are: 10000111, the double-headed arrows in fig. 6 indicate that swapping is possible. Similarly, in the middle physical page, the gray codes corresponding to the 8 distribution states sequentially are: 11001100, in the upper physical page, the gray codes corresponding to the 8 distribution states are: 11100001.

in an example of implementing step S12, the information bits may be encoded by using the above-described gray code to obtain a code word, and written into the storage unit of the memory.

Examples of implementing step S11 are described below with reference to fig. 4-8, and details of the concept of comprehensive distribution state (Pattern set) proposed by the present disclosure and how to determine the comprehensive distribution state of the current memory cell according to the influence of the neighboring memory cells on the distribution state of the current memory cell are presented.

Fig. 4 is a schematic diagram illustrating an example of the distribution state influence of neighboring memory cells on the same channel on a current memory cell according to the embodiment of the disclosure. Fig. 5 is a schematic diagram illustrating determination of a comprehensive distribution state after considering influence of adjacent memory cells on the current memory cell on the distribution state of the adjacent memory cell on the same channel according to an example of the disclosure.

Two distribution states P of T L C flash memory₆And P₇For example, referring to FIG. 4, the conventional reading and decoding method is based on P indicated by solid line in FIG. 4₆Distribution state and P₇The distribution state, reading and decoding operations are performed in the manner previously described with reference to fig. 1. In the present disclosure, however, the threshold voltage ranges corresponding to the distribution states are increased E, P in the order of increasing the threshold voltage ranges corresponding to the distribution states, in consideration of the E distribution states corresponding to low electron concentrations₁、P₂、P₃、P₄、P₅、P₆And P₇The electron concentrations corresponding to the respective distribution states also differ, P₇The electron concentration corresponding to the distribution state is higher than P₁Distribution state, P₂Electron concentration of distributed state, then on the same channelIf there is a large difference in electron concentration between adjacent memory cells, diffusion movement of electrons in the channel is promoted, and electrons diffuse in a direction of low concentration along a high concentration, thereby affecting the actual distribution state of one of the adjacent memory cells. Thus, the current distribution state of a memory cell can be influenced by the distribution state of the neighboring memory cell in the same channel as the memory cell, such as the comprehensive distribution state EP corresponding to the dotted line exemplarily shown in FIG. 4₆E, alternatively may be represented by E-P₆E, in the form of A-X-B or AXB, X represents the distribution of a memory location on the current physical page; in the following description, generally, a represents a distribution state of a memory cell on a lower adjacent physical page in the same channel as the memory cell, and B represents a distribution state of a memory cell on an upper adjacent physical page in the same channel as the memory cell.

Specifically, X represents the distribution state of a certain memory cell on the current physical page; a represents the distribution state of a first memory cell (same as the x and y coordinates of the memory cell and different from the z coordinate) adjacent to the memory cell on a first physical page adjacent to the current physical page; b represents the distribution state of a second memory unit adjacent to the memory unit on a second physical page adjacent to the current physical page. Referring to fig. 3, a current physical page is, for example, a middle physical page, a first physical page is, for example, a lower physical page, a second physical page is, for example, an upper physical page, and coordinates of a certain storage unit on the current physical page are: (a, b, c), wherein a, b, c are positive integers, c is greater than or equal to 2, then the coordinates of the first storage unit are: (a, b, c-1), the coordinates of the second storage unit being: (a, b, c + 1). The EP₆E shows an exemplary expression form of the integrated distribution state. Similarly, in the dotted distribution state illustrated in fig. 4, the distribution state P for the current memory cell₆In other words, the integrated distribution state determined by considering the influence of the neighboring memory cells on the current memory cell in the same channel may be P₇P₆P₇Or EP₆E. Likewise, for the distribution state P of the current memory cell₇In other words, the integrated distribution state determined by considering the influence of the neighboring memory cells on the current memory cell in the same channel may be P₇P₇P₇Or EP₇E. It should be noted that the above example is only with P₇And E as an example, the actual distribution state corresponding to A, B above may be E, P₁、P₂、P₃、P₄、P₅、P₆And P₇Any of the above.

Referring next to FIG. 5, distribution state P₆And distribution state P₇The threshold voltage at the overlap between them is usually used as a boundary, for example, the overlap dividing line indicated by 3.8V in fig. 5, two other boundaries can be obtained at the adjacent preset distance on the left and right of the 3.8V boundary, here, the 3.7V and 3.9V boundaries are used as examples, the 3.7V, 3.8V and 3.9V boundaries divide the read data in the current view into ①, ②, ③ and ④ of four LL R regions (partitions), and the preset distance on the left and right of the overlap dividing line can be adjusted according to actual needs.

In the configuration or calculation of LL R, the comprehensive distribution state corresponding to the dotted line is considered, instead of the distribution state corresponding to the solid line, so as to facilitate distinguishing from the comprehensive distribution state described herein, the distribution state corresponding to the solid line considered in the prior art may be referred to as an initial distribution state, and the initial distribution state does not consider the influence of the neighboring memory cells on the same channel on the current distribution state of the memory cell.

Comparing the initial and integrated profiles of FIG. 5, in one illustrative example, the initial profile P₆The threshold voltage corresponding to the peak value (maximum cell number) of (1) is 3.4V, and the initial distribution state P₇Peak value (maximum storage) ofCell number value) of 4.2V, and the integrated distribution state (pattern set) of the current memory cell determined in consideration of the influence of the neighboring memory cells of the same channel on the distribution state of the current memory cell is, for example, EP₆E and EP₇E, in FIG. 5 with EP₆P in E₆Distribution state (P)₆distribution in EP₆E) To describe the comprehensive distribution state EP₆E, in EP₇P in E₇Distribution state (P)₇distribution in EP₇E) To describe the comprehensive distribution state EP₇E。

As can be seen from FIG. 5, the EP of the integrated distribution state₆The threshold voltage corresponding to the peak value of E is 3.35V, and the comprehensive distribution state EP₇The threshold voltage corresponding to the peak value of E is 4.15V, and there is a difference from the threshold voltage corresponding to the peak value of the initial distribution state, so that the probability of calculating the LL R value in each partition is also different, in the embodiment illustrated in fig. 5, the LL R value of each partition calculated by using the initial distribution state in the prior art and the LL R value of each partition obtained by using the comprehensive distribution state of the present disclosure are shown in table 1, in the prior art, the signs of the LL R values corresponding to the regions ①, LL 0, LL, LL respectively correspond to + + -, whereas, by using the method of the embodiment of the present disclosure, the signs of the LL R values of each partition ①, LL, ③, ④ obtained based on the comprehensive distribution state correspond to ++ -, the method of the present disclosure is completely opposite to the results obtained by using the conventional error correction method at the region ②, and experiments verify that the method of the present disclosure effectively reduces the error rate and improves the capability of the device.

TABLE 1 comparison of R values of various partitions LL obtained using initial and integrated states of distribution

The following describes the beneficial effects of the decoding process based on LL R value of the integrated distribution configuration with reference to the experimental results illustrated in FIGS. 9 and 10.

Fig. 9 is a comparison graph of error correction capability between L DPC soft decoding method and the conventional decoding method according to the embodiment of the present disclosure, and fig. 10 is a comparison graph of bit error rate between L DPC soft decoding method and the conventional decoding method according to the embodiment of the present disclosure.

LL R of the region ② obtained by the conventional method illustrated in table 1 above is decoded to be an Error, and the result of decoding based on the LL R value obtained by the comprehensive distribution state proposed by the embodiment of the present disclosure achieves an Error correction effect, in fig. 9, the abscissa is the original Bit Error Rate (RBER), the ordinate is the Uncorrectable Bit Error Rate (UBER), in fig. 10, the abscissa is the storage time, and the ordinate is the average number of errors of the codeword, as shown in fig. 9 and fig. 10, the L DPC soft decoding method of the present disclosure effectively reduces RBER and effectively improves the Error correction capability compared with the conventional method.

In an embodiment of the present disclosure, the comprehensive distribution status of the flash memory is divided into three types, which are: the integral left-bias type, the integral center type, and the integral right-bias type are described in detail below with reference to fig. 7.

Fig. 7 is a schematic diagram illustrating a comprehensive distribution state of a memory cell divided into three types according to an example of the present disclosure.

In this embodiment, taking T L C flash memory as an example, as shown in fig. 3 and 7, for a memory cell on a current physical page, the distribution state of a memory cell on an adjacent physical page in the same channel as the memory cell affects the distribution state of the memory cell on the current physical page, so that the threshold voltage distributions of the memory cells on three physical pages, for example, the threshold voltage distributions of the memory cells on physical page 1, physical page 2 and physical page 3, can be sequentially obtained in a word line bottom-up reading manner, and the comprehensive distribution state of the memory cells on corresponding middle physical page — physical page 2 can be determined according to the obtained threshold voltage distributions of the memory cells on three physical pages.

Taking T L C as an example, the comprehensive distribution state determined based on the above method is divided into three types, namely, an integral left type, an integral center type and an integral partial typeRight type, where overall left type is Low/Medium-X-Low, LL R is Positive in region LL 1, all negative in regions LL 2, LL 3, and LL 0. Overall Right type is Low/Medium/high-X-high, Medium/high-X-in LL R is Positive in regions ①, ②, and ③, and negative in region LL 4. the case of the remaining forms is Overall centered type, LL R is Positive in regions ① and ②, and both negative in regions ③ and ④, "/" in this paragraph indicates the meaning of "OR". The Low correspondence distribution state is E, P₁、P₂(ii) a The medium corresponding distribution state is: p₃、P₄The high correspondence distribution state is: p₅、P₆、P₇The word line W L is read from bottom to top in a manner corresponding to low (0-2), medium (3-4) and high (5-7), the numbers in parentheses indicate the location of the word line on the z-axis, 0 indicates the word line is read from the bottom-most memory cell array, for example, the initial distribution state P illustrated in FIG. 7₆And P₇Based on EP in the global distribution obtained after the lateral diffusion effect₆E、EP₇E is of the overall left-biased type and is in a comprehensive distribution state P₄P₆P₄、P₇P₆P₇、P₄P₇P₄、P₇P₇P₇Is of the overall right-hand type. For example, the overall distribution state corresponding to the overall centering type may be as follows: p₇P₆E、P₇P₇E. Of course, X is P₆And P₇By way of example, it may actually be the distribution E, P₁、P₂、P₃、P₄、P₅、P₆And P₇Any of the above.

Experiments prove that for a 3D NAND flash memory, the influence of the storage units in the upper physical page on the current storage unit distribution state is larger than the influence of the storage units in the lower physical page on the current storage unit distribution state, so that in a preferred embodiment, only two layers of physical pages can be selected for reading operation, wherein the physical page in the lower layer (with a smaller word line number) is the physical page in which the current storage unit is located, and the physical page in the upper layer is the physical page in which the storage unit adjacent to the storage unit is located, so that higher reading accuracy is realized with the minimum reading cost.

In an embodiment of the present disclosure, the memory is a 3D NAND flash memory, the coordinate corresponding to the current storage unit is (m, n, k), k is greater than or equal to 1, and the way of selecting the storage unit adjacent to the storage unit is as follows: and sequentially selecting a plurality of storage units with preset distances from the current storage unit along the z-axis upwards and/or downwards.

For example, for a 3D NAND flash memory, in the process of determining the comprehensive distribution state, the method is not limited to selecting the number of layers, the selection direction, and the distance of the physical page, for example, at least 2 layers of physical pages may be selected, the current coordinate corresponding to the storage unit is (m, n, 1), one storage unit corresponding to the coordinate of (m, n, 2) may be selected when calculating the comprehensive distribution state, and two or more storage units corresponding to the coordinates of (m, n, 2), (m, n, 3) may also be selected.

In another example, the coordinate corresponding to the current storage unit is (m, n, 5), and different distances may be selected as the adjacent storage units according to a single direction when calculating the comprehensive distribution state, for example, one storage unit with the coordinate corresponding to (m, n, 6) is selected, or two storage units with the coordinates corresponding to (m, n, 6), (m, n, 7) are selected; of course, the selection may be performed in the opposite direction, for example, the storage unit with the coordinate (m, n, 4) is selected. In addition, the respective distances may be selected in a plurality of directions, for example, (m, n, 4), (m, n, 6); or (m, n, 3), (m, n, 4) and (m, n, 6) are selected; or (m, n, 4), (m, n, 6) and (m, n, 7) are selected; or (m, n, 3), (m, n, 4), (m, n, 6), (m, n, 7) is selected.

The above embodiment is described with reference to a structure corresponding to a 3D NAND flash memory, and it should be noted that the selection direction, the selection distance, and the like of the memory cell adjacent to the current memory cell corresponding to the structures of other memories may be considered comprehensively according to the structural features, the distribution influence, and the selection cost of the memory.

The operation of the L DPC soft decoding method of the present disclosure is described below with reference to FIG. 8. in the following description, the upper physical page is taken as an exemplary description, and the intermediate physical page and the lower physical page are the same.

Fig. 8 is a schematic diagram of a partitioned area of a T L C flash memory according to an embodiment of the present disclosure, where (a) is a partitioned LL R area, and (b) is binary gray code corresponding to each LL R area for three adjacent physical pages.

The partition setting is performed as described above, the threshold voltages corresponding to the overlapping portions of the adjacent distribution states are used as boundary lines, and the threshold voltages of the left and right adjacent preset distances of the boundary lines at the overlapping portions are selected as two adjacent boundary lines, fig. 8 (a) selectively illustrates the multi-component boundary lines, i.e., Rv4, Rv5, Rv6, Rv7, Rv8, Rv9, Rv19, Rv20, and Rv21, so that for T L C, 8 distribution states are totally generated, 7 overlapping boundary lines are generated, 3 boundary lines are actually generated for each overlapping boundary line, 21 boundary lines are totally generated, T L C is totally divided into 22 regions, i.e., 22 LL R partitions, the LL R partition case can be referred to fig. 8 (a), and for the above physical page partition case example, a part of the distribution state is omitted, and only P is used for illustrating the whole physical page partition case₂、P₃、P₆And P₇Fig. 8 (b) correspondingly illustrates a part of binary gray codes in distributed states shown in different physical pages, and the encoding manner of setting gray codes in distributed states in different physical pages may refer to the foregoing description about fig. 6, which is not described herein again.

In the upper physical page, E, P is corresponded as shown in (b) in fig. 6 and 8₁、P₂、P₃、P₄、P₅、P₆And P₇The gray codes of the 8 distribution states are 11100001 in sequence, the read data can be divided into three large areas according to the gray codes, namely E-P2, P3-P6 and P7, Rv7, Rv8, Rv9, Rv19, Rv20, Rv21 and extra Rv6, Rv10 and Rv18 are taken as the internal boundary of the large areas, 10 small areas of 1+4+1+4 to LL R are obtained, the LL R value of the areas 11-18 is set to be 10, the LL R value of the areas 1-6 is set to be-10, and for the small areas 7-10 (shown by (b) in FIG. 8 in ⑦ - ⑩) and the small areas 19-22 (equivalent to 19 and 22), the gray codes are integrated according to the integrated circles and the integrated circles according to the integrated circlesThe distribution state sets LL R values in each small region, in the process, LL R values can be configured according to test data of an actual flash memory.

After LL R values are set in the partitions (small areas) 7-10 and 19-22 according to the comprehensive distribution state, LL R values under different storage time, different threshold voltage partitions and the comprehensive distribution state can be established, a LL R table is obtained, and in the LL R table, the input is the storage time, the threshold voltage partitions and the comprehensive distribution state, and the output is LL R value.

The above-mentioned process describes the specific implementation process of determining the comprehensive distribution state of the current memory cell according to the influence of the adjacent memory cells of the same channel on the distribution state of the current memory cell in the T L C flash memory, and correspondingly establishing LL R values under different storage times, threshold voltage partitions and comprehensive distribution states, i.e. implementing the process of step S11. the above-mentioned step S11 may be performed in advance, and in the subsequent decoding process, it is not necessary to establish a LL R table every time of decoding, the pre-established LL R table may be stored in the memory, and it is only necessary to call directly in the subsequent decoding process.

Step S12 is performed to encode the information bits into code words and write the code words into the memory cells of the memory.

Step S13 is performed, the partition attribution of the memory cells in the upper physical page is read out by using the threshold voltages corresponding to Rv6, Rv7, Rv8, Rv9, Rv10, Rv18, Rv19, Rv20 and Rv21, and LL R table is queried according to the memory time, partition and comprehensive distribution state, and the corresponding LL R value is assigned to the upper physical page.

Step S14 is performed to perform soft decoding of LL R of the upper physical page codeword.

In summary, the present embodiment discloses an L DPC soft decoding method, in which, considering that a lateral diffusion effect exists in a memory cell array, due to the design of a memory using a shared charge storage space, information stored in adjacent memory cells has a great influence on the storage characteristics of a current memory cell, after dividing regions at an overlap based on an initial distribution state, a value of LL R is determined in each region according to a comprehensive distribution state considering the influence of the distribution state of the adjacent memory cells, and a soft decoding method according to the LL R value determined by the comprehensive distribution state reduces an error rate compared with an existing L DPC soft decoding method, improves an error correction capability, and reduces the number of iterations.

In a second exemplary embodiment of the present disclosure, a memory is provided for performing the L DPC soft decoding method described above, in particular a non-volatile memory, which may be a 2D or 3D flash memory, for example a 3D NAND flash memory.

It should be noted that, the memory is not limited to the lateral diffusion effect or the capacitive coupling effect mentioned in the foregoing embodiments, and the memory is within the protection scope of the present disclosure as long as there is an influence or interference effect of the memory cell on the current memory cell distribution state in the surrounding environment.

In one embodiment, the memory may be a computer-readable storage medium that may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The memory of the present embodiment is used as an implementation object of the soft decoding method, and the operations of step S11, step S13 and step S14 are executed on the memory, wherein step S11 only needs to be executed once in advance, and is not required to be executed each time the decoding operation is performed, step S12 may be executed before step S13, in another embodiment, step S11 of pre-establishing LL R table may be executed on the memory in advance, the established LL R may be stored in a storage module, the storage module may be located on the memory, or may be located in another storage device or server besides the memory, step S12, step S13 and step S14 are executed on the memory each time, and step S13 may directly retrieve the LL R table from the storage module.

The memory of the embodiment is a 3D NAND flash memory, adopts a comprehensive distribution state when LL R is configured when decoding operation is executed, considers the influence of adjacent memory cells of the same channel on the distribution state of the current memory cell, reduces the error rate, improves the error correction capability, and reduces the iteration times.

In a third exemplary embodiment of the present disclosure, an electronic device is provided, which is configured to implement the L DPC soft decoding method described above.

Fig. 11 is a block diagram of an electronic device according to another embodiment of the present disclosure.

Referring to fig. 11, the electronic device 3 of the present embodiment includes an LL R storage unit 31, an encoding unit 32, a reading unit 33, and a decoding unit 34.

LL R memory cell 31 for storing pre-established LL R table, the LL R table has the input quantity of storage time, threshold voltage partition and comprehensive distribution state, and the output quantity is LL R value, wherein, the comprehensive distribution state of the current memory cell is determined according to the influence of the memory cell adjacent to the current memory cell on the distribution state of the current memory cell.

And the encoding unit 32 is used for encoding the information bits to obtain code words and writing the code words into storage units of a memory.

And the reading unit 33 is used for reading the memory cell of which the information bit is coded, partitioning and comprehensively distributing the memory cell according to the storage time, the threshold voltage and the comprehensive distribution state corresponding to the current memory cell during reading, and extracting a pre-established LL R table from the LL R memory cell to obtain the LL R value of the current memory cell.

And the decoding unit 34 is used for performing soft decoding operation on the code words of the memory cells of which the information bits are coded according to the LL R values of the read current memory cells.

In an embodiment of the present disclosure, the electronic device 3 includes: computer, cell-phone, intelligent stereo set, wearable smart machine, robot, smart chip etc..

In one embodiment, the electronic device and the memory for performing encoding and decoding may be two independent entities, for example, the electronic device is a computer, and the memory is a usb disk, or the memory is a component of the electronic device, for example, the electronic device is a computer, and the memory is a NAND flash memory chip inside the computer, and correspondingly, the LL R storage unit 31 may be a storage unit in the memory for performing encoding and decoding operations, or may be hardware or a combination of software and hardware with storage functions in other storage devices besides the memory, for example, when the electronic device and the memory are two independent entities, the LL R storage unit 31 may be located in the memory, the electronic device, or a server that can communicate with the execution entity (the electronic device and/or the memory), and may be called when needed.

The method flows according to embodiments of the present disclosure may be implemented as computer software programs. The encoding unit 32, the reading unit 33, and the decoding unit 34 described above may be computer program instructions. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable storage medium, the computer program containing program code for performing the method illustrated by the flow chart.

In summary, the present disclosure provides an L DPC soft decoding method, a memory and an electronic device, in consideration of the lateral diffusion effect existing in a memory cell array, since the memory adopts a design of sharing a charge storage space, information stored by adjacent memory cells has a great influence on the storage characteristics of a current memory cell, after dividing regions based on an overlapping portion of an initial distribution state, a value of LL R is determined in each region according to a comprehensive distribution state considering the influence of the distribution state of the adjacent memory cells, and a decoding method based on the LL R value determined by the comprehensive distribution state reduces an error rate compared with the existing L DPC soft decoding method, improves an error correction capability, and reduces the number of iterations.

In the embodiments of the present disclosure, each block in the block diagrams or flowchart, and combinations of blocks in the block diagrams or flowchart, may be implemented by special purpose hardware-based systems that perform the specified functions or operations, or combinations of special purpose hardware and computer instructions.

The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The order of execution of the flowcharts and the example embodiments is not intended to be exclusive, and other logical orders of execution are within the scope of the present disclosure.

The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.