阅读说明：本技术 写入非易失性存储器的方法和相应的集成电路 (Method for writing to a non-volatile memory and corresponding integrated circuit ) 是由 F·拉罗萨 E·卡斯塔尔多 F·格兰德 S·N·A·帕加诺 G·纳斯塔西 F·伊塔里亚诺 于 2021-04-13 设计创作，主要内容包括：公开了写入非易失性存储器的方法和相应的集成电路。非易失性存储器的半导体阱容纳存储器单元。每个存储器单元具有浮置栅极和控制栅极。对存储器单元的擦除包括用第一擦除电压偏置半导体阱,第一擦除电压的绝对值大于存储器的控制栅极开关电路的双极结的击穿电压电平。第一擦除电压的绝对值基于存储器单元的磨损指示的值与磨损阈值的比较。(Methods of writing to non-volatile memory and corresponding integrated circuits are disclosed. The semiconductor well of the non-volatile memory houses the memory cells. Each memory cell has a floating gate and a control gate. Erasing the memory cell includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switching circuit of the memory. The absolute value of the first erase voltage is based on a comparison of a value of a wear indication of the memory cell to a wear threshold.)

1. A method, comprising:

erasing memory cells contained in a semiconductor well of a non-volatile memory, each of the memory cells having a floating gate and a control gate, the erasing comprising biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switching circuit of the memory, the absolute value of the first erase voltage based on a comparison of a value of a wear indication of the memory cell to a wear threshold; and

one or more of the memory cells are written.

2. The method of claim 1, wherein the absolute value of the first erase voltage is increased in response to the comparison indicating that the value of the wear indication is greater than the wear threshold.

3. The method of claim 2, wherein the erasing comprises: biasing the control gate of the selected memory cell with a second erase voltage using the control gate switching circuit.

4. The method of claim 1, wherein,

the memory includes a peripheral circuit, and a buffer transistor accommodated in a buffer semiconductor well;

the memory cell is coupled to the peripheral circuitry through a conductive terminal of the buffer transistor; and

the buffer semiconductor well and gates of the buffer transistors are biased by a buffer isolation voltage to isolate the peripheral circuitry from the first erase voltage.

5. The method of claim 4, wherein in response to the value of the wear indication being less than the wear threshold, the buffer isolation voltage is set to be at least equal to a difference between a level of the first erase voltage and the breakdown voltage level of the bipolar junction of the control gate switch circuit.

6. The method of claim 4, wherein a semiconductor isolation region is biased by the first erase voltage, the semiconductor isolation region surrounding the semiconductor well housing the memory cell and the buffer semiconductor well, the memory having a triple-well type structure.

7. The method of claim 1, wherein the erase cycle comprises: biasing, via the control gate switching circuit, the control gates of unselected memory cells with a neutralization voltage.

8. The method of claim 7, wherein in response to the value of the wear indication being less than the wear threshold, the level of the neutralization voltage is increased in absolute value to maintain a constant initial offset relative to the level of the first erase voltage.

9. The method of claim 7, wherein in response to the value of the wear indication being greater than the wear threshold, the level of the neutralization voltage is shifted to an offset neutralization voltage level, and the level of the offset neutralization voltage is increased in absolute value so as to keep the offset constant relative to the level of the first erase voltage.

10. The method of claim 9, wherein a level of the first erase voltage is maintained in response to a value of the wear indication being greater than the wear threshold and a level of the neutralization voltage reaching the breakdown voltage level of the bipolar junction of the control gate switching circuit.

11. The method of claim 1, wherein in response to a value of the wear indication being greater than the wear threshold, a level of the first erase voltage is maintained at a level equal to a tolerance margin taken for the breakdown voltage level of the bipolar junction of the control gate switch circuit.

12. A non-volatile memory integrated circuit, comprising:

memory cells housed in the semiconductor well, each memory cell including a state transistor having a floating gate and a control gate; and

control circuitry that, in operation, controls reading, writing, and erasing of the memory cell, wherein the erasing includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switching circuit of the non-volatile memory, the absolute value of the first erase voltage being based on a comparison of a value of a wear indication of the memory cell to a wear threshold.

13. The integrated circuit of claim 12, wherein the absolute value of the first erase voltage is increased in response to the comparison indicating that the value of the wear indication is greater than the wear threshold.

14. The integrated circuit of claim 12, wherein the control circuitry is operable to bias the control gate of the selected memory cell with a second erase voltage using the control gate switching circuit.

15. The integrated circuit of claim 12, comprising peripheral circuitry, and a buffer transistor housed in a buffer semiconductor well, wherein the memory cell is coupled to the peripheral circuitry through a conductive terminal of the buffer transistor, and the control circuitry is operable to bias the buffer semiconductor well and a gate of the buffer transistor with a buffer isolation voltage to isolate the peripheral circuitry from the first erase voltage.

16. The integrated circuit of claim 15, wherein in operation, when the value of the wear indication is greater than the wear threshold, the control circuitry generates the buffer isolation voltage that is at least equal to a difference between a level of the first erase voltage and the breakdown voltage level of the bipolar junction of the control gate switch circuit.

17. The integrated circuit of claim 15 wherein the semiconductor well housing the memory cell is surrounded by a semiconductor isolation region in a triple well structure, the buffer semiconductor well is surrounded by the semiconductor isolation region, and the control circuitry is operative to bias the semiconductor isolation region with the first erase voltage.

18. The integrated circuit of claim 12, wherein the control circuitry biases the control gates of unselected memory cells with a neutralization voltage via the control gate switching circuit during an erase cycle.

19. The integrated circuit of claim 18 wherein during the erase cycle, the control circuitry sets the level of the neutralization voltage in absolute value to maintain a constant initial offset from the level of the first erase voltage when the value indicative of wear is less than the wear threshold.

20. The integrated circuit of claim 18, wherein during the erase cycle, when the value indicative of wear is greater than the wear threshold, the control circuitry is operative to shift the level of the neutralization voltage to an offset neutralization voltage level and increase the level of the offset neutralization voltage in absolute value so as to keep the offset constant relative to the level of the first erase voltage.

21. The integrated circuit of claim 20, wherein the control circuitry maintains the level of the first erase voltage unchanged when the level of the neutralization voltage reaches the breakdown level of the bipolar junction of the control gate switching circuit when the value indicative of wear is greater than the wear threshold.

22. The integrated circuit of claim 12, wherein when the value indicative of wear is greater than the wear threshold, the control circuitry maintains the level of the first erase voltage unchanged when the level of the first erase voltage is equal to a tolerance margin taken for the breakdown level of the bipolar junction of the control gate switching circuit.

23. A system, comprising:

one or more processing cores; and

a non-volatile memory coupled to the one or more processing cores, the non-volatile memory comprising:

memory cells housed in the semiconductor well, each memory cell including a state transistor having a floating gate and a control gate; and

control circuitry that, in operation, controls reading, writing, and erasing of the memory cell, wherein the erasing includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switching circuit of the non-volatile memory, the absolute value of the first erase voltage being based on a comparison of a value of a wear indication of the memory cell to a wear threshold.

24. The system of claim 23, comprising an integrated circuit that includes the non-volatile memory.

25. The system of claim 24, wherein the integrated circuit comprises the one or more processing cores.

26. The system of claim 23, wherein the absolute value of the first erase voltage is increased in response to the comparison indicating that the value of the wear indication is greater than the wear threshold.

Technical Field

Embodiments and implementations relate to integrated circuits, and in particular, to non-volatile memory and writing in non-volatile memory.

Background

Writing in a non-volatile memory "EEPROM" (electrically erasable programmable read only memory), for example of the electrically erasable and programmable type, usually comprises an erase cycle followed by a programming cycle. For example, an erase cycle is collective in so-called selected memory cells belonging to a so-called selected full page (or row), while programming is selective according to the data ("0" or "1") to be written in different memory cells of the selected memory.

During erase and programming cycles, the floating gate transistor belonging to each memory cell is biased with a write voltage high enough to inject charges (positive or negative, depending on the erase and programming specifications employed) into the floating gate of the transistor by Fowler-Nordheim effect or by the effect of injecting hot carriers.

Therefore, the threshold value (value of the threshold voltage) of the floating gate transistor in the erased state is different from the threshold value of the floating gate transistor in the programmed state that allows reading of the stored data.

The write voltage is approximately 10 to 15 volts in absolute value and is applied, for example, between the control gate and the body (the substrate or well that houses the transistor) of the floating gate transistor during erase or between the control gate and a conductive terminal of the floating gate transistor, for example, during programming.

In order to generate a high write voltage, a voltage division technique is used for applying a positive voltage of moderate amplitude on the one hand and a negative voltage of moderate amplitude on the other hand.

This allows, among other things, a reduction in the size of the transistors of the memory (especially the transistors that carry the write voltage) in view of the voltage limitation in these transistors being alleviated by the voltage division technique.

Over many erase and programming cycles, charge injection is particularly prone to degradation of the dielectric layer through which the injected charge passes through by tunneling.

This degradation results in a shift in the threshold of the transistor in the erased and programmed states.

This drift is particularly high in erase involving charges injected between the semiconductor body and the floating gate. For example, after hundreds of thousands of write cycles (e.g., 500,000 cycles), the threshold in the erased state may be about 2 to 4 volts greater than the threshold in the erased state resulting from the first erase cycle.

Therefore, after a large number of write cycles, the distinction between the erased state and the programmed state becomes uncertain.

This aging phenomenon causes the endurance of the memory to be limited. Memory endurance is a characteristic that defines the number of write cycles that guarantee normal operation of the memory (in other words, the "life" of the memory). Durability is an important property from a commercial perspective.

This aging phenomenon is more pronounced as the size of the transistors in the memory is reduced.

Furthermore, the technique for increasing the lifetime of the erase cycle to limit the drift of the threshold in the erased state has the immediate drawback of slowing down the write operation. The speed of the write cycle is also an important characteristic from a commercial point of view.

Thus, conventional techniques for increasing the erase voltage to limit threshold drift are typically limited by the breakdown level of the junction of the transistor that passes the control gate voltage.

Disclosure of Invention

Therefore, there is a need to propose a compact non-volatile memory with longer endurance without limiting other characteristics of the memory.

According to one aspect, the present disclosure is directed to a method for writing to a non-volatile memory including memory cells housed in a semiconductor well, each memory cell including a state transistor having a floating gate and a control gate. The method includes an erase cycle that includes biasing the semiconductor well with a first erase voltage (e.g., positive), and in response to an increase in a wear value of the memory cell being greater than a wear threshold, increasing a level of the first erase voltage in absolute value to a level greater than a breakdown level of a bipolar junction of a control gate switching circuit of the memory.

In a method according to this aspect, the erase cycle can include biasing the control gate of the selected memory cell with a second erase voltage (e.g., negative) through the control gate switch circuit.

It goes without saying that the wear value of a memory cell is a value which represents the aging of the memory cell and which can be determined at a given moment by a circuit provided for this purpose. For example, the number of erase cycles performed may be counted and the count may be used as a wear indication for the memory cells; the difference between the storage voltage level and the threshold voltage level of the memory cell may be used as a wear indication; and the like; and combinations thereof.

The wear threshold may be a value that represents aging of the memory cell, since the maximum voltage level (breakdown level of the bipolar junction) in the aging control gate switch circuit is no longer sufficient to prevent drift (e.g., drift of about 2 volts) of the threshold of the state transistor in the erased state. This aging of the memory cells (corresponding to the wear threshold) may be illustrated, for example, by 500,000 write cycles implemented in the memory.

The first erase voltage and the second erase voltage are mutually configured to erase the selected memory cell, for example, by injecting charge into a floating gate of a state transistor of the selected memory cell, typically by the Fowler-Nordheim effect.

In other words, the method according to this aspect proposes that in the voltage dividing technique, the magnitude of the erase voltage is increased by increasing the component of the erase voltage (first erase voltage) applied in the well of the memory cell in absolute value.

However, the first erase voltage does not pass through the control gate switch circuit.

Therefore, the level of the first erase voltage is not limited by the breakdown level of the bipolar junction of the gate switch circuit.

This therefore allows limiting the drift of the threshold while strengthening the erase in the aged memory cell beyond the limit imposed by the breakdown of the bipolar junction of the control gate switching circuit and thus allowing increasing the overall endurance of the memory.

The memory may include a peripheral circuit, a buffer transistor housed in the buffer semiconductor well, the memory cell coupled to the peripheral circuit through a conductive terminal of the buffer transistor, and, according to one implementation, biasing the buffer semiconductor well and a gate of the buffer transistor with a buffer isolation voltage adapted to isolate the peripheral circuit from the first erase voltage.

For example, the bit line is coupled to a conductive terminal of a state transistor of the memory cell, and the bit line is coupled to the peripheral circuitry through a conductive terminal of a buffer transistor.

This allows the first erase voltage to not be transmitted to the peripheral circuit when the level of the first erase voltage is greater than the breakdown level of the control gate switch circuit, a voltage greater than the breakdown level of the control gate switch circuit being generally destructive to the peripheral circuit.

More specifically, since the bit line is not used during the erase period, the bit line is at a floating potential. Thus, the potential of the bit line may rise to the level of the first erase voltage, potentially to a voltage level that can degrade peripheral circuitry.

However, since the gate of the buffer transistor is biased with the buffer isolation voltage, the peripheral circuitry is protected from the first erase voltage present on the bit line during writing. In addition, since the buffer semiconductor well is also biased with the buffer isolation voltage, the buffer transistor will not be damaged by the first erase voltage of the bit line.

In this regard, when the wear value is greater than the wear threshold, the buffer isolation voltage may be at least equal to a difference between a level of the first erase voltage and a breakdown level of a bipolar junction of the control gate switching circuit.

According to one implementation, a semiconductor isolation region is biased with a first erase voltage, and a conductor isolation region surrounds a semiconductor well and a buffer semiconductor well in a triple-well type structure, wherein the semiconductor well accommodates a memory cell.

In one aspect, a semiconductor region of a memory is allowed to be electrically isolated from a first erase voltage. More specifically, the bipolar junction between the substrate and the semiconductor isolation region is generally capable of supporting a voltage greater than the breakdown voltage of the control gate switching circuit.

On the other hand, the semiconductor isolation region shared by the triple-well type structure for both the well for housing the memory cell and the buffer well is advantageously compact. This sharing is particularly obtained by the buffer isolation voltage, preventing breakdown of the bipolar junction between the buffer semiconductor well and the semiconductor isolation region biased with the first erase voltage.

According to one implementation, the erase cycle further includes biasing the control gates of the unselected memory cells with a neutralization voltage via the control gate switching circuit.

The neutralization voltage is configured relative to a first erase voltage applied in a well that also accommodates the unselected memory cells to neutralize the pseudo-erase phenomenon of the unselected memory cells. This is advantageous in terms of data retention.

For example, the neutralization voltage is selected so that it equals the first erase voltage. However, this neutralization voltage is limited by the breakdown level of the bipolar junction of the control gate switching circuit.

According to one implementation, when the wear value is less than the wear threshold, the method includes increasing the level of the neutralization voltage in absolute value so as to maintain a constant initial offset with respect to the level of the first erase voltage. In the case where the neutralization voltage is selected so that it is equal to the first erase voltage, the initial offset that remains constant is a zero offset.

This advantageously allows the pseudo-erase phenomenon of the unselected memory cells to be neutralized, while the first erase voltage increases as the memory cells age.

According to one implementation, when the wear value is greater than the wear threshold, the method includes shifting a level of the neutralization voltage to an offset neutralization voltage level, and increasing the level of the offset neutralization voltage in absolute value so as to keep the offset constant with respect to the level of the first erase voltage.

Furthermore, advantageously, when the wear value is greater than the wear threshold, the level of the first erase voltage remains unchanged when the level of the neutralization voltage reaches said breakdown level of the bipolar junction of the control gate switching circuit.

In other words, when the first erase voltage exceeds the breakdown voltage of the control gate switching circuit, the level of the neutralization voltage is shifted to not exceed the level of the breakdown voltage. Then, as a result of the shift, the neutralization voltage follows the evolution of the first erase voltage without exceeding the breakdown voltage. When the neutralization voltage reaches a level of breakdown voltage of the bipolar junction of the control gate switching circuit closest to the safety margin, the first erase voltage is no longer increased.

Maintaining a constant offset when increasing the first erase voltage to exceed the wear threshold is advantageous in regulating the generated voltage and allows for good control of the spurious erase phenomena caused by this constant difference. In this regard, the method may compensate for the false erase by conventional mechanisms (e.g., so-called "refresh" algorithms).

According to another implementation, when the wear value is greater than the wear threshold, the level of the first erase voltage remains unchanged at a level equal to a tolerance margin taken for the breakdown level of the bipolar junction of the control gate switch circuit.

In this other implementation, the level of the neutralization voltage does not shift and remains constant beyond the wear threshold. Therefore, the deviation between the level of the first erase voltage and the level of the neutralization voltage increases as the level of the first erase voltage evolves. Thus, the pseudo-erase phenomenon in unselected memory cells may not be well controlled, but is lower at the beginning than at the end for a period of time that begins after the wear threshold.

According to another aspect, the present disclosure is directed to a non-volatile memory integrated circuit, comprising:

memory cells housed in a semiconductor well and each including a state transistor having a floating gate and a control gate; and

an erase device configured to bias the semiconductor well with a first erase voltage (e.g., positive) during an erase cycle, the erase device configured to increase a level of the first erase voltage in absolute value to a level greater than a breakdown level of the bipolar junction of the control gate switching circuit in response to a wear value of the memory cell increasing to be greater than a wear threshold.

According to one embodiment, the erase device is configured to bias the control gate of the selected memory cell with a second erase voltage (e.g., negative) through the control gate switch circuit during an erase cycle.

According to one embodiment, the integrated circuit further includes peripheral circuitry, a buffer transistor housed in the buffer semiconductor well, and the memory cell is coupled to the peripheral circuitry through a conductive terminal of the buffer transistor, the buffer semiconductor well and a gate of the buffer transistor to be biased with a buffer isolation voltage adapted to isolate the peripheral circuitry from the first erase voltage.

According to one embodiment, when the wear value is greater than the wear threshold, the distribution circuit is configured to generate a buffer isolation voltage at least equal to a difference between a level of the first erase voltage and a breakdown level of a bipolar junction of the control gate switching circuit.

According to one embodiment, the semiconductor well housing the memory cell is surrounded by a semiconductor isolation region in a triple-well type structure, and in the triple-well type structure, the buffer semiconductor well is also surrounded by the same semiconductor isolation region, which is to be biased with the first erase voltage.

According to one embodiment, the erase means is further configured to bias the control gates of the unselected memory cells with a neutralization voltage through the control gate switch circuit during the erase cycle.

According to one embodiment, when the wear value is less than the wear threshold, the erase means is configured to increase the level of the neutralization voltage in absolute value so as to maintain a constant initial deviation with respect to said level of the first erase voltage.

According to one embodiment, when the wear value is greater than the wear threshold, the erase means is configured to shift the level of the neutralization voltage to an offset neutralization voltage level and increase the level of the offset neutralization voltage in absolute value so that the offset remains constant with respect to said level of the first erase voltage.

According to one embodiment, when the wear value is greater than the wear threshold, the erase means is configured to keep the level of the first erase voltage constant when the level of the neutralization voltage reaches said breakdown level of the bipolar junction of the control gate switch circuit.

According to one embodiment, when the wear value is greater than the wear threshold, the erase means is configured to keep the level of the first erase voltage constant when the level of the first erase voltage is equal to a tolerance margin taken for said breakdown level of the bipolar junction of the control gate switch circuit.

In an embodiment, a method comprises: erasing memory cells contained in a semiconductor well of a non-volatile memory, each memory cell having a floating gate and a control gate, the erasing comprising biasing the semiconductor well with a first erase voltage, the first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switching circuit of the memory, the absolute value of the first erase voltage based on a comparison of a value of a wear indication of the memory cell to a wear threshold; and writing to one or more of the memory cells. In an embodiment, the absolute value of the erase voltage is increased in response to a comparison indicating that the value of the wear indication is greater than the wear threshold. In an embodiment, erasing includes biasing the control gate of the selected memory cell with a second erase voltage using a control gate switch circuit. In an embodiment, a memory includes peripheral circuits and a buffer transistor accommodated in a buffer semiconductor well; the memory cell is coupled to the peripheral circuit through a conductive terminal of the buffer transistor; and biasing the buffer semiconductor well and the gate of the buffer transistor with a buffer isolation voltage to isolate the peripheral circuitry from the first erase voltage. In an embodiment, the buffer isolation voltage is at least equal to a difference between a level of the first erase voltage and a breakdown voltage level of a bipolar junction of the control gate switching circuit when the value of the wear indication is less than the wear threshold. In an embodiment, a semiconductor isolation region is biased with a first erase voltage, the semiconductor isolation region surrounding a semiconductor well housing a memory cell and a buffer semiconductor well, the memory having a triple-well type structure. In an embodiment, the erase cycle includes biasing the control gates of the unselected memory cells with a neutralization voltage via a control gate switching circuit. In an embodiment, when the value of the wear indication is less than the wear threshold, the method includes increasing the level of the neutralization voltage in absolute value so as to maintain a constant initial offset relative to the level of the first erase voltage. In an embodiment, when the value of the wear indication is greater than the wear threshold, the method includes shifting a level of the neutralization voltage to an offset neutralization voltage level, and increasing the level of the offset neutralization voltage in absolute value so as to keep the offset constant relative to a level of the first erase voltage. In an embodiment, when the value of the wear indication is greater than the wear threshold, the level of the first erase voltage remains unchanged after the level of the neutralization voltage reaches a breakdown voltage level of a bipolar junction of the control gate switching circuit. In an embodiment, when the value of the wear indication is greater than the wear threshold, the level of the first erase voltage remains unchanged, the level being equal to a tolerance margin taken for a breakdown voltage level of a bipolar junction of the control gate switching circuit.

In an embodiment, a non-volatile memory integrated circuit includes: memory cells housed in the semiconductor well, each memory cell including a state transistor having a floating gate and a control gate; and control circuitry that, in operation, controls reading, writing and erasing of the memory cells, wherein erasing comprises biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switching circuit of the non-volatile memory, the absolute value of the first erase voltage being based on a comparison of a value of the wear indication of the memory cells to a wear threshold. In an embodiment, the absolute value of the erase voltage is increased in response to a comparison indicating that the value of the wear indication is greater than the wear threshold. In an embodiment, the control circuitry is operable to bias the control gate of the selected memory cell with the second erase voltage using the control gate switch circuit. In an embodiment, the integrated circuit includes peripheral circuitry and a buffer transistor housed in the buffer semiconductor well, wherein the memory cell is coupled to the peripheral circuitry through a conductive terminal of the buffer transistor, and the control circuitry is operable to bias the buffer semiconductor well and a gate of the buffer transistor with a buffer isolation voltage to isolate the peripheral circuitry from the first erase voltage. In an embodiment, in operation, when the value of the wear indication is greater than the wear threshold, the control circuit generates a buffer isolation voltage at least equal to a difference between a level of the first erase voltage and a breakdown voltage level of a bipolar junction of the control gate switching circuit. In an embodiment, the semiconductor well housing the memory cell is surrounded by a semiconductor isolation region in a triple-well type structure, the buffer semiconductor well is surrounded by the semiconductor isolation region, and the control circuit biases the semiconductor isolation region with the first erase voltage in operation. In an embodiment, the control circuit biases the control gates of the unselected memory cells with a neutralization voltage via the control gate switch circuit during an erase cycle. In an embodiment, during the erase cycle, the control circuitry sets the level of the neutralization voltage in absolute value to an initial deviation that is kept constant with respect to the level of the first erase voltage when the value indicative of wear is smaller than the wear threshold. In an embodiment, during the erase period, when the value indicative of wear is greater than the wear threshold, the control circuit is operative to shift the level of the neutralization voltage to an offset neutralization voltage level and increase the level of the offset neutralization voltage in absolute value so as to keep the offset constant relative to the level of the first erase voltage. In an embodiment, the control circuit means maintains the level of the first erase voltage unchanged when the level of the neutralization voltage reaches a breakdown level of a bipolar junction of the control gate switching circuit when the value indicative of the wear is greater than the wear threshold value. In an embodiment, when the value indicative of wear is greater than the wear threshold, the control circuitry maintains the level of the first erase voltage unchanged when the level of the first erase voltage is equal to a tolerance margin taken for a breakdown level of a bipolar junction of the control gate switching circuit.

In an embodiment, a system comprises: one or more processing cores; and a non-volatile memory coupled to the one or more processing cores, the non-volatile memory comprising: memory cells housed in the semiconductor well, each memory cell including a state transistor having a floating gate and a control gate; and control circuitry that, in operation, controls reading, writing and erasing of the memory cells, wherein erasing comprises biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switching circuit of the non-volatile memory, the absolute value of the first erase voltage being based on a comparison of a value of the wear indication of the memory cells to a wear threshold. In an embodiment, the system includes an integrated circuit that includes a non-volatile memory. In an embodiment, an integrated circuit includes one or more processing cores. In an embodiment, the absolute value of the first erase voltage is increased in response to a comparison indicating that the value of the wear indication is greater than the wear threshold.

Drawings

Other advantages and features of the present disclosure will become apparent upon review of the detailed description of non-limiting embodiments and implementations and from the accompanying drawings in which:

fig. 1 shows a cross-sectional view of one example of a memory cell of an integrated circuit of a non-volatile memory NVM of an embodiment.

Fig. 2 shows an exemplary embodiment implementing an erase cycle of the memory NVM described with reference to fig. 1.

Fig. 3 shows an example of an embodiment of a control gate switching circuit GCSW for transferring a negative erase voltage-VNN or a positive sum voltage + VPP in a control gate line of a memory cell.

Fig. 4 and 5 show two exemplary embodiments of implementing the writing method in the memory NVM described with reference to fig. 1 to 3.

Fig. 6 illustrates an exemplary embodiment of a memory.

Detailed Description

Fig. 1 shows a cross-sectional view of one example of a memory cell of an integrated circuit of a non-volatile memory NVM. The integrated circuit shown further comprises control circuitry means 102 which control the writing, reading and erasing of the memory cells of the non-volatile memory NVM. In some embodiments, separate circuitry may be employed to control the reading, writing, and erasing of the memory cells. The non-volatile memory may be included in a system that includes one or more processing cores that may, for example, be coupled to the non-volatile memory and that may store data in and retrieve data from the non-volatile memory.

The memory cell comprises a state transistor TE (TEsel or TEnsel, depending on whether the state transistor TE is selected or unselected) and an access transistor TA coupled in series.

The memory cell is housed in and above a semiconductor well PW1, typically P-type doped.

Well PW1 houses memory cells in a memory array PM (see fig. 6), which is typically arranged in an array of rows and columns.

The state transistor TE (TEsel, TEnsel) comprises a floating gate FG and a control gate CG, the floating gate FG being electrically isolated from the well PW1 by a so-called "tunnel" dielectric layer and from the control gate CG by a so-called "gate" dielectric layer.

In this example, the access transistor TA is a buried vertically oriented gate transistor and is shared by two state transistors TE (TEsel, TEnsel) on both sides of the vertical gate. The vertical gates fill the vertically etched trenches in well PW1, with the sides and bottom of the trenches covered in a gate dielectric layer.

The vertical gate of the access transistor TA also forms a word line WL extending in a direction perpendicular to the plane in fig. 1, which word line WL is common to a row of memory cells, for example.

The buried semiconductor region NISO allows, on the one hand, the well PW1 accommodating the memory cell to be electrically isolated from the semiconductor substrate PSUB and, on the other hand, the formation of the source region of the access transistor TA.

According to a so-called "triple-well" isolation well structure, well PW1, which houses the memory cell, is effectively isolated from the semiconductor substrate PSUB by the buried semiconductor region NISO and by an isolation well of the N-doping type which laterally surrounds well PW 1. This allows well PW1 to be biased with a positive potential in particular.

The drain D of access transistor TA is located at the surface of well PW1 and at the same time forms the source region of the corresponding state transistor TEsel. The drain regions of the state transistors Tesel, TEnsel are coupled via contacts to bit lines BL in the first stage of the interconnect portion of the integrated circuit.

In order to record data in the memory, the write circuitry is configured to logically select memory cells to be written, memory cells not to be written being referred to as unselected.

The erase circuitry is configured to collectively erase memory cells belonging to at least one selected page during an erase cycle. A page of memory is a group of memory cells, typically an entire row of memory cells, in a matrix organization of the memory array.

The programming circuit is configured to selectively program the memory cells during an erase cycle. For example, the program cycle includes commonly biasing the control gate lines CGLsel with a first program voltage and selectively biasing the bit lines BL with a second program voltage according to data to be stored.

Reference is now made to fig. 2.

Fig. 2 shows an example of an erase cycle for implementing the memory NVM described above with reference to fig. 1.

During an erase cycle, erase circuitry is configured to bias semiconductor well PW1 with a first erase voltage VYP and to bias selected control gate line CGLsel with a second erase voltage-VNN.

The remainder of the description below will consider the common convention in which the first erase voltage VYP is positive and the second erase voltage VNN is negative. The first erase voltage VYP may thus be represented as a "positive erase voltage" and the second erase voltage VNN may thus be represented as a "negative erase voltage.

That is, by considering the increase in the absolute value of the negative voltage, the embodiments and implementations described below may be applied to voltages of opposite sign, and in particular in wells that accommodate memory cells of opposite conductivity (N-type).

The positive erase voltage VYP and the negative erase voltage-VNN are configured with respect to each other to generate a charge "e" that is transferred from the floating gate of the state transistor TESel of the selected memory cell to the well PW1, typically by the Fowler-Nordheim effect.

Furthermore, during the erase period, the erase circuitry is configured to bias the unselected control gate lines CGLnsel with a neutralization voltage + VPP (positive in this example).

The neutralization (neutralization) voltage + VPP neutralizes the pseudo-erase phenomenon in the unselected state transistor TEnsel, which may be caused by the positive erase voltage VYP applied in the well PW1 that also accommodates unselected memory cells. For example, the neutralization voltage + VPP may be initially selected to be equal to the positive erase voltage VYP.

Further, the bit line BL is held at the floating potential HZ; biasing the vertical gate of access transistor TA with approximately 5V or 7V (volts) to limit the stress on the gate oxide of access transistor TA caused by the positive erase voltage VYP in well PW 1; and the buried semiconductor isolation region NISO is biased with a positive erase voltage VYP.

The erase cycle thus comprises in particular biasing the selected control gate lines CGLsel with a negative erase voltage-VNN and biasing the unselected control gate lines CGLnsel with a positive sum voltage + VPP.

Reference is now made to fig. 3.

Fig. 3 shows an example of a control gate switch circuit GCSW for transferring a negative erase voltage-VNN or a positive sum voltage + VPP in the control gate lines CGLi, CGLi +1, CGLi +2, …, CLGi + k of the memory cells.

The control gate switch CGSW selectively transmits either a negative erase voltage-VNN or a positive sum voltage + VPP, depending on whether the memory cells of the page are selected or unselected. In this respect, the control gate switch CGSW decodes the selection control signal through an inverter type circuit using complementary high voltage metal oxide semiconductor HVMOS technology, which is well known to those skilled in the art.

Accordingly, the PMOS transistor of the inverter INVP is formed in the common N-type semiconductor well CMNPW, and the NMOS transistor of the inverter INVN is formed in the common P-type semiconductor well CMNPW. In addition, the PMOS and NMOS transistors of the cascode CASP, CASCN may be disposed on the CGLi-CGLi + k output of the inverter and formed in the isolated wells SGLNW, SGLPW.

Therefore, in the control gate switching circuit CGSW, the maximum value of the potential difference (HVmax, fig. 4 and 5) between the positive and negative voltages + VPP and the negative erase voltage-VNN is limited by the characteristics of the HVMOS transistors (INVP, INVN, CASCP, CASCN). In particular, the bipolar junction between a conductive region (in particular, the drain region, since the well is usually biased by the potential of the source region) of an HVMOS transistor and the corresponding well is usually limited by its breakdown level (HVmax), for example about 11V.

Therefore, in order to enhance the erase stimulus, the voltage condition of the erase cycle, the level of the voltages VPP, VNN in absolute value cannot be increased via the control gate switching circuit CGSW.

However, as the memory cell ages, the erase cycle is less efficient at the same erase voltage than at the beginning of the life of the memory NVM.

This aging phenomenon is typically caused by degradation of the floating gate oxide that has been subjected to a large number of erase cycles (e.g., approximately 500,000 cycles).

In this regard, the erase circuitry is configured to increase the level of the positive erase voltage VYP as the memory cells age.

For example, the write circuitry or the erase circuitry is configured to evaluate a wear value (AG) indicative of an aging of the memory cell by reading "in margin mode" in the memory cell after each application of an erase stimulus. Reading in margin mode is a reading that measures the threshold of the floating gate transistor TEsel in a quantitative manner. In this case, the write circuitry may be configured to implement a repetition of the iterative erase cycle in a closed loop until the correct erase state is obtained.

Alternatively, the write or erase circuitry may evaluate the wear value (AG, fig. 4 and 5) representing the aging of the memory cells from a record of the last value of the erase voltages VYP, VNN. More specifically, the write or erase circuitry may be automated to periodically measure the erase state "in margin mode" and increase the value of the erase voltages VYP, VNN as necessary. The new erase voltage values VYP, VNN are recorded and can be used as a reference to evaluate the wear value AG during the next erase cycle.

Thus, the level of the positive erase voltage VYP may increase according to the evolution of the wear value (AG).

Since positive erase voltage VYP biases well PW1 and is not transmitted via control gate switch circuit CGSW, this positive erase voltage is not directly limited by the breakdown level (HVmax) of the bipolar junction of circuit CGSW.

Accordingly, the level of the positive erase voltage VYP may be greater than the breakdown level (HVmax) of the control gate switch CGSW. The voltage condition of the write cycle is allowed to be enhanced when the aging of the memory cell is such that the maximum levels of the positive Voltage (VPP) and the negative Voltage (VNN) of the control gate switch circuit CGSW are reached and no longer sufficient to produce an erase state that can be strictly distinguished from a programmed state.

In this regard, reference is made to fig. 4 and 5.

Fig. 4 and 5 show two examples of implementing the writing method in the memory NVM described above with reference to fig. 1 to 3.

Fig. 4 and 5 show the evolution of the level of the positive voltage achieved during the erase cycle, including the positive erase voltage VYP applied in the well PW1 and the neutralization voltage VPP applied in the control gate CG of the unselected state transistor TEnsel.

In both examples, the method includes increasing the level of the positive erase voltage VYP due to an increase in the wear value AG that represents the aging of the memory cell. As a result, the magnitude of the erase stimulus is increased to limit the drift of the threshold of the aging memory cell, allowing the overall endurance of the memory to be increased.

For example, the increase in the level of the positive erase voltage VYP is due to an increase in the wear value AG because they are proportional. The increase in the level of the positive erase voltage VYP may also be broken down into several steps whose levels increase proportionally with the increase in the wear value AG.

It should be kept in mind that the wear value AG may be obtained directly or by reading erased memory cells in margin mode.

The neutralization voltage VPP is configured with respect to the positive erase voltage VYP to neutralize the pseudo-erase phenomenon of the unselected memory cells TEnsel.

The neutralization voltage may be selected so that it is at or near the positive erase voltage VYP.

Thus, the method includes increasing the level of the neutralization voltage VPP that is generated due to an increase in the level of the positive erase voltage VYP.

Although the neutralization voltage VPP and the positive erase voltage VYP are initially different, the neutralization voltage VPP is increased to keep the initial difference constant.

The neutralization voltage VPP is limited by the breakdown level of the control gate switch CGSW because it is transmitted on the control gate line of the unselected memory cell tens.

Therefore, in the example of fig. 4, when the neutralization voltage VPP is increased until the maximum level HVmax of the control gate switching circuit CGSW is reached, the neutralization voltage VPP is set to the maximum level HVmax and is not increased according to the wear value AG of the memory cell any more.

It goes without saying that the term maximum level is understood to mean a safety margin taken for the breakdown level of the bipolar junction of the control gate switch circuit CGSW.

The threshold AGplf of the wear value AG is defined as a wear value (which will be referred to as "wear threshold AGplf" hereinafter) at which the positive erase voltage VYP and the neutralization voltage VPP reach the maximum level HVmax.

Beyond the wear threshold AGplf, the level of the neutralization voltage VPP no longer increases, but the level of the positive erase voltage VYP still increases to a level exceeding the maximum level HVmax and to a level exceeding the breakdown level of the bipolar junction of the control gate switch circuit CGSW.

In the same manner as being below wear threshold AGplf, increasing positive erase voltage VYP further results in an increase in wear value AG in proportion to, and optionally in steps with, an increase in wear value AG.

Thus, above wear threshold AGplf, the deviation between positive erase voltage VYP and neutralization voltage VPP increases as the wear AG of the memory cell increases. This produces a pseudo-erase phenomenon that gradually increases from the wear threshold AGplf.

There are methods for compensating this type of artifact, such as refresh algorithms.

When the level of the positive erase voltage VYP is greater than the tolerance margin with respect to the breakdown level HVmax of the control gate switch CGSW, the level is no longer increased.

For example, the tolerance margin is chosen to be specifically 2V in order to limit the pseudo-erasure phenomenon and to be able to easily compensate for it using a "refresh" type method.

In the example shown in fig. 5, above the wear threshold AGplf, the method comprises, on the one hand, shifting the level of the Δ D neutralization voltage VPP, resulting in a shifted neutralization voltage DVPP, and, on the other hand, increasing the level of the shifted neutralization voltage DVPP, while keeping the shift Δ D (between the level of the shifted neutralization voltage DVPP and the level of the positive erase voltage VYP) constant.

The level of the positive erase voltage VYP continues to increase as the wear value AG increases.

Thus, as a result of the offset Δ D, the neutralization voltage VPP may also continue to follow the evolution of the positive erase voltage VYP without exceeding the maximum level HVmax.

Further, when the neutralization voltage VPP reaches the level of the breakdown voltage HVmax of the control gate switch CGSW closest to the safety margin, the positive erase voltage VYP is not increased any more.

Maintaining the offset Δ D constant when increasing the positive erase voltage VYP facilitates the adjustment of the positive voltages VYP, VPP generated and also allows for easy control of the compensation of the pseudo-erase phenomenon generated by this constant difference.

For example, the offset Δ D is set to about 2V in order to limit the pseudo-erase phenomenon and to be able to easily compensate the pseudo-erase phenomenon using the "refresh" type method.

For example, if the positive voltages VYP, VPP are equal before the wear threshold AGplf is reached, a positive erase voltage VYP and a positive sum voltage VPP are produced on the same output of the charge pump circuit (not shown). After reaching the wear threshold AGplf, additional charge pump stages may be coupled in parallel to provide a positive erase voltage VYP through a separate output that is then greater than the positive sum voltage VPP. Maintaining the deviation Δ V between the positive erase voltage VYP and the positive sum voltage DVPP constant advantageously allows for the regulation of the positive voltages VYP, DVPP to be pooled at least across the charge pump stage common to their generation.

Thus, in both examples described above with reference to fig. 4 and 5, the method includes increasing the level of the positive erase voltage VYP to exceed the breakdown voltage HVmax in order to continue to increase the magnitude of the erase stimulus to limit the drift of the threshold of the aged memory cells, thereby allowing the overall endurance of the memory to increase, well beyond the wear threshold AGplf.

Fig. 6 shows an advantageous exemplary embodiment of the memory NVM described above with reference to fig. 1 to 5 in a comprehensive and top view. As shown in fig. 6, the control circuit arrangement comprises, inter alia, a distribution circuit NISOVGEN.

Well PW1 houses memory cells in storage array PM that are typically arranged in an array of rows and columns. Specifically, the control gate lines CGLi-CGLi + k other than the word lines WL extend row by row in the memory array, and the bit lines BL and the control gate decode lines sent to the control gate switching circuit CGSW extend column by column in the memory array PM.

The well PW1 accommodates the transistor T1 of the column decoder COLPASS in addition to the transistor T2 of the ground CLAMP of the bit line BL.

The semiconductor well PW1, which houses the memory cell, is isolated from the rest of the circuit by a "triple well" type structure, in which a semiconductor isolation region NISO surrounds the well PW 1.

The semiconductor isolation region NISO has a conductivity opposite to that of the well PW1 housing the memory array and is biased with the same voltage as the well PW1 it surrounds.

Isolation results from the bipolar junctions between well PW1 and isolation region NISO and between isolation region NISO and the semiconductor substrate being opposite to each other.

The bias lines of the isolation regions NISOVL allow a bias to be obtained in the isolation regions NISO and in the well PW1 that houses the memory cell.

The distribution circuit NISOVGEN is configured to deliver a bias voltage that can specifically have the level of the positive erase voltage VYP during the erase period. For example, the distribution circuit NISOVGEN comprises a boost latch circuit. The boost latch circuit is configured to actuate a latch (e.g., of the type with two head-to-tail inverters, the output of one inverter cycling to the input of the other) to provide a high output voltage level; and then increases the low reference voltage to positively bias the output to the level of the positive erase voltage VYP.

Outside the erase period, the bias line of the isolation region NISOVL is brought to the ground reference potential GND, in particular through the reset transistor RSTGND as described below.

The conductive terminal of the transistor T2 of the grounding means CLAMP of the bit line BL is coupled on the one hand to the bit line BL of the memory array PM and on the other hand to the bias line of the isolation region NISOVL. The transistor T2 of the grounding means CLAMP is used to carry the unused bit line BL at the ground potential GND present on the bias line of the isolation region NISOVL or at the high impedance HZ in order to bring the bit line BL to a floating potential.

The conductive terminal of transistor T1 of column decoder COLPASS is coupled to the bit line BL of memory array PM on the one hand and to the devices of peripheral circuits PRPH on the other hand.

The peripheral circuits PRPH of the memory NVM comprise in particular a programming and direct memory access circuit PRGDMA and a read-out circuit RDAMP.

The programming and direct memory access circuit PRGDMA is used specifically during the programming cycle to selectively bias the decoded bit lines BL. The sense circuit RDAMP is configured to detect a voltage or current change on the bit line BL representing the state of the memory cell, the state transistor of which is also controlled at the read voltage. The sense circuit RDAMP is capable of reading the memory cells in the margin mode.

The devices of the peripheral circuit PRPH are generally not able to support voltages exceeding the maximum level HVmax described above with particular reference to fig. 4 and 5.

However, in the bit line BL, which is kept at a floating potential during the erase period, the potential may be raised to the level of the positive erase voltage VYP closest to the bipolar junction threshold. As a result, the voltage present in the bit line BL during the erase period may rise to a level exceeding the breakdown level of the peripheral circuit PRPH.

Therefore, a buffer semiconductor well PW2 housing buffer transistors TBF1, TBF2, TBF3 of the same conductivity type as the well PW1 of the memory array PM is advantageously provided.

The buffer transistors TBF1, TBF2 are configured to protect the peripheral circuit PRPH from possible high level values of the positive erase voltage VYP on the bit line BL.

More specifically, in one aspect, the bit line BL is coupled to the peripheral circuit PRPH through the conductive terminals of the buffer transistors TBF1, TBF2, TBF 3. In particular, the elements PRGDMA, RDAMP of the peripheral circuit PRPH are coupled to the sources of the buffer transistors TBF1, TBF2, while the bit line BL is coupled to the drains of the buffer transistors TBF1, TBF 2.

On the other hand, the gates of buffer well PW2 and buffer transistors TBF1-TBF3 are biased with a buffer isolation voltage VGNDLFT, e.g., generated by a buffer isolation control circuit.

The source of one of the buffer transistors (referred to as buffer control transistor TBF3) is coupled to the bias line LPW2 of the buffer well PW 2. Thus, the bias of buffer well PW2 is controlled by the gate voltage VGNFLFT of buffer control transistor TBF 3.

Further, a reset transistor RSTGND is provided in the peripheral circuit PRPH to re-bias the bias lines of the buffer well PW2 and the isolation region NISOVL with the ground reference potential GND outside the write period. The reset transistor RSTGND is blocked during the write cycle.

The buffer isolation voltage VGNDLFT is for example at least equal to the difference between the level of the positive erase voltage VYP and the breakdown level HVmax of the control gate switch CGSW.

Thus, assuming that the gates of buffer transistors TBF1-TBF3 are biased with the buffer isolation voltage VGNDLFT, the peripheral circuit PRPH is protected from the positive erase voltage VYP (closest to the bipolar junction threshold voltage) present on bitline BL during the erase cycle.

More specifically, assuming that the buffer transistors TBF1, TBF2, TBF3 are controlled at their gates with the buffer isolation voltage VGNDLFT, their sources cannot be biased above this buffer isolation voltage VGNDLFT.

Furthermore, whereas buffer semiconductor well PW2 is also biased with buffer isolation voltage VGNDLFT, the buffer transistor will not be damaged by the positive erase voltage VYP of bitline BL due to the above-specified selection of the level of buffer isolation voltage VGNDLFT.

Furthermore, the buffer isolation voltage VGNDLFT may advantageously be derived from the distribution circuit NISOVGEN of the positive erase voltage VYP.

More specifically, to distribute the positive erase voltage VYP (recall that it may be greater than the breakdown voltage of the bipolar junction of the circuit), the distribution circuit NISOVGEN is configured, for example, to activate a latch circuit to provide a high output voltage level initially equal to VPP-HVmax.

The distribution circuit NISOVGEN then increases the low reference voltage GND of the latch by the voltage VGNDLFT in order to shift the output (initially equal to VPP) forward by VGNDLFT until reaching the level VPP + VGNDLFT VYP of the positive erase voltage VYP without breaking down the junctions of the transistors of the latch.

In other words, according to one exemplary embodiment and implementation, upon exceeding the wear threshold AGplf, the increase in the level of the positive erase voltage VYP may include shifting VGNDLFT by the low reference voltage GND, whose output has been latched at the high reference voltage VPP, in the boost latch NISOVGEN, so as to shift the level of the output to a level of the positive erase voltage VYP that is greater than the breakdown level HVmax of the bipolar junction of the control gate switch circuit CGSW.

Furthermore, both the semiconductor well PW1 containing the memory cell and the buffer semiconductor well PW2 are isolated from the rest of the circuit by a "triple well" type structure, advantageously using the same semiconductor isolation region NISO to surround both wells PW1, PW 2.

Isolation is achieved by two reverse bipolar junctions, represented by diodes D1 and D2 coupled in series with opposite polarities.

Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer-readable medium is provided, comprising a computer program adapted to perform one or more of the above-described methods or functions. The medium may be a physical storage medium, for example a read-only memory (ROM) chip, or a magnetic disk, such as a digital versatile disk (DVD-ROM), a compact disk (CD-ROM), a hard disk, a memory, a network, or a portable media product to be read by an appropriate drive or via an appropriate connection, including one or more bar codes or other associated codes encoded as stored on one or more such computer-readable media and read by an appropriate reader device.

Moreover, in some embodiments, some or all of these methods and/or functionality can be implemented or provided in other ways, such as at least partially in firmware and/or hardware, including but not limited to one or more Application Specific Integrated Circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions and including microcontrollers and/or embedded controllers), Field Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), and the like, as well as devices employing RFID technology, as well as different combinations thereof.

The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.