阅读说明：本技术 半导体装置及读出方法 (Semiconductor device and readout method ) 是由 冈部翔 妹尾真言 于 2020-07-17 设计创作，主要内容包括：本发明提供一种实现数据输出的高速化并且对锁存电路的重置进行补偿的半导体装置及读出方法。本发明的NAND型闪速存储器的读出方法包括：预充电步骤,经由读出节点(SNS)对位线及连接于所述位线的NAND串进行预充电；重置步骤,在预充电后对锁存电路进行重置；以及放电步骤,在重置后对NAND串进行放电。(The invention provides a semiconductor device and a reading method for realizing high-speed data output and compensating reset of a latch circuit. The reading method of the NAND flash memory of the present invention comprises: a precharge step of precharging a bit line and a NAND string connected to the bit line through a Sense Node (SNS); a reset step of resetting the latch circuit after the precharge; and a discharging step of discharging the NAND string after the reset.)

1. A reading method of a nand flash memory, comprising:

a precharge step of precharging a bit line and a NAND string connected to the bit line via a sense node;

a reset step of electrically connecting a node of the latch circuit to a reference potential via the sense node after the precharge, and resetting the latch circuit; and

and a discharging step of discharging the NAND string after the reset.

2. A reading method of a nand flash memory, comprising:

a precharge step of precharging a bit line and a NAND string connected to the bit line via a sense node; and

a reset step of electrically connecting a node of the latch circuit to a reference potential via the sense node during a discharge period of the nand string, and resetting the latch circuit.

3. The readout method according to claim 2, wherein

The pre-charging step includes: generating a precharge voltage at a voltage supply node; electrically connecting the voltage supply node to the sense node via a first select transistor; the sense node is electrically connected to a bit line via a second select transistor,

the resetting step includes: generating the reference voltage at the voltage supply node; electrically connecting the voltage supply node to the latch circuit via the first select transistor; the sense node is electrically isolated via a second transistor.

4. A readout method according to claim 2 or 3, wherein

The steps are performed in successive reads of pages.

5. The readout method according to claim 4, wherein

The successive readout of the pages comprises:

holding data read from a selected page of a memory cell array in the latch circuit, transferring the data held in the latch circuit to another latch circuit, and then holding data read from the next selected page in the latch circuit;

the data held by the other latch circuits is continuously output to the outside in synchronization with an external clock signal.

6. The readout method according to claim 5, wherein

The continuous reading of the page further includes outputting a second part of the data subjected to the error detection and correction process to the outside while performing the error detection and correction process, that is, the error detection and correction process on the data of the first part of the other latch circuits, and performing the error detection and correction process on the data of the second part while outputting the first part of the data subjected to the error detection and correction process to the outside.

7. The readout method of claim 6, comprising:

transferring data of a next selected page of the first portion of the latch circuit to the first portion of the other latch circuit after outputting the error detection correction-processed data of the first portion of the other latch circuit to the outside;

after outputting the error detection correction-processed data of the second portion of the other latch circuit to the outside, transferring data of a next selected page of the second portion of the latch circuit to the second portion of the other latch circuit.

8. The readout method according to claim 6 or 7, wherein

The continuous readout is a first continuous readout with a restriction represented by tARRAY + tcac < tDOUT, where the data of the first portion and the second portion are data of 1/2 pages, respectively, tARRAY is a time required to read out a selected page, tcac is a time required to perform error detection correction processing for 1/2 pages, and tDOUT is a time required to output all data of one page.

9. The readout method according to claim 6 or 7, wherein

The continuous readout is a second continuous readout with a restriction represented by tARRAY < tDOUT, tcarc < tDOUT (page 1/2), where the data of the first portion and the second portion are data of 1/2 pages, respectively, tARRAY is a time required to read out a selected page, tcac is a time required to perform error detection correction processing on 1/2 pages, tDOUT is a time required to output all data of one page, tDOUT (page 1/2) is a time required to output data of 1/2 pages.

10. The readout method according to claim 9, wherein

The second sequential readout is earlier in readout timing of the selected page of the memory cell array than the first sequential readout.

11. A semiconductor device, comprising:

a NAND type memory cell array;

a reading section that reads out data from a selected page of the memory cell array; and

an output section that outputs the data read out by the readout section to the outside,

the sensing part includes a page buffer/sensing circuit connected to the memory cell array via bit lines,

the read unit resets a latch circuit included in the page buffer/read circuit between a precharge period of the bit line and a discharge period of the NAND string when performing continuous reading of the page.

12. A semiconductor device, comprising:

a NAND type memory cell array;

a reading section that reads out data from a selected page of the memory cell array; and

an output section that outputs the data read out by the readout section to the outside,

the sensing part includes a page buffer/sensing circuit connected to the memory cell array via bit lines,

the read means resets a latch circuit included in the page buffer/read circuit in a discharge period of the nand string after precharging the bit lines when performing continuous reading of the page.

13. The semiconductor device according to claim 12, wherein

The page buffer/readout circuit includes: a voltage supply node, a sense node, a latch circuit, a first select transistor connected between the voltage supply node and the sense node, a second select transistor connected between the sense node and a bit line, and a third select transistor connected between the sense node and the latch circuit, and

the first selection transistor and the third selection transistor are turned on, the second selection transistor is turned off, and the latch circuit is electrically connected to the reference potential of the voltage supply node to reset the latch circuit.

14. The semiconductor device according to claim 13, wherein

The readout unit turns on the first selection transistor and the second selection transistor, turns off the third selection transistor, and precharges the voltage of the voltage supply node to a bit line.

15. The semiconductor device according to claim 12, wherein

The output section continuously outputs the read data in synchronization with an external clock signal when the read section continuously reads pages.

16. The semiconductor device according to claim 12, wherein

The page buffer/readout circuit further includes other latch circuits that receive the data held by the latch circuits,

the read means holds data read from a next selected page of the memory cell array in the latch circuit while outputting data of the other latch circuit in continuous reading.

17. The semiconductor device according to claim 16, wherein

The semiconductor apparatus further includes an error detection correction circuit that performs error detection and correction of data,

the readout means outputs the data held in the second portion of the other latch circuit after the error detection and correction processing is performed on the data held in the first portion of the other latch circuit by the error detection and correction circuit when the readout means performs continuous readout.

Technical Field

The present invention relates to a semiconductor device including a flash memory or the like and a reading method, and more particularly to a continuous page reading operation.

Background

A NAND (NAND) flash memory is equipped with a continuous read function (burst read function) for continuously reading a plurality of pages in response to an external command. The page buffer/readout circuit includes, for example, two latches, and can output data held in one latch while data read out from the array is held in the other latch in a continuous readout operation (for example, patent document 1, patent document 2, and patent document 3).

[ Prior art documents ]

[ patent document ]

[ patent document 1] Japanese patent No. 5323170 publication

[ patent document 2] Japanese patent No. 5667143 publication

[ patent document 3] U.S. patent application US2014/0104947A1

Disclosure of Invention

[ problems to be solved by the invention ]

Fig. 1 shows a schematic configuration of a NAND flash memory having an on-chip (on-chip) Error detection and Correction (ECC) function. The flash memory includes: a memory cell array (memory cell array)10 including NAND strings (strings), a page buffer/readout circuit 20, a data transfer circuit 30, a data transfer circuit 32, an error detection correction circuit (hereinafter, referred to as an ECC circuit) 40, and an input-output circuit 50. The page buffer/readout circuit 20 includes two latches (latch) L1, L2 (one latch, e.g., 4KB) that hold readout data or input data that should be programmed, latch L1, latch L2 respectively include a first cache (cache) C0 and a second cache C1 (one cache, e.g., 2 KB).

Fig. 2 shows a timing chart when continuous reading of a plurality of pages is performed. Fig. 2 shows an example in which the page P0 is set as the start address. The start address can be arbitrarily selected. First, an array read of page P0 is performed, and data of page P0 is held in the first cache C0 and the second cache C1 of the latch L1 (P0C0, P0C 1). Then, the data in the first cache C0 and the second cache C1 of the latch L1 are transferred to the first cache C0 and the second cache C1 of the latch L2, and the data in the first cache C0 and the second cache C1 are ECC decoded by the ECC circuit 40, and when an error is detected, the data in the first cache C0 and the second cache C1 of the latch L2 are corrected.

In the consecutive readout, the row address counter is automatically incremented, and the readout of the next page P1 is performed, and the readout data is transferred to the first cache C0 and the second cache C1 of the latch L1. During this time, the data of the first cache C0 of the latch L2 is transferred to the input-output circuit 50, and the data held by the input-output circuit 50 is output in synchronization with the external clock signal ExCLK supplied from the outside. Then, the data of the second cache C1 of the latch L2 is output from the input-output circuit 50 in synchronization with the external clock signal ExCLK, during which the data of the first cache C0 of the latch L1 is transferred to the latch L2, and the ECC processing is performed by the ECC circuit 40.

While the data of the second cache C1 of the latch L1 is transferred to the latch L2 and the data of the first cache C0 of the latch L2 is output from the input-output circuit 50, the data of the second cache C1 of the latch L2 is ECC-processed, and then, while the data of the second cache C1 of the latch L2 is output from the input-output circuit 50, the next page P2 is read out from the array, transferred to the first cache C0 and the second cache C1 of the latch L1, and the data of the first cache C0 is transferred to the latch L2 for ECC processing.

In this manner, the data is output from the latch L2 while the pages of the memory cell array are continuously read, and in this period, the ECC processing of the second cache C1 is performed while the data of the first cache C0 is output, and the ECC processing of the first cache C0 is performed while the data of the second cache C1 is output.

Here, the readout of the array operates using an internal clock signal according to the determined timing, and on the other hand, the data output operates according to an external clock signal ExCLK that is not synchronized with the internal clock signal. Therefore, in the continuous read operation, there is a limitation as expressed by the following equation (1).

tARRAY+tECC＜tDOUT…(1)

Here, tARRAY is the time required to read a selected page from the memory cell array, tdec is the time required to perform ECC processing on 1/2 pages, and tDOUT is the time required to output all data of 1 page. tARRAY and maximum tcac (maximum time required for operation of ECC decoding and correction of data) are fixed times, and tDOUT is calculated from the frequency of the external clock signal ExCLK.

In order to read a large amount of data in a short time, the frequency of the external clock signal ExCLK needs to be increased. In this case, as shown in equation (1), the time of tARRAY + tECC needs to be shortened. On the other hand, in a sensing operation, latch L1 needs to be reset to more accurately receive charge from the sense node, the reset being performed prior to the precharge period of the bit line. In the continuous readout operation, the reset of latch L1 must be after the data of latch L1 is transferred to latch L2. That is, the reset of latch L1 must be performed after the data of latch L1 is transferred to latch L2, before the precharge period for reading out the bit line of the next page. Therefore, if the start timing of tARRAY is to be advanced, there is a possibility that a sufficient time for resetting latch L1 cannot be secured. As illustrated in fig. 2, when ts is the time to transfer data of the second cache C1 of the page P2 of the latch L1 to the latch L2 and tp is the period from the start timing of array reading of the page P3 to the completion of precharging of the bit lines, it is necessary to reset the latch L1 in the period tx. If the read start timing of the next page is advanced, the period tx is further shortened, and there is a possibility that the reset of the latch L1 cannot be compensated for.

An object of the present invention is to solve the above-described conventional problems and to provide a semiconductor device and a reading method for compensating for resetting of a latch circuit while achieving high-speed data output.

[ means for solving problems ]

The reading method of the NAND flash memory of the present invention comprises: a precharge step of precharging a bit line and a NAND string connected to the bit line via a sense node; a reset step of electrically connecting a node of the latch circuit to a reference potential via the sense node after the precharge, and resetting the latch circuit; and a discharging step of discharging the NAND string after the reset. Further, a method for reading out a NAND-type flash memory according to the present invention includes: a precharge step of precharging a bit line and a NAND string connected to the bit line via a sense node; and a reset step of electrically connecting a node of the latch circuit to a reference potential via the sense node during a discharge period of the NAND string, and resetting the latch circuit.

In one embodiment of the present invention, the precharging step includes: generating a precharge voltage at a voltage supply node; electrically connecting the voltage supply node to the sense node via a first select transistor; electrically connecting the sense node to a bit line via a second select transistor, the resetting step comprising: generating the reference voltage at the voltage supply node; electrically connecting the voltage supply node to the latch circuit via the first select transistor; electrically isolating the sense node via the second transistor.

In one embodiment of the present invention, the steps are performed in continuous reading of pages. In one embodiment of the present invention, the continuous reading of the pages comprises: holding data read from a selected page of a memory cell array in the latch circuit, transferring the data held in the latch circuit to another latch circuit, and then holding data read from the next selected page in the latch circuit; the data held by the other latch circuits is continuously output to the outside in synchronization with an external clock signal. In one embodiment of the present invention, the continuously reading out the page further includes outputting a second portion of the data subjected to the ECC processing to the outside while performing error detection and correction (ECC processing) on the data of the first portion of the other latch circuit, and performing the ECC processing on the data of the second portion while outputting the first portion of the data subjected to the ECC processing to the outside. In one embodiment of the present invention, the method includes: transferring data of a next selected page of the first portion of the latch circuit to the first portion of the other latch circuit after outputting the ECC-processed data of the first portion of the other latch circuit to the outside; after outputting the ECC-processed data of the second portion of the other latch circuit to the outside, transferring data of a next selected page of the second portion of the latch circuit to the second portion of the other latch circuit. In one embodiment of the present invention, the continuous readout is a first continuous readout having a limitation represented by tARRAY + tdoc < tDOUT (the data of the first part and the second part are data of 1/2 pages, respectively, tARRAY is a time required to read out a selected page, tdec is a time required to perform ECC processing on 1/2 pages, and tDOUT is a time required to output all data of one page). In one embodiment of the present invention, the continuous reading is a second continuous reading having a limit represented by tARRAY < tDOUT and tcarc < tDOUT (page 1/2) (data of the first portion and the second portion are 1/2 pages, tARRAY is time required to read a selected page, tcarc is time required to perform ECC processing on 1/2 pages, tDOUT is time required to output all data of one page, tDOUT (page 1/2) is time required to output data of 1/2 pages). In one embodiment of the present invention, the second sequential reading is performed at an earlier timing for reading the selected page of the memory cell array than the first sequential reading.

The semiconductor device of the present invention includes: a NAND-type memory cell array; a reading section that reads out data from a selected page of the memory cell array; and an output unit that outputs data read by the read unit to the outside, the read unit including a page buffer/read circuit connected to the memory cell array via a bit line, the read unit performing reset of a latch circuit included in the page buffer/read circuit between a precharge period of the bit line and a discharge period of the NAND string when performing continuous read of the page. Further, a semiconductor device of the present invention includes: a NAND-type memory cell array; a reading section that reads out data from a selected page of the memory cell array; and an output unit that outputs data read by the read unit to the outside, the read unit including a page buffer/read circuit connected to the memory cell array via a bit line, the read unit performing reset of a latch circuit included in the page buffer/read circuit in a discharge period of the NAND string after precharging the bit line when performing continuous reading of the page.

In one embodiment of the present invention, the page buffer/readout circuit includes: the latch circuit includes a voltage supply node, a sense node, a latch circuit, a first selection transistor connected between the voltage supply node and the sense node, a second selection transistor connected between the sense node and a bit line, and a third selection transistor connected between the sense node and the latch circuit, wherein the first selection transistor and the third selection transistor are turned on, the second selection transistor is turned off, and the latch circuit is electrically connected to a reference potential of the voltage supply node to reset the latch circuit. In one embodiment of the present invention, the readout unit turns on the first selection transistor and the second selection transistor, turns off the third selection transistor, and precharges the voltage of the voltage supply node to a bit line. In one embodiment of the present invention, when the reading means performs continuous reading of pages, the output means continuously outputs the read data in synchronization with an external clock signal. In one embodiment of the present invention, the page buffer/sense circuit further includes another latch circuit that receives data held by the latch circuit, and the sense unit holds data read from a next selected page of the memory cell array in the latch circuit while outputting data of the other latch circuit in continuous sensing. In one embodiment of the present invention, the semiconductor device further includes an ECC circuit for performing error detection and correction of data, and the readout means outputs ECC-processed data held in the second portion of the other latch circuit while ECC processing is performed on data held in the first portion of the other latch circuit by the ECC circuit in continuous readout.

[ Effect of the invention ]

According to the present invention, since the latch circuit included in the page buffer/sense circuit is reset between the precharge period of the bit line and the discharge period of the NAND string, it is possible to compensate for the reset of the latch circuit while achieving high-speed data output.

Drawings

Fig. 1 is a diagram showing a schematic configuration of a conventional NAND-type flash memory;

fig. 2 is a timing chart when a conventional NAND-type flash memory performs continuous reading of pages;

FIG. 3 is a block diagram showing the configuration of a NAND type flash memory according to an embodiment of the present invention;

FIG. 4 is a diagram showing an example of the structure of the NAND string of the flash memory according to the embodiment of the present invention;

FIG. 5 is a diagram showing the configuration of a bit line selection circuit of a flash memory according to an embodiment of the present invention;

fig. 6 (a) and 6 (B) are diagrams showing the configuration of the page buffer/read circuit of the flash memory according to the embodiment of the present invention;

fig. 7 is a timing diagram showing a reset operation of a latch circuit of a flash memory according to an embodiment of the present invention;

fig. 8 is a timing chart at the time of performing continuous read operation of a page of the embodiment of the present invention.

[ description of symbols ]

10. 110: memory cell array

20. 170: page buffer/readout circuit

30. 32: data transmission circuit

40. 130, 130: ECC circuit

50. 120: input/output circuit

100: flash memory

140: address register

150: controller

160: word line selection circuit

180: column selection circuit

190: internal voltage generating circuit

200: bit line selection circuit

210: decision circuit

Ax: line address information

Ay: column address information

BLCD1, BLCD2, BLCLAMP, BLCN, BLPRE, BLSe, BLSo, CACHE, DTG, EQ, NT1, NT2, PT1, PT2, REG, RESET2, VG, YBLo, YBLe: transistor with a metal gate electrode

BLK (0), BLK (1), …, BLK (m-1): memory block

BLS, SLR1, SLR2, SLS1, SLS2, TOBL: node point

C0: first cache

C1: second cache

DL,/DL: data line

ExCLK: external clock signal

GBLe: even digit line

GBLo: odd bit line

L1, L2: latch device

LAT1,/LAT 1: latch enable signal

MC0, MC1, MC2, …, MC 31: memory cell

NU: NAND string

P0, P1, P2, P3: page

And SA: differential sense amplifier

SGD, SGS: select gate line

SL: shared source line

SNS: read node

t 1-t 7: time of day

tARAY: array read out time

TD: bit line side select transistor

tDOUT: output time

tECC: time to ECC process data

tp: a period from the start timing of array read to the completion of precharge of bit lines

ts: time at which data of the second cache C1 of page P2 of latch L1 was transferred to latch L2

TS: source line side selection transistor

tx: period required for resetting of latch L1

V1, V2: voltage supply node

VCLMP 1: clamping voltage

Vdd: internal supply voltage/supply voltage

Vers: erase voltage

VIRPWR: virtual power supply

Vpass: passing voltage

Vpgm: write voltage/program voltage

Vread: sensing pass voltage

WL0, WL1, WL2, … …, WL 31: word line

Detailed Description

Next, embodiments of the present invention will be described in detail with reference to the drawings. The semiconductor device of the present invention is, for example, a NAND flash memory, or a microprocessor, a microcontroller, a logic, an Application Specific Integrated Circuit (ASIC), a processor that processes an image or sound, a processor that processes a signal such as a radio signal, or the like, which is embedded in the flash memory. In the following description, a NAND-type flash memory is exemplified. In one embodiment, in order to achieve compatibility with a NOR (NOR) type flash memory, the NAND type flash memory is equipped with a Serial Peripheral Interface (SPI) and can continuously read a plurality of pages in synchronization with an external clock signal.

[ examples ]

Fig. 3 is a diagram showing a configuration of a NAND-type flash memory according to an embodiment of the present invention. The flash memory 100 of the present embodiment includes: a memory cell array 110 in which a plurality of memory cells are arranged in a matrix; an input/output circuit 120 connected to an external input/output terminal, responding to an external clock signal ExCLK, and outputting read data to the outside or taking in data input from the outside; an ECC circuit 130 for performing symbol generation of data to be programmed or error detection and correction of data to be read; an address register (address register)140 that receives address data (address data) via the input/output circuit 120; a controller (controller)150 that controls each section based on command data received via the input/output circuit 120 or a control signal applied to a terminal; a word line (word line) selection circuit 160 that receives the row address information Ax from the address register 140, decodes (decodes) the row address information Ax, and selects a block, a word line, or the like based on the decoding result; a page buffer/readout circuit 170 holding data read out from the page selected by the word line selection circuit 160 or holding data to be programmed to the selected page; a column selection circuit 180 that receives the column address information Ay from the address register 140, decodes the column address information Ay, and selects a column in the page buffer/read circuit 170 based on the decoding result; and an internal voltage generation circuit 190 for generating various voltages (a write voltage Vpgm, a pass voltage Vpass, a read pass voltage Vread, an erase voltage Vers, etc.) necessary for reading, programming, erasing, etc. of data.

The memory cell array 110 includes, for example, m memory blocks BLK (0), BLK (1), …, and BLK (m-1) arranged in the column direction. A plurality of NAND strings, in which a plurality of memory cells are connected in series, is formed in one memory block. As shown in fig. 4, one NAND string NU includes a plurality of memory cells MCi (i ═ 0, 1, …, 31), a bit line side selection transistor TD, and a source line side selection transistor TS, which are connected in series. The drain of the bit line side selection transistor TD is connected to a corresponding one of the bit lines GBL, and the source of the source line side selection transistor TS is connected to a common source line SL. The control gates of the memory cells MCi are connected to the word line WLi, and the gates of the bit line side selection transistor TD and the source line side selection transistor TS are connected to the selection gate line SGD and the selection gate line SGS, respectively. The word line selection circuit 160 drives the bit line side selection transistor TD and the source line side selection transistor TS via the selection gate line SGD and the selection gate line SGS based on the row address information Ax to select a block or a word.

The NAND strings may be formed on the substrate surface in two dimensions or three dimensions. The memory Cell may be a Single Level Cell (SLC) type that stores one bit (binary data) or a Multi-Level Cell (MLC) type that stores a plurality of bits.

Fig. 5 shows a configuration of the bit line selection circuit. Fig. 5 illustrates a page buffer/sense circuit 170 shared by one even bit line GBLe and one odd bit line GBLo, and a bit line selection circuit 200 connected thereto.

The bit line selection circuit 200 includes: a transistor BLSe for selecting an even bit line GBLe, a transistor BLSo for selecting an odd bit line GBLo, a transistor YBLe for connecting a dummy power supply VIRPWR to the even bit line GBLe, and a transistor YBLo for connecting the dummy power supply VIRPWR to the odd bit line GBLo, a NAND string is connected between the even bit line GBLe and a source line SL, and a NAND string is connected between the odd bit line GBLo and the source line SL. For example, in the read operation, mask read is performed, and when even bit line GBLe is selected, odd bit line GBLo is not selected, and when odd bit line GBLo is selected, even bit line GBLe is not selected. The unselected bit lines are connected to the Ground (GND) level via a dummy power supply VIRPWR.

Fig. 6 (a) shows a configuration of the page buffer/readout circuit 170. Fig. 6 (a) shows a page buffer/readout circuit. For convenience, a transistor is referred to as a signal applied to a gate of the transistor. Page buffer/readout circuit 170 includes two latches L1 and L2, a transfer gate (transistor CACHE) is connected between latch L1 and latch L2, and data transfer in both directions from latch L1 to latch L2 or from latch L2 to latch L1 can be performed by turning on the transfer gate.

Latch L1 includes a pair of cross-coupled inverters, with node SLR1 of latch L1 connected to the common source/drain (S/D) of transistor BLCD1 and transistor DTG, and node SLS1 connected to decision circuit 210. The determination circuit 210 determines whether or not Program Verify (Program Verify) or erase Verify is acceptable, for example. When the node SLR1 is selectively charged to Vdd from the voltage supply node V2 or the node SLR1 is selectively discharged to GND in program verification or the like, the transistor DTG is turned on. Further, the latch L1 can short-circuit the node SLR1 and the node SLS1 through the transistor EQ.

Node SLR1 and node SLS1 of latch L1 are connected to node SLS2 and node SLR2 of latch L2 via a transistor CACHE, respectively. The node SLR2 of the latch L2 is connected to the sense node SNS via the transistor BLCD2, and the node SLS2 is connected to the transistor RESET 2. When latch L2 is RESET, transistor RESET2 is conductive. The nodes SLS2 and SLR2 are connected to a differential sense amplifier SA via a data line DL and a data line/DL, and the output of the differential sense amplifier SA is connected to the input/output circuit 120.

A transistor VG and a transistor REG are connected in series between the voltage supply node V2 and the sense node SNS, and the gate of the transistor VG is connected to the S/D of the transistor DTG. The voltage supply node V1 is connected to the sense node SNS via a transistor BLPRE. As will be described later, the voltage supply node V1 supplies the internal supply voltage Vdd when the bit line is precharged, and supplies the GND potential when the latch L1 is reset. A transistor BLCN and a transistor BLCLAMP are connected in series between the sense node SNS and the node BLS of the bit line selection circuit 200.

Fig. 6 (B) shows a circuit configuration of one inverter constituting the latch L1. The inverter includes four transistors connected in series, i.e., a P-type transistor PT1, a P-type transistor PT2, an N-type transistor NT1, and an N-type transistor NT2, and the voltages of a latch enable signal LAT1 and a latch enable signal/LAT 1 are input to the gates of the transistor PT1 and the transistor NT2, respectively, and the voltages of the common gate input nodes SLS1/SLR1 to the transistor PT2 and the transistor NT1, respectively. When the latch enable signal LAT1 is at the H level, the inverter can operate, and when the latch enable signal LAT1 is at the L level, the transistors PT2 and NT1 are in a tri-state separated from the internal supply voltages Vdd and GND, and the inverter can be reset. The reset of the latch L1 is performed using a current path through the sense node SNS, and thus is performed when the sense node SNS is free, i.e., when the sense node SNS is not adversely affected.

The word line selection circuit 160 and the column selection circuit 180 (see fig. 3) select a read start position of data in a page based on the row address information Ax and the column address information Ay, or automatically read data from a head position of the page without using a row address and a column address. Further, the word line selection circuit 160 and the column selection circuit 180 may include a row address counter and a column address counter that increment row and column addresses in response to a clock signal.

In a read operation of the flash memory, a positive voltage is applied to the bit line, a voltage (e.g., 0V) is applied to the selected word line, a pass voltage Vpass (e.g., 4.5V) is applied to the unselected word line, a positive voltage (e.g., 4.5V) is applied to the selected gate line SGD and the selected gate line SGS, the bit line side selection transistor TD and the source line side selection transistor TS are turned on, and 0V is applied to the common source line. In the program operation, a high-voltage program voltage Vpgm (15V to 20V) is applied to a selected word line, an intermediate potential (for example, 10V) is applied to a non-selected word line, the bit line side selection transistor TD is turned on, the source line side selection transistor TS is turned off, and a potential corresponding to data of "0" or "1" is supplied to a bit line. In the erase operation, 0V is applied to a selected word line in a block, a high voltage (for example, 20V) is applied to a P-well, and electrons of a floating gate (floating gate) are extracted to a substrate, whereby data is erased in units of blocks.

Next, a description will be given of a sequential read operation of a plurality of pages in the flash memory according to the present embodiment. When the controller 150 receives a command for a continuous read operation of pages via the input-output circuit 120, the controller 150 controls continuous read of pages from a start address, and when the controller 150 receives a command for ending the continuous read operation, ends continuous read of pages at an end address. In the page continuous read operation, as described with reference to fig. 1 and 2, data read from the selected page of the memory cell array is transferred to the latch L1 while data is output from the latch L2. Data transfer from latch L1 to latch L2 is performed not in units of 1 page but divided into 1/2 pages (first cache or second cache), and while data of one cache of latch L2 is transferred to input/output circuit 120, data of the other cache of latch L2 is processed by ECC circuit 130. The data transferred to the input-output circuit 120 is output from the external input-output terminal to the outside in synchronization with an external clock signal ExCLK (e.g., rising edge and falling edge). Reading of data from the memory cell array and data transfer from the latch L1 to the latch L2 are performed based on an internal clock signal, data transfer between the latch L2 and the input/output circuit 120 and data output from the input/output circuit 120 are performed based on an external clock signal ExCLK, and data transfer between the latch L2 and the ECC circuit 130 and operation of the ECC circuit are performed based on another internal clock signal or a clock signal obtained by dividing the external clock signal ExCLK.

When reading of a selected page of the memory cell array is performed, the sense node SNS reads a potential of a selected bit line, and then, charges of the sense node SNS are transferred to the node SLR1 of the latch L1 via the transistor BLCD 1. The latch L1 is determined to be data "1" when the transferred charge is equal to or greater than the threshold value, and determined to be data "0" when the transferred charge is less than the threshold value, and holds the data. The latch L1 resets the potential of the node SLR1 to the GND level in order to correctly reflect the charge transferred from the sense node SNS. When the latch L1 is reset, the voltage supply node V1 is switched to GND, the transistor BLCD1 and the transistor BLPRE are turned on, and the node SLR1 is electrically connected to the voltage supply node V1.

In the conventional continuous read of the flash memory, the reset of the latch L1 is performed before the precharge of the bit line when the next page is read. However, in the case where the data output speed is increased after the data of latch L1 has been transferred to latch L2 in the reset of latch L1, there is a possibility that the time for resetting latch L1 cannot be sufficiently ensured. To avoid this problem, in the page continuous read operation of the present embodiment, the reset of the latch L1 is performed after the precharge of the bit line is completed and before the discharge of the NAND string cell is started.

Fig. 7 shows a timing chart when resetting the latch L1. The bit lines are precharged in the same manner as in the conventional art, and therefore, the bit lines are not shown in detail here, but are precharged as follows. First, the voltage supply node V1 is converted to the supply voltage Vdd, the transistor BLPRE is turned on, and the sense node SNS is charged to the Vdd level. Further, the transistor BLCLAMP and the transistor BLCN are turned on, and the node BLS is charged to VCLMP 1. At Vdd ≧ VCLMP 1. At this time, the transistors BLCD1, BLCD2, and REG are rendered non-conductive. Further, the transistor BLSe is turned on (here, the even bit line GBLe is selected), and the node BLS is electrically connected to the even bit line GBLe. A bit line side selection transistor TD of a NAND string connected to an even bit line GBle is turned on, a source line side selection transistor TS is turned off, and a pass voltage is applied to a selected page and a non-selected page. Thus, even bit line GBLe is precharged with clamp voltage VCLMP 1. On the other hand, the unselected odd bit line GBLo is electrically connected to GND of the virtual power supply VIRPWR via the transistor YBLo.

After the precharge of the bit line is completed, the latch L1 is reset. In the reset period, the transistors BLPRE, BLCN, and BLCLAMP are turned on. As shown in fig. 7, at time t1, transistor BLSe is made non-conductive, and even bit line GBLe is electrically disconnected from page buffer/sense circuit 170. Next, at time t2, the voltage supply node V1 transitions to GND. Thus, the sense node SNS drops from the supply voltage Vdd to the GND level, and the node TOBL and the node BLS drop from the clamp voltage VCLMP1 to the GND level.

Next, at time t3, the latch enable signal LAT1 for resetting the latch L1 transitions from the H level to the L level, and the latch L1 is placed in a state capable of resetting. Next, at time t4, transistor EQ is turned on for a certain period of time, node SLR1 and node SLS1 are short-circuited at the same potential, and then at time t5, transistor BLCD1 is turned on for a certain period of time. Thereby, the charge of the node SLR1 is discharged to GND of the voltage supply node V1 via the sense node SNS, and the reset of the latch L1 is completed.

After the reset of the latch L1, the sense node SNS and the like are restored. That is, the sense node SNS, the node TOBL, and the node BLS are recharged, and the voltages of these nodes are restored to the precharge state of the latch L1 before reset. At time t6, the voltage supply node V1 transitions from GND to the supply voltage Vdd. Thus, the sense node SNS is charged again to Vdd, and the node TOBL and the node BLS are charged again to the clamp voltage VCLMP 1. Next, at time t7, transistor BLSe is turned on, and even bit line GBLe is electrically connected to page buffer/sense circuit 170.

The discharge and readout of the NAND string performed after the reset of the latch L1 are performed in the same manner as in the related art (not shown). That is, in the discharge of the NAND string, the transistor BLSe is turned off, the source line side selection transistor TS of the NAND string is turned on, and the NAND string is electrically connected to the source line SL. Further, a gate voltage for generating a clamp voltage VCLMP2 at the node TOBL is applied to the transistor BLCLAMP. VCLMP1 > VCLMP 2. Then, by turning on the transistor BLSe for a certain period, a potential corresponding to data "0" and data "1" of the selected memory cell is displayed on the sense node SNS. When the selected memory cell holds data "0", the potential of the bit line is not discharged to the source line SL, and therefore the potential of the sense node SNS hardly changes, whereas when the selected memory cell holds data "1", the potential of the bit line is discharged to the source line SL, and the potential of the sense node SNS decreases. In this way, the sense node SNS senses charges corresponding to data "0" and data "1" of the selected memory cell. Then, the charge sensed by the sense node SNS is transferred to the node SLR1 of the latch L1 via the transistor BLCD 1.

In the present embodiment, since the reset of the latch L1 is performed between the precharge period of the bit line and the discharge period of the NAND string, the reset of the latch L1 can be ensured, so that the reliability of data retention of the latch L1 can be improved. Further, the array read can begin immediately upon transferring the data from latch L1 to latch L2.

Next, the continuous readout of the improved page to which the reset of the latch L1 is applied according to the present embodiment will be described. Fig. 8 is a timing chart when continuous readout of an improved page is performed. Fig. 8 shows an example in which the page P0 is set as the start address. The start address may be arbitrarily selected. tp is a period from the start timing of array reading to the completion of precharging of the bit lines, and tx is a period required for resetting of the latch L1. As shown in fig. 8, the substantially continuous reading by the latch L1 and the latch L2 starts reading from the page P2, and the start timing of the array reading of the page P2 is earlier than the conventional timing shown in fig. 2. In the continuous readout shown in fig. 2, the start timing of the array readout of page P2 is the point in time when the transfer of data of page P1 (P1C1) from latch L1 to latch L2 ends. That is, after latch L2 holds the data of page P1, the data of the next page P2 is transferred to latch L1.

In contrast, in the improved sequential readout, the start timing of the array readout of page P2 is equal to the timing of transferring the data of page P1 of first cache C0 of latch L1 (P1C0) to latch L2. In this way, even if the timing of array reading of page P2 is advanced, it takes a certain time for array reading in practice, and if the external clock signal ExCLK of high-speed frequency is used to increase the speed of the continuous reading time, the transfer of data (P1C1) from latch L1 to page P1 of latch L2 is completed at the time point when the data of page P2 read from the array is transferred to latch L1. Since the reset of latch L1 is performed during the array read period, the reset of latch L1 is not affected even if the start timing of the array read is advanced.

In the improved sequential readout, the array readout time tARRAY is defined by the start timing of the array readout and the end timing of the array readout. The end timing of the array reading of page P2 is the start timing of the array reading of next page P3, and when pages P2, P3, and P4 … are read successively, the array read time tARRAY is also continued similarly.

By advancing the timing of starting the reading of the memory cell array in the improved continuous read operation, the limitation of expression (1) in the conventional continuous read operation is relaxed as in expression (2), and data output using the external clock signal ExCLK of high-speed frequency is possible.

tARAY < tDOUT (page 1)

tECC < tDOUT (1/2 page) … (2)

That is, if the time tDOUT for outputting data of 1 page is longer than the array read time tARRAY and the time tDOUT for outputting data of 1/2 pages is longer than the time tcac of ECC processing, the speed of continuous reading can be increased as compared with the conventional case, as long as the following restrictions are satisfied. In fig. 8, the following is illustrated: an output time tDOUT which is a sum of a time of outputting the data of the second cache of the page P0 and a time of outputting the data of the first cache of the page P1 is larger than an array read time tARRAY of the page P2 from a time point of starting to transfer the data of the first cache C0 of the page P1 from the latch L1 to the latch L2 to a time point of starting to transfer the data of the first cache C0 of the next page P2 from the latch L483l 6 to the latch L2; the time tDOUT at which the data of the second cache C1 of the latch L2 is output is large compared to the time tdec at which the data of the first cache C0 of the latch L2 is ECC processed.

In the improved continuous read operation, the timing to start the reset of latch L1 is after the completion of the precharge of the bit line, and therefore, if the period from the start timing of the array read to immediately before the start of the reset of latch L1 is tp, the restriction of equation (3) is added in addition to equation (2). That is, the data of latch L1 needs to be transferred to latch L2.

tDOUT (page 1/2) < tp … (3)

However, since the precharge period of the bit line is sufficiently long, the improved continuous reading speed shown in fig. 8 can be achieved as long as expressions (2) and (3) are satisfied.

In this way, in the improved continuous read operation, the reset of the latch L1 can be ensured and the read data can be speeded up.

Next, another embodiment of the present invention will be explained. In the embodiment, the reset of latch L1 is performed between the precharge operation of the bit line and the discharge operation of the NAND string, but in the other embodiment, the reset of latch L1 is performed in the discharge operation of the NAND string.

As described above, the reset of the latch L1 can be performed as long as the sense node is in a free state without being affected by other factors. During a discharge operation of the NAND string, the transistor BLSe is non-conductive, and the sense node SNS is in a state of being electrically isolated from the bit line. Therefore, the reset operation of latch L1 shown from time t2 to time t6 shown in fig. 7 can be performed in parallel with the discharge operation of the NAND string in time.

According to this embodiment, by performing the reset of the latch L1 in parallel in the discharge period of the NAND string, the array read time tARRAY can be shortened in fact, and the data output can be made faster by the continuous read, as compared with the case where the reset of the latch L1 is performed between the precharge operation of the bit line and the discharge operation of the NAND string.

While the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present invention described in the claims.