阅读说明：本技术 低电流电子抹除式可复写只读存储器阵列的操作方法 (Method for operating low-current electrically erasable rewritable read-only memory array ) 是由 林信章 钟承谕 黄文谦 于 2018-09-06 设计创作，主要内容包括：一种低电流电子抹除式可复写只读存储器阵列的操作方法,此低电流电子抹除式可复写只读存储器阵列包含多组位线、多条字线、多条共源线与多个子内存阵列,每一子内存阵列包含第一记忆晶胞与第二记忆晶胞,第一记忆晶胞连接第一组位线的一位线、第一共源线与第一字线,第二记忆晶胞连接第一组位线的另一位线、第一共源线与第二字线,第一、第二记忆晶胞互相对称配置,并分别位于第一共源线的相异两侧。本发明的操作方法利用特殊的偏压设定来达到低电流、低电压且低成本,又具有字节写入、抹除的功能。(An operation method of a low current EEPROM array comprises a plurality of groups of bit lines, a plurality of word lines, a plurality of common source lines and a plurality of sub-memory arrays, wherein each sub-memory array comprises a first memory cell and a second memory cell, the first memory cell is connected with one bit line of the first group of bit lines, the first common source line and the first word line, the second memory cell is connected with the other bit line of the first group of bit lines, the first common source line and the second word line, and the first memory cell and the second memory cell are symmetrically arranged and are respectively positioned at two different sides of the first common source line. The operation method of the present invention utilizes special bias voltage setting to achieve low current, low voltage and low cost, and has the functions of writing and erasing bytes.)

1. A method of operating a low current EEPROM array, the low current EEPROM array comprising: a plurality of parallel bit lines which are divided into a plurality of groups of bit lines, wherein the plurality of groups of bit lines comprise a first group of bit lines; a plurality of parallel word lines, which are perpendicular to the plurality of groups of bit lines and comprise a first word line and a second word line; a plurality of parallel common source lines parallel to the plurality of word lines and including a first common source line; and a plurality of sub-memory arrays, each of the sub-memory arrays connecting a set of the bit lines, two of the word lines, and a common source line, each of the sub-memory arrays comprising: a first memory cell connecting the first set of bit lines, the first common source line and the first word line; and a second memory cell connected to the first group of bit lines, the first common source line and the second word line, the first and second memory cells being symmetrically disposed and located on two different sides of the first common source line, the first group of bit lines including two bit lines connected to the first and second memory cells, respectively, the first and second memory cells having N-type field effect transistors located in a P-type substrate or a P-type well region, the first and second memory cells being used as an operation memory cell, when one of the operation memory cells is selected as a selection memory cell for operation, the operation memory cell being connected to the same bit line as the selection memory cell, the operation memory cells not connected to the same common source line as the selection memory cell being used as a plurality of parity memory cells, the operation memory cells being connected to the same word line as the selection memory cell, as a plurality of in-line memory cells, and the remaining plurality of operational memory cells as a plurality of unselected memory cells, the method comprising:

applying a base voltage V to the P-type substrate or the P-type well region connected to the selected memory cell_subpAnd applying a first bit voltage V to the bit line, the word line and the common source line connected to the selected memory cell_b1First word voltage V_w1A first common source voltage V_S1Applying a second word voltage V to the word line and the common source line connected to each of the parity memory cells_w2A second common source voltage V_S2Applying a second bit voltage V to the bit line and the common source line connected to each of the word-sharing memory cells_b2The first common source voltage V_S1Applying the second bit voltage V to the bit line, the word line and the common source line connected to each of the unselected memory cells_b2The second word voltage V_w2The second common source voltage V_S2And satisfies the following conditions:

when writing to the selected memory cell, V is satisfied_subpIs grounded (0), V_b1Is High Voltage (HV), V_S1Is High Voltage (HV), and V_w1High Voltage (HV);

when erasing the selected memory cell, it satisfies V_subpIs grounded (0), V_b1Is High Voltage (HV), V_S1Is High Voltage (HV), and V_w10 to low pressure (LV); and

when the plurality of unselected memory cells are operated, V is satisfied_subpIs grounded (0), V_b2Is Medium Voltage (MV), V_S1Is High Voltage (HV), and V_w1Is 0 to low pressure (LV), or satisfies V_subpIs grounded (0), V_b1Is High Voltage (HV), V_S2Is medium pressure (MV), and V_w20 to low pressure (LV).

2. The method of claim 1, wherein the first word line and the second word line in the same sub-memory cell array are connected to a same word voltage.

3. The method of claim 1, wherein in two adjacent sub-memory arrays, the two second memory cells are adjacent to each other and connected to the same bit line to share the same contact.

4. The method of claim 1, wherein the first memory cell further comprises: the field effect transistor is provided with a floating gate, the drain of the field effect transistor is connected with the first group of bit lines, the source of the field effect transistor is connected with the first common source line, one end of the capacitor is connected with the floating gate, the other end of the capacitor is connected with the first word line so as to receive the bias voltage of the first word line, and the field effect transistor receives the bias voltages of the first group of bit lines and the first common source line and writes data into the floating gate of the field effect transistor or erases the data of the floating gate of the field effect transistor.

5. The method of claim 1, wherein the second memory cell further comprises: a field effect transistor having a floating gate, a drain connected to the first set of bit lines and a source connected to the first common source line; and a capacitor, one end of which is connected with the floating gate and the other end is connected with the second word line so as to receive the bias voltage of the second word line, and the field effect transistor receives the bias voltages of the first group of bit lines and the first common source line, and writes data into the floating gate of the field effect transistor or erases the data of the floating gate of the field effect transistor.

6. The method of claim 4 or 5, wherein the FET is an NFET or PFET.

7. The method of claim 4 or 5, wherein the floating gate is sequentially formed with an oxide layer and a control gate, the control gate forms a capacitor with the oxide layer and the floating gate, and the floating gate and the control gate are polysilicon.

8. A method of operating a low current EEPROM array, the low current EEPROM array comprising: a plurality of parallel bit lines which are divided into a plurality of groups of bit lines, wherein the plurality of groups of bit lines comprise a first group of bit lines; a plurality of parallel word lines, which are perpendicular to the plurality of groups of bit lines and comprise a first word line and a second word line; a plurality of parallel common source lines parallel to the plurality of word lines and including a first common source line, and a plurality of sub-memory arrays, each of the sub-memory arrays connecting a set of the bit lines, two of the word lines and one of the common source lines, each of the sub-memory arrays including: a first memory cell connecting the first set of bit lines, the first common source line and the first word line; and a second memory cell connected to the first group of bit lines, the first common source line and the second word line, the first and second memory cells being symmetrically disposed and located on two different sides of the first common source line, the first group of bit lines including two bit lines connected to the first and second memory cells, respectively, the first and second memory cells having P-type field effect transistors in an N-type substrate or N-type well region, the first and second memory cells being operated as an operation memory cell, one of the operation memory cells being selected as a selection memory cell for operation, the operation memory cell being connected to the same bit line as the selection memory cell, the operation memory cells not connected to the same common source line as a plurality of parity memory cells, the operation memory cells being connected to the same word line as the selection memory cell, as a plurality of in-line memory cells, and the remaining plurality of operational memory cells as a plurality of unselected memory cells, the method comprising:

applying a base voltage V to the N-type substrate or the N-type well region connected to the selected memory cell_subnAnd applying a first bit voltage V to the bit line, the word line and the common source line connected to the selected memory cell_b1First word voltage V_w1A first common source voltage V_S1Applying a second word voltage V to the word line and the common source line connected to each of the parity memory cells_w2A second common source voltage V_S2Applying a second bit voltage V to the bit line and the common source line connected to each of the word-sharing memory cells_b2The first common source voltage V_S1Applying the second bit voltage V to the bit line, the word line and the common source line connected to each of the unselected memory cells_b2The second word voltage V_w2The second common source voltage V_S2And satisfies the following conditions:

when writing to the selected memory cell, V is satisfied_subnIs High Voltage (HV), V_b1＝V_S1＝V_w10, and V_w10 to low pressure (LV);

when erasing the selected memory cell, it satisfies V_subnIs High Voltage (HV), V_b1＝V_S10, and V_w1High Voltage (HV); and

when the plurality of unselected memory cells are operated, V is satisfied_subnIs High Voltage (HV), V_b2Is Medium Voltage (MV), V_S10, and V_w1Is High Voltage (HV), or satisfies V_subnHigh Voltage (HV), V_b1＝0，V_S2Is medium pressure (MV), and V_w2Is High Voltage (HV).

9. The method of claim 8, wherein the first word line and the second word line in the same sub-memory cell array are connected to a same word voltage.

10. The method of claim 8, wherein in two adjacent sub-memory arrays, the two second memory cells are adjacent to each other and connected to the same bit line to share the same contact.

11. The method of claim 8, wherein the first memory cell further comprises: the field effect transistor is provided with a floating gate, the drain of the field effect transistor is connected with the first group of bit lines, the source of the field effect transistor is connected with the first common source line, one end of the capacitor is connected with the floating gate, the other end of the capacitor is connected with the first word line so as to receive the bias voltage of the first word line, and the field effect transistor receives the bias voltages of the first group of bit lines and the first common source line and writes data into the floating gate of the field effect transistor or erases the data of the floating gate of the field effect transistor.

12. The method of claim 8, wherein the second memory cell further comprises: a field effect transistor having a floating gate, a drain connected to the first set of bit lines and a source connected to the first common source line; and a capacitor, one end of which is connected with the floating gate and the other end is connected with the second word line so as to receive the bias voltage of the second word line, and the field effect transistor receives the bias voltages of the first group of bit lines and the first common source line, and writes data into the floating gate of the field effect transistor or erases the data of the floating gate of the field effect transistor.

13. The method of claim 11 or 12, wherein the FET is an NFET or PFET.

14. The method of claim 11 or 12, wherein the floating gate is sequentially formed with an oxide layer and a control gate, the control gate forms a capacitor with the oxide layer and the floating gate, and the floating gate and the control gate are polysilicon.

Technical Field

The present invention relates to a memory array, and more particularly to a low current Electrically Erasable Programmable Read Only Memory (EEPROM) array.

Background

Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common method for manufacturing Application Specific Integrated Circuits (ASICs). Today, as computer information products are developed, Flash Memory (Flash) and Electrically Erasable Programmable Read Only Memory (EEPROM) have nonvolatile Memory functions of Electrically writing and erasing data, and data does not disappear after power is turned off, so that Flash Memory and EEPROM are widely used in electronic products.

Non-volatile memories are programmable, storing charge to change the gate voltage of the memory's transistor, or not storing charge to leave the gate voltage of the memory's transistor. The erase operation removes the charge stored in the non-volatile memory, and returns the non-volatile memory to the gate voltage of the transistor of the original memory. For the current flash memory architecture, although the area is small and the cost is low, the flash memory architecture only supports the erasing of a large block, can not erase only a specific one-bit memory cell, and is inconvenient to use; in addition, for the architecture of the electrically erasable programmable read only memory, the structure has a byte write function, which is more convenient for the flash memory to use, and a one-bit memory cell circuit diagram and a memory cell structure cross-sectional view thereof are shown in fig. 1 and fig. 2, respectively. Each memory cell includes two transistors: a memory transistor 10, a selection transistor 12 and a capacitor structure 13, the capacitor structure 13 is disposed above the memory transistor 10 as a polysilicon memory cell, because of this structure, the area is larger than that of the flash memory, and when performing bit erase, the unselected positions are often isolated by the transistor, thereby increasing the cost requirement.

Therefore, the applicant of the present invention has developed a low current Electrically Erasable Programmable Read Only Memory (EEPROM) array, and has proposed a low current, low voltage and low cost operation method based on the EEPROM array, which can simultaneously perform the writing and erasing of the bytes.

Disclosure of Invention

The main objective of the present invention is to provide a low current EEPROM (EEPROM) array, which has a low current, low voltage and low cost EEPROM architecture, and can further use a special bias method to achieve the functions of writing and erasing bytes.

To achieve the above objects, the present invention provides a low-cost eeprom array, which comprises a plurality of parallel bit lines divided into a plurality of groups of bit lines, wherein the plurality of groups of bit lines comprise a first group of bit lines, the bit lines are perpendicular to a plurality of parallel word lines, the word lines comprise a first word line and a second word line, the first word line and the second word line are parallel to a plurality of parallel common source lines, and the common source lines comprise a first common source line. And the first group of bit lines comprises two bit lines which are respectively connected with the first memory cell and the second memory cell.

The first and second memory cells are used as an operation memory cell, when one of the operation memory cells is selected as a selected memory cell to operate, the operation memory cell connected with the selected memory cell on the same bit line and not connected with the selected memory cell on the same common source line is used as a plurality of parity memory cells, the operation memory cell connected with the selected memory cell on the same bit line and common source line is used as a homologous memory cell, the operation memory cell connected with the selected memory cell on the same word line is used as a plurality of homologous memory cells, and the other operation memory cells are used as a plurality of unselected memory cells.

The first and second memory cells can both have NFETs in the P-well or the P-substrate, and can also both have PFETs in the N-well or the N-substrate.

When the memory cell has an N-type field effect transistor and is to be operated, a base voltage V is applied to the P-well or the P-substrate connected with the selected memory cell_subpAnd applying the first bit voltage to the bit line, the word line and the common source line connected to the selected memory cellV_b1First word voltage V_w1A first common source voltage V_S1Applying a second word voltage V to the word line and the common source line connected to each of the parity memory cells_w2A second common source voltage V_S2Applying a second bit voltage V to the bit line and the common source line connected to each word-sharing memory cell_b2A first common source voltage V_S1(each of the word-line memory cells also shares its common source line), applying a second word voltage V to the word line connected to the same memory cell_w2Applying a second bit voltage V to the bit line, the word line and the common source line of each unselected memory cell_b2A second word voltage V_w2A second common source voltage V_S2。

When writing to the selected memory cell, V is satisfied_subpIs grounded (0), V_b1Is High Voltage (HV), V_S1Is High Voltage (HV), and V_w1High Voltage (HV); when erasing selected memory cells, satisfy V_subpIs grounded (0), V_b1Is High Voltage (HV), V_S1Is High Voltage (HV), and V_w10 to low pressure (LV); when the unselected memory cells are operated, V is satisfied_subpIs grounded (0), V_b2Is Medium Voltage (MV), V_S1Is High Voltage (HV), and V_w1Is 0 to low pressure (LV), or satisfies V_subpIs grounded (0), V_b1Is High Voltage (HV), V_S2Is medium pressure (MV), and V_w20 to low pressure (LV).

When the memory cell has a P-type field effect transistor, a base voltage V is applied to the N-type well region or N-type substrate connected with the selected memory cell_subnAnd satisfies the following conditions: when writing to the selected memory cell, V is satisfied_subnIs High Voltage (HV), V_b1＝V_S1＝V_w10, and V_w10 to low pressure (LV); when erasing selected memory cells, satisfy V_subnIs High Voltage (HV), V_b1＝V_S10, and V_w1High Voltage (HV); when the unselected memory cells are operated, V is satisfied_subnIs High Voltage (HV), V_b2Is Medium Voltage (MV), V_S10, and V_w1Is High Voltage (HV), or satisfies V_subnHigh pressure(HV)，V_b1＝0，V_S2Is medium pressure (MV), and V_w2Is High Voltage (HV).

The purpose, technical content, features and effects of the present invention will be more readily understood by the following detailed description of the embodiments taken in conjunction with the accompanying drawings.

Drawings

FIG. 1 is a circuit diagram of a prior art one-bit memory cell.

FIG. 2 is a cross-sectional view of a prior art one bit memory cell.

FIG. 3 is a circuit diagram of an embodiment of the present invention.

Fig. 4 is a circuit layout diagram according to an embodiment of the invention.

Fig. 5 is a circuit diagram of a sub-memory array according to an embodiment of the invention.

FIG. 6 is a cross-sectional view of an NFET and capacitor of the present invention.

FIG. 7 is a cross-sectional view of a PFET and a capacitor according to the present invention.

Description of reference numerals: 10-a memory transistor; 12-a selection transistor; 13-a capacitive structure; 14-a bit line; 16-bit line; 18-a first set of bit lines; 20-word lines; 22-a first word line; 24-a second word line; 26-common source line; 28-first common source line; 30-a sub-memory array; 32-a first memory cell; 34-a second memory cell; 36-a field effect transistor; 38-capacitance; 40-field effect transistors; 42-capacitance; 44-a drain contact; 46-N type field effect transistor; 47-P type field effect transistor; a 48-P type semiconductor substrate; 49-N type semiconductor substrate; 50-a floating gate; 52-an oxide layer; 54-a control gate; 56-capacitance.

Detailed Description

Reference is now made to fig. 3 and 4 for a description of the preferred embodiments of the present invention. The present invention includes a plurality of parallel bit lines 14 divided into a plurality of groups of bit lines 16, the plurality of groups of bit lines 16 including a first group of bit lines 18, the first group of bit lines 18 including two bit lines 14. There are also a plurality of parallel word lines 20, including a first and second word line 22, 24, that are perpendicular to the bit lines 14. Parallel to the word lines 20 are a plurality of parallel common source lines 26, including a first common source line 28. The bit lines 14, word lines 20 and common source line 26 connect a plurality of sub-memory arrays 30, i.e., 2x1 bit memory cells. Each sub-memory array 30 connects a set of bit lines 16, two word lines 20, and a common source line 26. Since each sub-memory array 30 is connected to the bit line 16, two word lines 20, and the common source line 26 in close proximity, the same is stated below.

Referring to fig. 4 and 5, each sub-memory array 30 includes a first memory cell 32 and a second memory cell 34, the first memory cell 32 is connected to a bit line 14, a first common source line 28 and a first word line 22 of a first group of bit lines 18, the second memory cell 34 is connected to another bit line 14, a first common source line 28 and a second word line 24 of the first group of bit lines 18, and the first memory cell 32 and the second memory cell 34 are symmetrically disposed and located on two opposite sides of the first common source line 28. In addition, in two adjacent sub memory arrays 30, two second memory cells 34 are adjacent to each other and connected to the same bit line 14 to share the same contact, i.e., the field effect transistors 40 of two second memory cells 34 are adjacent to each other and connected to the same bit line 14 to share the same drain contact 44, so that the overall layout area can be reduced.

The first memory cell 32 further includes a field effect transistor 36 and a capacitor 38, the field effect transistor 36 has a floating gate, a drain of the field effect transistor 36 is connected to the bit line 14 of the first group of bit lines 18, a source of the field effect transistor 36 is connected to the first common source line 24, one end of the capacitor 38 is connected to the floating gate of the field effect transistor 36, and the other end is connected to the first word line 22 for receiving a bias voltage of the first word line 22, the field effect transistor 36 receives the bias voltages of the bit line 14 of the first group of bit lines 18 and the first common source line 24 for writing data into the floating gate of the field effect transistor 36 or erasing the data of the floating gate of the field effect transistor 36.

The second memory cell 34 further includes a field effect transistor 40 and a capacitor 42, the field effect transistor 40 has a floating gate, a drain of the field effect transistor 40 is connected to the bit line 14 of the first group of bit lines 18, a source of the field effect transistor 40 is connected to the first common source line 24, one end of the capacitor 42 is connected to the floating gate of the field effect transistor 40, the other end is connected to the second word line 24 for receiving the bias voltage of the second word line 24, the field effect transistor 40 receives the bias voltages of the bit line 14 of the first group of bit lines 18 and the first common source line 24 for writing data into the floating gate of the field effect transistor 40 or erasing the data of the floating gate of the field effect transistor 40. In addition, in two adjacent sub-memory arrays 30, the field effect transistors 40 of two second memory cells 34 are adjacent to each other and connected to the same bit line 14 to share the same drain contact 44, thereby reducing the circuit layout area.

Referring to fig. 3, the field effect transistors 36 and 40 may be both N-type field effect transistors located in a P-type substrate or a P-type well region, or P-type field effect transistors located in an N-type substrate or an N-type well region, but the operation of the present invention is different depending on the N-type or P-type field effect transistors, and the operation of the field effect transistors 36 and 40 is described as N-type field effect transistors. To clearly illustrate this operation, the name of each memory cell is clearly defined.

The first and second memory cells 32, 34 are both used as an operation memory cell, and one of the operation memory cells can be selected as a selected memory cell for operation. Operating memory cells connected to the same bit line 14 as the selected memory cells and not connected to the same common source line 26 as the selected memory cells as a plurality of parity memory cells; the operation memory cell connected to the same bit line 14 and common source line 26 as a source memory cell; the operation memory cell connected to the same word line 20 as the selected memory cell is used as a plurality of word-in memory cells; the remaining operational memory cells are used as a plurality of unselected memory cells.

The operation of the present embodiment is as follows, and other unselected memory cells are not affected by the following operation to operate a specific single memory cell.

Applying a base voltage V to the P-type substrate or P-type well region of the selected memory cell connection_subpAnd applying a first bit voltage V to the bit line 14, the word line 20 and the common source line 26 connected to the selected memory cell_b1First word voltage V_w1A first common source voltage V_S1Applying a second word voltage V to the word line 20 and the common source line 26 connected to each of the parity memory cells_w2A second common source voltage V_S2Applying a second bit voltage V to each of the bit line 14 and the common source line 26 connected to the word memory cell_b2A first common source voltage V_S1(each of the word-line memory cells also share its common source line), a second word voltage V is applied to the word line 20 connected to the same memory cell_w2Applying a second bit voltage V to the bit line 14, the word line 20, and the common source line 26 of each unselected memory cell_b2A second word voltage V_w2A second common source voltage V_S2And satisfies the following conditions:

when writing to the selected memory cell, V is satisfied_subpIs grounded (0), V_b1Is High Voltage (HV), V_S1Is High Voltage (HV), and V_w1Is High Voltage (HV).

When erasing selected memory cells, satisfy V_subpIs grounded (0), V_b1Is High Voltage (HV), V_S1Is High Voltage (HV), and V_w10 to low pressure (LV).

When the unselected memory cells are operated, V is satisfied_subpIs grounded (0), V_b2Is Medium Voltage (MV), V_S1Is High Voltage (HV), and V_w10 to low pressure (LV); or, satisfy V_subpIs grounded (0), V_b1Is High Voltage (HV), V_S2Is medium pressure (MV), and V_w20 to low pressure (LV).

When the field effect transistors 36, 40 are PFETs, a base voltage V is applied to the N-well region or the N-substrate according to the definition of the memory cell and the voltage_subnAnd satisfies the following conditions:

when writing to the selected memory cell, V is satisfied_subnIs High Voltage (HV), V_b1＝V_S1＝V_w10, and V_w10 to low pressure (LV).

When erasing selected memory cells, satisfy V_subnIs High Voltage (HV), V_b1＝V_S10, and V_w1Is High Voltage (HV).

When the unselected memory cells are operated, V is satisfied_subnIs High Voltage (HV), V_b2Is Medium Voltage (MV), V_S10, and V_w1At a high pressure(HV); or, satisfy V_subnHigh Voltage (HV), V_b1＝0，V_S2Is medium pressure (MV), and V_w2Is High Voltage (HV).

Since two memory cells 32, 34 in the same sub memory cell array 30 are connected to two bit lines 14, respectively; therefore, the first word line 22 and the second word line 24 in the same sub memory cell array 30 can be connected to the same bias voltage without affecting the byte write (byte write) and erase (byte erase) functions, i.e. they can be connected out by the same connection, thereby reducing the area of the decoding area.

The following is a cross-sectional view of the structure of the field effect transistors 36, 40 and the capacitors 38, 42, and an N-type field effect transistor is taken as an example. Referring to FIG. 6, the NFET 46 is disposed in a P-type semiconductor substrate 48 as a semiconductor substrate and has a floating gate 50, an oxide layer 52 and a control gate 54 are sequentially disposed on the floating gate 50, the control gate 54, the oxide layer 52 and the floating gate 50 form a capacitor 56, and the floating gate 50 and the control gate 54 are made of polysilicon. When the semiconductor substrate is N-type, a P-well can be formed in the substrate, and the NFET 46 can be formed in the P-well. The structure design of the memory cell, namely a Flash (Flash) structure, can greatly reduce the area and the cost of a non-volatile memory array.

Similarly, when the cross-sectional structure of the field effect transistors 36 and 40 and the capacitors 38 and 42 is a P-type field effect transistor, as shown in fig. 7, the P-type field effect transistor 47 is disposed in an N-type semiconductor substrate 49 as a semiconductor substrate and has a floating gate 50, an oxide layer 52 and a control gate 54 are sequentially disposed on the floating gate 50, the control gate 54 and the oxide layer 52, the floating gate 50 form a capacitor 56, and the floating gate 50 and the control gate 54 are made of polysilicon. When the semiconductor substrate is P-type, an N-well region can be formed in the substrate, and the PFET 46 can be formed in the N-well region.

When the memory cell is in the write operation, the voltage of the memory cell is increased from about 2.5 volts or 3.3 volts to a stable high voltage through a boost (charging), but the voltage difference between the drain and the source causes the current between the drain and the source to be generated, so that the high voltage is changed; when the current is larger and the variation generated by the high voltage is larger, the required charge pump is stronger, the area on the layout is larger, and when the Flash architecture is programmed, the bias voltage is: the gate capacitance and drain are applied with high voltage, the source is grounded, and the current between the drain and source is about 500u A/bit; when the present invention selects a part of memory cells to perform the write operation, the gate capacitance, source and drain are all applied with high voltage; when erasing operation is performed, no voltage is applied to the gate capacitor, the source and the drain, so that zero voltage and zero current are almost present between the drain and the source. The operation method of the invention can carry out byte write and erase under the condition of bias voltage, the generated current is smaller, the charge pump can be reduced, and the area on the layout is smaller.

In summary, the operation method of the low-current electrically erasable rewritable ROM array provided by the present invention not only has a flash architecture with a smaller area and a lower cost, but also can use a bias mode to achieve the functions of writing and erasing bytes.

The above-mentioned features of the present invention are provided by way of examples and are intended to enable persons skilled in the art to understand the invention and to implement it without limiting the scope of the invention, so that other equivalent modifications or changes may be made without departing from the spirit of the invention as disclosed in the claims.