阅读说明：本技术 用于nand存储操作的架构和方法 (Architecture and method for NAND memory operation ) 是由 李昌炫 于 2021-06-04 设计创作，主要内容包括：在一种用于对存储单元串进行编程的方法中,在选定的字线上施加编程电压以对存储单元串中的选定的存储单元进行编程。将第一通过电压施加在耦合到存储单元中的第一存储单元的第一字线上。将第二通过电压施加在耦合到存储单元中的第二存储单元的第二字线上。此外,将第三通过电压施加在耦合到存储单元中的第三存储单元的第三字线上。第一、第二和第三存储单元位于存储单元串中的选定的存储单元的第一侧,并且第二存储单元设置在第一存储单元和第三存储单元之间。第二通过电压高于第一通过电压和第三通过电压。(In a method for programming a memory cell string, a program voltage is applied on a selected word line to program a selected memory cell of the memory cell string. A first pass voltage is applied on a first wordline coupled to a first one of the memory cells. A second pass voltage is applied on a second wordline coupled to a second one of the memory cells. In addition, a third pass overvoltage is applied on a third wordline coupled to a third one of the memory cells. The first, second and third memory cells are located on a first side of a selected memory cell in the memory cell string, and the second memory cell is disposed between the first memory cell and the third memory cell. The second pass voltage is higher than the first pass voltage and the third pass voltage.)

1. A method for programming a memory cell in a string of memory cells in a memory device, the method comprising:

applying a programming voltage on a selected word line to program a selected one of the memory cells, the selected memory cell having a gate terminal coupled to the selected word line;

applying a first pass voltage on a first word line, the first word line coupled to a first one of the memory cells, the first memory cell located on a first side of the selected one of the strings of memory cells;

applying a second pass voltage on a second word line, the second word line coupled to a second one of the memory cells, the second memory cell located on the first side of the selected one of the strings of memory cells; and

applying a third pass voltage on a third word line, the third word line coupled to a third one of the memory cells, the third memory cell located on the first side of the selected one of the strings of memory cells, the second pass voltage being higher than the first pass voltage and the third pass voltage, and the second memory cell disposed between the first memory cell and the third memory cell.

2. The method of claim 1, wherein the memory cell string further comprises a Bottom Select Gate (BSG) transistor and a Top Select Gate (TSG) transistor, the BSG transistor, the memory cells, and the TSG transistor being connected in series.

3. The method of claim 2, wherein the first, second, and third memory cells are located between the selected memory cell and the BSG transistor, the method further comprising:

applying a pass voltage on a word line coupled to the memory cell located on a second side of the selected memory cell in the string of memory cells and disposed between the selected memory cell and the TSG transistor.

4. The method of claim 2, wherein the first, second, and third memory cells are located between the selected memory cell and the TSG transistor, the method further comprising:

applying a pass voltage on a word line coupled to the memory cell located on a second side of the selected memory cell in the string of memory cells and disposed between the selected memory cell and the BSG transistor.

5. The method of claim 2, further comprising:

applying the first pass voltage on a fourth word line, the fourth word line coupled to a fourth one of the memory cells, the fourth memory cell located on a second side of the selected one of the strings of memory cells;

applying the second pass voltage on a fifth word line, the fifth word line coupled to a fifth one of the memory cells, the fifth memory cell located on the second side of the selected one of the strings of memory cells; and

applying the third pass over voltage on a sixth word line coupled to a sixth one of the memory cells located on the second side of the selected one of the strings of memory cells, the fifth memory cell disposed between the fourth and sixth memory cells.

6. The method of claim 5, wherein:

the first, second, and third memory cells are disposed between the selected memory cell and the BSG transistor; and is

The fourth memory cell, the fifth memory cell, and the sixth memory cell are disposed between the selected memory cell and the TSG transistor.

7. The method of claim 6, further comprising:

applying an interface pass voltage on a first interface wordline, the first interface wordline coupled to a first interface memory cell, the first interface memory cell located on the first side of the selected memory cell and disposed between the second memory cell and the third memory cell; and

applying the interface pass voltage on a second interface wordline coupled to a second interface memory cell located on the second side of the selected memory cell and disposed between the fifth memory cell and the sixth memory cell.

8. The method of claim 7, wherein:

the interface pass voltage is in a range between the second pass voltage and the third pass voltage;

the interface pass voltage is greater than a highest program-verify voltage applied on the selected memory cell when the selected memory cell is verified; and is

The interface pass voltage at the last programming cycle of the incremental step pulse programming that programs the selected memory cell is one volt higher than the highest program-verify voltage.

9. The method of claim 7, further comprising:

applying a transition pass voltage on a first transition word line, the first transition word line coupled to a first transition memory cell, the first transition memory cell located on the first side of the selected memory cell and disposed between the second memory cell and the first interface memory cell; and

applying the transition pass voltage on a second transition word line coupled to a second transition memory cell located on the second side of the selected memory cell and disposed between the fifth memory cell and the second interface memory cell.

10. The method of claim 9, wherein:

the transition pass voltage is less than the second pass voltage;

the first pass voltage is in a range from 3 volts to 9 volts;

the second pass voltage is in a range from 7 volts to 13 volts;

the third overvoltage is in a range from 5 volts to 11 volts;

the programming voltage is in a range from 15 volts to 23 volts;

the interface pass voltage is in the range from 8 volts to 10 volts; and is

The transition pass voltage is in the range from 5 volts to 12 volts.

11. A memory device, comprising:

a memory cell string formed of memory cells, the memory cells including selected memory cells;

a voltage generator coupled to the string of memory cells; and

a controller configured to:

applying, by an address decoding circuit, a programming voltage generated by the voltage generator on a selected word line to program the selected one of the memory cells, the selected memory cell having a gate terminal coupled to the selected word line;

applying, by the address decoding circuit, a first pass voltage generated by the voltage generator on a first word line coupled to a first one of the memory cells, the first memory cell being located on a first side of the selected one of the memory cell strings;

applying, by the address decoding circuit, a second pass voltage generated by the voltage generator on a second word line coupled to a second one of the memory cells, the second memory cell located on the first side of the selected one of the memory cell strings; and

applying, by the address decoding circuit, a third pass voltage generated by the voltage generator on a third word line coupled to a third one of the memory cells, the third memory cell being located on the first side of the selected one of the memory cell strings, the second pass voltage being higher than the first pass voltage and the third pass voltage, and the second memory cell being disposed between the first memory cell and the third memory cell.

12. The memory device of claim 11, wherein the memory cell string further comprises a Bottom Select Gate (BSG) transistor and a Top Select Gate (TSG) transistor, the BSG transistor, the memory cells, and the TSG transistor being connected in series.

13. The memory device of claim 12, wherein the first, second, and third memory cells are located between the selected memory cell and the BSG transistor, the controller further configured to:

applying, by the address decoding circuit, a pass voltage generated by the voltage generator on a word line coupled to the memory cell located on a second side of the selected memory cell in the memory cell string and disposed between the selected memory cell and the TSG transistor.

14. The memory device of claim 12, wherein the first, second, and third memory cells are located between the selected memory cell and the TSG transistor, the controller further configured to:

applying, by the address decoding circuit, a pass voltage generated by the voltage generator on a word line coupled to the memory cell located on a second side of the selected memory cell in the memory cell string and disposed between the selected memory cell and the BSG transistor.

15. The storage device of claim 12, wherein the controller is further configured to:

applying, by the address decoding circuit, the first pass voltage on a fourth word line, the fourth word line coupled to a fourth one of the memory cells, the fourth memory cell located on a second side of the selected one of the strings of memory cells;

applying, by the address decoding circuit, the second pass voltage on a fifth word line, the fifth word line coupled to a fifth one of the memory cells, the fifth memory cell located on the second side of the selected one of the strings of memory cells; and

applying, by the address decoding circuit, the third pass voltage on a sixth word line coupled to a sixth one of the memory cells located on the second side of the selected one of the strings of memory cells, the fifth memory cell disposed between the fourth memory cell and the sixth memory cell.

16. The memory device of claim 15, wherein:

the first, second, and third memory cells are disposed between the selected memory cell and the BSG transistor; and is

The fourth memory cell, the fifth memory cell, and the sixth memory cell are disposed between the selected memory cell and the TSG transistor.

17. The storage device of claim 16, wherein the controller is further configured to:

applying, by the address decoding circuit, an interface pass voltage generated by the voltage generator on a first interface wordline coupled to a first interface memory cell located on the first side of the selected memory cell and disposed between the second memory cell and the third memory cell; and

applying, by the address decoding circuit, the interface pass voltage on a second interface wordline coupled to a second interface memory cell located on the second side of the selected memory cell and disposed between the fifth memory cell and the sixth memory cell.

18. The memory device of claim 17, wherein:

the interface pass voltage is in a range between the second pass voltage and the third pass voltage;

the interface pass voltage is greater than a highest program-verify voltage applied on the selected memory cell when the selected memory cell is verified; and is

The interface pass voltage at the last programming cycle of the incremental step pulse programming that programs the selected memory cell is one volt higher than the highest program-verify voltage.

19. The storage device of claim 17, wherein the controller is further configured to:

applying, by the address decoding circuit, a transition pass voltage generated by the voltage generator on a first transition word line coupled to a first transition memory cell located on the first side of the selected memory cell and disposed between the second memory cell and the first interface memory cell; and

applying, by the address decoding circuit, the transition pass voltage on a second transition word line coupled to a second transition memory cell located on the second side of the selected memory cell and disposed between the fifth memory cell and the second interface memory cell, wherein the transition pass voltage is less than the second pass voltage.

20. A storage system apparatus, comprising:

a plurality of memory devices;

a main control circuit coupled with the plurality of memory devices and configured to operate one or more of the plurality of memory devices for data generation and data transfer; and

interface circuitry coupled with the host control circuitry and configured to transfer data between the host control circuitry and an external device, wherein a memory device of the plurality of memory devices comprises:

a memory cell string formed of memory cells, the memory cells including selected memory cells;

a voltage generator coupled to the string of memory cells; and

a controller configured to:

applying, by an address decoding circuit, a programming voltage generated by the voltage generator on a selected word line to program the selected one of the memory cells, the selected memory cell having a gate terminal coupled to the selected word line;

applying, by the address decoding circuit, a first pass voltage generated by the voltage generator on a first word line coupled to a first one of the memory cells, the first memory cell being located on a first side of the selected one of the memory cell strings;

applying, by the address decoding circuit, a second pass voltage generated by the voltage generator on a second word line coupled to a second one of the memory cells, the second memory cell located on the first side of the selected one of the memory cell strings; and

applying, by the address decoding circuit, a third pass voltage generated by the voltage generator on a third word line coupled to a third one of the memory cells, the third memory cell being located on the first side of the selected one of the memory cell strings, the second pass voltage being higher than the first pass voltage and the third pass voltage, and the second memory cell being disposed between the first memory cell and the third memory cell.

Technical Field

Embodiments are described that relate generally to semiconductor memory devices.

Background

Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices may lose data when power is turned off. The nonvolatile memory device may retain stored data even if power is turned off. To achieve higher data storage densities, semiconductor manufacturers have developed vertical device technologies, such as three-dimensional (3D) NAND flash technology. The 3D NAND flash memory device is a kind of nonvolatile memory device.

Disclosure of Invention

Aspects of the present disclosure provide methods for programming a memory device including a string of memory cells. The memory cell string may include a Bottom Select Gate (BSG) transistor, a memory cell, and a Top Select Gate (TSG) transistor, which are connected in series. In the method, a programming voltage may be applied on a selected word line to program a selected one of the memory cells, wherein the selected memory cell includes a gate terminal coupled to the selected word line. A first pass voltage may be applied on a first word line coupled to a first one of the memory cells. The first memory cell may be located on a first side of the selected memory cell in the memory cell string. A second pass voltage may be applied on a second word line coupled to a second one of the memory cells, wherein the second memory cell may be located on the first side of the selected one of the strings of memory cells. In addition, a third pass voltage may be applied on a third word line, the third word line coupled to a third one of the memory cells. The third memory cell may be located at the first side of the selected memory cell in the memory cell string. The second pass voltage may be higher than the first pass voltage and the third pass voltage, and the second memory cell may be disposed between the first memory cell and the third memory cell.

In an embodiment, the first memory cell, the second memory cell, and the third memory cell may be located between the selected memory cell and the BSG transistor. A pass voltage may also be applied on a word line coupled to the memory cell located on a second side of the selected memory cell in the string of memory cells and disposed between the selected memory cell and the TSG transistor.

In another embodiment, the first memory cell, the second memory cell, and the third memory cell may be located between the selected memory cell and the TSG transistor. Accordingly, the pass voltage may be applied on a word line coupled to the memory cell located at the second side of the selected memory cell in the memory cell string and disposed between the selected memory cell and the BSG transistor.

In the method, the first pass voltage may be applied on a fourth word line coupled to a fourth one of the memory cells, wherein the fourth memory cell may be located on a second side of the selected one of the memory cell strings. The second pass voltage may be applied on a fifth word line coupled to a fifth one of the memory cells, where the fifth memory cell may be located on the second side of the selected one of the strings of memory cells. The third pass voltage may be applied on a sixth word line coupled to a sixth one of the memory cells, where the sixth memory cell may be located on the second side of the selected one of the memory cell strings. The fifth storage unit may be disposed between the fourth storage unit and the sixth storage unit. In addition, the first memory cell, the second memory cell, and the third memory cell may be disposed between the selected memory cell and the BSG transistor. The fourth memory cell, the fifth memory cell, and the sixth memory cell may be disposed between the selected memory cell and the TSG transistor.

In the method, an interface pass voltage may be applied on a first interface word line coupled to a first interface memory cell. The first interface storage unit may be located on the first side of the selected storage unit and disposed between the second storage unit and the third storage unit. In addition, the interface pass voltage may be applied on a second interface wordline coupled to a second interface memory cell. The second interface storage unit may be located at the second side of the selected storage unit and disposed between the fifth storage unit and the sixth storage unit.

In some embodiments, the interface pass voltage may be in a range between the second pass voltage and the third pass voltage.

In the method, a transition pass voltage may be applied on a first transition word line coupled to a first transition memory cell. The first transistor memory may be located on the first side of the selected memory cell and disposed between the second memory cell and the first interface memory cell. The transition pass voltage may also be applied on a second transition word line coupled to a second transition memory cell. The second transition storage unit may be located on the second side of the selected storage unit and disposed between the fifth storage unit and the second interface storage unit.

In some embodiments, the transition pass voltage may be less than the second pass voltage. The first pass voltage may be in a range from 3 volts to 9 volts. The second pass voltage may be in the range from 7 volts to 13 volts. The third pass overvoltage may be in a range from 5 volts to 11 volts. The programming voltage may range from 15 volts to 23 volts. The interface pass voltage may range from 8 volts to 10 volts. The transition pass voltage may range from 5 volts to 12 volts.

According to another aspect of the present disclosure, a memory device is provided. The memory device may include a memory cell string, wherein the memory cell string includes a Bottom Select Gate (BSG) transistor, a memory cell including a selected memory cell, and a Top Select Gate (TSG) transistor, the Bottom Select Gate (BSG) transistor, the memory cell, and the Top Select Gate (TSG) transistor being connected in series. The memory device may further include a voltage generator coupled to the memory cell string and a controller. The controller is configured to: applying, by an address decoding circuit, a programming voltage generated by the voltage generator on a selected word line to program the selected one of the memory cells. The selected memory cell includes a gate terminal coupled to the selected word line. The controller applies a first pass voltage generated by the voltage generator through the address decoding circuit on a first word line coupled to a first one of the memory cells. The controller may also apply, by the address decoding circuit, a second pass voltage generated by the voltage generator on a second word line coupled to a second one of the memory cells. The controller may apply a third pass voltage generated by the voltage generator through the address decoding circuit on a third word line coupled to a third one of the memory cells. The first, second, and third memory cells may be located on the first side of the selected memory cell in the memory cell string. The second pass voltage may be higher than the first pass voltage and the third pass voltage, and the second memory cell may be disposed between the first memory cell and the third memory cell.

In an embodiment, the first, second, and third memory cells are located between the selected memory cell and the BSG transistor, and the controller may be further configured to: applying, by the address decoding circuit, a pass voltage generated by the voltage generator on a word line coupled to the memory cell located on a second side of the selected memory cell in the memory cell string and disposed between the selected memory cell and the TSG transistor.

In another embodiment, when the first, second and third memory cells are located between the selected memory cell and the TSG transistor, the controller may be further configured to: applying, by the address decoding circuit, a pass voltage generated by the voltage generator on a word line coupled to the memory cell located on a second side of the selected memory cell in the memory cell string and disposed between the selected memory cell and the BSG transistor.

In some embodiments, the controller may be further configured to apply, by the address decoding circuit, the first pass voltage on a fourth word line, the fourth word line coupled to a fourth one of the memory cells. The controller may apply the second pass voltage on a fifth word line through the address decoding circuit, the fifth word line coupling a fifth one of the memory cells. The controller may apply the third pass voltage on a sixth word line coupled to a sixth one of the memory cells through the address decoding circuit. The fourth, fifth, and sixth memory cells may be located at the second side of the selected memory cell in the memory cell string. The fifth storage unit may be disposed between the fourth storage unit and the sixth storage unit. In addition, the first memory cell, the second memory cell, and the third memory cell may be disposed between the selected memory cell and the BSG transistor. The fourth memory cell, the fifth memory cell, and the sixth memory cell may be disposed between the selected memory cell and the TSG transistor.

In some embodiments, the controller may be further configured to apply, by the address decoding circuit, the interface pass voltage generated by the voltage generator on a first interface wordline coupled to the first interface memory cell. The first interface storage unit may be located on the first side of the selected storage unit and disposed between the second storage unit and the third storage unit. The controller may also apply, via the address decode circuit, the interface pass voltage on a second interface wordline coupled to a second interface memory cell. The second interface storage unit may be located at the second side of the selected storage unit and disposed between the fifth storage unit and the sixth storage unit. Further, the interface pass voltage may be in a range between the second pass voltage and the third pass voltage.

In some embodiments, the controller may be further configured to apply, by the address decoding circuit, the transition pass voltage generated by the voltage generator on a first transition word line coupled to the first transition memory cell. The first transition storage unit may be located on the first side of the selected storage unit and disposed between the second storage unit and the first interface storage unit. The controller may apply the transition pass voltage on a second transition word line coupled to a second transition memory cell through the address decoding circuit, wherein the second transition memory cell may be located on the second side of the selected memory cell and disposed between the fifth memory cell and the second interface memory cell.

In some embodiments, the transition pass voltage may be less than the second pass voltage. The first pass voltage may be in a range from 3 volts to 9 volts. The second pass voltage may be in the range from 7 volts to 13 volts. The third pass overvoltage may be in a range from 5 volts to 11 volts. The programming voltage may range from 15 volts to 23 volts. The interface pass voltage may range from 8 volts to 10 volts. The transition pass voltage may range from 5 volts to 12 volts.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased for clarity of discussion.

Fig. 1 illustrates a block diagram of a semiconductor memory device according to some exemplary embodiments of the present disclosure.

Fig. 2 illustrates a cross-sectional view of a semiconductor memory device and schematic symbols of a memory cell string according to some exemplary embodiments of the present disclosure.

Fig. 3 illustrates a schematic diagram of programming a memory cell string in a related example, according to some example embodiments of the present disclosure.

Fig. 4 illustrates a first schematic diagram of programming a string of memory cells, according to some example embodiments of the present disclosure.

Fig. 5 illustrates a second schematic diagram of programming a string of memory cells, according to some example embodiments of the present disclosure.

Fig. 6 illustrates a third schematic diagram of programming a string of memory cells, according to some example embodiments of the present disclosure.

Fig. 7 illustrates a fourth schematic diagram of programming a string of memory cells, according to some example embodiments of the present disclosure.

Fig. 8 illustrates a fifth schematic diagram of programming a string of memory cells, according to some example embodiments of the present disclosure.

Fig. 9 shows a flowchart outlining a method for programming a semiconductor memory device according to some example embodiments of the present disclosure.

FIG. 10 shows a block diagram of a memory system device, according to some demonstrative embodiments of the disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein to facilitate description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Aspects of the present disclosure provide semiconductor memory devices and techniques for operating semiconductor memory devices. In general, a semiconductor memory device includes a memory cell array portion and a peripheral circuit portion. The peripheral circuit portion interfaces the memory cell array portion with external circuits and provides various controls (e.g., write/program, erase, and read) to the memory cell array portion.

According to some aspects of the present disclosure, the memory cell array portion includes memory cells configured to store a plurality of binary bits in each of the memory cells. Generally, a memory cell can be configured in two states to store a binary bit, and can also be configured in more than two states to store multiple binary bits. In an example, each memory cell is configured to store two binary bits, and the memory cells can be configured into four states based on the threshold voltage of the memory cell. For example, the memory cell can be erased and have a threshold voltage within a first range (e.g., [ -3V, -1V ]) corresponding to a first state of two bits (e.g., binary "11"); the memory cell can be programmed to have a threshold voltage within a second range (e.g., [0V, 1V ]) corresponding to a second state (e.g., binary "01") of the two bits; the memory cell can be programmed to have a threshold voltage within a third range (e.g., [1V, 2V ]) corresponding to a third state (e.g., binary "10") of the two bits; and the memory cell can be programmed to have a threshold voltage within a fourth range (e.g., [2V, 3V ]) corresponding to a fourth state (e.g., binary "00") of the two bits.

It should be noted that although two binary bits are used in some examples of the present disclosure, the present disclosure is not limited to two binary bits. In some examples, each memory cell may be similarly configured to store another suitable number of binary bits, such as three bits, four bits, and so on.

According to aspects of the present disclosure, multiple binary bits may be written/programmed to selected memory cells using a program-verify cycle. Each program-verify cycle includes a programming step and a verifying step. In the programming step, a programming pulse (e.g., having a pulse voltage higher than 18V) may be applied to the gate terminal of the memory cell with other suitable bias voltages to appropriately increase the threshold voltage, for example, by injecting electrons into the floating gate of the memory cell. In the verify step, a verify voltage may be applied to the gate terminal with other suitable bias voltages to determine whether the threshold voltage of the memory cell is within a suitable range. When the threshold voltage is out of the proper range on the lower side (e.g., the memory cell is turned off in response to the verify voltage), another program-verify cycle may be performed. A program-verify cycle may be performed until the threshold voltage of the memory cell is within an appropriate range (e.g., the memory cell turns on in response to a verify voltage). In some examples, the voltage level of the programming pulse may be adjusted, such as using an Incremental Step Pulse Programming (ISPP) technique.

In order to prevent other memory cells from being programmed while programming a selected memory cell, which may be connected in series to the selected memory cell, a program inhibit operation or a boosting operation may be applied to the other memory cells. For example, the voltage potential of the source/drain regions of other memory cells may be raised to a higher value (e.g., 6-8V) to reduce the field across the channel regions of the other memory cells. In another example shown in fig. 3, a local boosting operation may be applied, which may electrically isolate charge sharing of the channel between the selected memory cell and other memory cells.

Fig. 1 illustrates a block diagram of a semiconductor memory device 100 according to some embodiments of the present disclosure. The semiconductor memory device 100 includes a memory cell array 102 and peripheral (also referred to as peripheral) circuitry 101 coupled together. In some examples, the memory cell array 102 and the peripheral circuitry 101 are disposed on the same die (chip). In other examples, the memory cell array 102 is disposed on an array die and the peripheral circuitry 101 is disposed on a different die, such as a die implemented using Complementary Metal Oxide Semiconductor (CMOS) technology and referred to as a CMOS die. The array die and the CMOS die are suitably bonded and electrically coupled together. An example of a bonded array die and CMOS die will be described with reference to fig. 2.

In some examples, a CMOS die may be coupled with multiple array dies. In an embodiment, the semiconductor memory device 100 is an Integrated Circuit (IC) package that encapsulates one or more array die and one or more CMOS die.

The semiconductor memory device 100 is configured to store data in the memory cell array 102 and perform an operation in response to a received Command (CMD). In some examples, the semiconductor memory device 100 may receive a write command (also referred to as a program command in some examples), a read command, an erase command, and the like, and operate accordingly. In an example, the semiconductor memory device 100 receives a write command having an Address (ADDR) and DATA (DATA), and then the semiconductor memory device 100 stores the DATA in the memory cell array 102 at the address. In another example, the semiconductor memory device 100 receives a read command having an address, and then the semiconductor memory device 100 accesses the memory cell array 102 and outputs data stored at the address of the memory cell array 102. In another example, the semiconductor memory device 100 receives an erase command having an address, and the semiconductor memory device 100 then resets one or more memory cell blocks at the address to an unprogrammed state (also referred to as an erase state), such as "1" in 1 bit, "11" in 2 bit, "111" in 3 bit, and the like in the NAND flash technology.

In general, memory cell array 102 may include one or more memory planes 160, and each memory plane 160 may include a plurality of memory blocks, such as block-1 through block-N shown in FIG. 1. In some examples, concurrent operations may occur at different storage planes 160. In some embodiments, each of the memory blocks-1 through-N is the smallest unit to perform an erase operation. Each memory block includes a plurality of pages. In some examples, a page is the smallest unit that can be programmed. In an example, memory cells of a page may share a wordline.

In some embodiments, the memory cell array 102 is a flash memory array and is implemented using 3D NAND flash memory technology. Each of memory blocks-1 through-N includes a plurality of memory cell strings arranged vertically (e.g., orthogonal to a major surface of the die). Each memory cell string includes a plurality of transistors connected in series. Details of the memory cell string may be described with reference to fig. 2.

In some embodiments, peripheral circuitry 101 includes interface circuitry 110 and controller 120 coupled together.

The interface circuit 110 includes appropriate circuits to interface with the memory cell array 102 or with components external to the semiconductor memory device 100 (e.g., the host device 180). In some examples, the interface circuit 110 includes a first portion that interfaces with the host device 180 and is referred to as a host interface, and a second portion that interfaces with the memory cell array 102 and is referred to as an array interface. In the example of FIG. 1, interface circuit 110 includes a command decode circuit 114, an address decode circuit 115, a page buffer circuit 112, a data input/output (I/O) circuit 111, and a voltage generator 113 coupled together as shown in FIG. 1.

In some examples, the address decode circuitry 115 may receive an Address (ADDR) from an I/O pin coupled to external circuitry (e.g., the host device 180) and perform decoding of the address. In some examples, the address decode circuitry 115 may operate with the controller 120 to perform decoding of addresses. In some embodiments, the address received from host device 180 is a file system logical block address. In some examples, address decode circuitry 115 and controller 120 may perform the functions of a Flash Translation Layer (FTL) to translate block addresses used by a file system to addresses of physical units in memory cell array 102. In an example, a translation from a block address used by the file system to a physical unit in the storage cell array 102 may be used to exclude bad storage cells. In some embodiments, the addresses of the physical units are in the form of row addresses (R-ADDR) and column addresses (C-ADDR). In response to the row address, the address decoding circuit 115 may generate a Word Line (WL) signal and a selection signal, such as a Top Selection Gate (TSG) signal, a Bottom Selection Gate (BSG) signal, and the like, based on the row address, and supply the WL signal and the selection signal to the memory cell array 102. In some examples, during a write operation, address decode circuit 115 provides a WL signal and a select signal to memory cell array 102 to select a page to be programmed. During a read operation, the address decoding circuit 115 may provide a WL signal and a select signal to select a page for buffering. During an erase operation, address decode circuitry 115 may provide the appropriate WL signal and select signal.

The page buffer circuit 112 is coupled to Bit Lines (BL) of the memory cell array 102 and is configured to buffer data, such as data of one or more pages, during read and write operations. In an example, during a write operation, page buffer circuitry 112 may buffer data to be programmed and drive the data to bit lines of memory cell array 102 to write the data into memory cell array 102. In another example, during a read operation, page buffer circuitry 112 may sense data on bit lines of memory cell array 102 and buffer the sensed data for output.

In some embodiments, page buffer circuitry 112 includes latch circuitry associated with the bit lines. The value in the latch circuit may indicate the programmed state. For example, during a write operation to write data to a memory cell in a memory string connected to a bit line, when a program-verify cycle is used, the latch circuit associated with the bit line may switch a value, such as from "0" to "1", in response to the turning on of the memory cell (e.g., the memory cell is sufficiently programmed) in a verify step of the program-verify cycle. When the latch circuit has a switching value (e.g., "1"), further programming of the memory cell is inhibited. In some examples, the latch circuit may hold the switching value (e.g., "1") for the remainder of the write operation. In an example, when all latch circuits have a value of "1", data (e.g., page data) in the page buffer circuit 112 has been written to the memory cell array 102.

In the example of FIG. 1, data I/O circuit 111 is coupled to page buffer circuit 112 via Data Lines (DL). In an example (e.g., during a write operation), the data I/O circuit 111 is configured to receive data from an external circuit (e.g., a host device (device)180) of the semiconductor memory device 100 and provide the received data to the memory cell array 102 via the page buffer circuit 112. In another example (e.g., during a read operation), the data I/O circuit 111 is configured to output data from the memory cell array 102 to an external circuit (e.g., the host device 180) based on the column address (C-ADDR).

The voltage generator 113 is configured to generate a voltage of an appropriate level for an appropriate operation of the semiconductor memory device 100. For example, during a read operation, the voltage generator 113 may generate voltages of appropriate levels, such as a source voltage, a body voltage (body voltage), various WL voltages, a select voltage, and the like, for the read operation. In some examples, during a read operation, the source voltage is provided to the source terminal of the memory cell array 102 as an Array Common Source (ACS) voltage; during a read operation, a bulk voltage is supplied to, for example, a P-type well (PW) which is a bulk portion of the memory cell string. The WL voltage and the select voltage are supplied to the address decoding circuit 115, and thus the address decoding circuit 115 may output the WL signal and the select signal (e.g., the TSG signal and the BSG signal) at appropriate voltage levels during a read operation.

In another example, during an erase operation, the voltage generator 113 may generate voltages of appropriate levels, such as a source voltage, a body voltage, various WL voltages, a select voltage, a BL voltage, and the like, which are appropriate for the erase operation. In some examples, during an erase operation, the source voltage is provided as an ACS voltage to the source terminal of the memory cell array 102; during an erase operation, the PW voltage is supplied to a P-type well, which is the body portion of the memory cell string. The WL voltage and the selection voltage are supplied to the address decoding circuit 115, so the address decoding circuit 115 can output the WL signal and the BSG and TSG signals at appropriate voltage levels during the erase operation. The BL voltage is supplied to the page buffer circuit 112, so the page buffer circuit 112 can drive the Bit Line (BL) at an appropriate voltage level during the erase operation. Note that in some examples, the BL voltage may be applied to the bit line without passing through the page buffer circuit 112.

In another example, during a write operation, the voltage generator 113 may generate voltages of appropriate levels suitable for the write operation, such as a source voltage, a body voltage, various WL voltages, a select voltage, a BL voltage, a verify voltage, a reference voltage, and the like. In some examples, during a write operation, the source voltage is provided as an ACS voltage to the source terminal of the memory cell array 102; during a write operation, the PW voltage is supplied to a P-type well, which is the bulk portion of the memory cell string. The WL voltage, the selection voltage, and the verification voltage are supplied to the address decoding circuit 115, so the address decoding circuit 115 can output the WL signal and the BSG and TSG signals at appropriate voltage levels during a write operation. The BL voltage and the reference voltage are supplied to the page buffer circuit 112, so the page buffer circuit 112 can drive the Bit Line (BL) at an appropriate voltage level during a write operation and can sense a program state in a verify step during the write operation.

In some embodiments, command decoding circuitry 114 is configured to receive a Command (CMD) from, for example, host device 180 via the I/O pins during a command cycle. In some embodiments, the I/O pins may transmit other information, such as an address in an address cycle, data in a data cycle. In some embodiments, the received command is a command according to some high-level protocol (e.g., the USB protocol).

In some embodiments, command decoding circuitry 114 and controller 120 may operate together to decode received commands. In an example, command decoding circuitry 114 performs an initial decoding of the received command, and the command decoded by command decoding circuitry 114 is provided to controller 120 for further processing. The controller 120 may perform further decoding and then generate control parameters based on the commands for controlling other circuits such as the page buffer circuit 112, the data I/O circuit 111, the voltage generator 113, and the like.

In some embodiments, the controller 120 may control the voltage generator 113 to generate a voltage of an appropriate level based on the command. The controller 120 may coordinate other circuitry to provide signals to the memory cell array 102 at the appropriate time and at the appropriate voltage levels.

In the example of fig. 1, controller 120 includes read control 121, erase control 122, and write control 123. In an example, in response to a read command, the read control 121 may generate a control parameter for generating a control signal to read data from the memory cell array 102. In another example, in response to a write command, the write control 123 may generate a control parameter for generating a control signal to write data to the memory cell array 102. In another example, in response to an erase command, the erase control may generate control parameters for generating control signals to erase one or more blocks of the array of memory cells 102.

The controller 120 may be implemented using any suitable technology.

In some examples, the controller 120 is implemented as a microcontroller unit (MCU) (not shown) and a Firmware (FW) memory (not shown). The MCU may include one or more processing cores, and the FW memory stores firmware executable by the one or more processing cores. For example, the firmware includes a read module, a write module, and an erase module. The MCU may run a read module to perform the functions of read control 121. The MCU may run the write module to perform the functions of the write control 123. The MCU may run the erase module to perform the functions of erase control 122.

Note that the FW memory may be implemented using any suitable non-volatile memory that can retain stored data even when power is turned off. In an example, the FW memory is implemented using a Read Only Memory (ROM). In another example, the FW memory is implemented using a programmable ROM. In another example, the FW memory is implemented using an erasable programmable ROM.

In some embodiments, the controller 120 may be implemented using logic circuitry. In some examples, some portions of the controller 120 or the entire controller 120 may be implemented by logic circuitry that may have a much faster processing speed than firmware-based implementations. In an example, some functions of the controller 120 may be implemented using programmable logic units that provide flexible development planning and fast processing speeds.

According to some aspects of the present disclosure, write control 123 is configured to determine a verify start cycle of a state (e.g., a state for programming a plurality of binary bits in a memory cell) based on a sensing result from programming to one or more word lines in a group of word lines. The determined verify start cycle of states may be stored in association with the set of word lines. Then, to program the word lines in the word line group later, write control 123 may use a program-verify cycle along with a verify start cycle of the state.

In some embodiments, write control 123 includes a group-based verify start cycle determination module 130 and memory 140 (or allocated storage space in memory). In an embodiment, the group-based verify start cycle determination module 130 is configured to detect a first write to a word line in the word line group (e.g., after the semiconductor memory device 100 is powered on), and perform a first program-verify cycle using a default verify start cycle of states (e.g., an earliest verify start cycle of states) and write data to the word line. Further, the group-based verification start cycle determination module 130 may monitor results, such as sensing results, values in latch circuits of the page buffer circuit 112, and the like, and determine a verification start cycle for the update of the states. The updated verify start cycle for the state may be stored in memory 140 in association with the group of word lines, such as the group-based verify start cycle for state 145 in FIG. 1. Thus, later, to further write to a word line in the set of word lines (e.g., the same word line as the first write, or other word line), a program-verify loop may be performed using a verify start loop of the update of the state for writing to the word line.

The verification start cycle for the update of the state may be determined based on various suitable techniques. In some examples, at each program-verify cycle of the first program-verify cycle, the total number of open memory cells (e.g., fully programmed memory cells) of a word line may be counted for each state, e.g., based on a value in a latch circuit of page buffer circuit 112. In a particular program-verify cycle, when the total number of open memory cells of a state increases to be equal to or greater than a threshold value, the particular program-verify cycle may be determined as a verify start cycle of the update of the state.

According to aspects of the present disclosure, word lines of similar programming speed may form a word line group. Thus, when a verify start cycle of a state is determined based on writing to one word line in the set of word lines, any word line in the set of word lines in the example may be written in a program-verify cycle using the determined verify start cycle of the state. In some examples, programming speeds of memory cells at different word lines may be characterized by a manufacturer of the semiconductor memory device, and then the word lines may be divided into word line groups based on the programming speed characterization.

In some examples, the set of word lines may be defined using addresses of word lines in the set of word lines. The definition of the word line group may be suitably stored on each semiconductor memory device. In an example, the definition of the word line group may be stored in a special partition (partition) of the memory cell array 102. For example, memory cell array 102 includes an initialization partition 165. The initialization partition 165 is a portion of the memory cell array 102 that can be loaded to the peripheral circuits 101 when the semiconductor memory device 100 is powered on. In some examples, at power up, information in initialization partition 165 is loaded into peripheral circuitry 101 to configure peripheral circuitry 101. In an example, a definition of a group of word lines may be stored in initialization partition 165 and loaded into peripheral circuitry 101 at power up. In another example, the definition of the set of word lines may be implemented explicitly or implicitly in firmware. In some embodiments, the definition of the set of word lines is stored in a non-volatile form so that the definition of the set of word lines is not lost when power is removed.

In some examples, the groups of word lines may be block-based, and each group of word lines includes one or more blocks, such as one or more of block-1 through block-N in fig. 1. In some examples, the groups of word lines may be word line based, and each group of word lines includes a plurality of word lines. In another example, the groups of word lines may be based on a single word line, and each group of word lines includes a single word line.

In some embodiments, the verification start cycle of the determination of the state may be stored in volatile form. In an example, memory 140 is implemented using Static Random Access Memory (SRAM). In another example, memory 140 is implemented using suitable register circuitry. The verification start cycle of the state may then be re-determined and stored after each power-up. Therefore, when a change in programming speed occurs, such as due to an increase in PE cycles, the verify start cycle of the state can be re-determined at each power-on time to compensate for the change in programming speed.

Note that in some examples, group-based authentication start loop determination module 130 is implemented as firmware to be executed by a processor; in some other examples, the group-based verification start cycle determination module 130 is implemented using circuitry.

Fig. 2 illustrates a cross-sectional view of a semiconductor memory device 200 according to some embodiments of the present disclosure. In some examples, the semiconductor memory device 200 may be the semiconductor memory device 100. According to some embodiments of the present disclosure, a semiconductor memory device 200 includes an array die 202 and a CMOS die 201 bonded together.

Note that in some embodiments, the semiconductor memory device may include a plurality of array dies and CMOS dies. Multiple array dies and CMOS dies may be stacked and bonded together. The CMOS dies are respectively coupled to a plurality of array dies, and the respective array dies can be driven to operate in a similar manner as the semiconductor memory device 200.

The array die 202 includes a substrate 203 and memory cells formed on the substrate 203. CMOS die 201 includes a substrate 204 and peripheral circuitry formed on substrate 204. For simplicity, the major surface of the substrate 203 is referred to as the X-Y plane, and the direction perpendicular to the major surface is referred to as the Z direction (or Z axis).

Substrate 203 and substrate 204 may each be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. The substrate 203 and the substrate 204 may each include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. The group IV semiconductor may include Si, Ge, or SiGe. Substrate 203 and substrate 204 may be bulk wafers or epitaxial layers, respectively.

The semiconductor memory device 200 includes a memory cell array (e.g., the memory cell array 102) and peripheral circuits (e.g., an address decoding circuit, a page buffer circuit, a data I/O circuit, a voltage generator, a main controller, etc.). In the example of fig. 2, the array of memory cells is formed on a substrate 203 of an array die 202 and the peripheral circuitry is formed on a substrate 204 of a CMOS die 201. The array die 202 and CMOS die 201 are placed face-to-face (the surface on which the circuitry is placed is referred to as the face and the opposite surface is referred to as the back) and bonded together.

In some examples, wells may be formed in the substrate 203 for the blocks, respectively, as a body portion of the blocks. In the figure. In the example of fig. 2, a P-well 205 is formed in substrate 203, and a block of three-dimensional (3D) NAND memory cell strings may be formed in P-well 205. A P-type well 205 may form a body portion (e.g., connected to a PW terminal) for a 3D NAND memory cell string, and a voltage referred to as PW may be applied to P-type well 205 via the PW terminal. In some examples, the memory cell array is formed as an array of vertical memory cell strings in the core region 206. In addition to the core region 206 and the peripheral region, the array die 202 includes a stepped region 207 (also referred to as a connection region in some examples) to facilitate connection to, for example, the gates of memory cells in a vertical string of memory cells, the gates of select transistors, and so forth. The gates of the memory cells in the vertical memory cell string correspond to word lines for a NAND memory architecture.

In the example of fig. 2, the vertical memory cell string 280 is shown as a representation of an array of vertical memory cell strings formed in the core region 206. FIG. 2 also shows a schematic symbolic version of a vertical memory cell string 280' corresponding to the vertical memory cell string 280. Vertical strings of storage cells 280 are formed in layer stack 290. Layer stack 290 includes gate layers (or word line layers) 295 and insulating layers 294 that are alternately stacked. The gate layer 295 and the insulating layer 294 are configured to form a vertically stacked transistor. In some examples, the transistor stack includes storage cells and select transistors, such as one or more bottom select transistors (also referred to as bottom select gate transistors), one or more top select transistors (also referred to as top select gate transistors), and so forth. In some examples, the transistor stack may include one or more dummy select transistors. The gate layer 295 corresponds to a gate of a transistor. The gate layer 295 is made of a gate stack material, such as a high dielectric constant (high-k) gate insulating layer, a Metal Gate (MG) electrode, or the like. The insulating layer 294 is made of an insulating material such as silicon nitride, silicon dioxide, or the like.

According to some aspects of the present disclosure, a vertical string of storage cells is formed from a channel structure 281 extending vertically (Z-direction) into layer stack 290. The channel structures 281 may be disposed apart from each other in the X-Y plane. In some embodiments, the channel structures 281 are disposed in an array between the gate line cutting structures (not shown). The gate line cutting structure is used to facilitate replacement of the sacrificial layer with the gate layer 295 in a post-gate process. The array of channel structures 281 may have any suitable array shape, such as a matrix array shape in the X-direction and Y-direction, a zigzag array shape in the X-or Y-direction, a honeycomb (e.g., hexagonal) array shape, and so on. In some embodiments, each channel structure has a circular shape in the X-Y plane and a columnar shape in the X-Z plane and the Y-Z plane. In some embodiments, the number and arrangement of channel structures between gate line cutting structures is not limited.

In some embodiments, the channel structure 281 may have a columnar shape extending in a Z direction orthogonal to the direction of the main surface of the substrate 203. In an embodiment, the channel structure 281 is formed of a circular material in the XY plane and extends in the Z direction. For example, channel structure 281 is includedFunctional layers having a circular shape in the XY plane and extending in the Z direction, such as a blocking insulating layer 282 (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride) 283, a tunnel insulating layer 284 (e.g., silicon oxide), a semiconductor layer 285, and an insulating layer 286. In an example, a blocking insulating layer 282 (e.g., silicon oxide) is formed on sidewalls of the hole (into the layer stack 290) for the channel structure 281, and then a charge storage layer (e.g., silicon nitride) 283, a tunnel insulating layer 284, a semiconductor layer 285, and an insulating layer 286 are sequentially stacked from the sidewalls. The semiconductor layer 285 may be any suitable semiconductor material, such as polysilicon or monocrystalline silicon, and the semiconductor material may be undoped or may include p-type or n-type dopants. In some examples, the semiconductor material is an undoped intrinsic silicon material. However, due to defects, in some examples, the intrinsic silicon material has a carrier density of 10¹⁰cm^-3Of the order of magnitude of (d). The insulating layer 286 is formed of an insulating material such as silicon oxide and/or silicon nitride, and/or may be formed as an air gap.

According to some aspects of the present disclosure, channel structure 281 and layer stack 290 together form a memory cell string 280. For example, the semiconductor layer 285 corresponds to a channel portion for a transistor in the memory cell string 280, and the gate layer 295 corresponds to a gate of the transistor in the memory cell string 280. Typically, a transistor has a gate that controls the channel, and has a drain and a source on each side of the channel. For simplicity, in the example of fig. 2, the upper side of the channel for the transistor in fig. 2 is referred to as the drain, and the bottom side of the channel for the transistor in fig. 2 is referred to as the source. Note that under some drive configurations, the drain and source can be switched. In the example of fig. 2, the semiconductor layer 285 corresponds to a connected channel of a transistor. For a particular transistor, the drain of the particular transistor is connected to the source of the upper transistor above the particular transistor, and the source of the particular transistor is connected to the drain of the lower transistor below the particular transistor. Thus, the transistors in the memory cell string 280 are connected in series.

The memory cell string 280 includes memory cell transistors (or referred to as memory cells). The memory cell transistors may have different threshold voltages based on carrier trapping in portions of the charge storage layer 283 corresponding to floating gates of the memory cell transistors. For example, when a large number of holes are trapped (stored) in the floating gate of the memory cell transistor, the threshold voltage of the memory cell transistor is below a predetermined value, and the memory cell transistor is in an unprogrammed state (also referred to as an erased state), which corresponds to logic "11" in two binary bits. When holes are drained from the floating gate (or electrons are trapped in the floating gate), the threshold voltage of the memory cell transistor is raised so that the memory cell transistor can be programmed to other suitable states, e.g., S2, S3, etc.

Memory cell string 280 includes one or more top select transistors configured to couple/decouple memory cells in memory cell string 280 from bit lines, and includes one or more bottom select transistors configured to couple/decouple memory cells in memory cell string 280 from ACS.

The top select transistor is controlled by a Top Select Gate (TSG). For example, when the TSG voltage (the voltage applied to the TSG) is greater than the threshold voltage of the top select transistor, the top select transistor turns on and the memory cell is coupled to the bit line; and when the TSG voltage (the voltage applied to the TSG) is less than the threshold voltage of the top select transistor, the top select transistor turns off and the memory cell is decoupled from the bit line.

Similarly, the bottom select transistor is controlled by a Bottom Select Gate (BSG). For example, when the BSG voltage (the voltage applied to the BSG) is greater than the threshold voltage of the bottom select transistor, the bottom select transistor turns on and the memory cell couples to ACS; and when the BSG voltage (the voltage applied to the BSG) is less than the threshold voltage of the bottom select transistor, the bottom select transistor is turned off and the memory cell is decoupled from the ACS.

According to some aspects of the present disclosure, a bottom portion of the semiconductor layer 285 in the channel hole corresponds to a source side of the vertical memory cell string 280, and the bottom portion is labeled 285 (S). A common source layer 289 is formed in conductive connection with the source of the vertical cell string 280. The common source layer 289 may include one or more layers. In some examples, common source layer 289 includes a silicon material, such as intrinsic polysilicon, doped polysilicon (such as N-type doped silicon, P-type doped silicon), or the like. In some examples, common source layer 289 may include a metal silicide to improve conductivity. The common source layer 289 is similarly conductively connected with the sources of other vertical strings of memory cells (not shown) and thereby forms an Array Common Source (ACS).

In some examples, when the vertical string of memory cells 280 is configured to be erased on a block basis, the common source layer 289 may extend and cover a core area of the block and a staircase area for the block. In some examples, for different blocks that are erased separately, the common source layer 289 may be suitably insulated for the different blocks.

As in the example of fig. 2, in the channel structure 281, the semiconductor layer 285 vertically extends upward from a source side of the channel structure 281 and forms a top portion corresponding to a drain side of the vertical memory cell string 280. The top portion of the semiconductor layer 285 is labeled 285 (D). Note that for ease of description, the drain side and source side are named. The drain side and source side may function differently than the names.

In the example of fig. 2, connection structures such as via structures 272a and metal lines 273a, bond structures 274, and the like may be formed to electrically couple the top portion 285(D) of the semiconductor layer to a Bit Line (BL).

Further, in the example of fig. 2, the stair-step region 207 includes a stair-step formed to facilitate word line connections to the gates of transistors (e.g., memory cell, top select transistor(s), bottom select transistor (s)). For example, word line connection structure 270 includes contact structure 271, via structure 272b, and metal line 273b conductively coupled together. The word line connection structure 270 may electrically couple the WL to the gate terminal of the transistor in the memory cell string 280.

In the example of fig. 2, the array die 202 and CMOS die 201 are placed face-to-face (circuit side is the face and substrate side is the back) and bonded together. Typically, peripheral circuitry on the CMOS die interfaces the semiconductor memory device 200 with external circuitry.

In the example of fig. 2, CMOS die 201 and array die 202 each include bonding structures that may be aligned with each other. For example, CMOS die 201 includes bonding structures 234 and array die 202 includes corresponding bonding structures 274. Array die 202 and CMOS die 201 may be properly aligned so that bonding structures 234 are aligned with bonding structures 274. When the array die 202 and the CMOS die 201 are bonded together, the bonding structures 234 are bonded and electrically coupled to the bonding structures 274, respectively.

Fig. 3 illustrates a schematic diagram of programming a memory cell string in a related example, according to some example embodiments of the present disclosure. As shown in fig. 3, the memory cell string 300 may include a Bottom Select Gate (BSG) transistor, memory cells MC1-MC11 that include a selected memory cell MC6 to receive a program operation, and a Top Select Gate (TSG) transistor connected in series. The memory cell string 300 may also include a bottom dummy cell adjacent to the BSG transistor and/or a top dummy cell adjacent to the TSG transistor. When present, the bottom dummy cells may work with the BSG to control the connection between the memory cell string 300 and the source line. When present, the top dummy cell may work with the TSG to control the connection between the memory cell string 300 and the bit line. Note that fig. 3 is an example only, and that memory cell string 300 may include any number of memory cells, one or more bottom dummy cells, and one or more top dummy cells, depending on the design of the memory device.

In a related example, memory cells MC1-MC5 and MC7-MC11 may be pre-programmed or may be memory cells that are not selected for programming, and the selected memory cell MC6 is to be programmed. Accordingly, a local boosting operation may be applied to the memory cell string 300 to form a program-inhibited channel in the programmed memory cells, so that the programmed memory cells may be prevented from being programmed. The local boosting operation is configured to introduce a Vlocal voltage to electrically isolate charge sharing of the channel between the programmed memory cell (e.g., MC1-MC5 and MC7-MC11) and the other remaining memory cells (e.g., MC6) selected for programming. In the local boosting operation, Vlocal voltage may be zero volts applied to at least one programmed memory cell adjacent to a selected memory cell. For example, the Vlocal voltage can be applied to one of the memory cells MC3 and MC9, or to both of the memory cells MC3 and MC9 that are located adjacent to the selected memory cell MC 6. Accordingly, a channel stop may be formed in the memory cell string 300. For example, when Vlocal is applied across MC3, charge sharing of the channel in memory cell string 300 may be broken by MC3, and the channel in memory cell string 300 may be divided into a first portion between MC1 and MC3, and a second portion between MC4 and MC 11.

When a local boosting operation is applied, a high channel boosting voltage can be established for the programmed memory cells (e.g., MC1-MC5 and MC7-MC11), which can reduce the electric field of the tunnel layer across the channel so that programming can be inhibited. However, a channel potential difference between the programmed cell and the selected memory cell may increase, and severe Hot Carrier Injection (HCI) may occur from the memory cell (e.g., MC3) to which Vlocal is applied to the selected memory cell (e.g., MC 6). Severe hot carrier injection can further lead to more severe program disturb. In FIG. 2, an exemplary channel potential profile 302 is provided in which the channel potential difference is increased between the selected memory cell MC6 and the memory cell MC3 to which Vlocal is applied. Severe hot carrier injection may occur due to the increased channel potential difference between the selected memory cell MC6 and the memory cell MC3 to which Vlocal is applied. For example, due to the increased channel potential difference, electrons in the channel (or charge storage layer of the channel) of MC3 may be injected into the channel of memory cell MC 6.

In the present disclosure, a bell-shaped pass voltage pattern may be applied when programming a string of memory cells. In the bell-shaped pass voltage pattern, the Vpass voltage applied on the Word Line (WL) coupled to the memory cells may be modulated in a "bell-shaped" form along the WL, which varies in a direction from the word line (or programmed WL) of the programmed cell in the drain side or source side of the memory cell string. The WL may be configured to have a plurality of regions, such as region 1, region 2, and region 3, defined from a word line of selected memory cells (also referred to as a selected program WL), and each of the plurality of regions may include at least one memory cell. The voltage Vpass in the middle area 2 may be higher than the Vpass voltages in the areas 1 and 3. By boosting the Vpass voltage in region 2, the potential difference between the programmed WL and the adjacent WL (e.g., the selected programmed WL) can be suppressed, which in turn can suppress HCI and lead to better program disturb.

For example, the Vpass voltage can be modulated by placing the WL of region 1, the WL of region 2, and the WL of region 3 down or up from the selected programmed WL. Further, the Vpass voltage in (or applied to) the WL of region 2 may be higher than the Vpass voltage in the WL of region 3.

In the bell-shaped pass voltage pattern, when the Vpass voltage in the WL of the region 2 is higher than the Vpass voltage in the WL of the region 3, the Vpass voltage in the WL of the region 3 may be sufficiently high to connect the channel in the WL of the region 2 and the channel in the WL of the region 3 to each other during a program inhibit operation (or program operation). Therefore, the program inhibit operation of the present disclosure is different from the program inhibit operation in the related example. As described above in fig. 3, in the related example, Vlocal voltage may be applied to isolate the channel in the WL of region 2 and the channel in the WL of region 3. However, in the present disclosure, the channels in the WL of region 2 and the channels in the WL of region 3 may still be connected.

In some embodiments, in the bell-shaped pass voltage mode, the interface (interface) WL between region 2 and region 3 may have a higher Vpass voltage than the highest program-verify level (e.g., 5 volts) in order to inhibit the channel from being isolated between region 2 and region 3. In another example, the interface WL may be driven by ISPP (incremental step pulse programming), and the Vpass voltage at the last program cycle of ISPP may be higher than the highest program-verify level by 1 volt.

In some embodiments, the Vpass voltage of region 2 (or applied over region 2) can gradually decrease toward region 2.

In some embodiments, the Vpass voltage of zone 1 is less than the Vpass voltage of zone 2, and the Vpass voltage of zone 2 is greater than the Vpass voltage of zone 3.

Fig. 4-8 are exemplary embodiments of the present disclosure for applying a bell-shaped pass voltage pattern in a program inhibit operation. Fig. 4 illustrates a first exemplary embodiment of a bell-shaped pass voltage pattern applied to a memory cell string 400 to perform a program inhibit operation. As shown in FIG. 4, the memory cell string 400 may include a selected memory cell MC6 selected for programming, as well as memory cells MC1-MC5 and MC7-MC11, MC1-MC5 and MC7-MC11 that may have been programmed or may be memory cells that are not selected for programming. The memory cells MC1-MC5 may be located on a first side (or source side) of the selected memory cell MC6, and the memory cells MC7-MC11 may be located on a second side (or drain side) of the selected memory cell MC 6. In the example of fig. 4, a bell-shaped pass voltage pattern may be applied to the memory cells on the first side of selected memory cell MC 6.

Still referring to FIG. 4, a program voltage Vpgm can be applied on a selected word line to program a selected memory cell (e.g., MC6), where the selected memory cell MC6 can have a gate terminal coupled to the selected word line. The first pass voltage Vpass1 can be applied on word lines coupled to memory cells (e.g., MC5) in area 1 located at a first side (or source side) of a selected memory cell in the memory cell string 400. The second pass voltage Vpass2 may be applied on word lines coupled to memory cells (e.g., MC3 and MC4) in region 2 located at a first side of a selected memory cell in the memory cell string. The third pass voltage Vpass3 may be applied on word lines coupled to memory cells (e.g., MC1 and MC2) in region 3 located at the first side of selected memory cells in the memory cell string. The second pass voltage Vpass2 may be higher than the first pass voltage Vpass1 and the third pass voltage Vpass 3.

Note that fig. 4 is merely an example. Each of the area 1, the area 2, and the area 3 may include any number of memory cells according to the structure of the memory cell string 400. Thus, the selected memory cell may be any memory cell in the memory cell string 400 starting from the fourth memory cell counted from the BSG transistor. Further, the voltage may be gradually decreased or increased within the region. For example, Vpass2 for region 2 can gradually decrease toward the WL of region 3. In addition, the pass voltage Vpass can be applied to the word line of the memory cell (e.g., MC7-MC11) located at the second side (or drain side) of the selected memory cell MC6 in the memory cell string 400 (or the word line coupled to the memory cell (e.g., MC7-MC 11)).

In the exemplary embodiment of FIG. 4, Vpgm can range from 15 volts to 23 volts. Vpass can range from 5 volts to 12 volts. The first pass voltage Vpass1 may range from 3 volts to 9 volts. The second pass voltage Vpass2 may be in the range from 7 volts to 13 volts. The third pass overvoltage Vpass3 may be in the range from 5 volts to 11 volts. It should be noted that the VCC voltage may be applied on both the bit line and the source line coupled to the memory cell string 400. Further, VCC may be applied on the WL coupled with the TSG transistor, and the WL coupled to the BSG transistor may be grounded. For example, VCC may range from 1.2 volts to 3.6 volts.

By applying a bell-shaped pass voltage pattern across the memory cell string 400 during a program inhibit operation, a program inhibit channel may be formed in the programmed memory cells to prevent the programmed memory cells from being programmed again. Further, a channel potential difference between the programmed memory cell and the selected memory cell can be reduced, and HCI between the programmed memory cell and the selected cell can be prevented.

Fig. 5 illustrates a second exemplary embodiment of a bell-shaped pass voltage pattern applied to a memory cell string 500 to perform a program inhibit operation. As shown in FIG. 5, the memory cell string 500 may include a selected memory cell MC6 selected for programming, as well as memory cells MC1-MC5 and MC7-MC11, memory cells MC1-MC5 and MC7-MC11 that have been programmed or may be memory cells that are not selected for programming. The memory cells MC1-MC5 may be located on a first side (or source side) of the selected memory cell MC6, and the memory cells MC7-MC11 may be located on a second side (or drain side) of the selected memory cell MC 6.

In the example of fig. 5, a bell-shaped pass voltage pattern may be applied to memory cells at the second side (or drain side) of selected memory cell MC 6. As shown in fig. 5, a program voltage Vpgm may be applied to a selected word line to program a selected memory cell MC 6. The first pass voltage Vpass1 may be applied on word lines coupled to memory cells (e.g., MC7) in region 1 located at a second side (or drain side) of the selected memory cells in the memory cell string 500. The second pass voltage Vpass2 may be applied on word lines coupled to memory cells (e.g., MC8 and MC9) in region 2 located on the second side of the selected memory cells in the memory cell string 500. The third pass voltage Vpass3 may be applied on word lines coupled to memory cells (e.g., MC10 and M11) in region 3 located at the second side of the selected memory cells in the memory cell string 500.

It should be noted that each of zone 1, zone 2, and zone 3 in fig. 5 may include any number of memory cells depending on the structure of the memory cell string 500. Thus, the selected memory cell may be any memory cell in the memory cell string 500 starting from the fourth memory cell counted from the TSG transistor. Further, the voltage may be gradually decreased or increased within the region. For example, Vpass2 for region 2 can gradually decrease toward the WL of region 3. Further, the pass voltage Vpass can be applied to the word line of the memory cell (e.g., MC1-MC5) located on the first side (or source side) of the selected memory cell MC6 (or the word line coupled to the memory cell (e.g., MC7-MC 11)) in the memory cell string 500.

In some embodiments, the pass voltage pattern in the related example may be applied when the selected memory cell is one of the first three memory cells counted from the BSG transistors (e.g., MC1-MC3) or one of the first three memory cells counted from the TSG transistors (e.g., MC9-MC 11). For example, a program voltage (e.g., Vpgm) may be applied to a selected memory cell and a pass voltage (e.g., Vpass) may be applied to the remaining memory cells in the memory cell string. In some embodiments, the selected memory cells may be further programmed by ISPP. Accordingly, the voltage level of the program voltage may be adjusted in a program loop of the ISPP.

Fig. 6 illustrates a third exemplary embodiment of a bell-shaped pass voltage pattern applied to a memory cell string 600 to perform a program inhibit operation. As shown in fig. 6, a bell-shaped pass voltage pattern may be applied across memory cells located at both the first side (or source side) and the second side (or drain side) of a selected memory cell (e.g., MC 6). For example, the first pass voltage Vpass1 may be applied on word lines coupled to memory cells (e.g., MC5 and MC7) in area 1 located at a first side (or source side) and a second side (or drain side) of a selected memory cell in the memory cell string 600. The second pass voltage Vpass2 can be applied on word lines coupled to memory cells (e.g., MC3-MC4 and MC8-MC9) in region 2 located on both the first side and the second side of the selected memory cell MC6 in the memory cell string 600. The third pass voltage Vpass3 may be applied on word lines coupled to memory cells (e.g., MC1-MC2 and MC10-MC11) in region 3 located at both the first side and the second side of the selected memory cell in the memory cell string 600.

In fig. 7, a fourth exemplary embodiment of a bell-shaped pass voltage pattern is provided that is applied to a memory cell string 700 to perform a program inhibit operation. In contrast to fig. 6, the interface pass voltage Vpass3_ interface may be applied on WLs coupled to memory cells (e.g., MC2 and MC10) in region 3 disposed adjacent to the memory cells in region 2. The interface pass voltage may be in a range between the second pass voltage Vpass2 and the third pass voltage Vpass 3. For example, the interface pass voltage may range from 8 volts to 10 volts. In fig. 7, an interface pass voltage may be applied to a first interface WL of a first interface memory cell (e.g., MC2) coupled to region 3 of a first side of the selected memory cell MC6 and to a second interface WL of a second interface memory cell (e.g., MC10) coupled to region 3 of a second side of the selected memory cell MC 3978. However, fig. 7 is only an example, and the interface pass voltage may be applied to one or more memory cells adjacent or closest to the memory cells of the region 2 of the first side and one or more memory cells adjacent or closest to the memory cells of the domain 2 of the second side.

In another embodiment of fig. 7, the first pass voltage Vpass1, the second pass voltage Vpass2, the third pass voltage Vpass3, and the interface pass voltage Vpass3_ interface may be applied to memory cells on the first side of only selected memory cells (e.g., MC6) or on the second side of only selected memory cells.

Fig. 8 illustrates a fifth exemplary embodiment of a bell-shaped pass voltage pattern applied on a memory cell string 800 to perform a program inhibit operation. In contrast to FIG. 7, the second one applied on WL of region 2The pass voltage Vpass2 may include a plurality of sub-second pass voltages (or sub-Vpass 2 voltages) that gradually decrease toward the WL of zone 3. For example, the second pass voltage Vpass2 can include two sub-second Vpass voltages applied across the memory cells of zone 2. For example, a first sub-Vpass 2 voltage (e.g., Vpass2_ 1)^st) May be applied to memory cells of sector 2 (e.g., MC4 on the first side and MC8 on the second side) that are adjacent to memory cells of sector 1. The second sub Vpass2 voltage Vpass2_2^nd(also referred to as a transitional pass voltage) may be applied to the memory cells of zone 2 (e.g., MC3 on the first side and MC9 on the second side) that are disposed adjacent to the memory cells of zone 3. The first sub Vpass2 voltage may be greater than the second sub Vpass2 voltage. In some embodiments, the first sub-Vpass 2 voltage Vpass2_1^stMay be in the range from 7 volts to 13 volts, and a second sub-Vpass 2 voltage (or transition pass voltage) Vpass2_2^ndAnd may range from 5 volts to 12 volts.

Of course, fig. 8 is only an example, and any number of memory cells may be included in the area 1, the area 2, and the area 3, respectively. Thus, the first sub Vpass2 voltage can be applied to any number of memory cells on either the first side or the second side of the selected memory cell in sector 2. The second sub-Vpass 2 voltage (or transition pass voltage) may be applied to any number of memory cells on either the first side or the second side of the selected memory cells in region 2. In addition, the second pass voltage Vpass2 can include the remaining memory cells applied to zone 2 (e.g., Vpass2_1 is not applied)^stAnd Vpass2_2^ndMemory cell) so that the second pass voltage Vpass2 applied to the WL of the region 2 may gradually decrease toward the WL of the region 3.

Still referring to FIG. 8, in some embodiments, MC5 may be named a first memory cell, MC4 may be named a second memory cell, MC3 may be named a first transitional memory cell, MC2 may be named a first interfacial memory cell, and MC1 may be named a third memory cell. In addition, the MC7 may be named a fourth memory cell, the MC8 may be named a fifth memory cell, the MC9 may be named a second transitional memory cell, the MC10 may be named a second interfacial memory cell, and the MC11 may be named a sixth memory cell.

Further, the Vpass1 and the first sub Vpass2 voltage Vpass2_1 of the first pass voltage may be applied only to the memory cells on the first side of the selected memory cell (e.g., MC6) or only to the memory cells on the second side of the selected memory cell^stA second sub-Vpass 2 voltage (or transition pass voltage) Vpass2_2^ndVpass3 for the third pass voltage, and/or interface pass voltage Vpass3_ interface.

Fig. 9 is a flow chart of a method 900 for programming a memory device including a string of memory cells. The memory cell string may include a Bottom Select Gate (BSG) transistor, a memory cell, and a Top Select Gate (TSG) transistor connected in series. As shown in fig. 9, method 900 may begin at S902 and proceed to S904. At S904, a programming voltage may be applied on a selected word line to program a selected one of the memory cells, wherein the selected memory cell includes a gate terminal coupled to the selected word line.

At S906, a first pass voltage may be applied on a first wordline coupled to a first memory cell of the memory cells. The first memory cell may be located on a first side of a selected memory cell in the string of memory cells.

At S908, a second pass voltage may be applied on a second word line coupled to a second memory cell of the memory cells, where the second memory cell may be located on a first side of a selected memory cell of the string of memory cells.

At S910, a third pass overvoltage may be applied on a third wordline coupled to a third one of the memory cells. The third memory cell may be located on a first side of a selected memory cell in the memory cell string. The second pass voltage may be higher than the first pass voltage and the third pass voltage, and the second memory cell may be disposed between the first memory cell and the third memory cell.

In an embodiment, the first, second, and third memory cells may be located between the selected memory cell and the BSG transistor. A pass voltage may be applied to a word line coupled to a memory cell located on a second side of a selected memory cell in the memory cell string and disposed between the selected memory cell and the TSG transistor.

In another embodiment, the first memory cell, the second memory cell, and the third memory cell may be located between the selected memory cell and the TSG transistor. Accordingly, a pass voltage may be applied to a word line coupled to a memory cell located at a second side of a selected memory cell in the memory cell string and disposed between the selected memory cell and the BSG transistor.

In method 900, a first pass voltage may be applied on a fourth word line coupled to a fourth memory cell of the memory cells, where the fourth memory cell may be located on a second side of the selected memory cell of the string of memory cells. The second pass voltage may be applied on a fifth wordline coupled to a fifth memory cell of the memory cells, where the fifth memory cell may be located on a second side of the selected memory cell of the string of memory cells. A third pass over voltage may be applied on a sixth wordline coupled to a sixth memory cell of the memory cells, where the sixth memory cell may be located on a second side of the selected memory cell in the string of memory cells. The fifth storage unit may be disposed between the fourth storage unit and the sixth storage unit. In addition, the first memory cell, the second memory cell, and the third memory cell may be disposed between the selected memory cell and the BSG transistor. The fourth memory cell, the fifth memory cell, and the sixth memory cell may be disposed between the selected memory cell and the TSG transistor.

In method 900, an interface pass voltage may be applied on a first interface word line coupled to a first interface memory cell. The first interface storage unit may be located on a first side of the selected storage unit and disposed between the second storage unit and the third storage unit. In addition, an interface pass voltage may be applied on a second interface wordline coupled to a second interface memory cell. The second interface memory cell may be located on a second side of the selected memory cell and disposed between the fifth memory cell and the sixth memory cell.

In some embodiments, the interface pass voltage may be in a range between the second pass voltage and the third pass voltage.

In method 900, a transition pass voltage can be applied on a first transition word line coupled to a first transition memory cell. The first transistor memory may be located on a first side of the selected memory cell and disposed between the second memory cell and the first interface memory cell. The transition pass voltage may be further applied to a second transition word line coupled to a second transition memory cell. The second transition memory cell may be located on a second side of the selected memory cell and disposed between the fifth memory cell and the second interface memory cell.

In some embodiments, the transient pass voltage may be less than the second pass voltage. The first pass voltage may range from 3 volts to 9 volts. The second pass voltage may be in the range from 7 volts to 13 volts. The third pass overvoltage may be in the range from 5 volts to 11 volts. The programming voltage may range from 15 volts to 23 volts. The interface pass voltage may range from 8 volts to 10 volts. The transition pass voltage may range from 5 volts to 12 volts.

Fig. 10 illustrates a block diagram of a storage system apparatus 1000 in accordance with some examples of the present disclosure. The memory system device 1000 includes one or more semiconductor memory devices, such as shown by semiconductor memory devices 811-814, which may be respectively configured similarly to the semiconductor memory device 100. In some examples, the storage system device 1000 is a Solid State Drive (SSD) or a storage module.

The storage system device 1000 may include other suitable components. For example, the memory system device 1000 includes an interface (or host interface circuit) 801 and a host controller (or host control circuit) 802 coupled together as shown in FIG. 10. The memory system apparatus 1000 may include a bus 820 coupling the main controller 802 with the semiconductor memory devices 811 and 814. In addition, the main controller 802 is connected to the semiconductor memory devices 811-814, respectively, such as shown by the corresponding control lines 821-824.

The interface 801 is suitably configured mechanically and electrically to interface between the storage system device 1000 and a host device, and may be used to transfer data between the storage system device 1000 and the host device.

The main controller 802 is configured to connect the respective semiconductor memory devices 811 and 814 to the interface 801 for data transfer. For example, the main controller 802 is configured to provide enable/disable signals to the semiconductor memory devices 811-814 to activate one or more of the semiconductor memory devices 811-814 for data transfer, respectively.

The main controller 802 is responsible for completing various instructions within the memory system device 1000. For example, the master controller 802 may perform bad block management, error checking and correction, garbage collection, and the like.

In some embodiments, main controller 802 is implemented using a processor chip. In some examples, master controller 802 is implemented using a technique for programming memory cells with a voltage pattern based on the bell shape shown in fig. 4-8. In some examples, master controller 802 is implemented using multiple MCUs and may be implemented using techniques that program memory cells through a voltage pattern based on the bell shape shown in fig. 4-8.

Various embodiments described herein provide several advantages over methods in related examples of programming memory cells of a string of memory cells in a 3D-NAND memory device. In a related example, a program inhibit operation may be performed by isolating channels of the memory cell strings, which may result in an elevated channel potential difference between programmed memory cells and selected memory cells, and HCI may occur from the channels of the programmed cells to the channels of the selected memory cells. In the present disclosure, a bell-shaped pass voltage pattern may be applied because the Vpass voltage may be modulated along the Word Lines (WL) of the memory cell string in a "bell-shaped" form that varies from the word line of the programmed cells (or programmed WLs) in the direction of the drain side or source side of the memory cell string. The WL is configured to have a region 1, a region 2, and a region 3 defined from a word line of a selected memory cell (also referred to as a selected program WL), and the Vpass voltage in the middle region 2 may be higher than the Vpass voltage in the regions 1 and 3. By increasing the Vpass voltage in region 2, the potential difference between the programmed WL and the adjacent WL (e.g., the selected programmed WL) can be suppressed, which in turn can suppress HCl and lead to better program disturb.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.