Memory system and method for optimizing read threshold
阅读说明:本技术 存储器系统和用于优化读取阈值的方法 (Memory system and method for optimizing read threshold ) 是由 张帆 蔡宇 熊晨荣 吕宣宣 于 2019-07-23 设计创作,主要内容包括:本发明提供一种存储器系统,该存储器系统包括存储器装置和控制器。控制器使用多个读取阈值条目对存储器装置的读取数据集执行测试读取操作,并且基于测试读取操作的结果确定哪些读取阈值条目为好读取阈值条目。控制器基于测试读取操作的结果在多个读取阈值条目之中选择最佳读取阈值条目,将读取数据集划分为由最佳读取阈值条目可解码的好数据集和由最佳读取阈值条目不可解码的坏数据集,并且将坏数据集设置为新读取数据集。(A memory system includes a memory device and a controller. The controller performs a test read operation on a read data set of the memory device using the plurality of read threshold entries and determines which read threshold entries are good read threshold entries based on results of the test read operation. The controller selects an optimal read threshold entry among the plurality of read threshold entries based on a result of the test read operation, divides the read data set into a good data set decodable by the optimal read threshold entry and a bad data set decodable by the optimal read threshold entry, and sets the bad data set as a new read data set.)
1. A memory system, comprising:
a memory device; and
a controller:
performing a test read operation on a read data set of the memory device using a plurality of read threshold entries; and is
Determining a good read threshold entry among the plurality of read threshold entries based on a result of the test read operation,
wherein determining the good read threshold entry comprises:
selecting an optimal read threshold entry among the plurality of read threshold entries based on a result of the test read operation;
dividing the read dataset into a good dataset comprising data in the read dataset decodable by the optimal read threshold entry and a bad dataset comprising data in the read dataset not decodable by the optimal read threshold entry; and
setting the bad data set as a new read data set.
2. The memory system of claim 1, wherein performing the test read operation comprises reading data from the new read data set using remaining read threshold entries, other than the optimal read threshold entry, from among the plurality of read threshold entries.
3. The memory system of claim 1, wherein a result of the test read operation comprises a number of failed bits of the read data set.
4. The memory system of claim 1, wherein the read data set corresponds to a physical address selected from a super block of the memory device.
5. The memory system of claim 1, wherein the controller performs a normal read operation on the memory device using the good read threshold entry in response to a read command from a host.
6. The memory system of claim 1, wherein reads of the test read operation are interleaved with reads of a normal read operation.
7. A method of operating a memory system, the memory system comprising a memory device, the method comprising:
performing a test read operation on a read data set of the memory device using a plurality of read threshold entries; and
determining a good read threshold entry among the plurality of read threshold entries based on a result of the test read operation,
wherein determining the good read threshold entry comprises:
selecting an optimal read threshold entry among the plurality of read threshold entries based on a result of the test read operation;
dividing the read dataset into a good dataset comprising data in the read dataset decodable by the optimal read threshold entry and a bad dataset comprising data in the read dataset not decodable by the optimal read threshold entry; and
setting the bad data set as a new read data set.
8. The method of claim 7, wherein performing the test read operation comprises reading data from the new read data set using remaining read threshold entries, other than the best read threshold entry, from among the plurality of read threshold entries.
9. The method of claim 7, wherein a result of the test read operation comprises a number of failed bits of the read data set.
10. The method of claim 7, wherein the read data set corresponds to a physical address selected from a super block of the memory device.
11. The method of claim 7, further comprising:
in response to a read command from a host, a normal read operation is performed on the memory device using the good read threshold entry.
12. The method of claim 7, wherein reads of the test read operation are interleaved with reads of a normal read operation.
Technical Field
Embodiments of the present disclosure relate to a scheme for handling read thresholds of a memory system.
Background
Computer environment paradigms have turned into pervasive computing systems that can be used anytime and anywhere. Therefore, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has been rapidly increasing. These portable electronic devices typically use a memory system with a memory device, i.e., a data storage device. The data storage device is used as a primary memory device or a secondary memory device of the portable electronic device.
A memory system using the memory device provides excellent stability, durability, high information access speed, and low power consumption since it has no moving parts. Examples of the memory system having these advantages include a Universal Serial Bus (USB) memory device, a memory card having various interfaces such as a universal flash memory (UFS), and a Solid State Drive (SSD). The memory system may use various encoders.
Disclosure of Invention
Aspects of the present invention include a memory system and a method for processing a read threshold capable of improving quality of service (QoS) of the memory system.
In one aspect, a memory system includes a memory device and a controller. The controller performs a test read operation on a read data set of the memory device using the plurality of read threshold entries and determines a good read threshold entry among the plurality of read threshold entries based on a result of the test read operation. The controller selects an optimal read threshold entry among the plurality of read threshold entries based on a result of the test read operation, divides the read dataset into a good dataset including data in the read dataset decodable by the optimal read threshold entry and a bad dataset including data in the read dataset not decodable by the optimal read threshold entry, and sets the bad dataset as a new read dataset.
In another aspect, a method of operating a memory system includes: performing a test read operation on a read data set of a memory device using a plurality of read threshold entries; and determining a good read threshold entry among the plurality of read threshold entries based on a result of the test read operation. Determining a good read threshold entry includes: selecting an optimal read threshold entry among the plurality of read threshold entries based on a result of the test read operation; dividing the read dataset into a good dataset comprising data in the read dataset decodable by the optimal read threshold entry and a bad dataset comprising data in the read dataset not decodable by the optimal read threshold entry; and setting the bad data set as a new read data set.
Other aspects of the invention will become apparent from the following description.
Drawings
FIG. 1 is a block diagram illustrating a data processing system according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a memory system according to an embodiment of the invention.
Fig. 3 is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention.
Fig. 4 is a diagram illustrating a concept of a super memory block in a memory device according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a memory system according to an embodiment of the invention.
Fig. 6A and 6B are flowcharts illustrating a method for managing a Read Level Table (RLT) according to an embodiment of the present invention.
Fig. 7 is a diagram illustrating an example of an optimization process of a Read Level Table (RLT) according to an embodiment of the present invention.
Detailed Description
Various embodiments are described in more detail below with reference to the figures. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Moreover, references herein to "an embodiment," "another embodiment," etc., do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment. Throughout the disclosure, like reference numerals refer to like parts in the figures and embodiments of the present invention.
The present invention may be implemented in a variety of ways including: proceeding; equipment; a system; a computer program product presented on a computer-readable storage medium; and/or a processor, such as a processor adapted to execute instructions stored on and/or provided by a memory, where the memory is coupled to the processor. In this specification, these embodiments, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless otherwise specified, a component such as a processor or a memory described as being suitable for performing a task may be implemented as a general component that is temporarily configured to perform the task at a given time or as a specific component that is manufactured to perform the task. As used herein, the term "processor" or the like refers to one or more devices, circuits, and/or processing cores adapted to process data, such as computer program instructions.
A detailed description of embodiments of the invention is provided below along with accompanying figures that illustrate aspects of the invention. The invention is described in connection with these embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims. The invention encompasses numerous alternatives, modifications and equivalents within the scope of the claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. These details are provided for the purpose of example; the present invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.
FIG. 1 is a block diagram illustrating a
Referring to fig. 1, a
The host device 5 may be implemented by any of various electronic devices. In various embodiments, the host device 5 may include electronic devices such as: a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and/or a digital video recorder and a digital video player. In various embodiments, the host device 5 may comprise a portable electronic device such as: mobile phones, smart phones, electronic book readers, MP3 players, Portable Multimedia Players (PMPs), and/or portable game consoles.
The
The
The
The
The
FIG. 2 is a block diagram illustrating a memory system according to an embodiment of the invention. For example, the memory system of FIG. 2 may depict the
Referring to fig. 2, the
The
The
The
The
The storage device 110 may serve as a working memory of the
The storage 110 may be implemented using volatile memory such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). As described above, the storage device 110 may store data used by the host device in the
The
During a read operation, the ECC component 130 may detect and correct errors in data read from the
In various embodiments, ECC component 130 may perform error correction operations based on coded modulation such as: low Density Parity Check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, Turbo Product Codes (TPC), Reed-Solomon (RS) codes, convolutional codes, Recursive Systematic Codes (RSC), Trellis Coded Modulation (TCM), or Block Coded Modulation (BCM). However, error correction is not limited to these techniques. As such, ECC component 130 may include any and all circuits, systems, or devices for appropriate error correction operations.
The host interface 140 may communicate with the host device through one or more of a variety of interface protocols such as: universal Serial Bus (USB), multi-media card (MMC), peripheral component interconnect express (PCI-e or PCIe), Small Computer System Interface (SCSI), serial SCSI (sas), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and/or Integrated Drive Electronics (IDE).
The memory interface 150 may provide an interface between the
The
The voltage generation circuit 230 may generate various levels of operating voltages. For example, in the erase operation, the voltage generation circuit 230 may generate various levels of operation voltages such as an erase voltage and a pass voltage.
The row decoder 240 may be in electrical communication with the voltage generation circuit 230 and the plurality of memory blocks 211. The row decoder 240 may select at least one memory block among the plurality of memory blocks 211 in response to a row address generated by the control circuit 220 and transfer an operating voltage supplied from the voltage generation circuit 230 to the selected memory block.
The page buffer array 250 may be coupled with the memory cell array 210 through bit lines BL (shown in fig. 3). The page buffer array 250 may precharge the bit lines BL with a positive voltage, transfer data to a selected memory block in a program operation and receive data from the selected memory block in a read operation, or temporarily store the transferred data in response to a page buffer control signal generated by the control circuit 220.
The column decoder 260 may transfer data to and receive data from the page buffer array 250, and transfer data to and receive data from the input/output circuit 270 and 270.
The input/output circuit 270 may transfer commands and addresses received from an external device (e.g., the
Control circuitry 220 may control peripheral circuitry in response to commands and addresses.
Fig. 3 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, the memory block of fig. 3 may be any one of the memory blocks 211 of the memory cell array 210 shown in fig. 2.
Referring to fig. 3, the exemplary memory block 211 may include a plurality of word lines WL0 through WLn-1 coupled to the row decoder 240, a drain select line DSL, and a source select line SSL. The lines may be arranged in parallel, with multiple wordlines between DSL and SSL.
The exemplary memory block 211 may further include a plurality of cell strings 221 coupled to bit lines BL0 through BLm-1, respectively. The cell strings of each column may include one or more drain select transistors DST and one or more source select transistors SST. In the embodiment shown, each string of cells has one DST and one SST. In the cell string, a plurality of memory cells or memory cell transistors MC0 through MCn-1 may be coupled in series between the selection transistors DST and SST. Each of the memory cells may be formed as any of various cells configured with different data storage capabilities. For example, each of the memory cells may be formed as a single-layer cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-level cell (MLC) storing 2-bit data. Each of the memory cells may be formed as a Triple Layer Cell (TLC) storing 3-bit data. Each of the memory cells may be formed as a four-layer cell (QLC) storing 4-bit data.
The source of the SST in each cell string may be coupled to the common source line CSL, and the drain of each DST may be coupled to a respective bit line. The gates of the SSTs in the cell string may be coupled to the SSL, and the gates of the DSTs in the cell string may be coupled to the DSL. The gates of the memory cells across the cell string may be coupled to respective word lines. That is, the gates of memory cell MC0 are coupled to a respective word line WL0, the gates of memory cell MC1 are coupled to a respective word line WL1, and so on. A group of memory cells coupled to a particular word line may be referred to as a physical page. Thus, the number of physical pages in memory block 211 may correspond to the number of word lines.
The page buffer array 250 may include a plurality of page buffers 251 coupled to bit lines BL0 through BLm-1. The page buffer 251 may operate in response to a page buffer control signal. For example, during a read operation or a verify operation, the page buffer 251 may temporarily store data received through the bit lines BL0 to BLm-1 or sense a voltage or current of the bit lines.
In some embodiments, memory block 211 may include NAND-type flash memory cells. However, the memory block 211 is not limited to this cell type, but may include NOR type flash memory cells. The memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or an One-NAND flash memory in which a controller is embedded within a memory chip.
In a memory system such as a Solid State Drive (SSD), data for storage in the memory device may be striped (stripe) across different dies and/or different planes through different channels. For such processing, a super block may be generated that includes physical blocks with the same block index across different lanes, dies, and possibly different planes.
Fig. 4 is a diagram illustrating the concept of a super block in the
Referring to fig. 4, the
The
Zeroth memory DIE0 includes multiple PLANEs, e.g., planet 00 and planet 01, corresponding to multiple lanes, e.g., WAY0 and WAY1, respectively, capable of receiving and outputting data in an interleaving scheme by sharing zeroth channel CH 0.
The first memory DIE1 includes multiple PLANEs, e.g.,
First PLANE plan 00 of zeroth memory DIE0 includes a set or predetermined number of memory BLOCKs BLOCK000 through BLOCK00N among all of the plurality of memory BLOCKs.
The second PLANE plan 01 of the zeroth memory DIE0 includes a set or predetermined number of memory BLOCKs BLOCK 010-BLOCK 01N among all of the plurality of memory BLOCKs.
Second PLANE plan 11 of first memory DIE1 includes a set or predetermined number of memory BLOCKs BLOCK110 through BLOCK11N among all of the plurality of memory BLOCKs.
In this way, multiple memory blocks of
Although
Alternatively, the
The
According to the first scheme, the
According to a second scheme,
According to the third scheme, the
In general, a storage device manufacturing company must ensure that its storage devices, such as Solid State Drives (SSDs), are able to meet all of the requirements in each specification for the life of each storage device. If a particular storage device deviates from its specification, the customer or user may recognize that the device has reached the end of its life (EOL) and replace the device. In enterprise-level SSDs, quality of service (QoS) is considered an EOL limiting factor. When an enterprise-level SSD approaches its EOL, most customers or users will consider the QoS violation. The QoS requirements are defined as the maximum delay for different percentages of read and/or write commands to be completed and returned to the host. A low 9 requirement, such as 90%, 99% or 99.9%, is commonly referred to as a low 9QoS requirement. The delay of low 9 is typically determined by the probability of failure of the default read, the history read, and the high priority read retry read. The probability of failure depends on the Error Correction Code (ECC) engine and the distribution of the Fail Bits (FB) of the memory device (e.g., NAND). Although the ECC engine does not change the lifetime of the SSD, FB distribution may significantly shorten the lifetime of the SSD depending on the operating conditions of the SSD.
Accordingly, embodiments of the present invention provide a scheme for improving QoS of a storage device such as an SSD by controlling FB distribution of the memory device by optimizing a read threshold. In various embodiments, the read thresholds for the default read or reads, the history read or reads, and the read retry or retries may be contained in a Read Level Table (RLT) and collectively referred to as RLT. Various embodiments provide a scheme for optimizing RLT on the fly.
FIG. 5 is a diagram illustrating a memory system according to an embodiment of the invention.
Referring to fig. 5, the memory system may include a
The
The
In various embodiments, the
In various embodiments, the
In various embodiments, the result of the test read operation may include the number of failed bits of the read data set.
In various embodiments, the read data set may correspond to a physical address selected from a super block of the memory device.
In various embodiments, the
Fig. 6A and 6B are flow diagrams illustrating a
Referring to fig. 6A,
In various embodiments, the
In various embodiments, the reads of the test read operation are interleaved with the reads of the normal read operation at a particular ratio. That is, compared to normal reading, the reading is performed at a lower percentage, for example at 1: a ratio of 100 performs a test read.
Referring to fig. 6B,
In various embodiments,
In various embodiments, the result of the test read operation includes a number of failed bits of the read data set.
In various embodiments, the read data set corresponds to a physical address selected from a super block of the memory device.
Fig. 7 is a diagram illustrating an optimization procedure of a Read Level Table (RLT) according to an embodiment of the present invention. For example, the optimization process can be performed by the
Referring to fig. 7, a set R of read thresholds including different read thresholds, e.g., RRT0 through RRT49, may be defined for each superblock of a memory device (e.g., NAND).
The Read Level Table (RLT) can be optimized from a set of read thresholds R. In other words, RLT may be a subset of the set of read thresholds R ═ RRT0,
in step 0, for each superblock, the
In
In
In step 3, the
In step 4, the
In fig. 7, by way of example, the selection of two best RRTRRT2 and RRT1 from the 50 RRTs of set R based on FB counts is shown. In other words, first, because the FB count FB2 corresponding to RRT2 is the lowest among the FB counts FB0 to FB49 corresponding to 50 RRTs, respectively, RRT2 is selected as the best RRT among the 50 RRTs. In this case, when the read data is decoded using the RRT2, the probability of decoding success may be 1-p0 and the probability of decoding failure may be p 0. Next, because FB count FB1 corresponding to RRT1 is the lowest among FB counts FB0, FB1, FB3 to FB49 corresponding to 49 RRTs, respectively, RRT1 is selected as the best RRT among the remaining 49 RRTs (i.e., excluding RRT 2). In this case, when the read data is decoded using the RRT1, the probability of decoding success may be 1-p1 and the probability of decoding failure may be
As described above, the controller according to the embodiment may perform online read level table optimization to improve QoS of a memory system such as an SSD. The optimization scheme accommodates changes in NAND quality over its lifetime and ensures QoS throughout the lifetime of the device.
Although the foregoing embodiments have been illustrated and described in some detail for purposes of clarity and understanding, the invention is not limited to the details provided. As will be appreciated by one skilled in the art in light of the foregoing disclosure, there are many alternative ways of implementing the invention. Accordingly, the disclosed embodiments are illustrative and not restrictive. The invention is intended to cover all modifications and alternatives falling within the scope of the claims.
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