Solid state storage device and read table management method thereof
阅读说明:本技术 固态储存装置及其读取表管理方法 (Solid state storage device and read table management method thereof ) 是由 曾士家 郭俊纬 陈冠群 傅仁傑 于 2018-07-25 设计创作,主要内容包括:本发明为一种固态储存装置的读取表管理方法。于一读取表调整程序时,当热群中的一最小计算值小于冷群中的一最大计算值时,对调该热群中对应于该最小计算值的一第一读取电压组与该冷群中对应于该最大计算值的一第二读取电压组,使该第二读取电压组属于该热群,且该第一读取电压组属于该冷群。(The invention relates to a management method for a reading table of a solid-state storage device. When a minimum calculated value in a hot group is smaller than a maximum calculated value in a cold group during a reading table adjusting procedure, a first reading voltage group corresponding to the minimum calculated value in the hot group and a second reading voltage group corresponding to the maximum calculated value in the cold group are exchanged, so that the second reading voltage group belongs to the hot group, and the first reading voltage group belongs to the cold group.)
1. A solid state storage device, comprising:
a control circuit including a read table for storing a plurality of read voltage sets and corresponding calculated values, wherein a first portion of the read voltage sets belongs to a hot group and a second portion of the read voltage sets belongs to a cold group; and
a non-volatile memory;
during a reading period, the control circuit determines a selected reading voltage set from the reading voltage sets to be provided to the non-volatile memory according to a specific providing sequence recorded by the reading table;
when the decoding is successful, modifying a calculated value corresponding to the selected reading voltage group in the reading table; and, when the decoding is unsuccessful, determining another selected read voltage set from the read voltage sets to provide to the non-volatile memory according to the specific providing sequence;
when a minimum calculation value in the hot group is smaller than a maximum calculation value in the cold group during a reading table adjusting program, the control circuit adjusts a first reading voltage group corresponding to the minimum calculation value in the hot group and a second reading voltage group corresponding to the maximum calculation value in the cold group, so that the second reading voltage group belongs to the hot group and the first reading voltage group belongs to the cold group.
2. The solid state storage device of claim 1, wherein an order of providing the first set of partial read voltages in the hot group is prioritized over an order of providing the second set of partial read voltages in the cold group according to the particular order of providing.
3. The solid state storage device of claim 2, wherein a most-prior-order set of read voltages in the thermal group is set to a predetermined set of read voltages.
4. The solid state storage device of claim 1, wherein the calculated value is an accumulated value, and the accumulated value corresponding to the selected read voltage group is incremented by one when decoding is successful.
5. The solid state storage device of claim 1, wherein the calculated value is a probability value representing a probability of decoding success for the selected set of read voltages.
6. The solid state storage device of claim 1, wherein the control circuit initiates the read table adjustment procedure after the control circuit performs a specified number of the read cycles.
7. The solid state storage device of claim 1, wherein the control circuit initiates the read table adjustment procedure after the solid state storage device has been operating for a specified time.
8. The solid state storage device of claim 1, wherein prior to the control circuit swapping the first read voltage set for the x-th order in the hot group and the second read voltage set for the y-th order in the cold group; and after the control circuit switches the first reading voltage group and the second reading voltage group, the second reading voltage group belongs to the x-th order in the hot group, and the first reading voltage group belongs to the y-th order in the cold group.
9. A method for managing a read table of a solid state storage device, the solid state storage device comprising a control circuit and a non-volatile memory, the control circuit comprising a read table for storing a plurality of read voltage sets and corresponding calculated values, a first portion of the read voltage sets belonging to a hot group and a second portion of the read voltage sets belonging to a cold group, the method comprising the steps of:
determining a selected read voltage set from the read voltage sets to provide to the non-volatile memory according to a specific providing sequence recorded by the read table during a read cycle;
when the decoding is successful, modifying the calculated value corresponding to the selected reading voltage group in the reading table;
when the decoding is unsuccessful, determining another selected read voltage set from the read voltage sets to provide to the non-volatile memory according to the specific providing sequence; and
when a minimum calculation value in the hot group is smaller than a maximum calculation value in the cold group during a reading table adjusting procedure, a first reading voltage group corresponding to the minimum calculation value in the hot group and a second reading voltage group corresponding to the maximum calculation value in the cold group are exchanged, so that the second reading voltage group belongs to the hot group, and the first reading voltage group belongs to the cold group.
10. The method of claim 9, wherein an order of providing the first set of partial read voltages in the hot group is prioritized over an order of providing the second set of partial read voltages in the cold group according to the specific order of providing.
11. The method of claim 10, wherein a highest-priority read voltage set of the thermal group is set as a predetermined read voltage set.
12. The method as claimed in claim 9, wherein the calculated value is an accumulated value, and the accumulated value corresponding to the selected read voltage group is incremented by one when the decoding is successful.
13. The method as claimed in claim 9, wherein the calculation value is a probability value representing a probability of successful decoding of the selected set of read voltages.
14. The method as claimed in claim 9, wherein the control circuit starts the read table adjustment procedure after the control circuit performs a specific number of the read cycles.
15. The method as claimed in claim 9, wherein the control circuit starts the read table adjustment procedure after the solid state storage device operates for a specific time.
16. The method of claim 9, wherein before the first read voltage set and the second read voltage set are swapped, the first read voltage set belongs to an x-th order in the hot group and the second read voltage set belongs to a y-th order in the cold group; and after the first reading voltage group and the second reading voltage group are exchanged, the second reading voltage group belongs to the x-th order in the hot group, and the first reading voltage group belongs to the y-th order in the cold group.
Technical Field
The present invention relates to a solid-state storage device and a related control method thereof, and more particularly, to a solid-state storage device and a read table (read table) management method thereof.
Background
As is well known, Solid State Storage Devices (SSD) are widely used in various electronic products, such as SD cards, Solid State disks, etc.
Generally, a non-volatile memory (non-volatile memory) is included in the solid-state storage device. After data is written into the non-volatile memory, once the power of the solid-state storage device is turned off, the data can still be stored in the non-volatile memory.
Referring to fig. 1, a schematic diagram of a conventional solid-state storage device is shown. The solid-
The control circuit 101 further includes an Error Correction Code (ECC) circuit 104 and a read table (ready) 105. The read table 105 may be stored in a memory of the control circuit 101, and the read table 105 includes a plurality of read voltage sets (read voltage sets).
Furthermore, the
The solid-
Furthermore, the control circuit 101 is connected to the
Basically, the read table (read)105 in the control circuit 101 includes a default read voltage set (default voltage set). A read cycle is initiated when the control circuit 101 receives a read command. During a read cycle (read cycle), the control circuit 101 transmits an operation command to the
Furthermore, an Error Correction Code (ECC) circuit 104 in the control circuit 101 is used to correct error bits (error bits) in the read data and transmit the correct read data to the
When the ECC circuit 104 cannot successfully correct all the error bits in the read data, the control circuit 101 sequentially provides another retry read voltage sets from the read table 105, so that the control circuit 101 performs a read retry (read retry) process on the
according to the amount of data stored in each memory Cell, the memory cells can be further divided into a Single-Level Cell (SLC Cell), a Multi-Level Cell (MLC Cell), a Triple-Level Cell (TLC Cell), and a Quad-Level Cell (QLC Cell), wherein each Cell stores one bit. Thus, the
In the
Referring to FIG. 2A, a schematic diagram of a storage state of a TLC memory cell is shown. One cell of the TLC cell may exhibit eight storage states "Erase", "a" to "G" according to the injection amount of the hot carriers. When the hot carrier is not injected, the memory cell can be regarded as the storage state "Erase", and the memory cell can be further divided into other seven storage states "a" to "G" with the increase of the amount of hot carrier injection. For example, the memory cell storing the state "G" has the highest threshold voltage level, and the memory cell storing the state "Erase" has the lowest threshold voltage level. Furthermore, after the memory cell is erased, the memory cell will return to the "Erase" state without hot carrier injection.
Generally, in a programming cycle, if a plurality of memory cells are programmed to the same storage state, the threshold voltage of each memory cell is not the same, but a distribution curve (distribution curve) is presented, and the distribution curve can correspond to a median threshold voltage. As can be seen from fig. 2A, the median threshold voltage of the storage state "Erase" is Ver, the median threshold voltage of the storage state "a" is Va, the median threshold voltage of the storage state "B" is Vb, the median threshold voltage of the storage state "C" is Vc, the median threshold voltage of the storage state "D" is Vd, the median threshold voltage of the storage state "E" is Ve, the median threshold voltage of the storage state "F" is Vf, and the median threshold voltage of the storage state "G" is Vg. For example, after counting the threshold voltages of all the memory cells in the storage state "A", the number of memory cells with the median threshold voltage Va is the largest.
As shown in FIG. 2A, seven read voltages Vra-Vrg can be generated as a default read voltage set according to the distribution curves of the respective storage states in the TLC memory cell. During a read cycle, the control circuit 101 provides a predetermined set of read voltages to the
As shown in FIG. 2A, the predetermined set of read voltages Vra Vrg is an important criterion for determining the storage status of the TLC memory cell. For example, the
Similarly, sixteen storage states of the QLC memory cell can be determined by applying fifteen read voltages of the preset read voltage set. The three read voltages of the preset read voltage set are used to determine the four storage states of the MLC memory cell. Two storage states of the SLC memory cell can be determined by applying a predetermined read voltage.
FIG. 2B is a schematic diagram showing the shift of the storage state of the TLC memory cell. Solid
As shown in fig. 2B, after the distribution curve of the TLC memory cell is shifted, the middle threshold voltage of the storage state "Erase" is Ver ', the middle threshold voltage of the storage state "a" is Va', the middle threshold voltage of the storage state "B" is Vb ', the middle threshold voltage of the storage state "C" is Vc', the middle threshold voltage of the storage state "D" is Vd ', the middle threshold voltage of the storage state "E" is Ve', the middle threshold voltage of the storage state "F" is Vf ', and the middle threshold voltage of the storage state "G" is Vg'.
Therefore, the use of the preset read voltage Vra Vrg to determine the storage state of the TLC memory cell will cause the number of error bits (error bits) in the read data to increase. When the ECC circuit 104 cannot successfully correct all the error bits in the read data, the control circuit 101 needs to provide other retry read voltage sets Vra 'to Vrg' in the read table 105 to perform a read retry (read retry) process.
Referring to fig. 3, a schematic diagram of an error correction process of a conventional solid-state storage device is shown. In a read cycle, the control circuit 101 first performs a decoding process (decoding) a, which uses a preset read voltage set to perform hard decoding. In the decoding process a, the control circuit 101 provides a predetermined read voltage set to the
When the error bit in the read data can be corrected, it represents that the decoding is successful through (pass) decoding flow A. Therefore, the control circuit 101 can transmit the correct read data to the
Furthermore, when the control circuit 101 enters the read retry process, the decoding process B is performed first. And a decoding flow B, which is to perform hard decoding by using the retry read voltage group. For example, the control circuit 101 obtains a selected retry read voltage set Vra 'Vrg' (selected retry read voltage set) from the read table 105 and provides the selected retry read voltage set to the
Since the read table 105 in the control circuit 101 stores a plurality of retry read voltage sets (e.g., n retry read voltage sets). If the control circuit 101 can successfully decode with one of the retry read voltage sets, pass decoding flow B is represented. On the contrary, if the decoding is still unsuccessful after all the n retry read voltage sets are used, it represents that the decoding process B fails (fail). Accordingly, the control circuit 101 performs the decoding flow C. Obviously, the time required for decoding flow B is greater than for decoding flow a.
The control circuit 101 performs a decoding flow C of performing soft decoding (softdecoding) with the retry read voltage set. Soft decoding has better error correction capability than hard decoding, but requires multiple retries of the read voltage set to obtain a single read data. Therefore, soft decoding is more time consuming, meaning that the time required for decoding flow C is greater than for decoding flow B.
Similarly, as long as the control circuit 101 can decode successfully, it represents a pass (pass) decoding process C, and can deliver the correct read data to the
As can be seen from the error correction process of the solid-state storage device, when the decoding process a fails, the control circuit 101 enters a read retry (read retry) process. In the read retry process, the control circuit 101 needs to perform the decoding process B first. After confirming that the decoding process B fails, the control circuit 101 continues the decoding process C. In addition, when the control circuit 101 confirms that the decoding process C fails, it will reply to the
Generally, after the manufacture of the
Referring to fig. 4A, a diagram of a conventional read table is shown. The reading table 105 includes sequential columns (Order) and (n +1) reading voltage sets RS 0-RSn. Basically, the control circuit 101 determines the providing sequence of the (n +1) sets of read voltages to the
For example, the read voltage set RS0 of
In the decoding process A of FIG. 3, the control circuit 101 provides the preset read voltage set RS0 in the read table 105 to the
In the conventional control circuit 101, when (n +1) read voltage groups RS0 to RSn are recorded in the read table 105, the order thereof is not changed. Therefore, the read speed (read speed) of the solid-
After the solid-
As shown in FIG. 4B, the preset read voltage set RS0 in
However, when entering the decoding process B of the read retry process, the control circuit 101 sequentially provides n retry read voltage sets to the
In other words, after the control circuit 101 enters the decoding process B of the read retry process, the control circuit 101 may continuously provide (n-1) retry read voltage sets RS 1-RSn-1 to the
Disclosure of Invention
The invention relates to a solid state storage device, comprising: a control circuit and a non-volatile memory. The control circuit includes a read table for storing a plurality of read voltage sets and corresponding calculated values. Wherein a first portion of the read voltage sets belongs to a hot group and a second portion of the read voltage sets belongs to a cold group. In a read cycle, the control circuit determines a selected read voltage set from the read voltage sets to provide to the non-volatile memory according to a specific providing sequence recorded by the read table. When the decoding is successful, the calculation value corresponding to the selected read voltage group in the read table is modified. When the decoding is unsuccessful, another selected read voltage set is determined from the read voltage sets and provided to the non-volatile memory according to the specific providing sequence. Furthermore, during a reading table adjusting procedure, when a minimum calculated value in the hot group is smaller than a maximum calculated value in the cold group, the control circuit adjusts a first reading voltage group corresponding to the minimum calculated value in the hot group and a second reading voltage group corresponding to the maximum calculated value in the cold group, so that the second reading voltage group belongs to the hot group and the first reading voltage group belongs to the cold group.
The invention relates to a read table management method of the solid-state storage device, which comprises the following steps: determining a selected read voltage set from the read voltage sets to provide to the non-volatile memory according to a specific providing sequence recorded by the read table during a read cycle; when the decoding is successful, modifying the calculated value corresponding to the selected reading voltage group in the reading table; when the decoding is unsuccessful, determining another selected read voltage set from the read voltage sets to provide to the non-volatile memory according to the specific providing sequence; and when a minimum calculated value in the hot group is smaller than a maximum calculated value in the cold group during a reading table adjusting program, exchanging a first reading voltage group corresponding to the minimum calculated value in the hot group and a second reading voltage group corresponding to the maximum calculated value in the cold group, so that the second reading voltage group belongs to the hot group and the first reading voltage group belongs to the cold group.
In order to better appreciate the above and other aspects of the present invention, reference will now be made in detail to the embodiments illustrated in the accompanying drawings.
Drawings
FIG. 1 is a diagram of a conventional solid state memory device.
FIG. 2A is a schematic diagram of the storage state of the TLC memory cell.
FIG. 2B is a schematic diagram of the shift of the storage state of the TLC memory cell.
FIG. 3 is a schematic diagram of an error correction process of a conventional solid-state storage device.
Fig. 4A is a diagram illustrating a conventional read table.
FIG. 4B is a graph of the relationship between all sets of read voltages and the probability of read success.
FIG. 5 is a diagram of a solid state memory device according to the present invention.
FIG. 6A is a read representation of the present invention.
FIG. 6B is a flowchart of the read table adjustment procedure initiated by the control circuit.
FIGS. 7A-7F are schematic diagrams of a read table and a management read table according to the present invention.
Detailed Description
The reading speed of the solid-state storage device is affected by the sequence of the reading table providing the reading voltage sets. Therefore, the present invention provides a solid-state storage device and a read table management method thereof. The order of the reading table for providing the reading voltage groups is dynamically adjusted according to the utilization condition of the reading voltage groups, and the reading speed of the solid-state storage device is improved.
Referring to fig. 5, a solid state storage device according to the present invention is shown. The solid-
Referring to FIG. 6A, a read representation according to the present invention is shown. In the read table 505, the read voltage groups RS0 to RS10 are divided into a Hot group (Hot group) and a Cold group (Cold group). Wherein the hot group corresponds to an order that precedes the order that the cold group corresponds to. Taking fig. 6A as an example, the hot group includes 4 read voltage sets RS 0-
In this embodiment, the hot group in the read table 505 includes 4 read voltage sets RS 0-
According to the embodiment of the present invention, when the control circuit 501 successfully decodes with any one of the read voltage sets, the accumulated value (cumulative count) corresponding to the read voltage set is increased by 1. For example, after the control circuit 501 successfully decodes and obtains the read data in the decoding process a, the cumulative value corresponding to the preset read voltage group RS0 is increased by 1. Similarly, after the control circuit 501 successfully decodes the data in the decoding process B by using the retry read voltage group RS6 and obtains the read data, the accumulated value corresponding to the preset read voltage group RS6 is added by 1. And so on.
Furthermore, after the control circuit 501 performs a specific number of read cycles (e.g., 1000), the control circuit 501 performs an adjustment procedure on the activated read table 505.
Referring to fig. 6B, a flowchart of the control circuit initiating the read table adjustment procedure is shown. When the control circuit starts the read table adjustment routine, the control circuit 101 determines whether the minimum integrated value in the hot group is smaller than the maximum integrated value in the cold group (step S602). When the minimum integrated value in the hot group is determined to be smaller than the maximum integrated value in the cold group, the read voltage group corresponding to the minimum integrated value in the hot group and the read voltage group corresponding to the maximum integrated value in the cold group are exchanged (swap) (step S604). The following describes the read table adjustment procedure by way of example.
Fig. 7A to 7F are schematic diagrams illustrating a read table and a management read table according to the present invention. First, when the solid-
After the control circuit 501 performs a specific number of read cycles (e.g., 1000), the control circuit 501 starts a read table adjustment procedure. Assume that the integrated value in the reading table 505 at this time is as shown in fig. 7A.
Since the minimum
In the implementation of the present invention, the sequence corresponding to the hot group and the sequence corresponding to the cold group do not change with the exchange of the read voltage sets. As shown in fig. 7B, the table is read 505 after the control circuit 501 performs the adjustment procedure. After the read voltage sets are exchanged, the hot groups are still in the order of 0 to 3, and the cold groups are still in the order of 4 to 10. Further, read voltage set RS7 belongs to order 2 in the hot group, and read voltage set RS2 belongs to order 7 in the cold group. In the subsequent read cycle, the control circuit 501 provides the read voltage sets according to the sequence of the read table 505 shown in FIG. 7B.
Take the error correction flow of fig. 3 as an example. In the decoding process A of FIG. 3, the control circuit 501 provides the read voltage set RS0 in the
Then, when the decoding process a fails and the decoding process B of fig. 3 is required, the control circuit 501 provides the read voltage set RS1 of
After the control circuit 501 performs the reading cycle again for a specific number of times (e.g., 1000 times), the control circuit 501 starts the reading table adjustment procedure again. Assume that the integrated value in the reading table 505 at this time is as shown in fig. 7C.
Since the minimum
As shown in fig. 7D, the contents of the table 505 are read after the control circuit 501 performs the adjustment procedure. Wherein, the read voltage set RS9 belongs to the
After the control circuit 501 performs the reading cycle again for a specific number of times (e.g., 1000 times), the control circuit 501 starts the reading table adjustment procedure again. Assume that the integrated value in the read table 505 at this time is as shown in fig. 7E.
Since the minimum
As shown in fig. 7F, the table is read 505 after the control circuit 501 performs the adjustment procedure. Wherein, the read voltage set RS10 belongs to the
Of course, as the reading period increases, all the accumulated values in the reading table 505 will continuously change, and the control circuit 501 will adjust the content of the reading table 505 at an appropriate time. Therefore, in the read cycle, the control circuit 501 can successfully decode the data by using the read voltage set in the hot group under most conditions, and only a few conditions need to use the read voltage set in the cold group. The reading speed of the solid-
As can be seen from the above description, the present invention provides a solid state storage device and a method for managing a read table thereof. After the control circuit 501 performs a specific number of reading cycles, the control circuit 501 starts the adjustment procedure of the reading table 505 to change the providing sequence of the reading voltage sets and increase the reading speed of the solid
In the above embodiment, the control circuit 501 counts the number of read cycles, and starts the read table adjustment procedure after the control circuit 501 performs a specific number of read cycles. However, the present invention is not limited thereto, and those skilled in the art can also start the read table adjustment procedure according to the operation time of the solid
In addition, the control circuit 501 performs a read table adjustment routine based on the integrated value of the read voltage group. However, the invention is not limited thereto, and those skilled in the art can adjust the calculation value according to other calculation values. For example, the calculated value may be a probability value representing a decoding success probability corresponding to the selected read voltage set.
In other words, the control circuit 501 takes the calculated value of the read voltage group as a basis for swapping when performing the read table adjustment procedure, and the calculated value may be a probability value or an accumulated value.
In summary, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.
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