阅读说明：本技术 读取延迟控制电路及方法 (Read delay control circuit and method ) 是由 杨尚辑 廖惇雨 张益维 于 2018-12-25 设计创作，主要内容包括：本发明公开了一种存储器装置包含一存储单元阵列,及耦接至该存储单元阵列的多个存储单元的多个感测放大器。一控制器系响应于一命令及一地址来执行包含一读取周期的一读取操作,其中,在该读取周期内,位于此地址的这些存储单元被电性耦接至这些感测放大器,且在该读取周期内,位于此地址的存储单元系响应于一时序信号而与这些感测放大器电性断开。(The invention discloses a memory device which comprises a memory cell array and a plurality of sense amplifiers coupled to a plurality of memory cells of the memory cell array. A controller is responsive to a command and an address to perform a read operation including a read cycle in which the memory cells at the address are electrically coupled to the sense amplifiers and in which the memory cells at the address are electrically decoupled from the sense amplifiers in response to a timing signal.)

1. A memory device, comprising:

a memory cell array;

a plurality of sense amplifiers coupled to a plurality of memory cells of the memory cell array;

a controller for performing a read operation in response to a command and an address, wherein the read operation comprises: the memory cells at the address are electrically coupled to the sense amplifiers during a read cycle, and the memory cells at the address are electrically disconnected from the sense amplifiers in response to a timing signal during the read cycle; and

a timing signal generating circuit for generating the timing signal, the timing signal generating circuit comprising: a first delay circuit generating a first signal having a first delay based on a frequency of a read clock signal; a second delay circuit generating a second signal having a second delay independent of the frequency of the read clock signal; and a selector circuit responsive to the first signal to generate the timing signal if the first delay is shorter than the second delay or responsive to the second signal if the second delay is shorter than the first delay.

2. The memory device of claim 1, further comprising:

a first port for receiving the read clock signal having the frequency;

a second port for receiving address signals, data signals and command signals synchronized with the read clock signal; and

and a plurality of data latches coupled to the sense amplifiers, the data latches storing data read from the memory cells at the address after the memory cells at the address are electrically disconnected from the sense amplifiers, at least until the read data is output from the second port.

3. The memory device of claim 1, further comprising:

a first port for receiving the read clock signal having the frequency; and

a second port for receiving address signals, data signals and command signals in synchronization with the read clock signal,

wherein the frequency of the read clock signal ranges from a lower read pulse frequency to an upper read pulse frequency, the first delay based on the upper read pulse frequency is longer than a sensing time between receiving all bits of the address from the first port to forming a signal representative of a sensed first data, and the second delay is longer than the sensing time and shorter than the first delay based on the lower read pulse frequency, the first data being provided to the second port.

4. The memory device of claim 1, further comprising:

a first port for receiving the read clock signal having the frequency,

wherein the first port is an external port of the memory device.

5. The memory device of claim 1, further comprising:

a first port for receiving the read clock signal having the frequency; and

a second port for receiving address signals, data signals and command signals in synchronization with the read clock signal,

the second port is an external port of the memory device, and the second port includes one or more external pins of the memory device.

6. The memory device of claim 1, wherein:

the first delay starts from a specific period in the reading clock signal, and a period of the first delay corresponds to a predetermined number of periods in the reading clock signal; and

the second delay starts at the specific period in the read clock signal and has a fixed duration.

7. The memory device of claim 6, wherein the address is received in a set of address cycles in the read clock signal, and the particular cycle in the read clock signal is subsequent to a final cycle in the set of address cycles.

8. The memory device of claim 1, further comprising:

a first port for receiving the read clock signal having the frequency; and

a second port for receiving address signals, data signals and command signals in synchronization with the read clock signal,

in a group of data output periods in the reading frequency signal, the data read from the memory cells at the address is output from the second port, and before a first period in the group of data output periods, the memory cells at the address are electrically disconnected from the sense amplifiers.

9. The memory device of claim 1, further comprising:

a first port for receiving the read clock signal having the frequency; and

a second port for receiving address signals, data signals and command signals in synchronization with the read clock signal,

the address is received in a set of address cycles of the read clock signal, the data read from the memory cells at the address is output from the second port in a set of data output cycles of the read clock signal, and the timing signal is generated within a delay that begins at a final cycle of the set of address cycles and ends at a first cycle of the set of data output cycles, a period of the delay being associated with a predetermined number of cycles of the read clock signal.

10. The memory device of claim 1, wherein the selector circuit comprises a logic AND gate having a plurality of inputs receiving the first signal at the first delay AND the second signal at the second delay, AND an output generating the timing signal.

11. A method for reading a memory device, the memory device comprising an array of memory cells and a plurality of sense amplifiers coupled to a plurality of memory cells of the array of memory cells, the method comprising:

receiving an address synchronized with a read clock signal;

electrically coupling the memory cells at the address to the sense amplifiers during a read cycle;

electrically disconnecting the memory cells at the address from the sense amplifiers in response to a timing signal during the read cycle; and

generating the timing signal, comprising:

generating a first signal having a first delay based on a frequency of the read clock signal;

generating a second signal having a second delay independent of the frequency of the read clock signal; and

the timing signal is generated in response to the first signal if the first delay is shorter than the second delay, or in response to the second signal if the second delay is shorter than the first delay.

12. The method of claim 11, wherein the memory device further comprises: a first port for receiving the read clock signal having the frequency; a second port for receiving address signals, data signals and command signals synchronized with the read clock signal; and a plurality of data latches coupled to the plurality of sense amplifiers, the method further comprising:

after the memory cells at the address are electrically disconnected from the sense amplifiers, the data latches store data read from the memory cells at the address at least until the read data is output from the second port.

13. The method of claim 11, wherein the memory device further comprises: a first port for receiving the read clock signal having the frequency and a second port for receiving address signals, data signals and command signals synchronized to the read clock signal, wherein the frequency of the read clock signal ranges from a lower read clock frequency to an upper read clock frequency, the first delay based on the upper read clock frequency is longer than a sensing time and shorter than the second delay, and the second delay is longer than the sensing time and shorter than the first delay based on the lower read clock frequency, the sensing time ranges from receiving all bits of the address from the first port to forming a signal representative of a first data sensed to be provided to the second port.

14. The method of claim 11, wherein the memory device further comprises a first port for receiving the read clock signal having the frequency, wherein the first port is an external port of the memory device.

15. The method of claim 11, wherein the memory device further comprises: a first port for receiving the read clock signal having the frequency; and a second port for receiving address signals, data signals and command signals synchronized with the read clock signal, wherein the second port is an external port of the memory device, the second port including one or more external pins of the memory device.

16. The method of claim 11, wherein

The first delay starts from a specific period in the reading clock signal, and a period of the first delay corresponds to a predetermined number of periods in the reading clock signal; and

the second delay starts at the specific period in the read clock signal and has a fixed duration.

17. The method of claim 16, wherein the address is received in a set of address cycles in the read clock signal, and the particular cycle in the read clock signal is subsequent to a final cycle in the set of address cycles.

18. The method of claim 11, wherein the memory device further comprises: a first port for receiving the read clock signal having the frequency; and a second port for receiving address signals, data signals and command signals synchronized with the read clock signal, wherein data read from the memory cells at the address are output from the second port in a set of data output periods of the read clock signal, and the memory cells at the address are electrically disconnected from the sense amplifiers before a first period of the set of data output periods.

19. The method of claim 11, wherein the memory device further comprises: a first port for receiving the read clock signal having the frequency; and a second port for receiving address signals, data signals and command signals synchronized with the read clock signal, wherein the address is received in a set of address cycles in the read clock signal, data read from the memory cells at the address is output from the second port in a set of data output cycles in the read clock signal, and the timing signal is generated with a delay that begins at a final cycle of the set of address cycles and ends at a first cycle of the set of data output cycles, a period of the delay being associated with a predetermined number of cycles in the read clock signal.

20. The method of claim 11, further comprising performing a logical AND function to receive the first signal at the first delay AND the second signal at the second delay AND generate the timing signal.

21. A circuit, comprising:

a first delay circuit generating a first signal having a first delay based on a frequency of a read clock signal;

a second delay circuit generating a second signal having a second delay independent of the frequency of the read clock signal; and

a selector circuit responsive to the first signal to generate a timing signal if the first delay is shorter than the second delay or responsive to the second signal to generate a timing signal if the second delay is shorter than the first delay.

22. A memory device, comprising:

a memory cell array;

a plurality of sense amplifiers coupled to a plurality of memory cells of the memory cell array;

a controller for performing a read operation in response to a command and an address; and

a timing signal generating circuit, comprising: a first delay circuit generating a first signal having a first delay based on a frequency of a read clock signal; a second delay circuit generating a second signal having a second delay independent of the frequency of the read clock signal; and a selector circuit responsive to the first signal to generate the timing signal if the first delay is shorter than the second delay or responsive to the second signal if the second delay is shorter than the first delay.

23. The memory device of claim 22, further comprising:

a first port for receiving the read clock signal having the frequency;

a second port for receiving address signals, data signals and command signals synchronized with the read clock signal; and

and a plurality of data latches coupled to the sense amplifiers, the data latches storing data read from the memory cells at the address.

24. The memory device of claim 22, further comprising:

a first port for receiving the read clock signal having the frequency; and

a second port for receiving address signals, data signals and command signals in synchronization with the read clock signal,

wherein the frequency of the read clock signal is between a lower read pulse frequency and an upper read pulse frequency, the first delay is related to a sensing time according to the upper read pulse frequency, and the second delay is related to the sensing time according to the lower read pulse frequency.

25. The memory device of claim 22, further comprising:

a first port for receiving the read clock signal having the frequency; and

a second port for receiving address signals, data signals and command signals in synchronization with the read clock signal,

wherein the data read from the memory cells at the address is output from the second port in a set of data output periods in the read clock signal.

26. A method for reading a memory device comprising an array of memory cells and a plurality of sense amplifiers coupled to a plurality of memory cells of the array of memory cells, the method comprising:

receiving an address synchronized with a read clock signal; and

generating a timing signal, comprising:

generating a first signal having a first delay based on a frequency of the read clock signal;

generating a second signal having a second delay independent of the frequency of the read clock signal; and

the timing signal is generated in response to the first signal if the first delay is shorter than the second delay, or in response to the second signal if the second delay is shorter than the first delay.

27. The method of claim 26, wherein the memory device further comprises: a first port for receiving the read clock signal having the frequency; a second port for receiving address signals, data signals and command signals synchronized with the read clock signal; and a plurality of and data latches coupled to the plurality of sense amplifiers, the method further comprising:

the data read from the memory cells at the address is stored in the data latches.

28. The method of claim 26, wherein the memory device further comprises: a first port for receiving the read clock signal having the frequency; a second port for receiving address signals, data signals and command signals synchronized with the read clock signal, wherein the clock frequency of the read clock signal is from a lower read clock frequency to an upper read clock frequency, the first delay is associated with a sensing time according to the upper read clock frequency, and the second delay is associated with the sensing time according to the lower read clock frequency.

29. The method of claim 26, wherein the memory device further comprises: a first port for receiving the read clock signal having the frequency; and a second port for receiving an address signal, a data signal and a command signal synchronized with the read clock signal, wherein data read from the memory cells at the address is output from the second port in a set of data output periods in the read clock signal.

Technical Field

The present invention relates to integrated circuit memory devices, and more particularly, to circuits and methods for reading data from such memory devices.

Background

The master controller communicates with the memory devices using a communication interface such as Serial Peripheral interface bus (SPI). The main controller generates a read frequency signal and selects the memory device through a chip select signal line. The read frequency signal may have a frequency range supported by the memory device.

A typical read instruction sequence includes a read command and a start address. After issuing the sequence of read instructions, the host controller must wait a delay time for data to be output from the memory device. During the delay time, the memory device senses data stored in the memory device.

In a prior art, the delay time is controlled by the read clock signal and depends on the frequency of the read clock signal. With this approach, the delay time may be longer than the sensing time required to sense data in the memory device and result in more power consumption than is required.

It is therefore desirable to provide circuits and methods for reducing power consumption during memory read operations.

Disclosure of Invention

In view of the foregoing, the present invention provides an apparatus and method for reducing power consumption of a memory device during a read operation.

According to one embodiment of the present invention, there is provided a memory device including: a memory cell array; a plurality of sense amplifiers coupled to the memory cells; a controller for performing a read operation in response to a command and an address, wherein the read operation comprises: the memory cells at the address are electrically coupled to the sense amplifiers during a read cycle, and the memory cells at the address are electrically disconnected from the sense amplifiers in response to a timing signal during the read cycle.

For example, in a NAND flash architecture, a memory cell array may include a block of memory cells arranged in a plurality of strings of memory cells. The memory cell strings have respective selection switch strings coupled to respective bit signal lines. In this case, electrically coupling the memory cells to the sense amplifiers comprises: the method includes applying a bias voltage to an addressed plurality of memory cells, applying a bias voltage to a plurality of select switch strings coupled to the memory cell strings including the addressed memory cells, and applying a bias voltage to a plurality of sense amplifiers coupled to the addressed memory cells to allow a current to flow from the addressed memory cells to the respective sense amplifiers. In the NAND flash architecture, electrically disconnecting the memory cells from the sense amplifiers in response to the timing signal comprises: the application of bias to the addressed memory cells, the select switch strings and the sense amplifiers is stopped to prevent current from flowing from the addressed memory cells to the sense amplifiers and to discharge the sense amplifiers.

The stopping of the application of the bias voltage is in response to a timing signal. In other words, stopping the application of the bias is initiated by the timing signal, but is not necessarily precisely aligned in time with the timing signal. For example, the bias voltage may be stopped from being applied within one cycle of the read clock signal in response to the timing signal.

For example, in a NOR flash architecture, a memory device may include: a plurality of semiconductor strip stacks on a substrate; a plurality of word signal lines orthogonally arranged on the stacked layers; a plurality of memory cells between the stacked surfaces and the word signal lines; a plurality of bit signal lines coupled to a plurality of locations along each of the plurality of semiconductor strip stacks; and a plurality of source signal lines coupled to a plurality of locations along each of the plurality of semiconductor strip stacks, wherein the bit signal lines and the source signal lines are between adjacent ones of the word signal lines.

In the NOR flash architecture, electrically coupling the memory cells to the sense amplifiers comprises: bias voltages are applied to a plurality of bit signal lines, a plurality of word signal lines, and a plurality of source signal lines coupled to the addressed memory cells, and bias voltages are applied to a plurality of sense amplifiers coupled to the bit signal lines to allow current to flow from the addressed memory cells to the respective sense amplifiers. In this case, electrically disconnecting the memory cells from the sense amplifiers in response to a timing signal includes: stopping applying bias voltages to the bit signal lines, the word signal lines, and the source signal lines coupled to the addressed memory cells, and stopping applying bias voltages to the sense amplifiers to prevent current from flowing from the addressed memory cells to the respective sense amplifiers and to discharge the sense amplifiers.

A circuit for generating timing signals includes: a first delay circuit generating a first signal having a first delay based on a frequency of a read clock signal; a second delay circuit generating a second signal having a second delay independent of the frequency of the read clock signal; and a selector circuit responsive to the first signal to generate a timing signal if the first delay is shorter than the second delay or responsive to the second signal if the second delay is shorter than the first delay. The selector circuit may include a logic AND gate having a plurality of inputs receiving the first signal at the first delay AND the second signal at the second delay, AND an output generating a timing signal.

The memory device includes: a first port for receiving the read clock signal having the frequency and a second port for receiving address, data and command signals synchronized with the read clock signal. The memory device further comprises: and a plurality of data latches coupled to the sense amplifiers, the data latches storing data read from the memory cells at the address after the memory cells at the address are electrically disconnected from the sense amplifiers, at least until the read data is output from the second port.

The first port may be an external port of the memory device, and the read clock signal is input from an external signal source of the chip through the first port. The second port may be an external port external to the memory device, including one or more external pins external to the memory device.

As used herein, a sensing time in a read operation is between the receipt of all bits of the address from an external source to a signal that forms a signal representative of a sensed first data that is provided to output circuitry that provides clock output data. The sensing time may depend on a number of factors and includes various read operations for the device, including: an address, a word line, and a bit line being charged are decoded, a sense current flowing through the memory cells is applied, and the sensing circuit is operated to develop a reliable signal for a worst-case signal path through the memory circuits.

The frequency of the read clock signal falls within a range from a lower read pulse frequency to an upper read pulse frequency. The first delay based on a higher read pulse frequency is longer than a sensing time and shorter than the second delay, and the second delay is longer than the sensing time and shorter than the first delay based on a lower read pulse frequency. The sensing time is between receiving all bits of the address from the first port to forming a signal representative of sensed first data provided to the second port.

The first delay may begin at a particular period in the read clock signal, and its duration corresponds to a predetermined number of periods in the read clock signal. The second delay may start at a specific period in the read clock signal and have a fixed duration. The address is received in a set of address cycles in the read clock signal, and a particular cycle in the read clock signal is after a final cycle in the set of address cycles. In a set of data output periods of the read clock signal, data read from the memory cells at the address is output from the second port, and the memory cells at the address are electrically disconnected from the sense amplifiers before a first period of the set of data output periods. The timing signal is generated within a delay that begins a final period in the set of address cycles and ends a first period in the set of data output cycles, a period of the delay corresponding to a predetermined number of cycles of the read clock signal.

The illustrated circuit of the present invention includes: a first delay circuit generating a first signal having a first delay based on a frequency of a read clock signal; a second delay circuit generating a second signal having a second delay independent of the frequency of the read clock signal; and a selector circuit responsive to the first signal to generate a timing signal if the first delay is shorter than the second delay or responsive to the second signal if the second delay is shorter than the first delay.

The invention also provides a method for operating a memory device.

Other embodiments and advantages of the invention will be apparent from a review of the following drawings, detailed description, and claims.

Drawings

FIG. 1 is a simplified block diagram of an integrated circuit memory device.

FIG. 2 is a timing diagram showing a read operation of the memory device.

FIG. 3 shows a circuit for generating timing signals.

FIG. 4 is a timing diagram showing the generation of timing signals when the read clock signal has a higher read pulse frequency.

FIG. 5 is a timing diagram showing the generation of timing signals when the read clock signal has a lower read pulse frequency.

FIG. 6 is an example flow diagram showing a method for reading a memory device.

[ notation ] to show

D0: sensing time

D1: first delay

D2: second delay

D3: third positive pulse/third negative pulse

SCLK: reading frequency signals

T1: first signal

T2: second signal

T3: timing signal

100: memory device

110: first port

115: frequency generator

117: internal frequency

120: second port

121: signal line

122: signal line

130: address generator

135: address

140: controller

141: command decoder

142: state machine

145: signal line

160: memory cell array

161: x-decoder

162: y-decoder

165: bit signal line

170: page buffer

175: signal line

180: output buffer

185: signal line

190: time sequence signal generator

201. 202: time sequence

203: command cycle

204: address cycle

205: delay

206. 207: time period

310: first delay circuit

320: second delay circuit

330: selector circuit

409-415: period of time

610-650: step (ii) of

Detailed Description

The following description will generally refer to particular constructed embodiments and methods. It is to be understood that the technology is not intended to be limited to the specifically disclosed embodiments and methods, but that the technology can be practiced using other features, components, methods and embodiments. Preferred embodiments are described to illustrate the present technology, not to limit its scope, which is defined by the claims. Those skilled in the art will appreciate a variety of equivalent variations from the description that follows.

FIG. 1 is a simplified block diagram of a memory device 100, comprising: a memory cell array 160; a plurality of sense amplifiers in a page buffer 170 coupled to the memory cells; a first port 110; and a second port 120. The first port 110 receives a read clock signal SCLK having a frequency ranging from a lower read pulse frequency to a read pulse frequency of an upper read pulse frequency. The first port 110 is an external port of the memory device, and the read frequency signal is provided to the first port 110 by an off chip source. In this example, the memory device 100 may include a serial interface, wherein read commands, addresses, and data are communicated over the serial interface. The Serial Interface may be a Serial Peripheral Interface (SPI) bus in which command channels may share I/O ports used by addresses and data.

As used herein, an external port has one or more pins on an integrated circuit package that encases an integrated circuit device (e.g., a memory device). External ports on an integrated circuit package may connect the integrated circuit device enclosed by the package to a circuit board for off chip communications. For example, a signal provided by an off-chip power supply to an external port of the integrated circuit device may drive circuitry internal to the integrated circuit device via the external port.

The second port 120 is used for receiving address signals, data signals and command signals synchronized with the read clock signal, and other signals not synchronized with the read clock signal. The second port 120 is an external port of the memory device. The second port 120 may include a plurality of pins including pins SI/SIO0, SO/SIO1, SIO2, SIO3, WP #, RESET #, CS #. The pins SI/SIO0, SO/SIO1, SIO2, and SIO3 are for serial data I/O (input and output) that is synchronized with the read clock signal. For example, the pins SI/SIO0 may be used for 1x I/O, the pins SI/SIO0 and SO/SIO1 may be used for 2x I/O, and the pins SI/SIO0, SO/SIO1, SIO2 and SIO3 may be used for 4x I/O. Pin WP # is write protected and it can use the same pin as SIO 2. Pin RESET # is a hardware RESET and it may use the same pin as SIO 3. The pin CS # is a chip select.

The memory device 100 includes a controller 140. The controller 140 is configured to respond to commands and addresses received from the second port 120 to perform read operations including read cycles in which the memory cell at the address is electrically coupled to the sense amplifier during a read cycle and electrically decoupled from the sense amplifier during the read cycle in response to a timing signal T3. Controller 140 provides signals 145 to control other circuits of memory device 100, such as: an X-decoder 161, a Y-decoder 162, and a sense amplifier and page buffer 170 to perform the various operations described herein. Read operations performed by the controller 140 include; synchronizing with the read frequency signal to receive an address on the second port in response to the timing signal; decoding the address; electrically coupling a sense amplifier to the memory cell at the address; in a read cycle, the sense amplifier is electrically disconnected from the memory cell at the address.

The controller 140 includes a command decoder 141 and a state machine 142, the command decoder 141 having logic to support sequential read commands received on the second port 120. The clock generator 115 receives the read clock signal SCLK and provides an internal clock 117 to the command decoder to decode the command received from the second port 120. The controller may be implemented using special purpose logic circuitry as is known in the art. In other embodiments, the controller may be a general purpose processor, which may be implemented on the same memory device 100, the memory device 100 executing a computer program to control the operation of the device. In one embodiment, the controller may be implemented using a combination of special purpose logic circuitry and a general purpose processor.

The timing signal generator 190 generates a timing signal T3. The timing signal generator 190 may include a first delay circuit, a second delay circuit, and a selector circuit, as further described with reference to fig. 3. The first delay circuit receives a read clock signal SCLK with a read pulse frequency and generates a first signal at a first delay. The first delay may begin with a specific period in the read clock signal, and its duration (duration) corresponds to a predetermined number of periods in the read clock signal. The second delay circuit may generate a second signal having a second delay. The second delay may start at this specific period in the reading clock signal SCLK, and it has a fixed duration. The selector circuit may receive the first signal at a first delay and the second signal at a second delay and generate the timing signal T3 corresponding to the shorter of the first delay and the second delay.

The address signal, synchronized with the read clock signal SCLK, is transmitted to the memory device 100 through the second port 120 and is provided to the address generator 130 through a signal line 121. Address generator 130 provides address 135 to X-decoder 161 and Y-decoder 162. An X-decoder 161 and a Y-decoder 162 are sequentially coupled to the memory cell array 160 (in turn). The memory cell array 160 may have a NOR architecture, a NAND architecture, or other architectures.

In this embodiment, the bit signal lines 165 in the memory cell array 160 are coupled to the sense amplifiers in the page buffer 170, which are in turn coupled to the output buffer 180 via a signal line 175. The output buffer 180 is coupled to the second port 120 via a signal line 185. The page buffer 170 may include a plurality of data latches coupled to a plurality of sense amplifiers for each connected bit signal line. The address decoders 161 and 162 may select a specific memory cell in the memory cell array 160 and couple the specific memory cell of the memory cell array 160 to the page buffer of the page buffer 170 via respective bit signal lines connected. The page buffer 170 then stores the data sensed by the specific memory cells or the data to be written into the memory cells into the data latches. After the memory cell at the address is electrically disconnected from the sense amplifier, the data read from the memory cell at the address is stored in the data latch at least until the read data is output from the second port 120.

The read command is provided to the memory device 100 through the second port 120 according to the SPI protocol and is provided to the command decoder 141 through the signal line 122. The command decoder 141 decodes the received read command. The command decoder 141 may also set the state of the memory device 100 in the state machine 142 based on the decoded read command. Based on the state of the state machine 142, the controller 140 provides signals to the address decoders 161 and 162, the page buffer 170, or other circuitry of the memory device 100 to perform one or more operations corresponding to the state stored in the state machine 142.

The data stored in the memory cell array 160 can be addressed in 1 byte, or in other suitable sizes, such as 4 bytes or 8 bytes, etc. Each block may have an address in the memory cell array 160. A block of data may be read from the memory device 100 by providing a read request to the memory device 100, wherein the read request includes a read command and an address of the block of data.

The memory device 100 supports a sequential read state (sequential read state). In the sequential read state, the memory device 100 automatically outputs a block of data having sequential addresses in the memory cell array 160 as long as SCLK remains active. For example, after outputting the first byte of data from the second port 120 (e.g., at address "03 FFF 2" in hexadecimal), the memory device 100 automatically outputs the second byte of data at address "03 FFF 3", which is subsequent to the first byte of data. The memory continues to output bytes of data that follow the address of the previously output byte (e.g., "03 FFF5," "03 FFF6," "03 FFF7," etc.) until SCLK is aborted, or until the state of the sequential read state changes.

FIG. 2 is a timing diagram illustrating a read operation of the memory device 100. In this example, at timing 201, the chip enable signal CS # changes from high to low. When the chip enable signal CS # is held low, the memory device 100 is in an active mode and can receive and process input signals. At timing 202, the read clock signal SCLK is provided to the memory device 100 (FIG. 1) via the first port 110. The memory device 100 inputs or outputs data by latching input/output data bits to the read clock signal SCLK.

As shown in the example of FIG. 2, during a command cycle 203 following timings 201 and 202, a command code of one byte or a series of bytes in length (e.g., binary code "00000011" of a sequential read command) is provided to memory device 100 via an input data signal line connected to second port 120. In this example, each bit of the command code is latched at the rising edge of the read clock signal SCLK (e.g., for a binary code "00000011", the command period 203 has 8 clock cycles). Alternatively, each bit of the command code may be latched at the falling edge of the read clock signal SCLK, which is appropriate for the design of the particular memory device.

In this example, the command decoder 141 (fig. 1) decodes the received command code (e.g., binary code "00000011") and determines it to be a serial read command. After determining that it is a sequential read command, command decoder 141 sets the sequential read state in state machine 142. Meanwhile, during the address cycle 204, the command decoder 141 or other modules of the controller 140 (FIG. 1) decodes the subsequent byte or bytes received via the input data signal line (which is connected to the input/output second port 120) into the start address of the data stored in the memory cell array 160 (requested by the sequential read command). For example, during address cycle 204, a 3-byte address (e.g., "03 FFF 2" in hexadecimal) may be provided to memory device 100 via an input data signal line connected to second port 120. In this example, each bit of the 3-byte address is latched on the rising edge of the read clock signal SCLK (i.e., address cycle 204 has 24 clock cycles for the 3-byte address). Alternatively, each bit of the 3-byte address may be latched at the falling edge of the read clock signal SCLK, which is appropriate for the design of the particular memory device.

After receiving the address, the memory device 100 may sense the data stored in the memory cell array 160 of the memory device 100 at the received address during the delay 205. After delay 205, memory device 100 may output the sensed data in a set of data output cycles of the read frequency signal. The read clock signal SCLK may have a read pulse frequency range from a lower read pulse frequency to a higher read pulse frequency. The address is received in a set of address cycles in the read clock signal and the sensed data is output in a set of data output cycles. The delay may begin at a final cycle of the set of address cycles and end at a first cycle of the set of data output cycles. The generation of the higher read frequency timing signal is described with reference to FIG. 4, while the generation of the lower read frequency timing signal is described with reference to FIG. 5.

The memory device 100 can continuously output data, starting with the data of the first block of the start address of the sequential read command. For example, the controller 140 may provide a start address and an output block size (e.g., one byte in size) to the address decoder 161 (FIG. 1). The address decoder 161 selects a memory cell in the memory cell array 160 corresponding to a byte located at the start address and couples the selected memory cell to the page buffer 170. The controller 140 also transmits control signals to the page buffer 170 via the signal line 145. The output buffer 180 transmits the data of the first byte stored in the selected memory cell to the second port 120 via the signal line 185. In this example, each bit of the first byte of data is latched on the falling edge of the read clock signal SCLK and shifted out to the output data signal line connected to the second port 120. Alternatively, each bit of the first byte of data may latch on the rising edge of the read clock signal SCLK and shift out to an output data signal line connected to the second port 120, which is appropriate for the design of the particular memory device. In this example, the first byte of data ("data output byte 1" shown in FIG. 2) at the start address (e.g., "03 FFF 2" in hexadecimal) of the sequential read command is output in 8 clock cycles within time period 206 of FIG. 2.

In the sequential read state, if the read clock signal SCLK is still valid and the chip enable signal CS # is low, the memory device 100 continuously outputs data following the first byte of data without the need for additional command and address data by the second port 120. For example, after outputting the first byte of data (at address "03 FFF 2" hex), the second byte of data with an address (e.g., "03 FFF 3" hex) after the address of the first byte of data is output to the second port 120. Each bit of the second byte of data is latched at the falling edge of the read clock signal SCLK and shifted out to the output data signal line connected to the second port 120. Here, the second byte of data ("data out byte 2" shown in FIG. 2) is output in 8 clock cycles of the time period 207 shown in FIG. 2.

The sequential read state may be ended by changing the chip enable signal CS # from low to high. When the chip enable signal CS # remains high, the memory device 100 is in the inactive mode and stops outputting data. After the chip enable signal CS # changes from low to high, the memory device 100 may change the state of the state machine 142 to the out-of-sequence read state.

The sequential data output shown in FIG. 2 can be stopped by suspending the read clock signal SCLK while keeping the chip enable signal CS # low. In this manner, sequential read status is suspended or retained in the state machine 142 and sequential data output is halted. Sequence data output can be restarted by restarting reading the frequency signal SCLK.

FIG. 3 shows a circuit for generating timing signals. The circuit may include a first delay circuit 310, a second delay circuit 320, and a selector circuit 330.

The first delay circuit 310 may receive the read clock signal SCLK and generate the first signal T1, wherein the read pulse frequency of the read clock signal SCLK is in a range from a lower read pulse frequency to an upper read time, and the first signal T1 has a first delay D1 (fig. 4 and 5) based on the frequency of the read clock signal SCLK. The first delay may begin with a specific period in the read clock signal, and its duration corresponds to a predetermined number of periods in the read clock signal SCLK. For example, a counter synchronized with the read clock signal may generate a pulse having a pulse width corresponding to a predetermined number of cycles in the read clock signal for representing the first delay.

The number of cycles in the read clock signal SCLK of the first delay D1 is predetermined such that the first delay (D1, FIG. 4) based on the high read pulse frequency is longer than the sensing time (D0, FIG. 4) and shorter than the second delay (D2, FIG. 4), and the second delay (D2, FIG. 5) is longer than the sensing time (D0, FIG. 5) and shorter than the first delay based on the low read pulse frequency.

The second delay circuit 320 receives the reading clock signal SCLK and generates a second signal T2 (FIG. 4 and FIG. 5) at a second delay D2. The second delay may begin at a particular period in the read clock signal (as may the particular period in the read clock signal from which the first delay D1 begins) and have a fixed duration. For example, the second delay circuit 320 may include an AND gate AND an inverted delay signal line having a fixed period. The first input of the AND gate may receive an input signal that begins at a particular period in the read clock signal. The input of the inverted delay signal line can receive an input signal, and the input signal is output after being inverted and delayed. A second input of the AND gate may receive the delayed inverted signal from the inverted delayed signal line. The AND gate outputs a one-shot signal representing a second delay when the input signal is switched from a low voltage level to a high voltage level. The selector circuit 330 may receive a first signal having a first delay and a second signal having a second delay. The selector circuit 330 may generate the timing signal in response to the first signal if the first delay is shorter than the second delay, or the selector circuit 330 may generate the timing signal in response to the second signal if the second delay is shorter than the first delay.

Depending on the pulse polarity of the first signal T1, the second signal T2, and the timing signal T3, the selector circuit 330 may include a logic gate having an input receiving the first signal T1 with the first delay and the second signal T2 with the second delay, and an output generating the timing signal T3. In the embodiment shown in FIG. 4, the first positive pulse of the first signal T1 may represent the first delay D1, the second positive pulse of the second signal T2 may represent the second delay D2, and the third positive pulse D3 of the timing signal T3 is shorter with respect to the first delay D1 and the second delay D2. In the present embodiment, the selector circuit 330 may include a logic AND gate, the inputs of which may receive the first signal T1 with the first delay AND the second signal T2 with the second delay; the output of the logic AND gate of the selector circuit 330 may generate the timing signal T3 in response to the first signal if the first delay is shorter than the second delay, or the output of the logic AND gate of the selector circuit 330 may generate the timing signal T3 in response to the second signal if the second delay is shorter than the first delay.

In an alternative embodiment, the first negative pulse of the first signal T1 may represent the first delay D1, the second negative pulse of the second signal T2 may represent the second delay D2, and the third negative pulse D3 of the timing signal T3 is shorter with respect to the first delay D1 and the second delay D2. In this alternative embodiment, the selector circuit 330 may include a logic NOR gate, the inputs of which may receive the first signal T1 having the first delay and the second signal T2 having the second delay; the output of the logic NOR gate of the selector circuit 330 may generate the timing signal T3 in response to the first signal if the first delay is shorter than the second delay, or the output of the logic NOR gate of the selector circuit 330 may generate the timing signal T3 in response to the second signal if the second delay is shorter than the first delay.

Those skilled in the art may implement the present technique using other combinations of pulse polarities for the first signal, the second signal and the timing signal, using appropriate logic gates to receive the first signal T1 at the first delay and the second signal T2 at the second delay, and generate the timing signal T3 in the manner described above.

FIG. 4 is a timing diagram showing the generation of timing signals when the read clock signal has a higher read frequency. The memory device comprises a memory cell array, a plurality of sense amplifiers coupled with the memory cells, a first port and a second port. The first port is used for receiving a read clock signal SCLK, the frequency of which is in the range from the lower read pulse frequency to the higher read pulse frequency, and the second port is used for receiving address signals, data signals and command signals synchronous with the read clock signal. In this example, the read clock signal SCLK with the higher read pulse frequency is input to the memory device 100 (FIG. 1) through the first port 110. The second port 120 (fig. 1) receives a set of addresses in a plurality of address cycles (e.g., 409, 410) in the read clock signal, the address cycles comprising a final cycle 410.

After receiving the address, the data in the memory cell of the memory cell array at the address is sensed during a sensing time D0.

The first signal T1 with the first delay D1 is generated according to the read pulse frequency of the read clock signal SCLK. The first delay D1 may begin at a particular period 411 in the read clock signal and its duration corresponds to a predetermined number of periods in the read clock signal. Although in this example, the predetermined number of cycles of the read frequency has 3 cycles (e.g., 411, 412, 413), this predetermined number may be greater or less than 3 cycles (which corresponds to a longer or shorter first delay D1) to suit the particular memory device. In this case, the first signal T1 may start at a rising edge of a specific period, or alternatively, the first signal T1 may start at a falling edge of a specific period, which is suitable for a specific memory device.

The second signal T2 at the second delay D2 is generated according to a second delay circuit independent of the read pulse frequency. For example, the second delay D2 may be approximately 50ns (nanoseconds). The second delay D2 may begin with a specific period 411 in the read clock signal (as with the first delay D1), and the second delay D2 has a fixed duration. For example, the second delay D2 may start at a leading edge (leading edge) of a specific period 411 in the reading clock signal SCLK. In one embodiment, the leading edge may be a rising edge. In an alternative embodiment, the leading edge may be a falling edge.

The timing signal T3 is generated in response to the first signal if the first delay is shorter than the second delay, or the timing signal T3 is generated in response to the second signal if the second delay is shorter than the first delay. In this example, the first delay D1 based on the high read pulse frequency is shorter than the second delay D2. For example, the second delay D2 is approximately 50ns, and the read clock signal has a high frequency of 100MHz, which is associated with one period (10ns) or 3 periods (30ns) of the first delay D1. The timing signal T3 is thus generated in response to the first signal T1, the first delay D1 ═ 30ns of the first signal T1 being shorter than the second delay D2 ═ 50ns of the second signal T2.

The memory device includes a plurality of data latches coupled to a plurality of sense amplifiers. After the memory cell at the address is electrically disconnected from the sense amplifier, the data read from the memory cell at the address is stored in the data latch at least until the read data is output from the second port.

The high read pulse frequency corresponds to a shorter period of a predetermined number of periods in the read clock signal and may be such that the first delay D1 of the first signal T1 is shorter than the second delay D2 of the second signal T2. For higher read pulse frequencies, the timing signal T3 is generated in response to the first signal T1.

Depending on the pulse polarity of the first signal T1, the second signal T2, and the timing signal T3, the timing signal T3 may be generated by performing appropriate logic functions for receiving the first signal T1 and the second signal T2. In the embodiment shown in FIG. 4, the first signal T1 has a first positive pulse representing the first delay D1, the second signal T2 has a second positive pulse representing the second delay D2, and the timing signal T3 has a third positive pulse D3, corresponding to the shorter of the first delay D1 and the second delay D2. In the present embodiment, the timing signal T3 can be generated by performing a logical AND function of receiving the first signal T1 at the first delay D1 AND the second signal T2 at the second delay D2.

In an alternative embodiment, the first signal T1 may have a first negative pulse representing the first delay D1, the second signal T2 may have a second negative pulse representing the second delay D2, and the timing signal T3 may have a third negative pulse D3 corresponding to the shorter of the first delay D1 and the second delay D2. In this alternative embodiment, the timing signal T3 may be generated by performing a logical NOR function of receiving the first signal T1 at the first delay D1 and the second signal T2 at the second delay D2.

Those skilled in the art may implement the present technique using other combinations of pulse polarities for the first signal, the second signal, and the timing signal, with appropriate logic functions to receive the first signal T1 at the first delay and the second signal T2 at the second delay and generate the timing signal T3 as described herein.

The address is received in a set of address cycles in the read clock signal, including a final cycle 410 in the set of address cycles. A particular cycle 411 in the read clock signal beginning at the first delay D1 and the second delay D2 is subsequent to the final cycle 410 in the set of address cycles.

In a set of data output cycles (e.g., 414, 415) in the read clock signal, the data read from the memory cell of the address is output from the second port (120, fig. 1). Before the first cycle 414 of the set of data output cycles, the memory cells at the address are electrically disconnected from the sense amplifiers.

FIG. 5 is a timing diagram showing the generation of timing signals when the read clock signal has a lower read pulse frequency. The memory device comprises a memory cell array, a plurality of sense amplifiers coupled with the memory cells, a first port and a second port. The first port is used for receiving a read clock signal SCLK, the frequency of which is in a read pulse frequency range from a lower read pulse frequency to an upper read pulse frequency, and the second port is used for receiving address signals, data signals and command signals (synchronous with the read clock signal). In this example, the read clock signal SCLK with the lower read pulse frequency is received by the memory device 100 via the first port 110 (FIG. 1). In a set of address cycles (e.g., 409, 410) in the read clock signal, including the final cycle 410, the address is received at the second port 120 (fig. 1).

After receiving the address, the memory cell data at the address from the memory cell array is sensed during sensing time D0.

The first signal T1 at the first delay D1 is generated based on the read pulse frequency of the read clock signal SCLK. Further description of the first signal T1 is provided with reference to fig. 4, which will not be repeated herein.

The second signal T2 at the second delay D2 is generated based on a second delay circuit independent of the read pulse frequency. Further description of the second signal T2 is provided with reference to fig. 4, which will not be repeated herein.

The timing signal T3 is generated in response to the first signal if the first delay is shorter than the second delay, or the timing signal T3 is generated in response to the second signal if the second delay is shorter than the first delay. In this example, the second delay D2 is shorter than the first delay D1 based on the lower read pulse frequency. For example, the second delay D2 is approximately 50ns, and the read clock signal has a lower frequency of 50MHz, corresponding to one period (20ns) or 3 periods (60ns) of the first delay D1. Therefore, the timing signal T3 is generated in response to the second signal T2, and the second signal T2 has a second delay D2 that is shorter than the first delay D1 of the first signal T1 by 60ns by 50 ns.

The memory device includes a plurality of data latches coupled to a plurality of sense amplifiers. After the memory cell at the address is electrically disconnected from the sense amplifier, the data read from the memory cell at the address is stored in the data latch at least until the read data is output from the second port in one set of output cycles (e.g., 414, 415). Therefore, when the read frequency has a lower read pulse frequency, power consumption can be reduced from the time when the memory cell at the address is electrically disconnected from the sense amplifier in response to the timing signal T3 to the time when the read data stored in the data latch is provided to the second port.

The lower read pulse frequency corresponds to a longer period of a predetermined number of periods in the read clock signal and may result in the first delay D1 of the first signal T1 being longer than the second delay D2 of the second signal T2. For lower read pulse frequencies, the timing signal T3 is generated in response to the second signal T2.

In the embodiment shown in FIG. 5 in which the first signal T1, the second signal T2 AND the timing signal T3 have positive pulse widths, the timing signal T3 can be generated by performing a logical AND function of receiving the first signal T1 at the first delay AND the second signal T2 at the second delay. Depending on whether the first signal T1, the second signal T2, and the timing signal T3 have positive/negative pulse widths, different logic functions suitable for performing the present technique may be used, as explained with reference to fig. 4.

The address is received in a set of address cycles in the read clock signal, including a final cycle 410 of the set of address cycles. The particular period 411 in the read clock signal that begins with the first delay D1 and the second delay D2 is after the final period 410 in the set of address cycles.

During a set of data output cycles (e.g., 414, 415) of the read clock signal, data read from the memory cell at the address is output from the second port (120, FIG. 1). Prior to the first cycle 414 of the set of data output cycles, the memory cell at the address is electrically disconnected from the sense amplifier in response to the timing signal T3.

FIG. 6 is a flow chart showing a method for reading a memory device. The memory device includes: the memory device comprises a memory cell array, a plurality of sense amplifiers coupled with the memory cells, a first port and a second port, wherein the first port receives a read frequency signal, the frequency of the read frequency signal is in a read pulse frequency range from a lower read pulse frequency to an upper read pulse frequency, and the second port is used for receiving address signals, data signals and command signals (synchronous with the read frequency signal). In step 610, an address synchronized with the read clock signal is received through the second port. In step 620, the memory cell at the address is electrically coupled to the sense amplifier during a read cycle. In step 630, in response to the timing signal, the memory cell at the address is electrically disconnected from the sense amplifier during the read cycle.

In step 640, a first signal having a first delay based on the frequency of the read clock signal and a second signal having a second delay independent of the frequency of the read clock signal are generated. In step 650, a timing signal is generated in response to the first signal if the first delay is shorter than the second delay, or in response to the second signal if the second delay is shorter than the first delay.

The memory device includes a plurality of data latches coupled to a plurality of sense amplifiers. After the memory cell at the address is electrically disconnected from the sense amplifier, the data read from the memory cell at the address is stored in the data latch at least until the read data is output from the second port.

The first delay (D1, fig. 4) based on the higher read pulse frequency is longer than the sensing time (D0, fig. 4) and shorter than the second delay (D2, fig. 4), while the second delay (D2, fig. 5) is longer than the sensing time (D0, fig. 5) and shorter than the first delay (D1, fig. 5) based on the lower read pulse frequency. The sensing time is between the first port receiving all bits of the address and forming a signal representing the sensed first data provided to the second port.

The first delay may start at a specific period in the read clock signal and have a period corresponding to a predetermined number of periods in the read clock signal, and the second delay may start at a specific period in the read clock signal and have a fixed period. The address is received in a set of address cycles in the read clock signal, and the particular cycle in the read clock signal is subsequent to a final cycle in the set of address cycles.

A logic AND function is performed to receive the first signal at the first delay AND the second signal at the second delay AND generate a timing signal.

The present technology is suitable for other Memory technologies, including dynamic Random Access Memory (dram), NAND flash Memory, NOR flash Memory, Resistive Random Access Memory (RRAM), and Phase Change Random Access Memory (PCRAM).

While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.