阅读说明：本技术 包括用于电流感测的分布式基准单元的存储器阵列 (Memory array including distributed reference cells for current sensing ) 是由 约翰·A·费尔德 艾瑞克·杭特史罗德 于 2019-06-11 设计创作，主要内容包括：本发明涉及包括用于电流感测的分布式基准单元的存储器阵列,揭示行列式存储器单元阵列,各列具有相应基准单元以及相应比较器。在给定行及给定列中的各存储器单元与该行的存储器字线及该列的存储器位线连接。各基准单元与针对这些基准单元的基准字线连接并与基准位线连接。针对列的各比较器具有电流镜,该电流镜具有与该列的该基准单元的该基准位线连接的基准部分以及与该列中的该存储器单元的该存储器位线连接的存储器部分。各基准部分具有电流镜节点,且该阵列中的所有电流镜节点被连接以减少失配并提升感测精度。改变施加于该存储器及基准字线的电压以提供精确的单端感测、容限测试等。(A column-wise array of memory cells, each column having a respective reference cell and a respective comparator, is disclosed. Each memory cell in a given row and a given column is connected to a memory word line of the row and a memory bit line of the column. Each reference cell is connected to a reference word line for the reference cell and to a reference bit line. Each comparator for a column has a current mirror with a reference portion connected to the reference bit line of the reference cell of the column and a memory portion connected to the memory bit line of the memory cell in the column. Each reference section has a current mirror node, and all current mirror nodes in the array are connected to reduce mismatch and improve sensing accuracy. The voltages applied to the memory and reference word lines are varied to provide accurate single-ended sensing, margin testing, etc.)

1. A memory array, comprising:

memory cells, wherein each memory cell has a first terminal connected to a common memory wordline for the memory cells of a row and a second terminal connected to a common memory bitline for the memory cells of a column;

reference cells, wherein each reference cell has a first terminal connected to a common reference word line and a second terminal connected to a reference bit line; and

comparators, wherein each comparator includes a current mirror, the current mirror including:

a reference part including a reference cell input node and a current mirror node, wherein the reference cell input node is electrically connected to a specific reference cell through a specific reference bit line, and wherein a current mirror node connector electrically connects all current mirror nodes of all the comparators; and

a memory portion including a memory cell input node and an output voltage node, wherein the memory cell input node is electrically connected to a particular common memory bit line for the memory cells of a particular column.

2. The memory array as set forth in claim 1,

wherein the reference portion includes two first P-type field effect transistors and a first N-type field effect transistor electrically connected in series between a supply voltage and a pull-down node,

wherein the reference unit input node is located at a junction between the two first PFETs, and the current mirror node is located at a junction between one of the two first PFETs and the first NFET,

wherein the memory portion includes two second PFETs and a second NFET electrically connected in series between the supply voltage and the pull-down node,

wherein the memory cell input node is located at a junction between the two second PFETs, and the output voltage node is located at a junction between one of the two second PFETs and the second NFET,

wherein the gates of the two first P-type field effect transistors and the two second P-type field effect transistors are controlled by a current mirror voltage at the current mirror node, an

Wherein the gates of the first N-type field effect transistor and the second N-type field effect transistor are controlled by a bias voltage, an

Wherein an additional NFET electrically connects the pull-down node to ground.

3. The memory array of claim 1, wherein each comparator further comprises a secondary comparator circuit that compares an output voltage at the output voltage node with a current mirror voltage at the current mirror node and outputs a digital signal at a digital output node, wherein a value of the digital signal varies according to a voltage difference between the current mirror voltage and the output voltage, and wherein the voltage difference is dependent on a current difference between a current conducted by the particular reference cell connected to the particular reference bit line and a current conducted by a selected memory cell connected to the particular common memory bit line.

4. The memory array of claim 1, wherein each comparator further comprises a secondary comparator circuit, the secondary comparator circuit comprising:

a differential amplifier receiving as inputs a current mirror voltage from the current mirror node and an output voltage from the output voltage node; and

an inverter connected in series with the differential amplifier and outputting a digital signal at a digital output node, wherein a value of the digital signal varies according to a voltage difference between the current mirror voltage and the output voltage, and wherein the voltage difference is dependent on a current difference between a current conducted by the particular reference cell connected to the particular reference bit line and a current conducted by a selected memory cell connected to the particular common memory bit line.

5. The memory array of claim 1, further comprising:

a memory word line voltage generator generating a memory word line voltage;

a memory word line decoder which applies the memory word line voltage to the memory word lines, respectively;

a reference word line voltage generator generating a reference word line voltage; and

a reference word line decoder applying the reference word line voltage to the reference word line,

wherein the levels of the memory wordline voltage and the reference wordline voltage are varied by the memory wordline voltage generator and the reference wordline voltage generator, respectively, depending on the operation being performed.

6. The memory array as set forth in claim 5,

wherein, during a read operation to determine whether a selected memory cell is unprogrammed or programmed, the reference word line voltage generator sets the reference word line voltage at a first level sufficient to ensure that each reference cell conducts a reference amount of current approximately midway between a first amount of current expected to be conducted by an unprogrammed memory cell and a second amount of current less than the first amount of current and expected to be conducted by a programmed memory cell, and

wherein the reference word line voltage generator sets the reference word line voltage at a second level different from the first level to facilitate margin testing during a write operation to program the selected memory cell.

7. The memory array of claim 1, wherein each of the memory cells and the reference cell comprises a single charge trapping field effect transistor.

8. The memory array of claim 1, wherein each of the memory cells and the reference cell comprises a plurality of charge trapping field effect transistors connected in parallel.

9. The memory array of claim 1, wherein all reference bit lines connecting the reference cell and the comparator are electrically connected.

10. A memory array, comprising:

memory cells, wherein each memory cell has a first terminal connected to a common memory wordline for the memory cells of a row, a second terminal connected to a common memory bitline for the memory cells of a column, and a third terminal connected to ground;

reference cells, wherein each reference cell has a first terminal connected to a common reference word line, a second terminal connected to a reference bit line, and a third terminal connected to ground;

comparators, each comparator including a current mirror, the current mirror including:

a reference part including a reference cell input node and a current mirror node, wherein the reference cell input node is electrically connected to a specific reference cell through a specific reference bit line, and wherein a current mirror node connector electrically connects all current mirror nodes of all the comparators; and

a memory portion including a memory cell input node and an output voltage node, wherein the memory cell input node is electrically connected to a particular common memory bit line for the memory cells of a particular column;

a memory word line voltage generator generating a memory word line voltage;

a memory word line decoder applying the memory word line voltage to the memory word line;

a reference word line voltage generator generating a reference word line voltage; and

a reference word line decoder applying the reference word line voltage to the reference word line,

wherein levels of the memory word line voltage and the reference word line voltage are changed by the memory word line voltage generator and the reference word line voltage generator, respectively, depending on whether a read, write or erase operation is being performed.

11. The memory array as set forth in claim 10,

wherein the reference portion includes two first P-type field effect transistors and a first N-type field effect transistor electrically connected in series between a supply voltage and a pull-down node,

wherein the reference unit input node is located at a junction between the two first PFETs, and the current mirror node is located at a junction between one of the two first PFETs and the first NFET,

wherein the memory portion includes two second PFETs and a second NFET electrically connected in series between the supply voltage and the pull-down node,

wherein the memory cell input node is located at a junction between the two second PFETs, and the output voltage node is located at a junction between one of the two second PFETs and the second NFET,

wherein the gates of the two first P-type field effect transistors and the two second P-type field effect transistors are controlled by a current mirror voltage at the current mirror node, an

Wherein the gates of the first N-type field effect transistor and the second N-type field effect transistor are controlled by a bias voltage, an

Wherein an additional NFET electrically connects the pull-down node to ground.

12. The memory array of claim 10, wherein each comparator further comprises a secondary comparator circuit that compares an output voltage at the output voltage node with a current mirror voltage at the current mirror node and outputs a digital signal at a digital output node, wherein a value of the digital signal varies according to a voltage difference between the current mirror voltage and the output voltage, and wherein the voltage difference is dependent on a current difference between a current conducted by the particular reference cell connected to the particular reference bit line and a current conducted by a selected memory cell connected to the particular common memory bit line.

13. The memory array of claim 10, wherein each comparator further comprises a secondary comparator circuit, the secondary comparator circuit comprising:

a differential amplifier receiving as inputs a current mirror voltage from the current mirror node and an output voltage from the output voltage node; and

an inverter connected in series with the differential amplifier and outputting a digital signal at a digital output node, wherein a value of the digital signal varies according to a voltage difference between the current mirror voltage and the output voltage, and wherein the voltage difference is dependent on a current difference between a current conducted by the particular reference cell connected to the particular reference bit line and a current conducted by a selected memory cell connected to the particular common memory bit line.

14. The memory array of claim 10, wherein each of the memory cells and the reference cell comprises a single charge trapping field effect transistor.

15. The memory array of claim 10, wherein each of the memory cells and the reference cell comprises a plurality of charge trapping field effect transistors connected in parallel.

16. The memory array of claim 10, wherein during a read operation to determine whether a selected memory cell is unprogrammed or programmed, the reference word line voltage generator sets the reference word line voltage at a first level sufficient to ensure that each reference cell conducts a reference amount of current that is approximately midway between a first amount of current expected to be conducted by an unprogrammed memory cell and a second amount of current less than the first amount of current and expected to be conducted by a programmed memory cell.

17. The memory array of claim 16, wherein the reference word line voltage generator sets the reference word line voltage at a second level during a write operation to program the selected memory cell, the second level being different from the first level to facilitate a margin test.

18. The memory array of claim 16, wherein the reference word line voltage generator sets the reference word line voltage at a second level during a write operation to program the selected memory cell, the second level being lower than the first level such that the amount of reference current conducted by each reference cell during the write operation is closer to the second amount of current.

19. The memory array of claim 10, wherein all reference bit lines connecting the reference cell and the comparator are electrically connected.

20. A memory array, comprising:

memory cells, wherein each of the memory cells includes at least one charge trapping field effect transistor, and wherein each of the memory cells has a first terminal connected to a common memory wordline for the memory cells of a row, a second terminal connected to a common memory bitline for the memory cells of a column, and a third terminal connected to ground;

a reference cell, wherein the reference cell is substantially identical to the memory cell, and wherein each reference cell has a first terminal connected to a common reference word line, a second terminal connected to a reference bit line, and a third terminal connected to ground;

comparators, each comparator including a current mirror, the current mirror including:

a reference part including a reference cell input node and a current mirror node, wherein the reference cell input node is electrically connected to a specific reference cell through a specific reference bit line, and wherein a current mirror node connector electrically connects all current mirror nodes of all the comparators; and

a memory portion including a memory cell input node and an output voltage node, wherein the memory cell input node is electrically connected to a particular common memory bit line for the memory cells of a particular column;

a memory word line voltage generator generating a memory word line voltage;

a memory word line decoder applying the memory word line voltage to the memory word line;

a reference word line voltage generator generating a reference word line voltage; and

a reference word line decoder applying the reference word line voltage to the reference word line,

wherein the levels of the memory word line voltage and the reference word line voltage are changed by the memory word line voltage generator and the reference word line voltage generator, respectively, depending on whether a read, write or erase operation is being performed,

wherein, during a read operation to determine whether a selected memory cell is unprogrammed or programmed, the reference word line voltage generator sets the reference word line voltage at a first level sufficient to ensure that each reference cell conducts a reference current approximately midway between a first amount of current expected to be conducted by an unprogrammed memory cell and a second amount of current less than the first amount of current and expected to be conducted by a programmed memory cell, and

wherein the reference word line voltage generator sets the reference word line voltage at a second level, the second level being lower than the first level, during a write operation to program the selected memory cell to facilitate margin testing.

Technical Field

The present invention relates to charge trap (charge trap) memory arrays, and more particularly to memory arrays having distributed charge trap reference cells to support single-ended current sensing of charge trap memory cells.

Background

Recently developed multi-time programmable memory (MTPM) arrays include charge trapping memory cells (cells) arranged in rows and columns. Each memory cell includes a pair of Charge Trap Field Effect Transistors (CTFETs), and thus the memory cell is referred to as a two-transistor memory cell. In each column, the CTFETs in each memory cell are connected in series between a pair of bit lines (bitlines) that are connected to a sense amplifier, and the node of the source line between the CTFETs connects each memory cell in the column to ground. In each row (row), the gates of the CTFETs in the memory cells are connected to a word line (word). Generally, during a read operation of a selected memory cell, a read voltage is applied through a word line to the gate of the CTFET in the selected memory cell, and a sense amplifier determines a voltage difference between adjacent bit lines to determine whether the selected memory cell stores a "1" bit or a "0" bit. During a write operation of a selected memory cell, the threshold voltage of one of the CTFETs in that memory cell is changed by injecting charge into its gate or gate oxide to program the memory cell (i.e., store a "1" therein). Specifically, a higher write voltage is applied to the gate of the CTFET in a selected memory cell through a word line, and a sense amplifier determines the voltage difference between the pair of adjacent bit lines connected to the selected memory cell. These processes are repeated until the desired voltage difference is confirmed to be present, indicating that the selected memory cell is programmed. During an erase operation for a previously programmed memory cell, a reverse field is applied so that the memory cell is no longer programmed. However, those skilled in the art will appreciate that the injected charge in the charge trapping field effect transistor will decrease over time, and this charge loss may eventually lead to a read error (e.g., may eventually lead to the memory cell being read as unprogrammed ("0") rather than programmed ("1")).

Disclosure of Invention

Embodiments of a memory array configured with a combination of charge trapping memory cells and distributed charge trapping reference cells (reference cells) to support (enable) single-ended current sensing of the memory cells, programming of the memory cells using margin testing with limited rewriting (marking testing) techniques, and optional de-programming (i.e., erasing of the memory cells) are disclosed herein.

In particular, the memory array may include memory cells arranged in rows and columns (e.g., charge trapping memory cells including one or more Charge Trap Field Effect Transistors (CTFETs)). The memory array may also include a reference cell and a comparator, with each column of memory cells having a respective reference cell and a respective comparator.

Each memory cell in a given row and a given column may have a first terminal (e.g., a gate terminal) electrically connected to a common memory wordline of the given row, a second terminal (e.g., a drain terminal) electrically connected to a common memory bitline of the given column, and a third terminal (e.g., a source terminal) electrically connected to ground.

Each reference cell may be substantially identical in structure to a memory cell. Each reference cell of a given column may have a first terminal (e.g., a gate terminal) electrically connected to a common reference word line for all of the reference cells, a second terminal (e.g., a drain terminal) electrically connected to the reference bit line of the reference cell, and a third terminal (e.g., a source terminal) electrically connected to ground.

Each comparator of a given column may be configured to output a digital (digital) signal indicative of a current difference between a current conducted by the reference cell of the given column and a current conducted by a selected memory cell in the given column. Specifically, the digital signal may indicate whether the current flowing through the selected memory cell is above or below a reference current amount (i.e., the current flowing through the reference cell).

To achieve this, each comparator may include a current mirror and a secondary comparator circuit. The current mirror may have a reference portion (also referred to as a reference segment) and a memory portion (also referred to as a memory segment). The reference portion may include a reference cell input node that is electrically connected to a particular reference bit line and thus to a particular reference cell (i.e., the reference cell of the given column). The reference portion may further include a current mirror node electrically connected to all of the current mirror nodes on all of the comparators to balance the threshold voltage difference across the reference cells. The memory portion may include a memory cell input node and an output voltage node. The memory cell input node may be electrically connected to a particular common memory bitline of the given row and thus to all of the memory cells in the given row. In response to different currents flowing through the reference cell and the selected memory cell, the current mirror will output different analog voltages, particularly a current mirror voltage and an output voltage at the current mirror node and the output voltage node, respectively. The secondary comparator circuit compares the different analog voltages and outputs a digital signal at a digital output node indicative of the voltage difference. The value of the digital signal at the digital output node will vary depending on the voltage difference between the current mirror voltage and the output voltage.

In addition to the above features, embodiments of the memory array may further include: a word line voltage generator generating a memory word line voltage; a word line decoder applying the memory word line voltage to the memory word line; a reference word line voltage generator generating a reference word line voltage; and a reference word line decoder applying the reference word line voltage to the reference word line. The levels (levels) of the memory word line voltage and the reference word line voltage generated by the memory word line voltage generator and the reference word line voltage generator respectively applied to the memory word line and the reference word line may be selectively changed depending on whether a read, write, or optional erase operation is being performed. For example, during a read operation to determine whether a selected memory cell is unprogrammed or programmed, the reference word line voltage generator may set the reference word line voltage at a first level sufficient to ensure that each reference cell conducts a reference current that is approximately halfway (midway) between a first amount of current expected to be conducted by an unprogrammed memory cell and a second amount of current less than the first amount of current and expected to be conducted by a programmed memory cell. During a write operation to program the selected memory cell, the reference word line voltage generator may set the reference word line voltage at a second level, the second level being lower than the first level, to facilitate margin testing.

Drawings

The invention will be better understood from the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

FIG. 1 shows a schematic diagram of an embodiment of a disclosed memory array;

FIGS. 2A and 2B show schematic diagrams of different exemplary memory cells that may be included in the memory array of FIG. 1;

FIG. 3 shows a schematic diagram of an example comparator that may be included in the memory array of FIG. 1;

FIG. 4A shows a schematic diagram of another example comparator that may be included in the memory array of FIG. 1; and

fig. 4B shows a timing diagram of the levels of control signals employed during operation of the comparator of fig. 4A.

Detailed Description

As described above, the injected charge in the Charge Trapping Field Effect Transistor (CTFET) of a memory cell will decrease over time, and this charge loss may eventually lead to read errors (e.g., may eventually lead to the memory cell being read as unprogrammed ("0") rather than programmed ("1")). A margin test technique may be employed in which more charge than is needed is injected into the gate or gate oxide during a write operation to compensate for the expected charge loss. For example, if the memory cell requires a 50mV difference to be read by the sense amplifier as programmed, a margin test technique may be performed in which a high voltage is repeatedly applied to the gate of the CTFET until a 100mV (not 50mV) difference is identified. Unfortunately, rewriting the memory cell, and particularly repeatedly applying a voltage higher than necessary to the memory cell, may damage the memory cell (e.g., may result in Time Dependent Dielectric Breakdown (TDDB)). Also, such margin testing techniques may not be accurate enough to prevent read errors.

In view of the foregoing, embodiments of memory arrays having distributed charge trapping reference cells to support single-ended current sensing of charge trapping memory cells are disclosed herein. The memory array may be a one-time programmable memory (OPTM) array or may include an optional erase function to make it a multi-time programmable memory (MTPM) array. In any case, the memory array includes a memory cell, a reference cell, and a comparator. The memory cells are arranged in rows and columns, each column having a respective reference cell and a respective comparator. Each memory cell in a given row and a given column has a common memory word line with the given row, a common memory bit line with the given column, respectively, and a terminal connected to ground. Each reference cell of a given column has a common reference word line with all reference cells, respectively, a reference bit line with the reference cell, and a terminal connected to ground. Each comparator of a given column has a current mirror with a reference portion and a memory portion. The reference portion is connected to a reference bit line and thus to the reference cells of the given column, and the memory portion is connected to a common memory bit line and thus to the memory cells in the given column. In addition, each reference portion has a current mirror node, and all current mirror nodes of all comparators in the memory array are electrically connected to balance process variations on the reference cells. Each comparator compares the current conducted by the reference cell with the current conducted by the selected memory cell during a read operation to determine the programmed state of the cell, during a write operation to verify programming, and optionally during an erase operation to verify erase. The voltages applied to the memory word lines and the reference word line are selectively varied (as described in more detail below) to support single-ended current sensing of the memory cells, programming of the memory cells using a margin test technique that limits rewriting, and optional de-programming (i.e., erasing) of the memory cells. It should be noted that by electrically connecting the current mirror nodes in the reference portion of all comparators on the memory array, the disclosed configuration balances process variations across the reference cell and other devices within the reference portion of the current mirror, thus reducing the effects of mismatch and increasing sensing accuracy.

In particular, referring to FIG. 1, an embodiment of a memory array 100 is disclosed herein. Such a memory array 100 may include memory cells 110, memory bit lines 181, memory word lines 183, a memory word line decoder 140 (i.e., a row address decoder), and a memory word line voltage generator 170 (e.g., a digital to analog converter (DAC)). The memory array 100 may also include a reference cell 120, a reference bit line 182, a single reference word line 184, a reference word line decoder 150, and a reference word line voltage generator 160. The array 100 may also include a comparator 130.

Specifically, the memory cells 110 may be arranged in rows 101 and columns 102. Each row 101 of memory cells 110 may share a single common memory word line 183. The common memory word lines 183 may be connected with the memory word line voltage generator 170 (e.g., via the connector 188) through respective memory word line decoders 140. During operation, the memory word line voltage generator 170 receives the word line DAC input signal (WL _ DAC) and sets the memory word line voltage (V _ WL) based on this signal. The memory word line decoder 140 receives a decoding input (i.e., address bit) identifying the selected memory word line 183 and, in response, applies a memory word line voltage (V _ WL) to the selected memory word line 183 through the appropriate memory word line decoder 140. Each column 102 of memory cells 110 may share a single common memory bit line 181, and may have a respective reference cell 120 and a respective comparator 130 at one end, as shown.

Each memory cell 110 may be a charge trapping memory cell including at least one Charge Trapping Field Effect Transistor (CTFET). For example, referring to fig. 2A, each memory cell 110 may include a single larger N-type CTFET 201 having three terminals including: a first terminal 211, in particular a gate terminal; a second terminal 212, in particular a drain terminal; and a third terminal 213, in particular a source terminal. Alternatively, referring to fig. 2B, each memory cell 110 may include a plurality of smaller N-type CTFETs (e.g., 201a-201B) electrically connected in parallel and having three common terminals, including: a common first terminal 211, in particular a common gate terminal, wherein all gates of all CTFETs in the cell are shorted together; a common second terminal 212, in particular a common drain terminal, wherein all drains of all CTFETs in the cell are shorted together; and a common third terminal 213, in particular a common source terminal, wherein all sources of all CTFETs in the cell are shorted together. In any case, the first terminals 211 (e.g., gate terminals) of the memory cells 110 in any given row may be electrically connected to the common memory word line 183 of that row. The second terminal 212 (e.g., drain terminal) of each memory cell 110 in any given column may be electrically connected to the common memory bit line 181 of that column. Finally, the third terminals 213 (e.g., source terminals) of all memory cells may be electrically connected to ground.

The reference cells 120 may be arranged in a single row, with each reference cell 120 located at an end of a respective column 102 of memory cells 110. The reference cells 120 of the row may share a single common reference word line 184. The common reference wordline 184 may be connected to the reference wordline voltage generator 160 through the reference wordline decoder 150. The reference word line voltage generator 160 may also be connected to a memory word line voltage generator 170. As described above, during operation, the memory word line voltage generator 170 receives the word line DAC input signal (WL _ DAC) and sets the memory word line voltage (V _ WL) based on the signal. Further, the reference word line voltage generator 160 receives the reference word line DAC input signal (REFWL _ DAC), sets a reference word line voltage (V _ REFWL) based on the signal and the memory word line voltage (V _ WL) output from the memory word line voltage generator 170, and applies the reference word line voltage to the reference word line 184 through the reference word line decoder 150. Each reference cell 120 associated with a given column 102 of memory cells may also be electrically connected to a corresponding comparator 130 of that column 102 by a separate reference bit line 182. Alternatively, all of the reference bit lines 182 respectively connecting the reference cells 120 and the comparators 130 may be electrically connected (e.g., via the reference bit line connector 187).

The reference cell 120 may be substantially identical in structure to the memory cell 110. That is, each reference cell 120 may be a charge trapping reference cell including at least one Charge Trapping Field Effect Transistor (CTFET), e.g., at least one N-type CTFET. For example, referring to fig. 2A, each reference cell 120 may include a single larger N-type CTFET 201 having three terminals including: a first terminal 211, in particular a gate terminal; a second terminal 212, in particular a drain terminal; and a third terminal 213, in particular a source terminal. Alternatively, referring to fig. 2B, each reference cell 120 may include a plurality of smaller N-type CTFETs (e.g., 201a-201B) electrically connected in parallel and having three common terminals, including: a common first terminal 211, in particular a common gate terminal, wherein all gates of all CTFETs in the cell are shorted together; a common second terminal 212, in particular a common drain terminal, wherein all drains of all CTFETs in the cell are shorted together; and a common third terminal 213, in particular a common source terminal, wherein all sources of all CTFETs in the cell are shorted together. However, the first terminals 211 (e.g., gate terminals) of the reference cells 120 may be electrically connected to the same common reference word line 184. The second terminal 212 (e.g., drain terminal) of each reference cell 120 associated with a given column may be electrically connected with the reference bit line 182. Finally, the third terminals 213 (e.g., source terminals) of all reference cells 120 may be electrically connected to ground.

Each comparator 130 of a given column 102 may include a memory cell input node 131, a reference cell input node 132, and a digital output node 134. The memory cell input nodes 131 may be electrically connected to a common memory bit line 181, and thus to each memory cell 110 in a given column 102. The reference cell input nodes 132 may be electrically connected to separate reference bit lines 182 and, thus, to the corresponding reference cells 120 of the given column. Each comparator 130 may also be configured to compare the currents conducted by the reference cell 120 (via reference cell input node 132 and reference bit line 182) and by the selected memory cell 110 (via memory cell input node 131 and common memory bit line 181), and in response, may output a digital signal (D-OUT) at digital output node 134 indicating the current difference. Specifically, the digital signal (D-OUT) indicates whether the amount of current conducted by the selected memory cell 110 is greater than or less than the amount of current conducted by the reference cell 120.

FIG. 3 shows a schematic diagram of an example comparator 130 that may be included in the memory array 100 of FIG. 1. Specifically, each comparator 130 of a given column 102 may include a current mirror 390 and a secondary comparator circuit 350.

Current mirror 390 may include a reference portion 391 and a memory portion 392.

The reference section 391 may include, for example, two first P-type field effect transistors (PFETs) 301, 303 and one first N-type field effect transistor (NFET)305 electrically connected in series between the supply voltage 380 and the pull-down node 320. The reference section 391 may also include a reference cell input node 132 located at the junction between the two first PFETs 301, 303. The reference cell input node 132 may also be electrically connected to a particular reference bit line 182 and, thus, to a particular reference cell 120 of the given row. Reference section 391 may also include a current mirror node 133 located at the junction between first PFET 303 and first NFET 305.

The memory portion 392 may include two second PFETs 302, 304 and one second NFET 306 electrically connected in series between the supply voltage 380 and the same pull-down node 320. The pull-down node 320 may be electrically connected to ground through the bottom device 307 (e.g., an additional NFET). The memory portion 392 may also include a memory cell input node 131 located at the junction between the two second PFETs 302, 304. The memory cell input node 131 may also be electrically connected to a particular common memory bit line 181, and thus to all of the memory cells 110 in the given row. Memory portion 392 may also include an output voltage node 310 located at the junction between second PFET 304 and second NFET 306.

The current mirror node 133 of the reference section 391 may also be electrically connected to the gates of the two first PFETs 301, 303 in the reference section 391 and the gates of the two second PFETs 302, 304 in the memory section 392. Thus, the current mirror voltage (V _ MID) at current mirror node 133 controls the flow of current through PFET 301-304. Further, the current mirror nodes 133 in the current mirrors 390 of all comparators 130 may be electrically connected (e.g., by the current mirror node connectors 186). By shorting current mirror nodes 133 together using current mirror node connector 186, the memory array configuration balances process variations, particularly threshold variations across the average reference cell 120 and first PFETs 301 and 303. In other words, the current mirror voltage (V MID) of the current mirror node 133 in the current mirror 390 of any comparator 130 in the array will be highly invariant with respect to threshold voltage variations in the reference cell 120 or in the first PFET 301, 303 of the reference section 391 on the array. Thus, the disclosed configuration reduces the effects of mismatch and increases sensing accuracy.

During operation, in the reference section 391 of the current mirror 390, current conducted through the first PFET 301, into the particular reference bit line 182 and further into the particular reference cell 120 (which is electrically connected to the reference cell input node 132 through the particular reference bit line 182) results in a current mirror voltage (V _ MID) on the current mirror node 133 of the reference section 391. This current mirror voltage (V MID) controls the gates of the first PFETs 301 and 303 in the reference portion 391 and the gates of the second PFETs 302 and 304 of the memory portion 392. In addition, in the memory portion 392 of the current mirror 390, current conducted through the second PFET 302, into the particular common memory bit line 181, and further into the selected memory cell 110 (which is electrically connected to the memory cell input node 131 through the particular common memory bit line 181) results in an output voltage (V _ OUT) at the output voltage node 310. The voltage difference between the current mirror voltage (V _ MID) at the current mirror node 133 and the output voltage (V _ OUT) at the output voltage node 310 will indicate the current difference between the currents conducted by the reference cell 120 and the selected memory cell 110.

The secondary comparator circuit 350 compares these different analog voltages (i.e., the current mirror voltage at the current mirror node 133 and the output voltage at the output voltage node 310) and outputs a digital signal (D-OUT) at the digital output node 134 indicating the voltage difference. That is, the value of the digital signal (D-OUT) at the digital output node 134 will vary depending on the voltage difference between the current mirror voltage (V _ MID) and the output voltage (V _ OUT), and in particular will switch depending on whether the output voltage (V _ OUT) is higher or lower than the current mirror voltage (V _ MID).

Fig. 4A shows a more detailed schematic diagram of the comparator 130 of fig. 3 including an example secondary comparator circuit 350 that may be incorporated. The example secondary comparator circuit 350 includes a differential amplifier 359 (see, e.g., the example differential amplifier 359 including FETs 351-355) and an inverter 357 connected in series with an output node (node a) of the differential amplifier 359. The differential amplifier 359 receives as inputs the current mirror voltage (V _ MID) from the current mirror node 133 and the output voltage (V _ OUT) from the output voltage node 310, and outputs an output signal at the output node a. The inverter 357 inverts the output signal, thereby outputting the inverter output signal (i.e., the digital signal (D _ OUT)) at the digital output node 134 (i.e., node B). Inverter 357 inputs near digital levels on node a and converts them to full CMOS levels on node B. The value of the digital signal (D _ OUT) will vary depending on the voltage difference between the current mirror voltage (V _ MID) from the current mirror 390 and the output voltage (V _ OUT), and this voltage difference will vary depending on the current difference between the current conducted by the particular reference cell 120 connected to the particular reference bit line 182 and the current conducted by the selected memory cell 110 connected to the particular common memory bit line 181.

Fig. 4B shows an example timing diagram of various control signal levels at different times during operation of the comparator of fig. 4A. Specifically, referring to fig. 4A and 4B in combination, the control signals of the comparator may include SAENP, SETN, DATAXP, and READP. The input SAENP activates the sensing period when it goes high (high). Input SETN starts high and shunts current mirror node 133 to output voltage node 310 to equalize the voltages on these two nodes prior to sensing. When input SETN goes low, the equalization operation is terminated and input READP goes high to activate bottom device 307, providing a conduction path to ground through current source NFETs 305 and 306, which current source NFETs 305 and 306 are controlled by the bias voltage (i.e., VBIAS supply level). It should be understood that VBIAS may be generated from an on-chip bandgap current source or from any other suitable source. At this time, the differential currents flowing in the reference cell input node 132 and the memory cell input node 131 from the reference cell 120 and the memory cell 110, respectively, generate voltage differences on the current mirror node 133 and the output voltage node 310, respectively. The voltage difference represents the type of data stored in the memory cell 110. Programmed cells cause the output voltage (V _ OUT) at the output voltage node 310 to be higher than the current mirror voltage (V _ MID) at the current mirror node 133, while unprogrammed cells cause V _ OUT to be lower than V _ MID. This differential voltage (V _ MID, V _ OUT) provides an input to a secondary comparator circuit 350, which further amplifies this difference at node a to a near full Vdd level signal. Inverter 357 converts the voltage level at node a to a full 0 volt or full Vdd-level digital signal level. After this data amplification operation is completed, SAENP goes low and the output strobe DATAXP goes high, indicating that the data on digital output node 134 (i.e., node B) is valid. At the end of the sense cycle, SETN returns high, and DATAXP and READP go low before beginning the subsequent sense operation.

It should be understood that the secondary comparator circuit 350 shown in fig. 4A is for purposes of example and is not intended to be limiting. Alternatively, any other secondary comparator circuit configured to output a digital signal (D _ OUT) indicative of the voltage difference between V _ MID and V _ OUT may be used.

With the above configuration, the levels of the memory word line voltage (V _ WL) and the reference word line voltage (V _ REFWL), which are generated by the memory word line voltage generator 170 and the reference word line voltage generator 160 and applied to the selected memory word line and the reference word line, respectively, can be selectively changed depending on whether a read, write, or optional erase operation is being performed. Specifically, as described in more detail below, the levels of the memory word line voltage (V _ WL) and the reference word line voltage (V _ REFWL) can be varied to achieve the following goals: (1) accurate single-ended current sensing of memory cells during a read operation to determine whether a selected memory cell is programmed or unprogrammed, during a write operation to confirm programming of the selected memory cell, and during an erase operation to confirm de-programming of the selected memory cell; (2) programming of selected memory cells during write operations using a margin test technique that compensates for charge loss while limiting rewriting; and (3) de-programming of selected memory cells during erase operations in the case of multi-time programmable memories (MTPM).

It should be noted that an unprogrammed memory cell in memory array 100 will have a first threshold voltage and will be expected to conduct a first amount of current, while a programmed memory cell in memory array 100 will have a second threshold voltage greater than the first threshold voltage and will be expected to conduct a second amount of current less than the first amount of current.

Thus, for example, during a READ operation to determine whether a selected memory cell is unprogrammed or programmed, the memory word line voltage (V _ WL) generated by the memory word line voltage generator 170 can be set (e.g., by applying the appropriate WL DAC signal) to some predetermined READ voltage level (V _ READ) above (e.g., 50-100mV above) this second threshold voltage of the programmed memory cell. Further, the reference word line voltage (V _ reffill) generated by the reference word line voltage generator 160 may be set (e.g., by applying a suitable reffill _ DAC) at a first reference word line voltage level (V _ REFREAD) sufficient to ensure that the corresponding reference cell (i.e., the reference cell connected to the same comparator as the selected memory cell) will conduct a reference current amount that is intermediate between the first current amount expected to be conducted by the selected memory cell being read when the selected memory cell is unprogrammed and the second current amount expected to be conducted by the selected memory cell being read when the selected memory cell is programmed. Depending on the current difference between the currents conducted by the reference cell 120 and the selected memory cell 110, the current mirror 390 will output different voltages, particularly a current mirror voltage (V _ MID) at the current mirror node 133 and an output voltage (V _ OUT) at the output voltage node 310. The secondary comparator circuit 350 then compares the current mirror voltage (V _ MID) with the output voltage (V _ OUT) and outputs a digital signal (D-OUT) at the digital output node 134 indicating the voltage difference.

More specifically, the cell overdrive (Vgs-Vt) is determined by the V _ WL level (i.e., VREAD) used during the read operation and by the threshold voltage of the selected memory cell 110 being read. As described above, this threshold voltage will be lower if the memory cell is unprogrammed and higher if the memory cell is programmed. Thus, for a given VREAD level, there is a "0" cell current level and a "1" cell current level. For example, given a V _ READ on the memory word line 183 and a V _ REFEAD on the reference word line, when the current mirror voltage (V _ MID) is greater than the output voltage (V _ OUT) (indicating that the amount of current conducted by the reference cell 120 is less than the amount of current conducted by the selected memory cell 110), the digital signal (D _ OUT) at the digital output node 134 will go low indicating that the selected memory cell is unprogrammed (i.e., storing a "0"). However, if the current mirror voltage (V _ MID) is less than the output voltage (V _ OUT) (indicating that the amount of current conducted by the reference cell 120 is greater than the amount of current conducted by the selected memory cell 110), then the digital signal (D _ OUT) at the digital output node 134 will go high indicating that the selected memory cell 110 is programmed (i.e., storing a "1").

During a write operation, the memory cell 110 is programmed by injecting charge into the first terminal 211 (see fig. 2A or 2B), particularly into the gate or gate oxide of the gate terminal, to increase the threshold voltage of the CTFET in the memory cell 110. Specifically, as described above, an unprogrammed memory cell will have a first threshold voltage and be expected to conduct a first amount of current. During a WRITE operation, the memory word line voltage (V _ WL) generated by the memory word line voltage generator 170 is set (e.g., by applying an appropriate WL _ DAC signal) at some predetermined WRITE voltage level (V _ WRITE), which is higher than the READ voltage level (V _ READ) and high enough to inject charge into the first terminal 211, particularly into the gate or gate oxide of the gate terminal of the selected memory cell 110 being programmed. The injection of charge increases the threshold voltage to at least a second threshold voltage greater than the first threshold voltage, and thus, the programmed memory is expected to conduct only a second amount of current that is less than the first amount of current during a READ operation when V _ WL is set at V _ READ. A higher write voltage is applied to the first terminal until comparator 130 confirms that the selected memory cell 110 has been programmed.

It should be noted that the reference word line voltage (V _ REFWL) applied to the reference word line 184 during a write operation and used to confirm that the selected memory cell 110 has been programmed may be the same as that used during the read process.

Alternatively, the reference word line voltage (V _ REFWL) may be offset to enable a unique margin test technique to be performed. With this margin testing technique, rather than increasing the threshold voltage of the selected memory cell to a baseline threshold voltage level sufficient to enable the selected memory cell to be read as programmed during a read operation, the threshold voltage is increased beyond the baseline threshold voltage level to some higher target threshold level. To this end, when verifying whether the selected memory cell 110 has been programmed during this write operation, the reference wordline voltage (V _ REFWL) is set (e.g., by applying an appropriate REFWL _ DAC) at some predetermined second reference wordline voltage level (V _ refland) that is different from the predetermined first reference wordline voltage level (V _ refred) used during the read operation (as described above). The predetermined second reference wordline voltage level (V _ refland) is particularly less than the predetermined first reference wordline voltage level (V _ REFREAD), so that the reference cell 120 (connected to the same comparator 130 as the selected memory cell 110 being programmed) conducts a lower reference current amount during the write operation than it otherwise conducts during the read operation. That is, the predetermined second reference word line voltage level (V _ reffringe) may be set such that the reference current amount during the write operation is closer to a lower second current amount associated with the programmed memory cells relative to a higher first current amount associated with the unprogrammed memory cells. Therefore, before the required voltage difference is sufficient to switch the digital signal (D _ OUT) from low to high (indicating that the memory cell has been properly programmed), more charge will need to be injected into the first terminal 211 of the memory cell 110. Specifically, during a write operation, the level of the reference word line voltage (V _ refbold) may be reduced from V _ refresh to V _ refbright by an amount equal to the required margin test in millivolts (i.e., by an amount equal to the required extra charge to be injected into the first terminal 211 of the memory cell). Margin test accuracy is ensured by using this technique because there is a 1:1 relationship between the amount of reduction in the reference word line voltage level (V _ WL) (i.e., the difference between V _ refresh and V _ fwrite) during a write operation and the amount of margin voltage (i.e., the amount of extra charge injected into the gate or gate oxide of the gate terminal 211 to compensate for subsequent charge loss).

As described above, the disclosed memory array may be a one-time programmable memory (OPTM) in which the memory cells remain programmed once programmed. Alternatively, the disclosed memory array can be configured to support de-programming of memory cells to make it a multi-time programmable memory (MTPM) array. In this case, during the erase operation, the injected charges are removed from the first terminal 211 (see fig. 2A or 2B), particularly from the gate or gate oxide of the gate terminal to lower the threshold voltage of the CTFET in the memory cell 110, thereby de-programming (i.e., erasing) the memory cell 110. In this case, the memory word line voltage (V _ WL) generated by the memory word line voltage generator 170 is set (e.g., by applying an appropriate WL _ DAC signal) at some predetermined ERASE voltage level (V _ ERASE) that is substantially opposite to the write voltage level (i.e., a reverse field) to invert the charge in the first terminal 211. V _ ERASE is applied to the first terminal until comparator 130 confirms that the selected memory cell 110 has been unprogrammed. The reference word line voltage (V _ reffl) applied to the reference word line 184 during the erase operation and used to verify that the selected memory cell 110 has been programmed may be the same as that used during the read process. Alternatively, the reference word line voltage (V _ REFWL) may be offset to support unique margin testing. In this case, when it is confirmed during this erase operation whether the selected memory cell 110 has been unprogrammed, the reference wordline voltage (V _ REFWL) (e.g., by applying the appropriate REFWL _ DAC) is set at some predetermined third reference wordline voltage level (V _ REFERASE). The predetermined third reference wordline voltage level (V _ reference) is particularly greater than the predetermined first reference wordline voltage level (V _ refresh) so that the reference cell 120 (connected to the same comparator 130 as the selected memory cell 110 being programmed) conducts a higher reference current amount during the erase operation than it otherwise conducts during the read operation.

It is to be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods, and is not intended to be limiting. For example, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, terms such as "right," "left," "vertical," "horizontal," "top," "bottom," "above," "below," "upper," "lower," "parallel," "straight," and the like are intended to describe relative positions as they are oriented and shown in the drawings (unless otherwise indicated), and terms such as "contacting," "directly contacting," "abutting," "directly adjacent," "immediately adjacent," and the like are intended to mean that at least one element physically contacts another element (without the other elements separating the elements). The term "transverse" as used herein describes the relative position of elements as they are oriented and shown in the drawings, particularly meaning that one element is positioned on a side of another element and not above or below the other element. For example, one element will be laterally adjacent to another element to the side of the other element, one element will be laterally immediately adjacent to the other element to the side of the other element, and one element will be laterally around the other element to be adjacent to and surround the outer sidewall of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

The description of the various embodiments of the present invention is provided for purposes of illustration and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. For example, the invention disclosed herein includes a single-ended sensing reference and also provides single-ended signal tolerance techniques. The embodiments described and shown in the figures are configured with memory cells that are charge trapping NFET memory cells. The description and drawings are not intended to be limiting. It should be understood that the memory cell may alternatively be a charge trapping PFET memory cell. Also, it should be understood that the charge trapping NFET memory cell could alternatively be configured differently. In either case (i.e., in the case of charge trapping PFET memory cells or in the case of charge trapping NFET memory cells having different configurations), it is contemplated that the practice of applying NFET-PFET pairs to the disclosed circuits may be applied. In such applications, the NFET may be replaced with a PFET and vice versa, and the supply level may be replaced or altered. For example, the concept of the illustrative comparator 130 is readily implemented with PFET or NFET current mirrors and differential amplifier technology. In any event, the terminology used herein is selected to best explain the principles of the described embodiments, the practical application, or technical improvements over known technologies in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Thus, embodiments of a memory array having distributed charge trapping reference cells to support single-ended current sensing of charge trapping memory cells are disclosed above. This memory array may be a one-time programmable memory (OPTM) array or may include an optional erase function to make it a multiple-time programmable memory (MTPM) array. In any case, the memory array includes a memory cell, a reference cell, and a comparator. The memory cells are arranged in rows and columns, each column having a respective reference cell and a respective comparator. Each memory cell in a given row and a given column has a common memory word line with the given row, a common memory bit line with the given column, respectively, and a terminal connected to ground. Each reference cell of a given column has a common reference word line with all reference cells, respectively, a reference bit line with the reference cell, and a terminal connected to ground. Each comparator of a given column has a current mirror with a reference portion and a memory portion. The reference portion is connected to a reference bit line and thus to the reference cells of the given column, and the memory portion is connected to a common memory bit line and thus to the memory cells in the given column. In addition, each reference portion has a current mirror node, and all current mirror nodes of all comparators in the memory array are electrically connected. Each comparator circuit compares the current conducted by the reference cell with the current conducted by the selected memory cell during a read operation to determine the programmed state of the cell, during a write operation to verify programming, and optionally during an erase operation to verify erase. As described, the voltages applied to the memory word lines and the reference word line are selectively varied to support single-ended current sensing of the memory cells, programming of the memory cells using a margin test technique that limits rewriting, and optional de-programming (i.e., erasing) of the memory cells. As described above, by electrically connecting the current mirror nodes in the reference portion of all comparators on the memory array, the disclosed configuration balances process variations across the reference cell and other devices within the reference portion of the current mirror, thus reducing the effects of mismatch and increasing sensing accuracy.