阅读说明：本技术 一种ped样品及其制备方法 (PED sample and preparation method thereof ) 是由 邹锭 于 2019-10-28 设计创作，主要内容包括：本发明提供了一种PED样品及其制备方法,包括：提供待切割器件；对所述待切割器件进行切割形成待制备样品,所述待制备样品包括衬底、设置在所述衬底上的多个间隔排列的待量测结构和位于所述待测量结构之间的干扰结构；向所述待量测结构之间的区域通入离子刻蚀加强气体,利用所述离子刻蚀加强气体去除所述待量测结构之间的干扰结构,从而可以排除干扰结构对待量测结构量测准确度的影响,进而可以提高待量测结构如沟道孔内多晶硅层晶粒尺寸的量测准确度。(The invention provides a PED sample and a preparation method thereof, wherein the preparation method comprises the following steps: providing a device to be cut; cutting the device to be cut to form a sample to be prepared, wherein the sample to be prepared comprises a substrate, a plurality of structures to be measured arranged at intervals on the substrate and interference structures positioned among the structures to be measured; and introducing ion etching strengthening gas into the area between the structures to be measured, and removing the interference structures between the structures to be measured by using the ion etching strengthening gas, so that the influence of the interference structures on the measurement accuracy of the structures to be measured can be eliminated, and the measurement accuracy of the structures to be measured, such as the grain size of the polycrystalline silicon layer in the trench hole, can be improved.)

1. A method of preparing a PED sample, comprising:

providing a device to be cut;

cutting the device to be cut to form a sample to be prepared, wherein the sample to be prepared comprises a substrate, a plurality of structures to be measured arranged at intervals on the substrate and interference structures positioned among the structures to be measured;

and introducing ion etching strengthening gas into the area between the structures to be measured, and removing the interference structures between the structures to be measured by using the ion etching strengthening gas.

2. The method of claim 1, wherein introducing an ion etch enhancing gas into the region between the structures to be measured comprises:

inserting a gas needle into the area between the structures to be measured;

and introducing ion etching reinforcing gas to the region between the structures to be measured through the gas needle.

3. The method of claim 1 or 2, wherein the ion etch enhancing gas is XeF₂。

4. The method of claim 1, wherein the device to be cut is a three-dimensional memory, the structure to be measured is a trench hole exposing an inner polysilicon layer, the interference structure is a gate electrode, and a material of the gate electrode is tungsten.

5. The method of claim 4, wherein prior to flowing an ion etch enhancing gas into the region between the structures to be measured, further comprising:

and depositing a protective layer on at least one side surface of the sample to be prepared, wherein the at least one side surface comprises a side surface exposing the polycrystalline silicon layer in the channel hole.

6. The method of claim 5, wherein depositing a protective layer on at least one side of the sample to be prepared comprises:

and depositing a protective layer on at least one side surface of the sample to be prepared by adopting an electron beam deposition process.

7. A PED sample prepared by the method of any one of claims 1 to 6, comprising a substrate and a plurality of structures to be measured arranged on the substrate at intervals, wherein the structures to be measured do not have interference structures therebetween, and the interference structures are removed by introducing an ion etching enhancing gas into the region between the structures to be measured.

8. The PED sample of claim 7, wherein the structure to be measured is a trench hole exposing an inner polysilicon layer, the interference structure is a gate electrode, and the gate electrode is made of tungsten.

9. The PED sample of claim 8, further comprising: a protective layer on at least one side of the PED sample, the at least one side including a side surface that exposes the polysilicon layer inside the channel hole.

10. The PED sample of claim 9, wherein the protective layer is a silicon oxide layer.

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a PED sample and a preparation method thereof.

Background

In a manufacturing process of a three-dimensional memory (3D NAND), in order to measure a grain size of a polycrystalline silicon layer in a channel hole using a Transmission Electron Microscope (TEM), it is necessary to prepare a relatively special PED (process Electron Diffraction) sample for the TEM.

In order to measure the grain size of the polysilicon layer in the trench hole for PED samples, a sample cutting method as shown in fig. 1 is generally adopted, i.e. half of the trench hole 10 is cut along cutting lines AA 'and BB', so that a larger area can be obtained, and the overlapping of the polysilicon layers 101 on the front and rear layers can be avoided. However, the grain size of the polysilicon layer measured using such PED samples is not highly accurate.

Disclosure of Invention

In view of the above, the present invention provides a PED sample and a method for preparing the same, so as to improve the accuracy of measuring the grain size of the polysilicon layer in the trench hole.

In order to achieve the purpose, the invention provides the following technical scheme:

a method of preparing a PED sample, comprising:

providing a device to be cut;

cutting the device to be cut to form a sample to be prepared, wherein the sample to be prepared comprises a substrate, a plurality of structures to be measured arranged at intervals on the substrate and interference structures positioned among the structures to be measured;

and introducing ion etching strengthening gas into the area between the structures to be measured, and removing the interference structures between the structures to be measured by using the ion etching strengthening gas.

Optionally, the step of introducing an ion etching enhancing gas into the region between the structures to be measured comprises:

inserting a gas needle into the area between the structures to be measured;

and introducing ion etching reinforcing gas to the region between the structures to be measured through the gas needle.

Optionally, the ion etching enhancing gas is XeF₂。

Optionally, the device to be cut is a three-dimensional memory, the structure to be measured is a trench hole exposing the internal polysilicon layer, the interference structure is a gate electrode, and the gate electrode is made of tungsten.

Optionally, before introducing the ion etching enhancing gas into the region between the structures to be measured, the method further includes:

and depositing a protective layer on at least one side surface of the sample to be prepared, wherein the at least one side surface comprises a side surface exposing the polycrystalline silicon layer in the channel hole.

Optionally, depositing a protective layer on at least one side of the sample to be prepared comprises:

and depositing a protective layer on at least one side surface of the sample to be prepared by adopting an electron beam deposition process.

A PED sample prepared by the method comprises a substrate and a plurality of structures to be measured arranged on the substrate at intervals, wherein interference structures are not arranged between the structures to be measured, and the interference structures are removed by introducing ion etching strengthening gas into the area between the structures to be measured.

Optionally, the structure to be measured is a trench hole exposing the inner polysilicon layer, the interference structure is a gate electrode, and the gate electrode is made of tungsten.

Optionally, the method further comprises: a protective layer on at least one side of the PED sample, the at least one side including a side surface that exposes the polysilicon layer inside the channel hole.

Optionally, the protective layer is a silicon oxide layer.

Compared with the prior art, the technical scheme provided by the invention has the following advantages:

according to the PED sample and the preparation method thereof provided by the invention, the ion etching strengthening gas is introduced into the area between the structures to be measured, and the ion etching strengthening gas is used for removing the interference structures between the structures to be measured, so that the influence of the interference structures on the measurement accuracy of the structures to be measured can be eliminated, and the measurement accuracy of the structures to be measured, such as the polycrystalline silicon layer grain size in the trench hole, can be improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a cutting structure of a three-dimensional memory channel hole;

fig. 2 is a flow chart of a method for preparing a PED sample according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a sample to be prepared according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a PED sample according to an embodiment of the present invention.

Detailed Description

As described in the background, the grain size of the polysilicon layer measured using the PED sample shown in fig. 1 is not highly accurate. The inventors have found that the reason for this problem is mainly that the channel hole 10 surrounds the gate electrode 11, the gate electrode 11 is made of metal tungsten, and the electron microscope cannot completely distinguish between the tungsten grains of the gate electrode 11 and the grains of the polysilicon layer 101, which results in a low accuracy of grain size measurement of the polysilicon layer 101.

Accordingly, the present invention provides a method for preparing PED samples, which overcomes the above problems of the prior art, and comprises:

providing a device to be cut;

cutting the device to be cut to form a sample to be prepared, wherein the sample to be prepared comprises a substrate, a plurality of structures to be measured arranged at intervals on the substrate and interference structures positioned among the structures to be measured;

and introducing ion etching strengthening gas into the area between the structures to be measured, and removing the interference structures between the structures to be measured by using the ion etching strengthening gas.

According to the preparation method of the PED sample, provided by the invention, the ion etching strengthening gas is introduced into the area between the structures to be measured, and the interference structures between the structures to be measured are removed by using the ion etching strengthening gas, so that the influence of the interference structures on the measurement accuracy of the structures to be measured can be eliminated, and the measurement accuracy of the structures to be measured, such as the grain size of the polycrystalline silicon layer in the trench hole, can be further improved.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the above is the core idea of the present invention, and the above objects, features and advantages of the present invention can be more clearly understood. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a method for preparing a PED sample, as shown in fig. 2, including:

s101: providing a device to be cut;

in the embodiment of the present invention, the device to be cut is exemplified as a three-dimensional memory, however, the present invention is not limited thereto, and in other embodiments, the device to be cut may be any device that needs to perform TEM detection.

S102: cutting a device to be cut to form a sample to be prepared, wherein the sample to be prepared comprises a substrate, a plurality of structures to be measured arranged at intervals on the substrate and interference structures positioned between the structures to be measured;

in the embodiment of the present invention, a FIB (Focused Ion beam) is used to cut a to-be-cut device to form a to-be-prepared sample. When the grain size of the polysilicon layer in the channel hole in the three-dimensional memory is measured, as shown in fig. 1, the three-dimensional memory is cut along cutting lines AA 'and BB', and the cut sample to be prepared has a half channel hole 10.

As shown in fig. 3, the cut sample to be prepared includes a substrate 2, a plurality of structures to be measured 20 arranged at intervals on the substrate 1, and an interference structure 21 located between the structures to be measured 20. Alternatively, the substrate 2 is a semiconductor substrate such as a silicon substrate, a germanium substrate, or the like; the structure 20 to be measured is a channel hole exposing the inner polysilicon layer 201; the interference structure 21 is a gate electrode made of metal tungsten.

Of course, as shown in fig. 3, there are interlayer insulating layers 22 between the structures to be measured 20, the interlayer insulating layers 22 and the interference structures 21 are alternately disposed, and the structures to be measured 20 penetrate through the alternately disposed interlayer insulating layers 22 and the interference structures 21 in a direction perpendicular to the substrate 2. Alternatively, the interlayer insulating layer 22 is silicon oxide.

S103: and introducing ion etching strengthening gas into the area between the structures to be measured, and removing the interference structures between the structures to be measured by using the ion etching strengthening gas.

Wherein the step of introducing an ion-etching enhancing gas into the region between the structures 20 to be measured comprises:

inserting gas needles into the area between the structures 20 to be measured;

an ion etch enhancing gas is introduced through the gas needles into the region between the structures 20 to be measured.

Optionally, the ion etch enhancing gas is XeF₂. Alternatively, a gas needle may be inserted into the region between the structures 20 to be measured from the upper right side of the sample as shown in FIG. 3.

XeF gas enhancement due to ion etching₂The etching efficiency for metal is higher than that for silicon, so as shown in FIG. 4, an ion etching enhancing gas XeF is introduced into the region between the structures 20 to be measured₂Thereafter, an ion etching enhancing gas XeF₂The gate electrode, i.e., the interference structure 21, can be etched away, and the structure 20 to be measured and the interlayer insulating layer 22 are remained, so that the influence of the interference structure 21 on the measurement accuracy of the structure 20 to be measured can be eliminated during measurement, and the measurement accuracy of the grain size of the structure 20 to be measured, e.g., the polysilicon layer 201 in the trench, can be improved.

Although it is also possible to eliminate the influence of the gate electrode, i.e. the interference structure 21, on the measurement accuracy of the structure 20 to be measured by re-fabricating the three-dimensional memory without gate electrode, the cycle time is too long and the cost is too high. Compared with the method, the method for preparing the PED sample provided by the embodiment of the invention can not only completely eliminate the influence of the interference structure 21 on the measurement accuracy of the structure 20 to be measured, but also has short period and low cost.

In another embodiment of the present invention, before introducing the ion etching enhancing gas into the region between the structures 20 to be measured, the method further comprises:

a protective layer is deposited on at least one side surface of the sample to be prepared, the at least one side surface including the one side surface S1 exposing the polycrystalline silicon layer 201 inside the channel hole, although the present invention is not limited thereto, and in other embodiments, a protective layer may be deposited on the surfaces of the bottom surface S2 of the substrate and the top surface S3 of the channel hole, as shown in fig. 3.

Optionally, depositing a protective layer on at least one side of the sample to be prepared comprises:

and depositing a protective layer on at least one side surface of the sample to be prepared by adopting an electron beam deposition process.

Optionally, the protective layer is a silicon oxide layer, and of course, the material of the protective layer may also be carbon or tetraethoxysilane, and the invention is not limited thereto. The protective layer is a silicon oxide layer which does not influence the measurement of the grain size of the polycrystalline silicon layer, so that the protective layer on the surface of the sample can be reserved during measurement. Of course, the invention is not limited to this, and in other embodiments, the protective layer on the sample surface may be etched away before the measurement.

It should be noted that after the interference structure 21 is removed, another film layer, such as a silicon oxide layer, may also be grown at the position of the interference structure 21, that is, in the embodiment of the present invention, another structure may also be used to replace the interference structure 21, so as to eliminate the influence of the interference structure 21.

An embodiment of the present invention further provides a PED sample prepared by the method provided in any of the above embodiments, as shown in fig. 4, including a substrate 2 and a plurality of structures to be measured 20 arranged on the substrate 2 at intervals, where the structures to be measured 20 do not have interference structures 21 therebetween. Wherein the perturbation structures 21 are etched away by introducing an ion-etching enhancing gas into the region between the structures 20 to be measured. Optionally, the ion etch enhancing gas is XeF₂。

Alternatively, the structure 20 to be measured is a channel hole exposing the inner polysilicon layer 201, the interference structure 21 is a gate electrode, and the material of the gate electrode is tungsten. However, since the interlayer insulating layer 22 is a silicon oxide layer, it does not affect the measurement of the grain size of the polysilicon layer 201 in the trench hole of the structure 20 to be measured, and therefore, the interlayer insulating layer 22 between the structures 20 to be measured is remained in the embodiment of the present invention.

In one embodiment of the invention, the PED sample further comprises: a protective layer on at least one side of the PED sample, the at least one side including a side surface S1 exposing the polysilicon layer inside the channel hole, although the invention is not limited thereto, and in other embodiments, the protective layer may be formed on the bottom surface S2 of the substrate and the top surface S3 of the channel hole, as shown in fig. 3.

Optionally, the protective layer is a silicon oxide layer, and of course, the material of the protective layer may also be carbon or tetraethoxysilane, and the invention is not limited thereto. Because the silicon oxide layer does not affect the measurement of the grain size of the polysilicon layer, the protective layer on the sample surface can be retained during measurement, thereby simplifying the process steps.

According to the PED sample and the preparation method thereof provided by the invention, the ion etching strengthening gas is introduced into the area between the structures to be measured, and the ion etching strengthening gas is used for removing the interference structures between the structures to be measured, so that the influence of the interference structures on the measurement accuracy of the structures to be measured can be eliminated, and the measurement accuracy of the structures to be measured, such as the polycrystalline silicon layer grain size in the trench hole, can be improved.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.