阅读说明：本技术 用于闪存存储器系统的改进的感测放大器 (Improved sense amplifier for flash memory system ) 是由 钱晓州 X.Y.皮 K.M.岳 L.F.卞 于 2018-06-15 设计创作，主要内容包括：用于闪存存储器系统的改进的感测放大器。本发明公开了在闪存存储器系统中使用的改进的低功率感测放大器。基准位线和选择的位线在有限周期期间被预充电并且消耗的功率有限。预充电电路可在配置过程期间进行修调,以进一步优化预充电操作期间的功率消耗。(An improved sense amplifier for a flash memory system. The invention discloses an improved low power sense amplifier for use in a flash memory system. The reference bit line and the selected bit line are precharged during a limited period and consume limited power. The precharge circuit may be trimmed during the configuration process to further optimize power consumption during the precharge operation.)

1. A flash memory system, comprising:

a read circuit comprising a selected flash memory cell, a first bit line coupled to the selected flash memory cell, a first capacitor, and a first switch, wherein at the beginning of a sensing operation, the first switch is closed and the first capacitor charges the first bit line, and the first bit line is discharged through the selected flash memory cell:

a reference circuit comprising a reference flash memory cell, a second bit line coupled to the reference flash memory cell, a second capacitor, and a second switch, wherein at the beginning of a sensing operation, the second switch is closed and the second capacitor charges the second bit line, and the second bit line is discharged through the reference flash memory cell; and

a timing comparison circuit to output a first value when the voltage of the first bit line drops below a voltage threshold before the voltage of the second bit line during a read operation and to output a second value when the voltage of the second bit line drops below a voltage threshold before the voltage of the first bit line during a read operation, wherein the first and second values are each indicative of a value stored in the selected flash memory cell.

2. The flash memory system of claim 1, wherein the first capacitor is a variable capacitor and the second capacitor is a variable capacitor.

3. The flash memory system of claim 1, wherein the timing comparison circuit comprises a flip-flop.

4. The flash memory system of claim 2, wherein the timing comparison circuit comprises a flip-flop.

5. The flash memory system of claim 1, wherein the timing comparison circuit comprises an R-S latch.

6. The flash memory system of claim 2, wherein the timing comparison circuit comprises an R-S latch.

7. A flash memory system, comprising:

a read circuit comprising a selected flash memory cell, a first bit line coupled to the selected flash memory cell, a first capacitor, and a first switch, wherein at the beginning of a sensing operation, the first switch is closed and the first capacitor charges the first bit line, and the first bit line is discharged through the selected flash memory cell;

a reference circuit comprising a reference flash memory cell, a second bit line coupled to the reference flash memory cell, a second capacitor, and a second switch, wherein at the beginning of a sensing operation, the second switch is closed and the second capacitor charges the second bit line, and the second bit line is discharged through the reference flash memory cell;

a timing comparison circuit for outputting a first value when the voltage of the first bit line drops below a voltage threshold before the voltage of the second bit line during a read operation and outputting a second value when the voltage of the second bit line drops below a voltage threshold before the voltage of the first bit line during a read operation, wherein the first and second values each indicate a value stored in a selected flash memory cell; and

a trimming controller to adjust a capacitance of the first variable capacitor and a capacitance of the second variable capacitor during a calibration process.

8. The flash memory system of claim 7, wherein the trimming controller is configured to adjust voltage sources of the reference circuit and the read circuit during the calibration process.

9. The flash memory system of claim 7, wherein the timing comparison circuit comprises a flip-flop.

10. The flash memory system of claim 8, wherein the timing comparison circuit comprises a flip-flop.

11. The flash memory system of claim 7, wherein the timing comparison circuit comprises an R-S latch.

12. The flash memory system of claim 8, wherein the timing comparison circuit comprises an R-S latch.

Technical Field

The invention discloses an improved low power sense amplifier for use in a flash memory system.

Background

Flash memory systems are well known. In a typical flash memory system, data is read from flash memory cells using sense amplifiers.

Fig. 1 shows a prior art sense amplifier 100. The sense amplifier 100 includes a selected flash memory cell 102, which is the cell to be read. The sense amplifier 100 also includes a reference flash memory cell 122 to which the selected flash memory cell 102 is compared. The arrangement of the PMOS transistors 104, 106, 124, and 126 and the NMOS transistors 108, 110, 112, 128, and 130 is shown. PMOS transistor 104 is controlled by CASREF (column address sense reference), PMOS 106 is controlled by SEN _ B (sense amplifier enabled, active low), NMOS transistors 108, 112, and 128 are controlled by ATD (address transition detection, which detects a change in received address), and NMOS transistors 110 and 130 are controlled by YMUX (Y multiplexer) which activates BL (bit line). The selected flash memory cell 102 receives a WL (word line) and a SL (source line), and the reference memory cell 122 receives a SL (source line). The comparator 130 receives two inputs that are directly related to the current consumed by the selected flash memory cell 102 and the reference memory cell 122, and outputs SOUT directly indicative of the data value stored in the selected flash memory cell 102.

Disclosure of Invention

The invention discloses an improved low power sense amplifier for use in a flash memory system. The reference bit line and the selected bit line are precharged during a limited period and consume limited power. The precharge circuit may be trimmed during the configuration process to further optimize power consumption during the precharge operation.

Drawings

FIG. 1 illustrates a prior art sense amplifier in a flash memory system.

FIG. 2 illustrates an embodiment of a low power sense amplifier for a flash memory system previously disclosed by applicants.

FIG. 3A illustrates an embodiment of a timing circuit for use with a sense amplifier.

FIG. 3B illustrates another embodiment of a timing circuit for use with a sense amplifier.

FIG. 4 illustrates another embodiment of a low power sense amplifier for a flash memory system.

Fig. 5 illustrates a trimming operation of the sense amplifier of fig. 4.

Detailed Description

Fig. 4 illustrates a sense amplifier 400. Sense amplifier 400 includes a reference circuit 410 and a read circuit 430.

The reference circuit 410 includes a reference memory cell 411, NMOS transistors 412, 416, and 419. PMOS transistor 418, switch 414, node 415, reference bit line 417, inverter 420, and variable capacitor 413, all configured as shown. NMOS transistor 412 is controlled by VB, NMOS transistor 416 is controlled by YMUX (a part of the column decoder for selecting the column containing reference memory cell 411), NMOS transistor 419 is controlled by BIAS, switch 414 is controlled by ATD (address transition detection), and PMOS transistor 418 is controlled by node 415.

The read circuit 430 includes a selected memory cell 431, and NMOS transistors 432, 436, and 439. PMOS transistor 438, switch 434, node 435, selected bit line 437, inverter 440, and variable capacitor 433, all configured as shown. NMOS transistor 432 is controlled by VB, NMOS transistor 436 is controlled by YMUX (a part of the column decoder for selecting the column containing the selected memory cell 431), NMOS transistor 439 is controlled by BIAS, switch 434 is controlled by ATD (address transition detection), and PMOS transistor 438 is controlled by node 435.

In operation, the sense amplifier 400 operates as follows. Prior to a read operation, the BIAS signal is high, which turns on NMOS transistors 419 and 439 and pulls the inputs of inverters 420 and 440 to ground potential, which places ROUT and SOUT in a high state. At the beginning of a read operation, the ATD rises, indicating that a change in the address received by the memory system is being detected, which occurs simultaneously with the beginning of the read operation. When the ATD rises, switches 414 and 434 are closed. NMOS transistors 416 and 436 are turned on by YMUX. This allows the reference cell 411 and the selected memory cell 431 to consume current. Initially, variable capacitors 413 and 433 will store the voltage generated by voltage NMOS transistors 412 and 432 during the charging process before switches 414 and 434 are closed. After switches 414 and 434 are closed, the charge on capacitors 413 and 433 is distributed to nodes 415 and 435, respectively, for a short period of time. At the same time, the reference cell 411 will consume current from the variable capacitor 413, and the selected cell 431 will consume current from the variable capacitor 433.

The ATD will then go low, which will open switches 414 and 434. The node 415 and the reference bit line 417 will continue to discharge through the reference cell 411. Thus, the voltage at node 415 will drop, and at some point the voltage will drop low enough (below VDDS — Vthp, where VDDS is the voltage source provided to PMOS transistors 418 and 438 and Vthp is the threshold voltage of PMOS transistors 418 and 438) to cause PMOS transistor 418 to turn on. This causes ROUT to drop to a low state. At the same time, node 435 and selected bit line 437 are also discharged through selected memory cell 431. Thus, the voltage at node 435 will drop (below VDDS-Vthp), and at some point the voltage will drop low enough to turn on PMOS transistor 438. This causes ROUT to drop to a low state.

Essentially, a race condition exists between reference circuit 410 and read circuit 430. If the selected memory cell 431 is consuming more current than the reference cell 411 (as would be the case if the selected memory cell 431 is storing a "1" value), SOUT will fall to a low state before ROUT falls to a low state. But if the selected memory cell 431 is consuming less current than the reference cell 411 (as would be the case if the selected memory cell 431 is storing a "0" value), SOUT will fall to a low state after ROUT falls to a low state. Thus, the relative timing of the SOUT and ROUT falling to a low state indicates the value stored in the selected memory cell 431.

SOUT and ROUT are input into the timing comparison circuit 260 and output as DOUT, which indicates the value stored in the selected memory cell 236. Timing comparison circuit 260 may include the structure previously described with respect to fig. 3A or 3B, or may include another timing circuit.

Fig. 5 shows the configuration stages of reference circuit 410 and read circuit 430. The trimming controller 510 optionally may adjust the voltage VDDS using known techniques. Similarly, when the ATD rises and switches 414 and 434 are closed, trimming controller 510 may adjust the capacitance of variable capacitors 413 and 433 to change the voltage initially provided to nodes 415 and 435.

Reference herein to the invention is not intended to limit the scope of any claim or claim term, but rather only to one or more features that may be encompassed by one or more claims. The above-described examples of materials, processes, and values are illustrative only and should not be construed as limiting the claims. It should be noted that, as used herein, the terms "above" and "on" each include, by way of example, both "directly on" (with no intervening material, element, or space disposed therebetween) and "indirectly on" (with intervening material, element, or space disposed therebetween). Likewise, the term "adjacent" includes "directly adjacent" (no intermediate material, element, or space disposed therebetween) and "indirectly adjacent" (intermediate material, element, or space disposed therebetween). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intervening materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials/elements therebetween.