阅读说明：本技术 闪存及通过电压的控制方法 (Flash memory and pass voltage control method ) 是由 陈哲平 李亚睿 沈欣彰 杨宜山 于 2020-05-08 设计创作，主要内容包括：本发明公开了一种闪存及通过电压的控制方法。闪存包括多个存储单元串以及通过电压产生器。各存储单元串具有多个存储单元。通过电压产生器用以提供通过电压至选中存储单元串的多个未选中存储单元的多条字线。其中,在读取操作时,通过电压产生器使通过电压在第一时间点由第一电压上升,并在第二时间点上升至第二电压。其中上述的第二电压小于目标电压乘以预设比例。第一时间点早于选中存储单元串接收的位线电压的启动时间点,第二时间点发生在位线电压的启动时间点。(The invention discloses a flash memory and a control method of pass voltage. The flash memory includes a plurality of memory cell strings and a pass voltage generator. Each memory cell string has a plurality of memory cells. The pass voltage generator is used to provide pass voltages to a plurality of word lines of a plurality of unselected memory cells of a selected memory cell string. In the read operation, the pass voltage is raised by the voltage generator from a first voltage at a first time point and is raised to a second voltage at a second time point. Wherein the second voltage is smaller than the target voltage multiplied by a preset ratio. The first time point is earlier than the start time point of the bit line voltage received by the selected memory cell string, and the second time point occurs at the start time point of the bit line voltage.)

1. A flash memory, comprising:

a plurality of memory cell strings each having a plurality of memory cells; and

a pass voltage generator coupled to the memory cell strings for providing a pass voltage to word lines of unselected memory cells of a selected memory cell string,

wherein, during a read operation, the pass voltage generator makes the pass voltage rise from a first voltage at a first time point and rise to a second voltage at a second time point,

the second voltage is smaller than a target voltage multiplied by a preset proportion, the first time point is earlier than the starting time point of the voltage of the bit line received by the selected memory cell string, and the second time point occurs at the starting time point of the voltage of the bit line.

2. The flash memory of claim 1, wherein the predetermined ratio is 90%.

3. The flash memory of claim 1, wherein the first time occurs at a start time of a word line voltage received by a selected memory cell, or the first time is later than the start time of the word line voltage and earlier than the start time of the bit line voltage.

4. The flash memory of claim 1, wherein the pass voltage generator pulls up the pass voltage to the target voltage during a sensing time interval after the second time point.

5. The flash memory of claim 1, wherein the pass voltage generator pulls up the pass voltage to a third voltage at a third time point between the first time point and the second time point during the read operation,

the pass voltage generator provides a first driving capability between the first time point and the third time point, and provides a second driving capability between the third time point and the second time point, wherein the first driving capability is different from the second driving capability.

6. The flash memory of claim 1, wherein the pass voltage generator comprises:

the booster circuit receives a frequency signal and executes a pumping action aiming at a reference voltage according to the frequency signal to generate a control voltage;

a target voltage generator for generating the target voltage; and

a switch having a first end receiving the target voltage, the switch controlled by the control voltage to provide an equivalent resistance, and a second end providing the pass voltage.

7. The flash memory of claim 6, wherein the pass voltage generator further comprises:

a frequency generator for generating a reference frequency signal; and

a frequency adjuster, which adjusts the frequency of the reference frequency signal according to an adjustment signal to generate the frequency signal.

8. The flash memory of claim 6, wherein the target voltage generator is a digital-to-analog converter, receives a digital target voltage code, and converts the target voltage code to generate the target voltage.

9. The flash memory of claim 1, wherein the pass voltage generator sequentially provides a plurality of output voltages that are incremented at a plurality of sub-time points between the first time point and the second time point to generate the pass voltage.

10. The flash memory of claim 9, wherein the pass voltage generator comprises:

a candidate voltage generator for generating a plurality of output voltages; and

and a voltage selector for sequentially selecting each output voltage as the pass voltage corresponding to each sub-time point.

11. The flash memory of claim 9, wherein the pass voltage generator comprises:

and the digital-to-analog converter is used for sequentially receiving a plurality of voltage control codes corresponding to the sub-time points, and sequentially converting the voltage control codes to generate each output voltage.

12. The flash memory of claim 11, wherein the pass voltage generator further comprises:

a control code generator coupled to the DAC for generating the output voltage control codes.

13. A method of controlling a pass voltage, comprising:

providing a pass voltage generator to provide a pass voltage to word lines of unselected memory cells of a selected memory cell string;

in a read operation, the pass voltage generator is provided to make the pass voltage rise from a first voltage at a first time point and rise to a second voltage at a second time point,

the second voltage is smaller than a target voltage multiplied by a preset proportion, the first time point is earlier than the starting time point of the voltage of the bit line received by the selected memory cell string, and the second time point occurs at the starting time point of the voltage of the bit line.

14. The pass voltage control method of claim 13, wherein the predetermined ratio is 90%.

15. The pass voltage control method of claim 13, further comprising:

the first time point is made to occur at the starting time point of a word line voltage received by a selected memory cell, or the first time point is made to be earlier than the starting time point of the word line voltage and later than the starting time point of the bit line voltage.

16. The pass voltage control method of claim 13, further comprising:

enabling the pass voltage generator to provide a first driving capability, and pulling up the pass voltage to a third voltage at a third time point between the first time point and the second time point; and

the pass voltage generator provides a second driving capability to pull up the pass voltage to a second voltage between the third time point and the second time point.

17. The pass voltage control method of claim 13, wherein providing the pass voltage generator such that the pass voltage is raised from the first voltage at the first time point and raised to the second voltage at the second time point comprises:

generating a control voltage by performing a pumping action aiming at a reference voltage according to a frequency signal; and

and enabling a switch to provide an equivalent resistance according to the control voltage, and enabling a target voltage to pass through the equivalent resistance of the switch to generate the passing voltage.

18. The method of claim 17, further comprising:

the frequency signal is generated by adjusting the frequency of a reference frequency signal according to an adjusting signal.

19. The pass voltage control method of claim 13, wherein providing the pass voltage generator such that the pass voltage is raised from the first voltage at the first time point and raised to the second voltage at the second time point comprises:

sequentially providing a plurality of output voltages which are increased progressively to generate the supply voltage at a plurality of sub-time points between the first time point and the second time point.

Technical Field

The present invention relates to a flash memory and an operating method thereof, and more particularly, to a NAND gate (NAND) flash memory and a pass voltage control method thereof.

Background

In modern electronic devices, flash memory is used in large quantities as a storage device for data. With the progress of integrated circuit technology, the density of memory has been greatly increased to increase the data storage capacity. In order to reduce the product price, as the bit density increases, and as the number of memory cells increases, the number of reads also increases.

In any case, read disturb may occur when a high number of read operations are performed for a page of flash memory. Multiple read operations may cause a read failure when the digital value of a particular bit changes from 1 to 0. Such a read disturb phenomenon is a factor affecting the reliability of the flash memory.

Disclosure of Invention

The invention provides a flash memory and an operation method thereof, which effectively reduce the probability of read interference.

The flash memory of the present invention includes a plurality of memory cell strings and a pass voltage generator. Each memory cell string has a plurality of memory cells. The pass voltage generator is coupled to the memory cell strings for providing pass voltages to word lines of unselected memory cells of a selected memory cell string. In the read operation, the pass voltage is raised by the voltage generator from a first voltage at a first time point and is raised to a second voltage at a second time point. The second voltage is smaller than the target voltage multiplied by a preset proportion, the first time point is earlier than the starting time point of the bit line voltage received by the selected memory cell string, and the second time point occurs at the starting time point of the bit line voltage.

The operation method of the flash memory of the invention comprises the following steps: providing a pass voltage to a plurality of word lines of a plurality of unselected memory cells of the selected memory cell string; in a read operation, a pass voltage is raised from a first voltage at a first time point and raised to a second voltage at a second time point, wherein the second voltage is smaller than a target voltage multiplied by a preset proportion, the first time point is earlier than a starting time point of a bit line voltage received by a selected memory cell string, and the second time point occurs at the starting time point of the bit line voltage.

Based on the above, in the present invention, when the memory cell is read, the pass voltage is gradually increased to the second voltage smaller than the target voltage multiplied by the predetermined ratio before the start time point of the bit line voltage, so that the disturbance phenomenon of the bit line caused by the pass voltage increase operation can be effectively reduced, and the probability of the occurrence of the read disturb can be reduced.

Drawings

Fig. 1 is a schematic diagram of a flash memory according to an embodiment of the invention.

FIG. 2 is a voltage waveform diagram of a flash memory according to an embodiment of the present invention.

FIG. 3 is a diagram showing a selected memory cell string versus voltage waveform according to an embodiment of the present invention.

FIG. 4 is a waveform diagram of pass voltages according to another embodiment of the present invention.

Fig. 5A and 5B are schematic diagrams respectively illustrating different embodiments of a pass voltage generator according to an embodiment of the invention.

FIG. 6 is a schematic diagram of another embodiment of a pass voltage generator according to the present invention.

FIG. 7 is a schematic diagram of another embodiment of a pass voltage generator according to the present invention.

FIG. 8 is a flow chart showing a method for operating a flash memory according to an embodiment of the present invention.

[ notation ] to show

100 flash memory

110: pass voltage generator

510. 520, 600, 700: pass voltage generator

511. 521: target voltage generator

512. 522: voltage booster circuit

513. 523: switch with a switch body

524: frequency generator

525: frequency regulator

610: digital-to-analog converter

711: candidate voltage generator

712: voltage selector

CLK: frequency signal

CLK 0: reference frequency signal

CS: adjusting signals

DAC [ N: 0]: target voltage code

dL 1: delay time

En: enable signal

MC₁～MC_m: memory cell

MS 1: memory cell string

RA 1: a predetermined proportion

S810 and S820: control step by voltage

SR 1-SR 4: pull up curve

SSL, GSL: selection signal

SV 1-SVN: candidate voltage

SW1, SW 2: switch with a switch body

TP1, TP 1', TP2, TP 3: point in time

TSEN: sensing time intervals

V1, V2, V3: voltage of

VBL: bit line voltage

VPASSR: passing voltage

VSR: control voltage

VTG: target voltage

WLn: word line voltage

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a flash memory according to an embodiment of the invention. The flash memory 100 includes a pass voltage generator 110 and a plurality of cell strings MS1 as shown in fig. 1. To simplify the complexity of the illustration, fig. 1 depicts only a single string of memory cells MS 1. The pass voltage generator 110 is used to generate a pass voltage VPASSR. And provides a pass voltage VPASSR to a plurality of unselected memory cells (memory cells MC) of a selected memory cell string (memory cell string MS1 for example) in a read operation of the pass voltage generator 110₁～MC_n-1And MC_m) A plurality of word lines. Selected memory cell MC_nThe word line receives a word line voltage WL corresponding to the read operation_n. In addition, the memory cell string MS1 includes switches SW1 and SW2 coupled to the selection signals SSL and GSL, respectively.

Fig. 1 and fig. 2 are synchronously referred to, wherein fig. 2 is a voltage waveform diagram of a flash memory according to an embodiment of the present invention. In a read operation, the pass voltage generator 110 causes the generated pass voltage VPASSR to rise from the first voltage V1 at a first time point TP1 and pulls the pass voltage VPASSR to the second voltage V2 at a second time point TP 2. Wherein the second voltage V2 is less than the target voltage VTG multiplied by a preset ratio RA 1.

In this embodiment, the first time point TP1 and the selected memory cell MC are_nThe received word line voltage WL_nIs the same. The second time point TP2 is the same as the starting time point of the bit line voltage VBL received by the bit line corresponding to the selected memory cell string MS 1. That is, the word line voltage WL_nThe bit line voltage VBL starts to be pulled up at a first time point TP1, and the bit line voltage VBL starts to be pulled up at a second time point TP2 after the first time point TP 1.

Incidentally, the word line voltage WL is activated at the first time point TP1_nPull-up of (1) to make selected memory cell MC_nThe word line performs a precharge operation. After a second time point TP2 when bit line voltage VBL is enabled, memory cell MC is selected_nIs sensed for a sensible time interval TSEN of data. During the sensing time interval TSEN, the pass voltage generator 110 may pull up the pass voltage VPASSR to the target voltage VTG.

The predetermined ratio RA1 may be determined by a designer according to the actual design condition of the flash memory, and in the embodiment of the invention, the predetermined ratio RA1 may be 90%.

The flash memory 100 in the embodiment of the present invention may be a NAND gate (NAND) flash memory. In the hardware architecture, the flash memory 100 may be a two-dimensional structure or a three-dimensional structure. In addition, the flash memory 100 may provide Single-level cells (SLC), multi-level cells (MLC), Triple-level cells (TLC), Quad-level cells (QLC), or a combination thereof.

FIG. 3 is a graph showing a comparison of a selected memory cell string and a voltage waveform (pass voltage VPASS) according to the prior art and the present invention. In the prior art, the pass voltage VPASS (shown as a dotted line portion of the pass voltage VPASS waveform in the drawing) has a high rising speed, and the pass voltage VPASS is pulled up to the target voltage VTG before the sensing time interval TSEN. The pass voltage generator according to the embodiment of the invention can effectively reduce the influence of the pass voltage VPASSR on the memory cell string channel, reduce the jitter phenomenon of the bit line voltage VBL caused by the rise of the pass voltage VPASSR, and reduce the probability of the read disturbance by slowing down the pull-up speed of the pass voltage VPASSR (as shown by the solid line part of the pass voltage VPASS waveform in the figure) and not pulling up the pass voltage VPASSR to the target voltage VTG before the sensing time interval TSEN.

Referring to fig. 4, fig. 4 is a waveform diagram of a pass voltage according to another embodiment of the invention. In the embodiment of the invention, the pull-up of the pass voltage VPASSR in the read operation can be performed in various ways. The pull-up curves SR1 to SR4 in fig. 4 correspond to the four embodiments of the embodiment of the present invention, respectively.

In the first embodiment, the word line voltage WL is selected by the voltage generator corresponding to the pull-up curve SR1 of the pass voltage VPASSR_nIs taken as a first time point TP1, and the pass voltage VPASSR is pulled up from the first voltage V1 at the first time point TP 1. The pass voltage generator is at a second time point TP2 (a start time point of the bit line voltage VBL), and makes the pass voltage VPASSR (a second voltage) smaller than the product of the target voltage VTG and the preset ratio RA 1.

In addition, in the second embodiment, the pull-up curve SR2 of the passing voltage VPASSR (as shown by the dotted line of the passing voltage VPASSR waveform) can be divided into two segments. Wherein the word line voltage WL is selected by a voltage generator_nIs taken as a first time point TP1, and starts to pull up from the first voltage V1 at the first time point TP1, and pulls up the pass voltage VPASSR to the third voltage V3 at the third time point TP 3. Next, the pass voltage generator pulls up the pass voltage VPASSR from the third voltage V3 at a third time point TP3, and pulls up the pass voltage VPASSR to the second voltage V2 at a second time point TP 2. Wherein the third voltage V3 is greater than the first voltage V1, the third voltage V3 andless than the second voltage V2. The third time point TP3 is later than the first time point TP1, the third time point TP3 and earlier than the second time point TP 2.

It should be noted that the pass voltage generator can pull up the pass voltage VPASSR from the first time point TP1 to the third time point TP3 through the first driving capability, and can pull up the pass voltage VPASSR from the third time point TP3 to the second time point TP2 through the second driving capability. Wherein the first driving capability is different from the second driving capability.

In addition, in the third embodiment, the word line voltage WL is also set by the voltage generator_nAs a first time point TP1, and starts to pull up the pass voltage VPASSR at the first time point TP 1. According to the pull-up curve SR3, the pass voltage VPASSR is maintained constant after the pass voltage VPASSR is pulled up by the pass voltage generator for a period of time. And the voltage value at the second time point TP2 is smaller than the voltage value at the second time point TP2 of the passing voltage VPASSR corresponding to the pull-up curves SR1 and SR2, and certainly smaller than the product of the target voltage VTG and the preset ratio RA 1.

In addition, in the fourth embodiment, the word line voltage WL is not set by the voltage generator_nAs a start-up time point to pull up the pass voltage VPASSR. And the first time point TP 1' is changed to be at the word line WL_nAnd a time point before the start time point of the bit line voltage VBL (the second time point TP2) is a first time point TP 1'. In response, the pull-up curve SR4 starts to be pulled up from the first voltage V1 at the first time point TP 1' and is pulled up to a voltage value smaller than the product of the target voltage VTG and the preset ratio RA1 at the second time point TP 2. Wherein, the first time point TP 1' is related to the word line voltage WL_nHas a delay time dL1 between its starting points.

Incidentally, the delay time may be set to be 0 to 71 μ sec. In addition, the time zone from the read operation of the memory cell string after the bit line voltage VBL starting time point (time point TP2) to the entering of the sensing is 0-36 μ s. Of course, the time ranges may be adjusted according to the process, the operating voltage, or other various factors used in the memory device. The above description is intended by way of example only and is not intended to limit the scope of the present invention.

As can be seen from the above description, in the embodiments of the present invention, the pass voltage VPASSR can be pulled up in different ways. The waveform of the pull-up process of the pass voltage VPASSR is not particularly limited, but the pass voltage VPASSR needs to be pulled up to a voltage value smaller than the product of the target voltage VTG and the predetermined ratio RA1 at the starting time point (the second time point TP2) of the bit line voltage VBL, so as to reduce the interference of the pull-up process on the bit line voltage VBL.

Referring to fig. 5A and 5B, fig. 5A and 5B are schematic diagrams illustrating different embodiments of a pass voltage generator according to an embodiment of the invention. In fig. 5A, the pass voltage generator 510 includes a target voltage generator 511, a boosting circuit 512, and a switch 513. The target voltage generator 511 is used for generating a target voltage VTG. In this embodiment, the target voltage generator 511 may generate the target voltage according to the target voltage code DAC [ N:0] to determine the voltage value of the target voltage VTG, wherein the number of bits of the target voltage code may be 1(N ═ 0) or more (N >0), and the target voltage generator 511 may be a digital-to-analog converter.

The voltage boost circuit 512 receives the clock signal CLK and the enable signal En. The voltage boost circuit 512 is enabled according to the enable signal En, and performs a pumping up operation on a reference voltage based on the clock signal CLK to generate the control voltage VSR. In this embodiment, the voltage boost circuit 512 may be a voltage pump (charge pump) circuit.

The switch 513 may be a transistor switch. One terminal of the switch 513 receives the target voltage VTG, a control terminal of the switch 513 receives the control voltage VSR, and the other terminal of the switch 513 provides the pass voltage VPASSR. It is noted that the switch 513 may be implemented as a clamp (clamp). When the control voltage VSR is less than the target voltage VTG plus the threshold voltage VTH of the switch 513, the pass voltage VPASS may be equal to the control voltage VSR minus the threshold voltage VTH of the switch 513. After the control voltage VSR is greater than or equal to the sum of the target voltage VTG and the threshold voltage VTH of the switch 513, the pass voltage vapsrs is equal to the target voltage VTG.

The voltage value of the pass voltage VPASSR may be adjusted by an equivalent resistance provided by switch 513. Wherein the voltage value of the pass voltage VPASSR is inversely related to the equivalent resistance of the switch 513. The pass voltage VPASSR may be equal to the target voltage VTG when the equivalent resistance of the switch 513 is substantially equal to 0.

As can be seen from the above description, the voltage boost circuit 512 can boost the voltage value of the control voltage VSR over time when the flash memory performs a read operation, and thereby control the equivalent resistance provided by the switch 513, so that the pass voltage VPASSR can gradually increase in time sequence.

In fig. 5B, the pass voltage generator 520 includes a target voltage generator 521, a boost circuit 522, a switch 523, a frequency adjustor 525, and a frequency generator 524. The target voltage generator 511 is used for generating a target voltage VTG. Unlike the embodiment of fig. 5A, the frequency of the clock signal CLK received by the voltage boost circuit 522 can be adjusted. The clock generator 524 is configured to generate a reference clock signal CLK0, and the clock adjuster 525 is configured to adjust the frequency of the reference clock signal CLK0 according to the adjustment signal CS to generate the clock signal CLK.

In the present embodiment, the frequency adjuster 525 may dynamically change the frequency of the clock signal CLK. For example, the frequency adjustor 525 may perform a frequency division operation on the reference frequency signal CLK0 to generate the frequency signal CLK, wherein the frequency adjustor 525 may generate a divisor of the frequency division signal according to the adjustment signal CS. Here, the adjustment signal CS is dynamically variable.

By dynamically adjusting the frequency of the clock signal CLK, the control voltage VSR can be increased linearly or nonlinearly, and the pass voltage VPASSR can be pulled up in a one-step or multi-step manner.

On the other hand, the target voltage code DAC [ N:0 can also be dynamically adjusted in time sequence during the passing voltage VPASSR, and thus adjust the rising speed of the passing voltage VPASSR.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating another embodiment of a pass voltage generator according to the present invention. In fig. 6, the pass voltage generator 600 includes a digital-to-analog converter 610. The DAC 610 receives the DAC [ N:0] and converts the DAC [ N:0] to generate an output voltage as a pass voltage VPASSR. Please note that the voltage control code DAC [ N:0] generates a plurality of variations in time sequence. Specifically, according to the embodiment of the present invention shown in fig. 2, a plurality of sub-time points can be divided between the first time point TP1 and the second time point TP 2. The DAC [ N:0] can be sequentially increased corresponding to the time points. In this way, the DAC 610 can increase the pass voltage VPASSR at a plurality of time points corresponding to the increasing DAC [ N:0 ].

In the embodiment of the invention, the increment action of the voltage control code DAC [ N:0] can be linear or non-linear. The value of each increment of the voltage control code DAC [ N:0] can be fixed or unfixed, and is not limited specifically. In addition, the number of sub-time points may be set by the designer, and there is no fixed limit.

Referring to fig. 7, fig. 7 is a schematic diagram illustrating another embodiment of a pass voltage generator according to the present invention. The pass voltage generator 700 includes a candidate voltage generator 711 and a voltage selector 712. The candidate voltage generator 711 may generate a plurality of candidate voltages SV1 SVN having different voltage values. In addition, according to the embodiment of the present invention shown in fig. 2, a plurality of sub-time points can be divided between the first time point TP1 and the second time point TP 2. The voltage selector 712 selects and outputs the candidate voltages SV1 to SVN corresponding to the sub-time points, and generates the pass voltage VPASSR. Taking the candidate voltage SV1< candidate voltage SV2< … < candidate voltage SVN as an example, the voltage selector 712 may sequentially select the candidate voltage SV1, the candidate voltages SV2, …, the candidate voltage SVN to be outputted, and thereby generate the pass voltage VPASSR pulled up in time sequence.

In the present embodiment, the candidate voltage generator 711 may perform multi-stage voltage division (by a voltage division circuit known to those skilled in the art) on a reference voltage to generate the candidate voltages SV1 SVN. The voltage selector 712 can be implemented by a voltage selection circuit known to those skilled in the art, without limitation.

Referring to fig. 8, fig. 8 is a flowchart illustrating a pass voltage control method according to an embodiment of the invention. In step S810, a pass voltage is applied to word lines of unselected memory cells of a selected memory cell string. In step S820, in the read operation, the pass voltage is increased from the first voltage at a first time point and increased to the second voltage at a second time point. The second voltage is smaller than the target voltage multiplied by a preset proportion, the first time point is earlier than the starting time point of the bit line voltage received by the selected memory cell string, and the second time point occurs at the starting time point of the bit line voltage.

The details of the above steps are described in detail in the above embodiments and implementations, and are not repeated herein.

In summary, the present invention reduces the possible disturbance of the pass voltage to the bit line voltage by adjusting the rising rate of the pass voltage before the sensing time interval during the read operation of the flash memory. Therefore, the read disturb phenomenon during the read operation can be reduced, and the probability of read errors can be reduced.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.