阅读说明：本技术 磁性隧道结器件及方法 (Magnetic tunnel junction device and method ) 是由 简瑞芬 邱维刚 林灿 于 2020-11-13 设计创作，主要内容包括：本公开涉及磁性隧道结器件及方法。在实施例中,一种器件包括磁阻式随机存取存储器单元,该磁阻式随机存取存储器单元包括：底部电极；基准层,位于底部电极之上；隧道阻挡层,位于基准层之上,隧道阻挡层包括镁和氧的第一组合物；自由层,位于隧道阻挡层之上,自由层具有比基准层更小的矫顽力；帽盖层,位于自由层之上,帽盖层包括镁和氧的第二组合物,镁和氧的第二组合物具有比镁和氧的第一组合物更高的氧原子浓度和更小的镁原子浓度；以及顶部电极,位于帽盖层之上。(The present disclosure relates to magnetic tunnel junction devices and methods. In an embodiment, a device includes a magnetoresistive random access memory cell comprising: a bottom electrode; a reference layer located over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer comprising a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a coercivity less than the reference layer; a capping layer located over the free layer, the capping layer comprising a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a higher atomic concentration of oxygen and a smaller atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode located over the cap layer.)

1. A semiconductor device, comprising:

a substrate including an active device;

a first inter-metal dielectric IMD layer;

a first conductive feature extending through the first IMD layer, the first conductive feature being electrically coupled to the active device;

a bottom electrode over the first conductive feature;

a magnetic tunnel junction element comprising:

a reference layer located over the bottom electrode;

a tunnel barrier layer over the reference layer, the tunnel barrier layer comprising magnesium oxide;

a free layer located over the tunnel barrier layer; and

a capping layer over the free layer, the capping layer comprising magnesium oxide, the magnesium oxide of the capping layer being more oxidized than the magnesium oxide of the tunnel barrier layer;

a top electrode located over the cap layer;

a second IMD layer over the top electrode; and

a second conductive feature extending through the second IMD layer, the second conductive feature contacting the top electrode.

2. The device of claim 1, further comprising:

a spacer surrounding the bottom electrode and the magnetic tunnel junction element; and

a third IMD layer surrounding the spacer and the top electrode;

a fourth IMD layer adjacent to the first IMD layer and the third IMD layer; and

a third conductive feature extending through the fourth IMD layer, the third conductive feature being electrically coupled to the active device.

3. The device of claim 1, wherein the tunnel barrier layer has equal atomic concentrations of magnesium and oxygen.

4. The device of claim 1, wherein the ratio of oxygen to magnesium in the tunnel barrier layer is in the range of 0.95 to 1.05 and the tunnel barrier layer has a thickness in the range of 0.6nm to 1.2 nm.

5. The device of claim 1, wherein the capping layer has a higher atomic concentration of oxygen than magnesium.

6. The device of claim 1, wherein the ratio of oxygen to magnesium in the capping layer is in the range of 1.0 to 1.2, and the capping layer has a thickness in the range of 0.4nm to 1.0 nm.

7. A semiconductor device, comprising:

a magnetoresistive random access memory cell, comprising:

a bottom electrode;

a reference layer located over the bottom electrode;

a tunnel barrier layer over the reference layer, the tunnel barrier layer comprising a first composition of magnesium and oxygen;

a free layer over the tunnel barrier layer, the free layer having a lower coercivity than the reference layer;

a capping layer located over the free layer, the capping layer comprising a second composition of magnesium and oxygen having a higher concentration of oxygen atoms and a smaller concentration of magnesium atoms than the first composition of magnesium and oxygen; and

a top electrode located over the cap layer.

8. The device of claim 7, further comprising:

a row decoder;

word lines electrically coupling the row decoder to the bottom electrodes;

a row decoder; and

a bit line electrically coupling the column decoder to the top electrode.

9. The device of claim 7, wherein the first composition of magnesium and oxygen has equal atomic concentrations of magnesium and oxygen, and wherein the second composition of magnesium and oxygen has an atomic concentration of oxygen that is higher than the atomic concentration of magnesium.

10. A method for forming a semiconductor device, comprising:

forming a bottom electrode layer over a substrate;

forming a ground layer over the bottom electrode layer;

forming a seed layer over the ground layer;

forming a reference layer over the seed layer;

sputtering magnesium oxide by radio frequency RF sputtering, forming a tunnel barrier layer over the reference layer;

forming a free layer over the tunnel barrier layer;

forming a capping layer over the free layer by repeating deposition and oxidation of magnesium;

forming a top electrode layer over the cap layer; and

patterning the top electrode layer, the capping layer, the free layer, the tunnel barrier layer, the reference layer, the seed layer, the ground layer, and the bottom electrode layer to form a magnetoresistive random access memory cell.

Technical Field

The present disclosure relates to magnetic tunnel junction devices and methods.

Background

Semiconductor memories are used in integrated circuits for electronic applications including, for example, radios, televisions, cell phones, and personal computing devices. One type of semiconductor memory is Magnetoresistive Random Access Memory (MRAM), which relates to spintronics devices that incorporate semiconductor technology and magnetic materials and devices. The spins of the electrons, through their magnetization, are used to represent the bit code. An MRAM cell typically includes a Magnetic Tunnel Junction (MTJ) element that includes two ferromagnets separated by a thin insulator.

Disclosure of Invention

According to an embodiment of the present disclosure, there is provided a semiconductor device including: a substrate including an active device; a first inter-metal dielectric IMD layer; a first conductive feature extending through the first IMD layer, the first conductive feature being electrically coupled to the active device; a bottom electrode over the first conductive feature; a magnetic tunnel junction element comprising: a reference layer located over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer comprising magnesium oxide; a free layer located over the tunnel barrier layer; and a capping layer over the free layer, the capping layer comprising magnesium oxide, the magnesium oxide of the capping layer being more oxidized than the magnesium oxide of the tunnel barrier layer; a top electrode located over the cap layer; a second IMD layer over the top electrode; and a second conductive feature extending through the second IMD layer, the second conductive feature contacting the top electrode.

According to another embodiment of the present disclosure, there is provided a semiconductor device including: a magnetoresistive random access memory cell, comprising: a bottom electrode; a reference layer located over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer comprising a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lower coercivity than the reference layer; a capping layer located over the free layer, the capping layer comprising a second composition of magnesium and oxygen having a higher concentration of oxygen atoms and a smaller concentration of magnesium atoms than the first composition of magnesium and oxygen; and a top electrode located over the cap layer.

According to still another embodiment of the present disclosure, there is provided a method for forming a semiconductor device, including: forming a bottom electrode layer over a substrate; forming a ground layer over the bottom electrode layer; forming a seed layer over the ground layer; forming a reference layer over the seed layer; sputtering magnesium oxide by radio frequency RF sputtering, forming a tunnel barrier layer over the reference layer; forming a free layer over the tunnel barrier layer; forming a capping layer over the free layer by repeating deposition and oxidation of magnesium; forming a top electrode layer over the cap layer; and patterning the top electrode layer, the capping layer, the free layer, the tunnel barrier layer, the reference layer, the seed layer, the ground layer, and the bottom electrode layer to form a magnetoresistive random access memory cell.

Drawings

Various aspects of this disclosure will be best understood from the following detailed description when read with the accompanying drawings. It is noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a block diagram of a semiconductor device according to some embodiments.

Fig. 2 is a cross-sectional view of a semiconductor device according to some embodiments.

Fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8, fig. 9A, fig. 9B, fig. 9C, fig. 9D, fig. 9E, fig. 10, fig. 11, fig. 12, fig. 13, fig. 14, fig. 15, fig. 16, fig. 17, and fig. 18 are cross-sectional views of intermediate stages of fabricating a semiconductor device according to some embodiments.

Fig. 19 is a flow chart of an example method for fabricating a semiconductor device according to some embodiments.

FIG. 20 is a block diagram of a processing tool.

Fig. 21 is a flow chart of an example method for fabricating a semiconductor device according to some other embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "beneath," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments, the perpendicular Magnetic Tunnel Junction (MTJ) element is formed from a capping layer of full magnesium oxide. Complete oxidation of the capping layer is accomplished by forming the capping layer by repeated depositions and oxidations of multiple conductive sublayers. The deposition may be performed by Direct Current (DC) sputtering or Atomic Layer Deposition (ALD), which results in a capping layer having a higher oxidation concentration than Radio Frequency (RF) sputtering. Forming the MTJ element from a capping layer of full magnesium oxide allows the Perpendicular Magnetic Anisotropy (PMA) of the MTJ element to be increased, allowing the resulting Magnetoresistive Random Access Memory (MRAM) cells to have improved Write Error Rates (WER) and Read Error Rates (RER).

Fig. 1 is a block diagram of a semiconductor device 50 according to some embodiments. Semiconductor device 50 includes an MRAM array 52, a row decoder 54, and a column decoder 56. MRAM array 52 includes MRAM cells 58 arranged in rows and columns. The row decoder 54 may be, for example, a static CMOS decoder, a pseudo NMOS decoder, or the like. During operation, the row decoder 54 selects the desired MRAM cells 58 in a row of the MRAM array 52 by activating the corresponding word line WL in that row. The column decoder 56 may be, for example, a static CMOS decoder, a pseudo NMOS decoder, etc., and may include write drivers, sense amplifiers, combinations thereof, etc. During operation, the column decoder 56 selects the bit line BL of the desired MRAM cell from the column of the MRAM array 52 in the selected row, and reads data from or writes data to the selected MRAM cell 58 using the bit line BL.

Fig. 2 is a cross-sectional view of a semiconductor device 50 according to some embodiments. Fig. 2 is a simplified view and omits some features of semiconductor device 50 (discussed below) for clarity of illustration. The semiconductor device 50 includes a logic region 50L and a memory region 50M. A memory device (e.g., MRAM) is formed in the memory region 50M, and a logic device (e.g., logic circuit) is formed in the logic region 50L. For example, the MRAM array 52 (see fig. 1) may be formed in the memory region 50M, and the row decoder 54 and the column decoder 56 (see fig. 1) may be formed in the logic region 50L. The logic region 50L may occupy most of the area of the semiconductor device 50. For example, the logic region 50L may occupy 95% to 99% of the area of the semiconductor device 50, while the memory region 50M occupies the remaining area of the semiconductor device 50. The memory area 50M may be disposed at an edge of the logic area 50L, or the logic area 50L may surround the memory area 50M.

The logic region 50L and the memory region 50M are formed over the same substrate (e.g., a semiconductor substrate 60). The semiconductor substrate 60 may be doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 60 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

The device 62 is formed at the active surface of the semiconductor substrate 60. The devices 62 may be active devices or passive devices. For example, the electrical components may be transistors, diodes, capacitors, resistors, etc., formed by any suitable formation method. Devices 62 are interconnected to form memory devices and logic devices of semiconductor device 50. For example, some of the devices 62 may be access transistors of the MRAM cells 58.

One or more interlayer dielectric (ILD) layers 64 are formed on the semiconductor substrate 60 and conductive features (e.g., contact plugs 66) are formed to be physically and electrically coupled to the devices 62. ILD layer(s) 64 may be formed of any suitable dielectric material, such as: oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like; nitrides, such as silicon nitride; and so on. The ILD layer(s) may be formed by any suitable deposition process, such as spin-on coating, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), the like, or combinations thereof. The conductive features in the ILD layer(s) may be formed by any suitable process, such as deposition, damascene (e.g., single damascene, dual damascene, etc.), the like, or combinations thereof.

Interconnect structure 68 is formed over semiconductor substrate 60, such as over ILD layer(s) 64. Interconnect structure 68 interconnects devices 62 to form an integrated circuit in each of logic region 50L and memory region 50M. The interconnect structure 68 includes a plurality of metallization layers M1-M6. Although six metallization layers are shown, it should be understood that more or fewer metallization layers may be included. Each of the metallization layers M1-M6 includes a metallization pattern in a dielectric layer. The metallization patterns are electrically coupled to the devices 62 of the semiconductor substrate 60 and include metal lines L1-L6 and vias V1-V6, respectively, formed in one or more inter-metal dielectric (IMD) layers. Interconnect structure 68 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like. In some embodiments, contact plug 66 is also part of the metallization pattern, such as part of the lowest layer of metal via V1.

MRAM cells 58 of MRAM array 52 (see fig. 1) are formed in interconnect structure 68. MRAM cell 58 may be formed in any of metallization layers M1-M6, and is shown as being formed in intermediate metallization layer M5. Each MRAM cell 58 includes a conductive via 110, a bottom electrode 132 on conductive via 110, an MTJ element 134 on bottom electrode 132, and a top electrode 136 on MTJ element 134. Another IMD layer 108 may be formed around MRAM cell 58 with conductive via 110 extending through IMD layer 108. Spacers 140 may also be formed around MRAM cells 58. IMD layer 108 and/or spacers 140 surround and protect the components of MRAM cell 58. The resistance of the MTJ element 134 is programmable and can be at a high resistance (R)_AP) And low resistance (R)_P) Is changed between R_APMay represent a code such as "1", R_PA code such as "0" may be represented. Thus, a code may be written to MRAM cell 58 by programming the resistance of its MTJ element 134 with the respective access transistor of MRAM cell 58, and a code may be read from MRAM cell 58 by measuring the resistance of its MTJ element 134 with the respective access transistor of MRAM cell 58.

MRAM cell 58 is electrically coupled to device 62. The conductive vias 110 are physically and electrically coupled to an underlying metallization pattern, such as metal line L4 in the illustrated example. The top electrode 136 is physically and electrically coupled to the overlying metallization pattern, such as to metal via V6 in the illustrated example. The MRAM cells 58 are arranged in an MRAM array having rows and columns of memory. The metallization pattern includes access lines (e.g., word lines and bit lines) of the MRAM array. For example, the lower level metallization pattern (e.g., M1-M4) may include word lines disposed along rows of the MRAM array, and the overlying metallization pattern (e.g., M6) may include bit lines disposed along columns of the MRAM array. Some of the devices 62 (e.g., access transistors) are electrically coupled to word lines of the MRAM array (e.g., devices of the row decoder 54). Top electrode 136 is electrically coupled to other devices, such as the devices of column decoder 56, through bit lines of the MRAM array.

Fig. 3-18 are various views of intermediate stages in the manufacture of semiconductor device 50, according to some embodiments. In particular, fabrication of interconnect structure 68 (see fig. 2) for semiconductor device 50 is shown. As described above, interconnect structure 68 includes MRAM cells 58 of MRAM array 52 (see FIG. 1).

In fig. 3, a metallization layer of an interconnect structure is formed (e.g., M4, see fig. 2). The metallization layer includes an IMD layer 102 and a conductive feature 104 (which may correspond to a metal line L4, see fig. 2). IMD layer 102 is formed over ILD layer(s) 64. IMD layer 102 may be formed of any suitable dielectric material, such as: oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like; nitrides, such as silicon nitride; and so on. The IMD layer 102 may be formed by any suitable deposition process, such as spin coating, PVD, Chemical Vapor Deposition (CVD), the like, or combinations thereof. IMD layer 102 may be a layer formed from a low-k dielectric material having a k value below about 3.0. IMD layer 102 may be a layer formed of an ultra-low k (elk) dielectric material having a k value less than 2.5.

Conductive features 104 are formed in IMD layer 102 and electrically coupled to devices 62. According to some embodiments, the conductive feature 104 includes a diffusion barrier layer and a conductive material over the diffusion barrier layer. An opening is formed in the IMD layer 102 using, for example, an etching process. The opening exposes an underlying conductive feature, such as an underlying metal via. The diffusion barrier layer may be formed of tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, or the like, and may be formed in the opening by a deposition process such as Atomic Layer Deposition (ALD), or the like. The conductive material may include copper, aluminum, tungsten, silver, combinations thereof, and the like, and may be formed over the diffusion barrier layer in the opening by an electrochemical plating process, CVD, ALD, PVD, the like, or combinations thereof. In an embodiment, the conductive material is copper, and the diffusion barrier is a thin barrier that prevents copper from diffusing into the IMD layer 102. After the diffusion barrier and the conductive material are formed, the excess portions of the diffusion barrier and the conductive material may be removed by, for example, a planarization process (e.g., a Chemical Mechanical Polishing (CMP) process). In some embodiments, the conductive feature 104 is a metal line (which may correspond to metal line L4, see fig. 2).

An etch stop layer 106 is formed on the conductive feature 104 and the IMD layer 102. Etch stop layer 106 may be formed from a dielectric material such as aluminum nitride, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, combinations thereof, and the like. The etch stop layer 106 may be formed by Chemical Vapor Deposition (CVD), PVD, ALD, spin-on dielectric processes, the like, or combinations thereof. Etch stop layer 106 may also be a composite layer formed from a plurality of different dielectric proton layers. For example, the etch stop layer 106 may include a silicon carbide sub-layer and an aluminum oxide sub-layer formed on the silicon carbide sub-layer. The silicon carbide sublayer may be used as a glue layer to improve adhesion between the alumina sublayer and the IMD layer 102.

An IMD layer 108 is formed on the etch stop layer 106. In some embodiments, IMD layer 108 is formed from tetraethyl orthosilicate (TEOS) oxide (e.g., silicon oxide deposited using, for example, a Chemical Vapor Deposition (CVD) process with TEOS as a precursor). In some embodiments, IMD layer 108 may be formed using PSG, BSG, BPSG, Undoped Silicate Glass (USG), fluorosilicate glass (FSG), SiOCH, flowable oxide, porous oxide, or the like, or combinations thereof. For example, IMD layer 108 may also be formed from a low-k dielectric material having a k value less than about 3.0. The IMD layer 108 may be formed to a thickness in a range of about 50nm to about 150 nm.

Conductive vias 110 are formed to extend through IMD layer 108 and etch stop layer 106. The conductive vias 110 may also be referred to as bottom vias. In some embodiments, the conductive via 110 includes a conductive region 112 and a conductive barrier layer 114, the conductive barrier layer 114 lining sidewalls and a bottom surface of the conductive region 112. Conductive barrier layer 114 may be formed of titanium, titanium nitride, tantalum nitride, cobalt, combinations thereof, and the like. The conductive region 112 may be formed of a metal such as copper, aluminum, tungsten, cobalt, alloys thereof, and the like. The forming of the conductive via 110 may include: the IMD layer 108 and the etch stop layer 106 are etched to form a via opening, a conductive barrier layer is formed to extend into the via opening, a metal material is deposited over the conductive barrier layer, and a planarization process, such as a CMP process or a mechanical polishing process, is performed to remove excess portions of the conductive barrier layer and the metal material.

In fig. 4-10, a plurality of layers are deposited over the conductive vias 110 and the IMD layer 108. Specifically, a bottom electrode layer 116, a MTJ stack 118, and a top electrode layer 120 are deposited (see FIG. 10). The MTJ stack 118 is a multilayer that includes a ground layer 118A, a seed layer 118B, one or more reference layers 118C, a tunnel barrier layer 118D, one or more free layers 118E, a cap layer 118F, and one or more capping layers 118G. The bottom electrode layer 116, the MTJ stack 118, and the top electrode layer 120 will be patterned in subsequent processing to form the bottom electrode 132, the MTJ element 134, and the top electrode 136, respectively, of the corresponding MRAM cell 58 (see FIG. 2). Fig. 4-10 are described in conjunction with fig. 19.

Fig. 19 is a flow chart of an example method 200 for fabricating semiconductor device 50 according to some embodiments. The method 200 may be performed by, for example, a processing tool. FIG. 20 is a block diagram of a processing tool 300 that can perform the method 200. The processing tool 300 includes a plurality of modules 304, 306, 308, 310, 312, 314, 316, 318, and each of the steps 202, 204, 206, 208, 210, 212, 218 of the method 200 may be performed on a wafer by some or all of the modules of the processing tool 300. The modules may be, for example, different regions or functions of the processing tool 300, and may be located in the same chamber or different chambers of the processing tool 300. Wafer processing may be in-situ, for example, wafers may be processed without breaking vacuum in the processing tool 300 between each of the steps 202, 204, 206, 208, 210, 212, 218 of the method 200. Each of the steps 202, 204, 206, 208, 210, 212, 218 of the method 200 may also be performed in-situ, e.g., when the steps include depositing layers with the module, the layers may be deposited between each deposition without breaking the vacuum in the module. The vacuum may be set by a load lock 302 of the processing tool 300, the load lock 302 receiving wafers for processing. As discussed further below, the modules of the process tool 300 include different types of sputtering modules (e.g., Direct Current (DC) and Radio Frequency (RF)) for performing PVD that will be used to deposit the layers described with respect to fig. 4-10.

In fig. 4, a bottom electrode layer 116 is formed on the conductive via 110 and the IMD layer 108. The bottom electrode layer 116 is formed of a conductive material such as titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), chromium (Cr), ruthenium (Ru), nitrides thereof, combinations thereof, multilayers thereof, and the like. The bottom electrode layer 116 is conformally formed, and may be formed using CVD, PVD, ALD, electrochemical plating, electroless plating, or the like.

A ground layer 118A is formed on the bottom electrode layer 116. The ground layer 118A is formed of a conductive material such as tantalum (Ta), titanium (Ti), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), chromium (Cr), ruthenium (Ru), nitrides thereof, combinations thereof, multilayers thereof, or the like. The ground layer 118A is conformally formed and may be formed using CVD, PVD, ALD, electrochemical plating, electroless plating, or the like.

The seed layer 118B is formed on the ground layer 118A. The seed layer 118B is formed of a conductive material such as ruthenium (Ru), titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), chromium (Cr), nitrides thereof, combinations thereof, multilayers thereof, and the like. The seed layer 118B is conformally formed, and may be formed using CVD, PVD, ALD, electrochemical plating, electroless plating, and the like.

As an example for forming the bottom electrode layer 116, the ground layer 118A, and the seed layer 118B, these layers may be deposited by DC sputtering in step 202 of the method 200. Specifically, a DC sputtering module is used to deposit a titanium nitride layer, thereby forming the bottom electrode layer 116. The titanium nitride layer (e.g., the bottom electrode layer 116) may have a thickness in the range of about 8nm to about 12 nm. A DC sputtering module is then used to deposit a tantalum nitride layer to form the ground layer 118A. The tantalum nitride layer (e.g., ground layer 118A) may have a thickness in the range of about 1nm to about 5 nm. A layer of ruthenium is then deposited using a DC sputtering module to form seed layer 118B. The ruthenium layer (e.g., seed layer 118B) can have a thickness in the range of about 2nm to about 7 nm. In some embodiments, the same DC sputtering module is used to deposit each of bottom electrode layer 116, ground layer 118A, and seed layer 118B. For example, each of these layers may be deposited using the DC sputtering module 304 of the process tool 300. The DC sputtering module 304 may be a multi-target module capable of sputtering material for each desired layer. During DC sputtering, the wafer is placed under the target and an inert gas is introduced into the DC sputtering module. DC power is applied to the target to activate the inert gas into a plasma state and bombard the target with ionized gas molecules, causing atoms from the target to be sputtered onto the wafer being processed. DC sputtering of conductive materials can be performed at lower cost and at higher deposition rates than other sputtering techniques, such as Radio Frequency (RF) sputtering.

In fig. 5, a reference layer(s) 118C is formed on the seed layer 118B. The reference layer(s) 118C are formed of a ferromagnetic material (e.g., cobalt (Co), iron (Fe), iron boron (FeB), cobalt iron boron (CoFeB), combinations thereof, multilayers thereof, and the like). The reference layer(s) 118C may be formed of a plurality of different ferromagnetic and non-magnetic sublayers, which may be referred to as flux-closure layer(s). In some embodiments, the flux-closing layer(s) include a hard-biasing layer, an anti-parallel coupling layer, and a reference layer. During operation, antiparallel coupling occurs on the antiparallel coupling layer, causing the magnetizations of the hard bias layer and the reference layer to orient in antiparallel directions and form a flux closure with a small net magnetization. Thus, stray fields (stray fields) emanating from the flux closure into the free layer(s) 118E (discussed further below) become sufficiently negligible such that the magnetization of the free layer(s) 118E can be freely switched. In other words, the free layer(s) 118E has a lower coercivity than the flux-closing layer(s). The reference layer(s) 118C are conformally formed, and may be formed using CVD, PVD, ALD, electrochemical plating, electroless plating, and the like.

As an example of forming the reference layer(s) 118C, in step 204 of method 200, the layer may be deposited by DC sputtering. Specifically, the DC sputtering module is used to deposit cobalt and platinum laminates, such as [ Co/Pt ] x n/Co, where n represents the number of laminates, which can range from about 2 to about 6, to form a hard bias layer. The cobalt sublayers may each have a thickness in a range of about 0.1nm to about 0.4nm, and the platinum sublayers may each have a thickness in a range of about 0.1nm to about 0.4 nm. The top cobalt sublayers of the laminate may each have a thickness in the range of about 0.4nm to about 1.2 nm. A DC sputtering module is then used to deposit an iridium layer, forming an antiparallel coupling layer. The iridium layer may have a thickness in a range of about 0.4nm to about 0.6 nm. A DC sputtering module was then used to deposit a cobalt layer, a molybdenum layer on the cobalt layer, and a ferroboron layer on the molybdenum layer, forming a reference layer. The cobalt layer may have a thickness in a range of about 0.4nm to about 0.8nm, the molybdenum layer may have a thickness in a range of about 0.2nm to about 0.4nm, and the iron boron layer may have a thickness in a range of about 0.6nm to about 1.6 nm. In some embodiments, the same DC sputtering module is used to deposit each of the reference layer(s) 118C, e.g., each of the hard bias layer, the anti-parallel coupling layer, and the reference layer. For example, each of these layers may be deposited using the DC sputtering module 306 of the process tool 300. The DC sputtering module 306 can be a multi-target module capable of sputtering material for each desired layer. DC sputtering of ferromagnetic materials can be performed at lower cost and at higher deposition rates than other sputtering techniques, such as RF sputtering.

In fig. 6, a tunnel barrier layer 118D is formed on the reference layer(s) 118C. The tunnel barrier layer 118D is formed of a dielectric material, such as magnesium oxide (MgO), aluminum nitride (AlN), aluminum oxide (AlO), combinations thereof, multilayers thereof, and the like. The tunnel barrier layer 118D is conformally formed, and may be formed using CVD, PVD, ALD, or the like.

As an example for forming the tunnel barrier layer 118D, in step 206 of the method 200, the layer may be deposited by RF sputtering. Specifically, the RF sputtering module is used to deposit a magnesium oxide layer, thereby forming the tunnel barrier layer 118D. The magnesium oxide layer (e.g., tunnel barrier layer 118D) may have a thickness T in the range of about 0.6nm to about 1.2nm₁. During RF sputtering, the wafer is placed under a target in an RF sputtering module. An inert gas is flowed into the RF sputtering module. RF power is applied to the target to activate the inert gas into a plasma state and bombard the target with ionized gas molecules, causing atoms from the target to be sputtered onto the wafer being processed. Each cycle of applied RF power includes a bombardment period (in which the target material is bombarded with ions) and a cleaning period (in which electrons are attracted)To the target material to clear it of ion accumulation).

In some embodiments, the bonding process is performed in an RF sputtering module prior to depositing the magnesium oxide layer. The bonding process may be a metal bonding process, for example, performed by sputtering a metal, such as tantalum, on the sidewalls of the chamber of the RF sputtering module. Sputtering metal on the surfaces of the chamber (e.g., over the undesired dielectric material) helps to reduce negative effects that may result from the accumulation of the undesired dielectric material on the interior surfaces of the chamber after repeating the deposition steps. In addition, sputtering metal on the surfaces of the chamber may induce a gettering effect (gettering effect), which helps to reduce the vapor pressure in the chamber, thereby improving the properties of the magnesium oxide layer. In some embodiments, the same RF sputtering module is used to both bond the chamber and deposit the magnesium oxide layer. For example, the RF sputtering module 308 of the processing tool 300 may be used for bonding and sputtering. The RF sputtering module 308 can be a dual target module capable of sputtering both magnesium oxide and a bonding metal.

In some embodiments, the magnesium oxide is deposited by bombarding a magnesium oxide target with ions. Argon gas may be flowed into the RF sputtering module 308 at a low flow rate (e.g., a flow rate in a range of about 20sccm to about 35 sccm) and activated to a plasma state. Flowing argon at low flow rates can reduce the deposition rate by producing less plasma, thereby reducing the number of ions bombarding the target. The deposition rate of the RF sputtering module 308 may be lower than the deposition rate of the DC sputtering modules 304, 306, 314, 316, 318. Reducing the deposition rate and performing a cleaning cycle during RF sputtering avoids the accumulation of ions on the target, which helps to avoid the deposition of undesirable pure magnesium byproducts. Reducing the amount of magnesium byproducts when depositing tunnel barrier layer 118D helps the resulting MTJ element 134 (see FIG. 2) to be free of undesirable conductive materials, thereby maintaining its desired high resistance (R)_AP) And low resistance (R)_P) And (4) code. Accordingly, the resistance of the resulting MTJ element 134 (see FIG. 2) may be more uniform across the MRAM cells 58 (see FIG. 1) of the MRAM array 52. However, when depositing magnesium oxide by RF sputtering, the oxygen concentration of the deposited magnesium oxide layer is limited. In particular, preference for magnesium may occurSputtering, which results in the tunnel barrier layer 118D having an oxygen concentration lower than that of the magnesium oxide target. In some embodiments, the stoichiometric ratio of oxygen to magnesium for the magnesium oxide target is greater than the stoichiometric ratio of oxygen to magnesium for the deposited magnesium oxide layer. For example, a magnesium oxide target may have a stoichiometric ratio of oxygen to magnesium equal to about 1. Similarly, the deposited magnesium oxide layer may have a stoichiometric ratio of oxygen to magnesium of less than or equal to about 1, such as in the range of about 0.95 to about 1.05. In some embodiments, tunnel barrier layer 118D has a substantially equal concentration of magnesium atoms and oxygen atoms. Oxygen starvation during RF sputtering can result in undesirable retention of pure magnesium byproducts, which can lead to problems such as electrical shorts, PMA degradation, and the like.

Although depositing magnesium oxide by RF sputtering can reduce the amount of undesirable magnesium byproducts, the oxygen concentration of the deposited magnesium oxide layer is limited by the initial oxygen concentration of the magnesium oxide target. In some embodiments, the magnesium oxide target is oxygen deficient, and thus, the deposited magnesium oxide layer may have a low concentration (in atomic percent) of oxygen and may only be a portion of the magnesium oxide. For example, the deposited magnesium oxide layer may have a stoichiometric ratio of oxygen to magnesium of less than or equal to about 1 (e.g., in the range of about 0.95 to about 1.05). In some embodiments, tunnel barrier layer 118D has a concentration of magnesium atoms that is greater than a concentration of oxygen atoms. In some embodiments, tunnel barrier layer 118D has a substantially equal concentration of magnesium atoms and oxygen atoms.

Optionally, in step 208 of method 200, tunnel barrier layer 118D is annealed. The anneal may increase the thickness T of the tunnel barrier layer 118D₁. As an example of annealing, a heating module 310 of the process tool 300 may be used to heat a wafer being processed, after which a cooling module 312 of the process tool 300 may be used to cool the heated wafer and help speed up the process. In an embodiment, the anneal may be performed at a temperature in a range of about 350 ℃ to about 425 ℃ and for a duration in a range of about 30 minutes to about 200 minutes, which increases the thickness of the tunnel barrier layer 118D to a thickness T in a range of about 0.7nm to about 1.0nm₁. When the tunnel barrier layer 118D is formed by RF sputtering,increasing its thickness may help to increase the high resistance (R) of the resulting MTJ element 134 (see FIG. 2)_AP) And low resistance (R)_P) The relative change in resistance between states may improve the Write Error Rate (WER) and Read Error Rate (RER) of MRAM cell 58 (see fig. 1).

In fig. 7, the free layer(s) 118E are formed on the tunnel barrier layer 118D. The free layer(s) 118E are formed of ferromagnetic materials, such as cobalt (Co), iron (Fe), iron boron (FeB), cobalt iron boron (CoFeB), combinations thereof, multilayers thereof, and the like. The free layer(s) 118E are conformally formed and may be formed using CVD, PVD, ALD, electrochemical plating, electroless plating, and the like.

As an example for forming the free layer(s) 118E, in step 210 of method 200, the layer may be deposited by DC sputtering. Specifically, the DC sputtering module is used to deposit a first cofeb layer, a molybdenum layer on the first cofeb layer, and a second cofeb layer on the molybdenum layer, thereby forming the free layer(s) 118E. The first cobalt iron boron layer may have a thickness in a range of about 0.8nm to about 1.4nm, the molybdenum layer may have a thickness in a range of about 0.2nm to about 0.4nm, and the second cobalt iron boron layer may have a thickness in a range of about 0.8nm to about 1.4 nm. In some embodiments, the first cobalt-iron-boron layer is doped with more boron than the second cobalt-iron-boron layer. In some embodiments, the same DC sputtering module is used to deposit each of the free layer(s) 118E. For example, each of these layers may be deposited using the DC sputtering module 314 of the process tool 300. The DC sputtering module 314 can be a multi-target module capable of sputtering material for each desired layer. DC sputtering of ferromagnetic materials can be performed at lower cost and at higher deposition rates than other sputtering techniques, such as RF sputtering.

The magnetization of the free layer(s) 118E can be freely switched, and thus the resistance of the resulting MTJ element 134 (see fig. 2) is correspondingly programmable. In particular, the resistance of the MTJ element 134 may be at a high resistance (R)_AP) And low resistance (R)_P) To change between. When the magnetization of the free layer(s) 118E is level with the magnetization of the reference layer(s) 118CIn the row, the MTJ element has a low resistance (R)_P). When the magnetization of the free layer(s) 118E is anti-parallel to the magnetization of the reference layer(s) 118C, the MTJ element has a high resistance (R)_AP). Thus, the resulting MTJ element 134 may also be referred to as a programmable resistance element. The MTJ element 134 is a perpendicular MTJ element, for example, with the magnetization direction perpendicular to the main surface of the semiconductor substrate 60.

In fig. 8, a cap layer 118F is formed on the free layer(s) 118E. The capping layer 118F is formed of a dielectric material, such as magnesium oxide (MgO), aluminum nitride (AlN), aluminum oxide (AlO), combinations thereof, multilayers thereof, and the like. The cap layer 118F is conformally formed and may be formed using CVD, PVD, ALD, or the like.

As an example for forming capping layer 118F, in step 212 of method 200, the layer is formed by a plurality of DC sputtering and oxidation steps. Specifically, in step 214 of the method 200, a DC sputtering module is used to deposit the pure magnesium sublayer. Next, in step 216 of method 200, the deposited magnesium sub-layer is oxidized in the DC sputtering module to form a magnesium oxide layer. Steps 214 and 216 are repeated for several cycles (e.g., four cycles) until the magnesium oxide layer reaches the desired thickness, thereby forming cap layer 118F. Each step is performed in the same DC sputtering module and, between each sputtering and oxidation step, for example, is performed in situ without breaking the vacuum in the sputtering module. For example, the DC sputtering module 316 of the process tool 300 can be used to deposit a magnesium oxide layer. The DC sputtering module 316 can be a single target module capable of sputtering magnesium oxide without contaminating other targets. Figures 9A through 9E are cross-sectional views of an intermediate stage in the fabrication of cap layer 118F according to some embodiments.

In FIG. 9A, a DC sputtering module is used to deposit the first magnesium sublayer 118F₁. First magnesium sublayer 118F₁May be deposited to a thickness in the range of about 0.2nm to about 0.4 nm. The first magnesium sublayer 118F is then oxidized₁To form a magnesium oxide sub-layer. In some embodiments, the oxidation is performed by flowing oxygen into the DC sputtering module (e.g., in the first magnesium sublayer 118F) at a flow rate in a range from about 8sccm to about 40sccm₁Above), for about 10 seconds to about 40 secondsIs completed by a time within the range of (1). Oxidizing at a large flow rate and for a long duration helps ensure that the first magnesium sublayer 118F₁Substantially oxidized, particularly when the first magnesium sublayer 118F₁When thicker.

In FIG. 9B, a DC sputtering module is used to deposit the second magnesium sublayer 118F₂. Second magnesium sublayer 118F₂May be deposited to a thickness in the range of about 0.08nm to about 0.24 nm. The second magnesium sublayer 118F is then oxidized₂To form a magnesium oxide sub-layer. In some embodiments, the oxidation is performed by flowing oxygen into the DC sputtering module (e.g., at the second magnesium sublayer 118F) at a flow rate in a range from about 1sccm to about 20sccm₂Above), for a time in the range of about 10 seconds to about 40 seconds. Note that the second magnesium sublayer 118F₂Is deposited to the first magnesium sublayer 118F₁A small thickness, and a second magnesium sublayer 118F₂To be smaller than the first magnesium sublayer 118F₁A smaller oxygen flow rate. Because of the second magnesium sublayer 118F₂Is thinner so it is thinner than the first magnesium sublayer 118F₁Is more easily oxidized.

In FIG. 9C, a DC sputtering module is used to deposit the third magnesium sublayer 118F₃. Third magnesium sublayer 118F₃May be deposited to a thickness in the range of about 0.08nm to about 0.24 nm. The third magnesium sublayer 118F is then oxidized₃To form a magnesium oxide sub-layer. In some embodiments, the oxidation is performed by flowing oxygen into the DC sputtering module (e.g., at the third magnesium sublayer 118F) at a flow rate in a range from about 1sccm to about 20sccm₃Above), for a time in the range of about 10 seconds to about 40 seconds. Note that the third magnesium sublayer 118F₃Is deposited to the first magnesium sublayer 118F₁A small thickness, and a third magnesium sublayer 118F₃To be smaller than the first magnesium sublayer 118F₁A smaller oxygen flow rate. In some embodiments, the third magnesium sublayer 118F₃Is deposited on the second magnesium sublayer 118F₂The same thickness, and a third magnesium sublayer 118F₃To interact with the second magnesium sublayer 118F₂Oxidized in the same manner. Due to the third magnesium sublayer 118F₃Is thinner so it is thinner than the first magnesium sublayer 118F₁Is more easily oxidized.

In FIG. 9D, a DC sputtering module is used to deposit the fourth magnesium sublayer 118F₄. A fourth magnesium sublayer 118F₄May be deposited to a thickness in the range of about 0.08nm to about 0.24 nm. The fourth magnesium sublayer 118F is then oxidized₄To form a magnesium oxide sub-layer. In some embodiments, the oxidation is performed by flowing oxygen into the DC sputtering module (e.g., at the fourth magnesium sublayer 118F) at a flow rate in a range from about 100sccm to about 1000sccm₄Above), for a time in the range of about 10 seconds to about 40 seconds. A fourth magnesium sublayer 118F₄Is deposited on the second magnesium sublayer 118F₂And a third magnesium sublayer 118F₃The same thickness. A fourth magnesium sublayer 118F₄To be smaller than the first magnesium sublayer 118F₁A second magnesium sublayer 118F₂And a third magnesium sublayer 118F₃Greater oxygen flow rate for oxidation. A fourth magnesium sublayer 118F₄And may be larger than the first magnesium sublayer 118F₁A second magnesium sublayer 118F₂And a third magnesium sublayer 118F₃Each of which is oxidized for a longer duration. Oxidizing at a large flow rate and for a long duration helps ensure that the first magnesium sublayer 118F₁A second magnesium sublayer 118F₂A third magnesium sublayer 118F₃And a fourth magnesium sublayer 118F₄Is sufficiently oxidized.

In FIG. 9E, a DC sputtering module is used to deposit the fifth magnesium sublayer 118F₅. A fifth magnesium sublayer 118F₅May be deposited to a thickness in the range of about 0.08nm to about 0.24 nm. Forming a fifth magnesium sublayer 118F₅The underlying layer may be protected during subsequent processing. A fifth magnesium sublayer 118F₅Instead of being oxidized separately, it may be formed by oxidizing the fourth magnesium sublayer 118F₄Diffused to oxidize.

Although the sub-layers of the cap layer 118F are discretely deposited and oxidized, the cap layer 118F is a single uniform dielectric material composition after formation is complete. Returning to fig. 8, forming the capping layer 118F by repeated deposition and oxidation of magnesium allows for fine control of the composition of the capping layer 118F and allows for the formation of the cap using more oxygen than other deposition techniques (e.g., reactive sputtering)A cap layer 118F. Specifically, capping layer 118F may be formed of magnesium oxide with a large concentration of oxygen (in atomic percent), and may be fully magnesium oxide, or at least may be oxidized more than tunnel barrier layer 118D. In other words, tunnel barrier layer 118D is formed from a first composition of magnesium and oxygen, and capping layer 118F is formed from a second composition of magnesium and oxygen, wherein the second composition has a higher concentration of oxygen atoms and a smaller concentration of magnesium atoms than the first composition. In an embodiment, capping layer 118F is deposited to a thickness T in the range of about 0.4nm to about 1.0nm₂. Thickness T of capping layer 118F₂Thickness T less than tunnel barrier layer 118D₁. In an embodiment, cap layer 118F has a stoichiometric ratio of oxygen to magnesium greater than about 1, for example in the range of about 1.0 to about 1.2. In other words, when capping layer 118F is deposited using repeated deposition and oxidation, the magnesium oxide of capping layer 118F has a greater atomic concentration of oxygen than magnesium. In some embodiments, capping layer 118F has a higher concentration of oxygen atoms and a smaller concentration of magnesium atoms than tunnel barrier layer 118D. In other words, capping layer 118F has a first stoichiometric ratio of oxygen to magnesium and tunnel barrier layer 118D has a second stoichiometric ratio of oxygen to magnesium, where the first stoichiometric ratio is greater than the second stoichiometric ratio. In addition, the capping layer 118F may have a uniform oxygen concentration throughout the process, or at least may have a more uniform oxygen concentration than the tunnel barrier layer 118D. Forming the cap layer 118F of full magnesium oxide allows the cap layer 118F to act as a protective layer to reduce damage to the free layer(s) 118E by etching in a subsequent process for patterning the MTJ stack 118. Further, forming the capping layer 118F of full magnesium oxide allows the Perpendicular Magnetic Anisotropy (PMA) of the resulting MTJ element 134 (see fig. 2) to be increased. Increasing the PMA of the resulting MTJ element 134 facilitates increasing the high resistance (R) of the resulting MTJ element 134_AP) And low resistance (R)_P) The relative change in resistance between states may improve the Write Error Rate (WER) and Read Error Rate (RER) of MRAM cell 58 (see fig. 1).

In fig. 10, capping layer(s) 118G are formed on capping layer 118F. The capping layer(s) 118G are formed of a ferromagnetic material, such as cobalt (Co), iron (Fe), iron boron (FeB), cobalt iron boron (CoFeB), combinations thereof, multilayers thereof, and the like. The capping layer(s) 118G are conformally formed and may be formed using CVD, PVD, ALD, electrochemical plating, electroless plating, and the like.

A top electrode layer 120 is formed on the capping layer(s) 118G. The top electrode layer 120 is formed of a conductive material, such as titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), chromium (Cr), ruthenium (Ru), nitrides thereof, combinations thereof, multilayers thereof, and the like. The top electrode layer 120 is conformally formed, and may be formed using CVD, PVD, ALD, electrochemical plating, electroless plating, or the like.

As an example for forming the capping layer(s) 118G and the top electrode layer 120, in step 218 of the method 200, the layer may be deposited by DC sputtering. Specifically, the DC sputtering module is used to deposit a layer of CoFeB, a layer of tantalum on the CoFeB, and a layer of ruthenium on the tantalum layer, thereby forming the capping layer(s) 118G. The cofeb layer may have a thickness in a range of about 0.2nm to about 0.4nm, the ta layer may have a thickness in a range of about 1.5nm to about 4nm, and the ru layer may have a thickness in a range of about 3nm to about 6 nm. Forming a cobalt-iron-boron layer between the capping layer 118F and the tantalum layer causes the resulting MTJ element 134 (see fig. 2) to exhibit Perpendicular Magnetic Anisotropy (PMA), thereby enhancing the polarization of the conduction electrons and improving the Tunneling Magnetoresistance (TMR) effect.

A DC sputtering module is then used to deposit a titanium nitride layer, forming the top electrode layer 120. The titanium nitride layer (e.g., top electrode layer 120) may have a thickness in the range of about 60nm to about 100 nm. In some embodiments, the same DC sputtering module is used to deposit each of the capping layer(s) 118G and the top electrode layer 120. For example, each of these layers may be deposited using the DC sputtering module 318 of the process tool 300. The DC sputtering module 318 can be a multi-target module capable of sputtering material for each desired layer. DC sputtering of conductive and ferromagnetic materials can be performed at lower cost and higher deposition rates than other sputtering techniques, such as RF sputtering.

It should be understood that many variations in the materials and structure of the MTJ stack 118 are possible and are within the scope of the present disclosure. For example, layers 118A, 118B, 118C, 118D, 118E, 118F, 118G may be formed in the reverse order of the order described above. Thus, the capping layer(s) 118G may be located at the bottom of the MTJ stack 118 and the ground layer 118A may be located at the top of the MTJ stack 118.

In fig. 11, one or more masks are formed over the top electrode layer 120. These masks will be used to simultaneously pattern the different layers and form the MRAM cell. In some embodiments, the one or more masks may include one or more hard masks, tri-layer masks, combinations thereof, and the like. For example, a hard mask layer 122 may be formed over the top electrode layer 120, and a photosensitive mask 124 may be formed over the hard mask layer 122. In some embodiments, the hard mask layer 122 is formed of an oxide such as titanium oxide, silicon oxide, combinations thereof, or the like. The photosensitive mask 124 may be a photoresist, such as a single layer photoresist, a bilayer photoresist, a trilayer photoresist, and the like. A photosensitive mask 124 is formed in the memory region 50M, wherein the pattern of the photosensitive mask 124 corresponds to the pattern of subsequently formed MRAM cells.

In fig. 12, the photosensitive mask 124 is used as an etch mask to etch and pattern the hard mask layer 122 to form a patterned hard mask. The top electrode layer 120, the MTJ stack 118, and the bottom electrode layer 116 are then etched and patterned using the patterned hard mask as an etch mask. The patterning may include one or more etching processes and may form a recess 130 in the IMD layer 108. The etching method may include a plasma etching method, such as Ion Beam Etching (IBE). IBE has a high degree of accuracy (e.g., a high degree of anisotropy), which helps control the profile of the resulting MRAM cell. Etching may be performed using Glow Discharge Plasma (GDP), Capacitive Coupled Plasma (CCP), Inductively Coupled Plasma (ICP), or the like. The photosensitive mask 124 and the hard mask layer 122 may be consumed in an etching process or may be removed after the etching process.

The etching process forms bottom electrode 132, MTJ element 134, and top electrode 136, which together form MRAM cell 58. Each MRAM cell 58 includes a bottom electrode 132, an MTJ element 134, and a top electrode 136, where the MTJ element 134 is disposed between the bottom electrode 132 and the top electrode 136. The bottom electrode 132 includes the remaining portion of the bottom electrode layer 116. The MTJ element 134 includes the remaining portion of the MTJ stack 118. The top electrode 136 comprises the remaining portion of the top electrode layer 120. In some embodiments, the etching process partially etches the IMD layer 108 and the conductive vias 110. In such embodiments, the remaining portion of IMD layer 108 has sloped sidewalls and, in the cross-section shown, has a trapezoidal shape. After the etching process, the remaining portion of the IMD layer 108 in the logic region 50L may have a thickness in the range of about 3nm to about 30 nm. Bottom electrode 132, MTJ element 134, and top electrode 136 may also have sloped sidewalls and have a trapezoidal shape in the cross-section shown.

In fig. 13, spacers 140 are formed on sidewalls of MRAM cell 58. Spacers 140 surround and protect the components of MRAM cell 58. In particular, the spacer 140 is disposed about the bottom electrode 132 and the MTJ element 134, and may be disposed at least partially about the top electrode 136. The spacer 140 may be formed of: oxides (e.g., silicon oxide, aluminum oxide, etc.), nitrides (e.g., silicon nitride, aluminum nitride, etc.), carbides (e.g., silicon carbide), combinations thereof (e.g., silicon oxynitride, silicon carbonitride, etc.), multilayers thereof, and the like.

In embodiments where the spacer 140 includes multiple layers, the spacer 140 includes a passivation layer 142, a passivation layer 144, and an oxide layer 146. As an example for forming spacers 140, passivation layer 142 may be formed conformally over MRAM cells 58 and recess 130. In some embodiments, passivation layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, and the like, and may be formed using CVD, Plasma Enhanced Chemical Vapor Deposition (PECVD), ALD, Plasma Enhanced Atomic Layer Deposition (PEALD), PVD, combinations thereof, and the like. In some embodiments, the passivation layer 142 may reduce or prevent moisture (e.g., H) during subsequent processing₂O) into MRAM cell 58. The passivation layer 142 is then patterned to expose portions of the top electrode 136. In some embodiments, the patterning is a dry etch process, such as an anisotropic etch process. The horizontal portion of the passivation layer 142 is patterned. Subsequently, another passivation layer 144 is formed over the passivation layer 142. In some embodiments, passivation layer 144 is formed from one of the candidate materials and methods for passivation layer 142, but is formed from a different material than passivation layer 142. For example, the passivation layer 142 may be formed of an oxide (e.g., silicon oxide), and the passivation layer 144 may be formed of a nitride (e.g., silicon nitride). An oxide layer 146 is then formed over the passivation layer 144. In some embodiments, the oxide layer 146 may include silicon oxide or the like, and may be formed using CVD, PECVD, ALD, PEALD, combinations thereof, or the like. Subsequently, one or more dry etch processes are performed to etch the passivation layer 144 and the oxide layer 146 and expose portions of the top electrode 136. In some embodiments, the one or more dry etch processes are anisotropic etch processes and remove horizontal portions of the oxide layer 146. The remaining portions of passivation layer 142, passivation layer 144, and oxide layer 146 form spacers 140. The IMD layer 108 in the logic region 50L is exposed after patterning the spacers 140.

In fig. 14, IMD layer 150 is formed over spacer 140, MRAM cell 58, and IMD layer 108. IMD layer 150 is disposed on and around spacer 140 and is disposed on and around top electrode 136 and top electrode 136. In some embodiments, IMD layer 150 is formed using similar materials and methods as IMD layer 108. An anti-reflection layer 152 is then formed on the IMD layer 150. The anti-reflective layer 152 may be a nitrogen-free anti-reflective layer (NFARL) and may be formed of a nitrogen-free dielectric material (e.g., silicon oxycarbide). The IMD layer 150 and anti-reflective layer 152 will be used to protect the memory region 50M during subsequent processing of the logic region 50L.

In fig. 15, the anti-reflection layer 152, the IMD layer 150, and the IMD layer 108 are patterned to expose the etch stop layer 106 in the logic region 50L. In some embodiments, the patterning process may include suitable photolithography and etching processes. After the patterning process, the anti-reflection layer 152 and the portion of the IMD layer 150 located in the memory region 50M remain.

In fig. 16, an IMD layer 160 is formed over the etch stop layer 106 and the remaining portions of the anti-reflective layer 152, IMD layer 150, and IMD layer 108. The IMD layer 160 is adjacent to the IMD layers 108, 150. In some embodiments, IMD layer 160 is formed using similar materials and methods as IMD layer 108. An anti-reflection layer 162 is then formed on the IMD layer 160. In some embodiments, the anti-reflective layer 162 is formed using similar materials and methods as the anti-reflective layer 152.

In fig. 17, conductive features 164 are formed in IMD layer 160 and etch stop layer 106. The conductive feature 164 may include a conductive line 164L and a conductive via 164V, and is formed in the logic region 50L. The memory region 50M may be devoid of the conductive features 164. The conductive features 164 may be formed by a suitable method, such as a damascene process. Example damascene processes include single damascene processes, dual damascene processes, and the like. In some embodiments, the opening for the conductive feature 164 is formed by a via-first process (via-first process). In other embodiments, the opening for the conductive feature 164 is formed by a trench-first process. Suitable photolithography and etching techniques may be used to form the openings. The openings are then filled with a suitable conductive material (e.g., copper, aluminum, combinations thereof, etc.). Next, a planarization process (e.g., a CMP process) is performed to remove excess material over the memory region 50M and expose the top electrode 136. In some embodiments, the top surface of the top electrode 136 is coplanar with the top surface of the conductive feature 164 after planarization. In some embodiments, the planarization process completely removes the anti-reflective layer 162 (see fig. 16). Although each conductive via 164V and corresponding conductive line 164L are shown as separate elements, it should be understood that each conductive via 164V and corresponding conductive line 164L may be a continuous conductive feature in embodiments where they are formed by a dual damascene process, for example.

In fig. 18, another metallization layer of the interconnect structure is formed (e.g., M6, see fig. 2). The metallization layers include an etch stop layer 170, an IMD layer 172, and a conductive feature 174. Conductive feature 174 includes a conductive via 174V (which may correspond to metal via V6, see fig. 2) and a conductive line 174L (which may correspond to metal line L6, see fig. 2). Conductive features 174 are formed in both logic region 50L and memory region 50M. In some embodiments, etch stop layer 170 is formed using similar materials and methods as etch stop layer 106. In some embodiments, IMD layer 172 is formed using similar materials and methods as IMD layer 160. In some embodiments, the conductive features 174 are formed using similar materials and methods as the conductive features 164. The conductive feature 174 is electrically coupled to a memory device (e.g., MRAM) formed in the memory region 50M and a logic device (e.g., logic circuit) formed in the logic region 50L. In particular, the conductive feature 174 is physically and electrically coupled to the conductive feature 164 and the top electrode 136. In some embodiments, the conductive features 174 electrically couple the memory device to the logic device. For example, the conductive features 174 may be used to electrically couple some of the conductive features 164 to some of the top electrodes 136, such as in the illustrated metallization layer or in another metallization layer. Although each conductive via 174V and corresponding conductive line 174L are shown as separate elements, it should be understood that each conductive via 174V and corresponding conductive line 174L may be a continuous conductive feature in embodiments where they are formed by a dual damascene process, for example.

Fig. 21 is a flow chart of an example method 400 for fabricating semiconductor device 50 according to some other embodiments. Method 400 includes steps 402, 404, 406, 408, 410, 418, which are similar to steps 202, 204, 206, 208, 210, 218, respectively, of method 200 (see fig. 19). In the present embodiment, capping layer 118F is also deposited in step 412 by multiple deposition and oxidation steps (see fig. 9A-9E), however ALD is deposited instead of DC sputtering. Specifically, in step 414, an ALD module is used to deposit a pure magnesium sublayer. Next, in step 416, the deposited magnesium sub-layer is oxidized in the ALD module to form a magnesium oxide layer. Steps 414 and 416 may be repeated until the magnesium oxide layer reaches a desired thickness, thereby forming cap layer 118F. Depositing the magnesium sub-layer by ALD in step 414 may provide a final thickness T for cap layer 118F₂(see fig. 8).

Embodiments may realize advantages. Tong (Chinese character of 'tong')Repeating the deposition and oxidation to form the cap layer 118F allows the cap layer 118F to be formed of magnesium oxide with a high concentration of oxygen. In some embodiments, cap layer 118F may be fully magnesium oxide. Forming cap layer 118F of full magnesium oxide allows for an increase in the Perpendicular Magnetic Anisotropy (PMA) of the resulting MTJ element 134, thereby increasing the high resistance (R) of MRAM cell 58_AP) And low resistance (R)_P) The relative change in resistance between states. Thus, the Write Error Rate (WER) and Read Error Rate (RER) of MRAM cell 58 may be improved.

In an embodiment, a device comprises: a substrate including an active device; a first inter-metal dielectric (IMD) layer; a first conductive feature extending through the first IMD layer, the first conductive feature being electrically coupled to the active device; a bottom electrode over the first conductive feature; a magnetic tunnel junction element comprising: a reference layer located over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer comprising magnesium oxide; a free layer located over the tunnel barrier layer; and a capping layer over the free layer, the capping layer comprising magnesium oxide, the magnesium oxide of the capping layer being more oxidized than the magnesium oxide of the tunnel barrier layer; a top electrode over the cap layer; a second IMD layer over the top electrode; and a second conductive feature extending through the second IMD layer, the second conductive feature contacting the top electrode.

In some embodiments, the device further comprises: a spacer surrounding the bottom electrode and the magnetic tunnel junction element; and a third IMD layer surrounding the spacer and the top electrode; a fourth IMD layer adjacent to the first IMD layer and the third IMD layer; and a third conductive feature extending through the fourth IMD layer, the third conductive feature electrically coupled to the active device. In some embodiments of the device, the tunnel barrier layer has an equal concentration of magnesium atoms and oxygen atoms. In some embodiments of the device, the ratio of oxygen to magnesium in the tunnel barrier layer is in the range of 0.95 to 1.05, and the tunnel barrier layer has a thickness in the range of 0.6nm to 1.2 nm. In some embodiments of the device, the capping layer has a higher atomic concentration of oxygen than the atomic concentration of magnesium. In some embodiments of the device, the ratio of oxygen to magnesium in the capping layer is in the range of 1.0 to 1.2, and the capping layer has a thickness in the range of 0.4nm to 1.0 nm.

In an embodiment, a device comprises: a magnetoresistive random access memory cell, comprising: a bottom electrode; a reference layer located over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer comprising a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a coercivity less than the reference layer; a capping layer located over the free layer, the capping layer comprising a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a higher atomic concentration of oxygen and a smaller atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode located over the cap layer.

In some embodiments, the device further comprises: a row decoder; word lines electrically coupling the row decoder to the bottom electrodes; a row decoder; and a bit line electrically coupling the column decoder to the top electrode. In some embodiments of the device, the first composition of magnesium and oxygen has equal atomic concentrations of magnesium and oxygen, wherein the second composition of magnesium and oxygen has an atomic concentration of oxygen that is higher than the atomic concentration of magnesium. In some embodiments of the device, the ratio of oxygen to magnesium in the tunnel barrier layer is in the range of 0.95 to 1.05 and has a thickness in the range of 0.6nm to 1.2 nm. In some embodiments of the device, the ratio of oxygen to magnesium in the capping layer is in the range of 1.0 to 1.2 and has a thickness in the range of 0.4nm to 1.0 nm. In some embodiments of the device, the capping layer has a more uniform oxygen concentration than the tunnel barrier layer.

In an embodiment, a method comprises: forming a bottom electrode layer over a substrate; forming a ground layer over the bottom electrode layer; forming a seed layer over the ground layer; forming a reference layer over the seed layer; sputtering magnesium oxide by Radio Frequency (RF) sputtering to form a tunnel barrier layer over the reference layer; forming a free layer over the tunnel barrier layer; forming a capping layer over the free layer by repeating deposition and oxidation of magnesium; forming a top electrode layer over the cap layer; and patterning the top electrode layer, the cap layer, the free layer, the tunnel barrier layer, the reference layer, the seed layer, the ground layer, and the bottom electrode layer to form the magnetoresistive random access memory cell.

In some embodiments of the method: a bottom electrode layer, a ground layer, and a seed layer are formed in a first multi-target DC sputtering module; a reference layer is formed in the second multi-target DC sputtering module; a tunnel barrier layer is formed in the dual target RF sputtering module; the free layer is formed in a third multi-target DC sputtering module; the cap layer is formed in a single target DC sputtering module; and a top electrode layer is formed in the fourth multi-target DC sputtering module. In some embodiments, the method further comprises: a metal adhesion process is performed in the dual target RF sputtering module prior to forming the tunnel barrier layer. In some embodiments of the method, forming the capping layer comprises: depositing a first magnesium sublayer on the free layer, the first magnesium sublayer having a first thickness in a range of 0.2nm to 0.4 nm; flowing oxygen over the first magnesium sublayer at a first flow rate in a range of 8sccm to 40sccm for a first duration in a range of 10 seconds to 40 seconds; depositing a second magnesium sublayer on the first magnesium sublayer, the second magnesium sublayer having a second thickness in a range of 0.08nm to 0.24 nm; and flowing oxygen over the second magnesium sublayer at a second flow rate in a range of 1sccm to 20sccm for a second duration in a range of 10 seconds to 40 seconds; depositing a third magnesium sublayer on the second magnesium sublayer, the third magnesium sublayer having a third thickness, the third thickness being in a range of 0.08nm to 0.24 nm; flowing oxygen over the third magnesium sublayer at a third flow rate in a range of 1sccm to 20sccm for a third duration in a range of 10 seconds to 40 seconds; depositing a fourth magnesium sublayer on the third magnesium sublayer, the fourth magnesium sublayer having a fourth thickness, the fourth thickness being in a range of 0.08nm to 0.24 nm; flowing oxygen over the fourth magnesium sublayer at a fourth flow rate in a range of 100sccm to about 1000sccm for a fourth duration in a range of 10 seconds to 40 seconds; and depositing a fifth magnesium sublayer over the fourth magnesium sublayer. In some embodiments of the method, each of the first, second, third, fourth, and fifth magnesium sublayers are deposited by Direct Current (DC) sputtering. In some embodiments of the method, each of the first, second, third, fourth, and fifth magnesium sublayers is deposited by Atomic Layer Deposition (ALD). In some embodiments of the method, each of the first, second, third, fourth, and fifth magnesium sublayers are deposited and oxidized in the same module without breaking the vacuum in the module between each deposition and flow step. In some embodiments of the method, the fourth flow rate is greater than each of the first, second, and third flow rates, wherein the fourth duration is greater than each of the first, second, and third durations.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is a semiconductor device including: a substrate including an active device; a first inter-metal dielectric IMD layer; a first conductive feature extending through the first IMD layer, the first conductive feature being electrically coupled to the active device; a bottom electrode over the first conductive feature; a magnetic tunnel junction element comprising: a reference layer located over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer comprising magnesium oxide; a free layer located over the tunnel barrier layer; and a capping layer over the free layer, the capping layer comprising magnesium oxide, the magnesium oxide of the capping layer being more oxidized than the magnesium oxide of the tunnel barrier layer; a top electrode located over the cap layer; a second IMD layer over the top electrode; and a second conductive feature extending through the second IMD layer, the second conductive feature contacting the top electrode.

Example 2 is the device of example 1, further comprising: a spacer surrounding the bottom electrode and the magnetic tunnel junction element; and a third IMD layer surrounding the spacer and the top electrode; a fourth IMD layer adjacent to the first IMD layer and the third IMD layer; and a third conductive feature extending through the fourth IMD layer, the third conductive feature electrically coupled to the active device.

Example 3 is the device of example 1, wherein the tunnel barrier layer has an equal concentration of magnesium atoms and oxygen atoms.

Example 4 is the device of example 1, wherein a ratio of oxygen to magnesium in the tunnel barrier layer is in a range of 0.95 to 1.05, and the tunnel barrier layer has a thickness in a range of 0.6nm to 1.2 nm.

Example 5 is the device of example 1, wherein the cap layer has a higher atomic concentration of oxygen than magnesium.

Example 6 is the device of example 1, wherein a ratio of oxygen to magnesium in the capping layer is in a range of 1.0 to 1.2, and the capping layer has a thickness in a range of 0.4nm to 1.0 nm.

Example 7 is a semiconductor device, including: a magnetoresistive random access memory cell, comprising: a bottom electrode; a reference layer located over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer comprising a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lower coercivity than the reference layer; a capping layer located over the free layer, the capping layer comprising a second composition of magnesium and oxygen having a higher concentration of oxygen atoms and a smaller concentration of magnesium atoms than the first composition of magnesium and oxygen; and a top electrode located over the cap layer.

Example 8 is the device of example 7, further comprising: a row decoder; word lines electrically coupling the row decoder to the bottom electrodes; a row decoder; and a bit line electrically coupling the column decoder to the top electrode.

Example 9 is the device of example 7, wherein the first composition of magnesium and oxygen has equal atomic concentrations of magnesium and oxygen, and wherein the second composition of magnesium and oxygen has an atomic concentration of oxygen that is higher than the atomic concentration of magnesium.

Example 10 is the device of example 7, wherein a ratio of oxygen to magnesium in the tunnel barrier layer is in a range of 0.95 to 1.05, and has a thickness in a range of 0.6nm to 1.2 nm.

Example 11 is the device of example 7, wherein a ratio of oxygen to magnesium in the cap layer is in a range of 1.0 to 1.2, and has a thickness in a range of 0.4nm to 1.0 nm.

Example 12 is the device of example 7, wherein the cap layer has a more uniform oxygen concentration than the tunnel barrier layer.

Example 13 is a method for forming a semiconductor device, comprising: forming a bottom electrode layer over a substrate; forming a ground layer over the bottom electrode layer; forming a seed layer over the ground layer; forming a reference layer over the seed layer; sputtering magnesium oxide by radio frequency RF sputtering, forming a tunnel barrier layer over the reference layer; forming a free layer over the tunnel barrier layer; forming a capping layer over the free layer by repeating deposition and oxidation of magnesium; forming a top electrode layer over the cap layer; and patterning the top electrode layer, the capping layer, the free layer, the tunnel barrier layer, the reference layer, the seed layer, the ground layer, and the bottom electrode layer to form a magnetoresistive random access memory cell.

Example 14 is the method of example 13, wherein: the bottom electrode layer, the ground layer, and the seed layer are formed in a first multi-target DC sputtering module; the reference layer is formed in a second multi-target DC sputtering module; the tunnel barrier layer is formed in a dual target RF sputtering module; the free layer is formed in a third multi-target DC sputtering module; the capping layer is formed in a single target DC sputtering module; and the top electrode layer is formed in a fourth multi-target DC sputtering module.

Example 15 is the method of example 14, further comprising: performing a metal adhesion process in the dual target RF sputtering module prior to forming the tunnel barrier layer.

Example 16 is the method of example 15, wherein forming the cap layer comprises: depositing a first magnesium sublayer on the free layer, the first magnesium sublayer having a first thickness in a range of 0.2nm to 0.4 nm; flowing oxygen over the first magnesium sublayer at a first flow rate in a range of 8sccm to 40sccm for a first duration in a range of 10 seconds to 40 seconds; depositing a second magnesium sub-layer on the first magnesium sub-layer, the second magnesium sub-layer having a second thickness, the second thickness being in a range of 0.08nm to 0.24 nm; and flowing oxygen over the second magnesium sublayer at a second flow rate in a range of 1sccm to 20sccm for a second duration in a range of 10 seconds to 40 seconds; depositing a third magnesium sub-layer on the second magnesium sub-layer, the third magnesium sub-layer having a third thickness, the third thickness being in a range of 0.08nm to 0.24 nm; flowing oxygen over the third magnesium sublayer at a third flow rate in a range of 1sccm to 20sccm for a third duration in a range of 10 seconds to 40 seconds; depositing a fourth magnesium sub-layer on the third magnesium sub-layer, the fourth magnesium sub-layer having a fourth thickness, the fourth thickness being in a range of 0.08nm to 0.24 nm; flowing oxygen over the fourth magnesium sublayer at a fourth flow rate in a range of 100sccm to about 1000sccm for a fourth duration in a range of 10 seconds to 40 seconds; and depositing a fifth magnesium sublayer on the fourth magnesium sublayer.

Example 17 is the method of example 16, wherein each of the first, second, third, fourth, and fifth magnesium sublayers are deposited by Direct Current (DC) sputtering.

Example 18 is the method of example 16, wherein each of the first, second, third, fourth, and fifth magnesium sublayers are deposited by atomic layer deposition, ALD.

Example 19 is the method of example 16, wherein each of the first, second, third, fourth, and fifth magnesium sublayers are deposited and oxidized in a same module without breaking a vacuum in the module between each deposition and flow step.

Example 20 is the method of example 16, wherein the fourth flow rate is greater than each of the first, second, and third flow rates, and wherein the fourth duration is greater than each of the first, second, and third durations.