阅读说明：本技术 用于逻辑到物理映射的双重地址编码 (Dual address encoding for logical to physical mapping ) 是由 G·卡列洛 J·S·帕里 于 2021-04-29 设计创作，主要内容包括：本申请涉及用于逻辑到物理映射的双重地址编码。存储器器件能够标识对应于由主机器件生成的第一逻辑块地址的第一物理地址以及对应于由主机器件生成的第二(连续的)逻辑块地址的第二物理地址。所述存储器器件能够将对应于所述第一逻辑块地址的所述第一物理地址和所述第二物理地址存储在逻辑到物理映射表的单个条目中。所述存储器器件能够将所述逻辑到物理表传输到所述主机器件以存储在所述主机器件处。所述主机器件随后能够基于所述逻辑到物理表将包含所述第一物理地址和所述第二物理地址的单个读取命令传输到所述存储器器件。(The application relates to dual address encoding for logical to physical mapping. The memory device is capable of identifying a first physical address corresponding to a first logical block address generated by the host device and a second physical address corresponding to a second (consecutive) logical block address generated by the host device. The memory device is capable of storing the first physical address and the second physical address corresponding to the first logical block address in a single entry of a logical-to-physical mapping table. The memory device is capable of transmitting the logical-to-physical table to the host device for storage at the host device. The host device is then able to transmit a single read command including the first physical address and the second physical address to the memory device based on the logical-to-physical table.)

1. A memory device, comprising:

an array of memory cells; and

a controller coupled with the memory cell array and operable to cause the memory device to:

receiving a read command from a host device, the read command comprising:

a first physical address of the memory device corresponding to a first logical block address generated by the host device; and

a second physical address of the memory device corresponding to a second logical block address generated by the host device;

retrieving a first page of data from the first physical address of the memory device and retrieving a second page of data from the second physical address of the memory device; and is

Transmitting the first page data and the second page data to the host device based at least in part on retrieving the first page data and the second page data.

2. The memory device of claim 1, wherein the read command includes an indication of a data transfer length, and wherein a combined length of the first page data and the second page data is associated with the data transfer length.

3. The memory device of claim 1, wherein the controller is further operable to cause the memory device to:

transmitting, to the host device, a set of entries mapping a set of logical block addresses to a corresponding set of physical addresses prior to receiving the read command, wherein a first entry of the set of entries includes the first physical address and the second physical address, and a second entry of the set of entries includes the second physical address and a third physical address corresponding to a third logical block address.

4. The memory device of claim 3, wherein each entry of the set of entries is 8 bytes in length.

5. The memory device of claim 3, wherein the controller is further operable to cause the memory device to:

receiving, at the memory device, a write command comprising the first logical block address from the host device prior to transmitting the set of entries, wherein the write command is associated with writing the first page of data to the memory device; and is

Writing the first page of data to the memory device at the first physical address corresponding to the first logical block address based at least in part on the write command.

6. The memory device of claim 5, wherein the controller is further operable to cause the memory device to:

storing the first entry of the set of entries at the memory device based at least in part on writing the first page data to the memory device at the first physical address and writing the second page data to the memory device at the second physical address.

7. The memory device of claim 1, wherein the first physical address and the second physical address are contained within 8 bytes of the read command.

8. The memory device of claim 1, wherein the read command comprises the first logical block address.

9. The memory device of claim 1, wherein the first logical block address and the second logical block address are consecutive logical block addresses.

10. The memory device of claim 1, wherein the first physical address and the second physical address are non-consecutive physical addresses.

11. A method performed by a memory device, the method comprising:

receiving a read command from a host device, the read command comprising:

a first physical address of the memory device corresponding to a first logical block address generated by the host device; and

a second physical address of the memory device corresponding to a second logical block address generated by the host device;

retrieving a first page of data from the first physical address of the memory device and retrieving a second page of data from the second physical address of the memory device; and

transmitting the first page data and the second page data to the host device based at least in part on retrieving the first page data and the second page data.

12. The method of claim 11, wherein the read command includes an indication of a data transfer length, and wherein a combined length of the first page data and the second page data is associated with the data transfer length.

13. The method of claim 11, further comprising:

transmitting, to the host device, a set of entries mapping a set of logical block addresses to a corresponding set of physical addresses prior to receiving the read command, wherein a first entry of the set of entries includes the first physical address and the second physical address, and a second entry of the set of entries includes the second physical address and a third physical address associated with a third logical block address.

14. The method of claim 13, wherein each entry of the set of entries is 8 bytes in length.

15. The method of claim 11, further comprising:

receiving, at the memory device, a write command comprising the first logical block address from the host device prior to receiving the read command, wherein the write command is associated with writing the first page of data to the memory device; and

writing the first page of data to the memory device at the first physical address associated with the first logical block address based at least in part on the write command.

16. The method of claim 15, further comprising:

storing a first entry of a set of entries at the memory device based at least in part on writing the first page data to the memory device at the first physical address and writing the second page data to the memory device at the second physical address.

17. The method of claim 11, wherein the first physical address and the second physical address are contained within 8 bytes of the read command.

18. The method of claim 11, wherein the read command comprises the first logical block address.

19. The method of claim 11, wherein the first logical block address and the second logical block address are consecutive logical block addresses.

20. The method of claim 11, wherein the first physical address and the second physical address are non-contiguous physical addresses.

21. A memory device, comprising:

an array of memory cells; and

a controller coupled with the memory cell array and operable to cause the memory device to:

identifying a first logical block address associated with a first physical address of the memory device;

identifying a second logical block address associated with a second physical address of the memory device;

storing a first entry of a set of entries, the first entry including the first physical address and the second physical address, the first entry for mapping the first logical block address to the first physical address and the second physical address;

storing a second entry of the set of entries, the second entry including the second physical address and a third physical address associated with a third logical block address, the second entry for mapping the second logical block address to the second physical address and the third physical address; and is

Transmitting the set of entries to a host device.

22. The memory device of claim 21, wherein the controller is operable to store the first entry by:

retrieving the first physical address from a first memory region based at least in part on a value of a first pointer;

storing the first physical address in a first portion of the first entry;

increasing the value of the first pointer to a second value of the first pointer;

retrieving the second physical address from the first memory region based at least in part on the second value of the first pointer; and is

Storing the second physical address in a second portion of the first entry.

23. The memory device of claim 22, wherein the controller is further operable to:

storing the first physical address in a second memory region based at least in part on a first value of a second pointer;

increasing the first value of the second pointer to a second value of the second pointer; and is

Storing the second physical address in the second memory region based at least in part on the second value of the second pointer, wherein storing the second entry comprises storing the second physical address in the first portion of the second entry.

24. The memory device of claim 22, wherein the first portion of the first entry and the second portion of the first entry each have a size of four bytes.

25. The memory device of claim 21, wherein the controller is further operable to:

determining an error detection value associated with the first physical address and the second physical address, wherein the first entry includes the error detection value.

Technical Field

The technical field relates to dual address encoding for logical to physical mapping.

Background

The following generally relates to one or more memory systems and, more particularly, to dual address encoding for logical to physical mapping.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell can be programmed to one of two support states, typically represented by a logic 1 or a logic 0. To access the stored information, the component may read or read at least one storage state in the memory device. To store information, a component may write or program a state in a memory device.

There are various types of memory devices, including magnetic hard disks, Random Access Memories (RAMs), Read Only Memories (ROMs), dynamic RAMs (drams), synchronous dynamic RAMs (sdrams), ferroelectric RAMs (ferams), magnetic RAMs (mrams), resistive RAMs (rrams), flash memories, Phase Change Memories (PCMs), 3-dimensional cross point memories (3D xpoints), flash memories (such as floating gate flash memories and charge trap flash memories that may be used in NOR (NOR) or NAND (NAND) memory devices), and the like. The memory device may be volatile or non-volatile. Non-volatile memory cells, such as flash memory cells, can maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory cells, such as DRAM cells, may lose their stored state over time unless they are periodically refreshed by an external power source. Flash-based memory devices may have different performance compared to other non-volatile and volatile memory devices.

Disclosure of Invention

A memory device is described. The memory device may include an array of memory cells and a controller coupled to the array of memory cells. The controller may be operable to cause the memory device to: receiving a read command from a host device, the read command including a first physical address of the memory device corresponding to a first logical block address generated by the host device and a second physical address of the memory device corresponding to a second logical block address generated by the host device; retrieving a first page of data from the first physical address of the memory device and retrieving a second page of data from the second physical address of the memory device; and transmitting the first page data and the second page data to the host device based at least in part on retrieving the first page data and the second page data.

A method is described. The method may comprise: receiving a read command from a host device, the read command including a first physical address of the memory device corresponding to a first logical block address generated by the host device and a second physical address of the memory device corresponding to a second logical block address generated by the host device; retrieving a first page of data from the first physical address of the memory device and retrieving a second page of data from the second physical address of the memory device; and transmitting the first page data and the second page data to the host device based at least in part on retrieving the first page data and the second page data.

A memory device is described. The memory device may include an array of memory cells and a controller coupled to the array of memory cells. The controller may be operable to cause the memory device to: identifying a first logical block address associated with a first physical address of the memory device; identifying a second logical block address associated with a second physical address of the memory device; storing a first entry of a set of entries, the first entry including the first physical address and the second physical address, the first entry for mapping the first logical block address to the first physical address and the second physical address; storing a second entry of the set of entries, the second entry including the second physical address and a third physical address associated with a third logical block address, the second entry for mapping the second logical block address to the second physical address and the third physical address; and transmitting the set of entries to the host device.

Drawings

FIG. 1 shows an example of a memory device supporting dual address encoding for logical to physical mapping according to examples disclosed herein.

FIG. 2 shows an example of a NAND circuit supporting dual address encoding for logical-to-physical mapping in accordance with examples disclosed herein.

FIG. 3 illustrates an example of a system that supports dual address encoding for logical to physical mapping in accordance with examples disclosed herein.

FIG. 4 illustrates an example of a set of entries supporting dual address encoding for logical to physical mapping in accordance with examples disclosed herein.

FIG. 5 illustrates an example of a process to support dual address encoding for logical to physical mapping in accordance with examples disclosed herein.

FIG. 6 illustrates a block diagram of a memory device that supports dual address encoding for logical to physical mapping according to examples disclosed herein.

Fig. 7 and 8 illustrate flow diagrams that demonstrate one or more methods of supporting dual address encoding for logical-to-physical mapping in accordance with examples disclosed herein.

Detailed Description

Flash memory is typically organized into pages and blocks, where each block contains multiple pages. Flash memory cells can be read and written at a page level of granularity, but can be erased at a block level of granularity. In some cases, a flash memory cell may be erased before it can be overwritten with new data. Thus, when a flash memory device updates a page of data (e.g., in response to a command from a host device), the memory device may write new data to a different page and mark old pages as obsolete, rather than erasing a block of memory and rewriting pages in the block.

The memory device may receive commands from the host device, such as read commands and write commands for reading or writing data. For write operations, the host device may reference the location of data stored in the memory device using Logical Block Addresses (LBAs) that map to physical addresses of memory pages of the memory device where the data is stored. Because the physical addresses of data may change (e.g., when data is updated by writing updated data to a different page), some memory devices maintain one or more logical-to-physical (L2P) tables that map LBAs generated by a host device to corresponding physical addresses of pages in the memory device. In this way, the host device can use the same LBA to request data to be read from the memory device even though the data has been moved to a different physical address of the memory device.

In some cases, each entry in the L2P table may contain a single physical address that points to a page of data stored in the memory device. Since L2P entries may be updated frequently as data is written, overwritten, moved, etc., the L2P table is typically stored in DRAM or other memory components associated with flash memory (supporting relatively fast reads and writes).

However, for memory devices with large memory capacities, the L2P table may be too large to store on the memory device itself. In addition, some memory devices, such as universal flash memory (UFS) devices, may lack on-chip DRAM for storing and updating the L2P tables. Thus, some memory devices may use memory resident on the host device (e.g., host DRAM) to store the L2P mapping table, rather than storing such tables locally. In such cases, during a read operation, the host device may generate an LBA and look up the corresponding physical address in the L2P table, and then include the physical address in a read command to the memory device (e.g., rather than the memory device looking up the physical address based on the LBA received in the command from the host device).

In some cases, each entry in the L2P table may contain a single physical address that points to a single page of memory. Thus, reading more than one page of data may use multiple accesses to the L2P table to retrieve multiple physical addresses, potentially increasing read latency. In some cases, the host device may read multiple pages of logically contiguous data-that is, data stored for contiguous LBAs (but not necessarily at contiguous physical addresses). For example, analysis of the usage of handset data shows that approximately 50% of the random read traffic consists of single page reads, and the remaining 50% consists of multiple page reads.

As described herein, to reduce latency associated with reading multiple pages of data, a memory device may encode (e.g., pack, store) multiple physical addresses corresponding to multiple consecutive LBAs into a single entry of an L2P table. The host may retrieve this entry of the L2P table based on the first LBA of the entry, and may include multiple physical addresses (which may be non-consecutive physical addresses) of a single entry in a single read command sent to the memory device. The host device may also include an indication of the data transfer size (e.g., the number of pages or bytes to be read from the memory device) in the read command to indicate to the memory device how many or less physical addresses are included in the read command. The memory device may read data from a plurality of physical addresses and transmit the data to the host device based on receiving the read command.

To enable access to each individual LBA and corresponding physical address in the L2P table, in some cases, the memory device may repeat the physical address in an individual entry of the L2P table when generating the L2P table. For example, a first entry of the L2P table may contain a first physical address corresponding to LBA1 and a second physical address corresponding to LBA 2. The second entry of the L2P table may contain (e.g., duplicate) a second physical address corresponding to LBA 2 and a third physical address corresponding to LBA 3. In this way, the host device may be able to access each LBA separately while also being able to retrieve two (or more) physical addresses from a single entry. In some cases, this L2P table may also contain L2P entries containing a single physical address, thereby maintaining backward compatibility with earlier systems.

The features of the present disclosure are first described in the context of a NAND circuit and a memory device as described with reference to fig. 1 and 2. The features of the present disclosure are further described in the context of a system, a set of entries of a double encoded L2P table, and an algorithm for generating a double encoded L2P table as described with reference to fig. 3-5. These and other features of the present disclosure are further illustrated by, and described with reference to, the apparatus diagrams and flow diagrams associated with dual address encoding for L2P mapping as described with reference to fig. 6-8.

Fig. 1 shows an example of a memory die 100 according to examples as disclosed herein. In some cases, memory die 100 may be referred to as a Universal Flash Storage (UFS) device, a solid state storage device, a managed memory device, a memory chip, or an electronic memory device. Memory die 100 may include one or more memory cells, such as memory cell 105-a and memory cell 105-b (other memory cells not labeled). The memory cells 105 may be, for example, flash memory cells (as depicted in the enlarged view of memory cell 105-a shown in fig. 1), DRAM memory cells, FeRAM memory cells, PCM memory cells, or another type of memory cells.

Each memory cell 105 may be programmed to store a logic state representing one or more bits of information. Different memory cell architectures may store logic states in different ways. In a FeRAM architecture, for example, each memory cell 105 may include a capacitor that includes a ferroelectric material for storing a charge and/or polarization representing a programmable state. In a DRAM architecture, each memory cell 105 may contain a capacitor that contains a dielectric material (e.g., an insulator) for storing a charge representing a programmable state. In a flash memory architecture, each memory cell 105 may contain a transistor having a floating gate and/or dielectric material for storing charge representing a logic state. For example, an enlarged view of memory cell 105-a is a flash memory cell that includes a transistor 110 (e.g., a Metal Oxide Semiconductor (MOS) transistor) that may be used to store a logic state. Transistor 110 has a control gate 115 and may include a floating gate 120 sandwiched between dielectric materials 125. The transistor 110 includes a first node 130 (e.g., source or drain) and a second node 135 (e.g., drain or source). A logic state may be stored in the transistor 110 by placing (e.g., writing, storing) an amount of electrons (e.g., charge) on the floating gate 120. The amount of charge to be stored on the floating gate 120 may depend on the logic state to be stored. The charge stored on floating gate 120 may affect the threshold voltage of transistor 110 and, thus, the amount of current that may flow through transistor 110 when transistor 110 is activated. The logic state stored in the transistor 110 can be read by applying a voltage to the control gate 115 (e.g., at the control node 140) to activate the transistor 110 and measure (e.g., detect, sense) the final amount of current flowing between the first node 130 and the second node 135.

For example, the sense component 170 may determine the logic state stored on the flash memory cell based on the presence or absence of current from the memory cell, or based on whether the current is above or below a threshold current. Similarly, a flash memory cell may be written by applying a voltage (e.g., a voltage above a threshold or a voltage below a threshold) to the memory cell to store (or not store) a charge on the floating gate that represents one of the possible logic states.

The charge trapping flash memory cell may operate in a manner similar to the operation of a floating gate flash memory cell, but rather than (or in addition to) storing charge on the floating gate 120, it may store charge representing states in the dielectric material under the control gate 115. Thus, a charge trapping flash memory cell may or may not include a floating gate 120.

In some examples, each row of memory cells 105 is connected to a word line 160 and each column of memory cells 105 is connected to a digit line 165. Thus, one memory cell 105 may be located at the intersection of word line 160 and digit line 165. This intersection may be referred to as the address of the memory cell. Digit lines are sometimes referred to as bit lines. In some cases, word line 160 and digit line 165 can be substantially perpendicular to each other, and can create an array of memory cells 105 (e.g., in a memory array). In some cases, word line 160 and digit line 165 may be referred to generally as an access line or a select line.

In some cases, memory die 100 may include a three-dimensional (3D) memory array, where multiple two-dimensional (2D) memory arrays are formed on top of each other. This may increase the number of memory cells that may be placed or created on a single die or substrate as compared to a 2D array, which in turn may reduce production costs or improve performance of the memory array, or both. In the example of fig. 1, memory die 100 includes multiple levels of memory arrays. In some examples, the levels may be separated by electrically insulating material. Each level may be aligned or positioned such that memory cells 105 may be aligned (precisely, overlapping, or approximately) with each other across each level, forming memory cell stack 175. In some cases, memory cell stack 175 may be referred to as a memory cell string, which is discussed in more detail with reference to fig. 3.

Access to memory cells 105 may be controlled by a row decoder 145 and a column decoder 150. For example, row decoder 145 may receive a row address from memory controller 155 and activate the appropriate word line 160 based on the received row address. Similarly, column decoder 150 may receive a column address from memory controller 155 and activate the appropriate digit line 165. Thus, a memory cell 105 can be accessed by activating a word line 160 and a digit line 165.

After access, memory cell 105 may be read or read by sense component 170. For example, the readout component 170 can be configured to determine a stored logic state of the memory cell 105 based on a signal generated by accessing the memory cell 105. The signal may comprise a voltage or a current or both, and the sensing component 170 may comprise a voltage sense amplifier, a current sense amplifier, or both. For example, a current or voltage may be applied to memory cell 105 (using corresponding word line 160 and/or digit line 165), and the magnitude of the resulting current or voltage on digit line 165 may depend on the logical state stored by memory cell 105. For example, for a flash memory cell, the amount of charge stored on the floating gate or in the insulating layer of the transistor in memory cell 105 may affect the threshold voltage of the transistor, thereby affecting the amount of current flowing through the transistor in memory cell 105 when accessing memory cell 105. Such current differences may be used to determine the logic state stored on memory cell 105.

Sense component 170 may include various transistors or amplifiers to detect and amplify signals (e.g., currents or voltages) on digit line 165. The detected logic state of memory cell 105 may then be output via input/output block 180. In some cases, the readout component 170 may be part of the column decoder 150 or row decoder 145, or the readout component 170 may be otherwise connected to or in electronic communication with the column decoder 150 or row decoder 145.

Memory cell 105 may be set or written by activating the associated word line 160 and digit line 165 in a similar manner to enable a logic state (e.g., representing one or more bits of information) to be stored in memory cell 105. Column decoder 150 or row decoder 145 may accept data to be written to memory cells 105, for example, from input/output block 180. As previously discussed, in the case of flash memory (such as flash memory for NAND and 3D NAND memory devices), memory cell 105 may be written by storing electrons in a floating gate or insulating layer.

The memory controller 155 may control the operation (e.g., read, write, rewrite, refresh, verify, erase) of the memory cells 105 through various components, such as the row decoder 145, the column decoder 150, and the sense component 170. In some cases, one or more of row decoder 145, column decoder 150, and readout component 170 can be co-located with memory controller 155. Memory controller 155 may generate row address signals and column address signals to activate desired word lines 160 and digit lines 165. Memory controller 155 may also generate and control various voltages or currents used during operation of memory die 100.

In some cases, memory controller 155 or another electronic component of memory die 100 may build (e.g., establish, generate, and/or maintain) one or more L2P tables for mapping LBAs generated by a host device to physical addresses in memory die 100 (e.g., addresses of physical pages in memory die 100 corresponding to LBAs). Memory die 100 may transmit such an L2P table to the host device, and the host device may store the L2P table for subsequent lookup access for read operations.

In some cases, memory die 100 may receive a read command from a host device that includes one or more physical addresses and an indication of a data transfer length. Memory die 100 may extract a physical address from the read command and may retrieve data from multiple physical addresses based on the read command. Memory die 100 may transmit the retrieved data to a host device.

Fig. 2 shows an example of a NAND circuit 200 supporting dual address encoding for logical-to-physical mapping in accordance with an example of the present disclosure. NAND circuit 200 may be an example of a portion of a memory device, such as memory die 100. Although some of the elements included in fig. 2 are labeled with reference numerals, other corresponding elements are not labeled, but are identical or are to be understood as being similar to increase the visibility and clarity of the depicted features.

NAND circuit 200 includes a plurality of flash memory cells 205 (which may be, for example, flash memory cells as described with reference to fig. 1) connected in a NAND configuration. In a NAND memory configuration (referred to as NAND memory), a plurality of flash memory cells 205 are connected in series with one another to form a string 210 of memory cells 205, where the drain of each flash memory cell 205 in the string 210 is coupled to the source of another flash memory cell 205 in the string. In some cases, flash memory cells connected in a NAND configuration to form a NAND memory may be referred to as NAND memory cells.

Each string 210 of memory cells 205 may be associated with a corresponding digit line 215 (e.g., digit lines 215-a, 215-b) shared by memory cells 205 in string 210. Each memory cell 205 in the string 210 may be associated with a separate word line 230 (e.g., word lines 230-a, 230-i, 230-n), such that the number of word lines 230 may equal the number of memory cells 205 in the string 210.

The NAND memory may be hierarchically organized into strings 210 containing multiple memory cells 205, pages 255 containing memory cells 205 connected to the same word line 230 (e.g., memory cells 205 from multiple strings 210), and blocks 260 containing multiple pages 255. The NAND memory cells can be erased before they can be rewritten. In some cases, the NAND memory may be written and read at the granularity of a page level (e.g., by activating the corresponding word line 230), but may not be erasable at the granularity of a page level. In some cases, in contrast, NAND memory may be erasable at a higher level of granularity (e.g., at a block level of granularity). Different memory devices may have different read/write/erase characteristics.

Each string 210 of memory cells 205 in the NAND circuit 200 is coupled with a drain Select Gate Device (SGD) transistor 220 at one end of the string 210 and a source select gate device (SGS) transistor 235 at the other end of the string 210. The SGD transistor 220 and the SGS transistor 235 may be used to couple the string 210 of memory cells 205 to the digit line 215 and/or to the source node 250 (e.g., source nodes 250-a, 250-b) by applying a voltage at the gate 245 of the SGD transistor 220 and/or at the gate 240 of the SGS transistor 235, respectively.

During a NAND memory operation, various voltage levels associated with the source node 250, the gate 240 of the SGS transistor 235 associated with the source node 250, the word line 230, the drain node 225, the gate 245 of the SGD transistor 220 associated with the drain node 225, and the digit line 215 may be applied to perform one or more operations (e.g., program, erase, or read) on at least some of the NAND memory cells in the string 210.

In some cases, during a read operation, a positive voltage may be applied to digit line 215 connected to drain node 225, while source node 250 may be connected to ground or virtual ground (e.g., approximately 0V). For example, the voltage applied to the drain node 225 may be 1V. At the same time, the voltage applied to gates 245 and 240 may be increased above the threshold voltage of the one or more SGS 235 associated with source node 250 and the one or more SGD 220 associated with drain node 225, such that the channel associated with string 210 may be electrically connected with drain node 225 and source node 250. A channel may be an electrical path through the memory cells 205 in the string 210 (e.g., through transistors in the memory cells 205) that may conduct current under certain operating conditions.

Meanwhile, a plurality of word lines 230 (e.g., word lines 230-a, 230-i, 230-n, or in some cases all word lines 230) other than the selected word line (i.e., the word lines associated with the unselected cells in the string 210) may be connected to a voltage (e.g., VREAD) that is higher than the highest threshold Voltage (VT) of the memory cells in the string 210. VREAD may turn on some or all of the unselected memory cells in string 210 so that each unselected memory cell may maintain high conductivity in its associated channel. In some examples, the word line 230 associated with the selected cell may be connected to a voltage VTarget. VTarget may be selected at a value between the VT of erased memory cells and the VT of programmed memory cells in string 210. When a selected memory cell exhibits an erased VT (e.g., VTarget > VT of the selected memory cell), the selected memory cell 205 may turn "on" in response to application of VTarget and thereby cause current to flow in the channel of the string 210 from the digit line 215 to the source 250. When the selected memory cell exhibits a programmed VT (e.g., so VTarget < VT of the selected memory cell), the selected memory cell may "turn off" in response to VTarget and thereby inhibit current from flowing in the channel of the string 210 from the digit line 215 to the source 250. The amount of current flow (or lack thereof) may be sensed by sensing component 170 as described with reference to fig. 1 to read information stored in selected memory cells 205 within a string 210.

Fig. 3 is an example of a system 300 that supports dual address encoding for logical to physical mapping in accordance with an example of the present disclosure. System 300 includes a host device 305 coupled to a memory device 310.

Memory device 310 may be a memory device, a memory module, or a mixture of memory devices and memory modules. Examples of storage devices include Solid State Drives (SSDs), flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, Universal Flash Storage (UFS) drives, and Hard Disk Drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

Host device 305 may use memory device 310 to store data in memory array 330 and to read data from memory array 330. The host device 305 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other vehicle), an internet of things (IoT) -enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment, or networked commercial device), or such a computing device containing memory and processing devices. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, fibre channel, serial attached scsi (sas), and the like.

Memory device 310 may include a memory device controller 325 and one or more memory dies 330 for storing data. In some examples, memory device controller 325 may be included in a controller die that is separate (e.g., different) from memory die 330 and may be packaged with memory die 330 in a single package (e.g., a package containing memory device 310).

Memory die 330 may be an example of memory die 100 described with reference to fig. 1, and may include, for example, a NAND memory array or other type of memory array for reading and writing data to host device 305.

In some examples, each memory die 330 in the memory device 310 may contain a local memory controller that may be responsible for organizing lower level operations (e.g., activating row and column drivers) during read operations, write operations, verify operations, erase operations, or other operations that may be performed on the memory array of the memory die 330, as described with reference to the memory controller 155 of fig. 1.

In some examples, memory device controller 325 may communicate with each of the local memory controllers (e.g., memory controller 155) of the respective memory die 330 to direct the memory die 330 to perform memory operations. Memory device controller 325 may also handle some higher level operations of memory device 310, such as garbage collection or other operations. In some examples, the term "controller" as used herein may refer to memory device controller 325, local memory controller 155, or a combination thereof.

In some cases, memory device 310 may also contain Static Random Access Memory (SRAM) memory 340 or other types of memory that may be used by memory device 310 for, for example, internal storage or computation. Access to SRAM memory 340 may be faster than access to a memory array (e.g., a NAND memory array) in memory die 330, and therefore it is desirable to use SRAM memory 340 to store and update the L2P table. In some instances, however, the SRAM memory 340 may be integrated with the memory device controller 325 on a single die, which may limit the size of the SRAM memory 340 (e.g., due to cost or other limiting factors associated with the memory device controller 325). Thus, in some instances, the size of SRAM memory 340 may be smaller than the size of the L2P table used by memory device 310, and may therefore be insufficient to store L2P mapping information. Thus, in some instances, rather than storing L2P tables locally on memory die 330, memory device 310 may generate and transmit an L2P mapping table to host device 305 for storage. As described in more detail with reference to fig. 5, in some examples, SRAM memory 340 may be used by memory device 310 to establish one or more L2P tables, which may be transferred to host device 305 for storage.

The host device 305 includes a host controller interface 320. Host controller interface 320 may provide an interface for passing control, address, data, and other signals between host device 305 and memory device 310. Host device 305 may transmit memory access commands (such as read or write commands) to memory device 310 using host controller interface 320.

Memory device controller 325 may receive signals from host device 305 via host controller interface 320 and may cause memory device 310 to perform certain operations in response to receiving such signals. For example, memory device controller 325 may receive a read or write command from host device 305 and, in response, may cause memory device 310 to read data or write data to memory die 330 based on the received command.

The host device 305 includes host memory 315, which may include one or more types of volatile or non-volatile memory. For example, host memory 315 may comprise SRAM, DRAM, flash, or other types of memory.

In some examples, memory device 310 may establish and maintain one or more sets of entries (e.g., an L2P lookup table) for mapping LBAs generated by host device 305 to physical addresses (e.g., page addresses) of memory die 330. Such a set of entries may be generated based on receiving one or more write commands from the host device 305 that include LBAs for writing data. Each entry in the L2P table may contain one or more physical addresses corresponding to one or more LBAs in one or more write commands. In some cases, memory device 310 may transmit such a set of entries to host device 305 such that the set of entries (the L2P table) is stored in host memory 315. For example, the memory device controller 325 may transmit such a set of entries to the host device 305 (e.g., via the host controller interface 320).

The memory device 310 may contain an accelerator 345 for building a set of entries. In some cases, some or all of the accelerators 345 may be hardware accelerators configured to perform dedicated functions in the memory device 310. In some cases, some or all of the accelerators 345 may be implemented in hardware, software, firmware, or a combination thereof that is executed by the memory device controller 325, or by a local memory controller of the memory die 330, or by another component of the memory device 310, or by some combination of these.

In some instances, the entries in the set of entries may be ordered in order by LBA index. That is, the first entry in the set of entries may correspond to LBA 0, the second (consecutive) entry in the set of entries may correspond to LBA1, the third entry may correspond to LBA 2, and so on. In some examples, memory device 310 may encode (e.g., pack, store) two or more physical addresses (e.g., corresponding to two or more consecutive LBAs) into a single entry of a set of entries. For example, if memory device 310 receives multiple write commands from host device 305 specifying consecutive (e.g., LBAs having numerically consecutive, contiguous indices) LBAs, memory device 310 may determine (e.g., select, identify) multiple corresponding physical addresses to which to write data, and may store a single entry containing the multiple physical addresses in a set of entries.

When host device 305 reads data from memory device 310, host device 305 may identify one or more LBAs for the data to be read and may look up the corresponding physical addresses in a set of entries residing in host memory 315. The host device 305 may transmit a read command to the memory device 310 that includes an indication of one or more physical addresses, LBAs, and data transfer lengths based on looking up an entry in the set of entries (e.g., whether a read operation is a 4kB read or an 8kB read). Memory device 310 may then retrieve the data at the one or more physical addresses specified in the read command and transmit the retrieved data to host device 305. For example, the host device 305 may transmit a read command that contains a first physical address corresponding to a first LBA and a second physical address corresponding to a second (contiguous) LBA. The read command may contain an indication that the data transfer length is two (e.g., two pages); for example, a read command contains an indication of two physical addresses for a data transfer length of two pages. Memory device 310 may retrieve a first portion of data from a first physical address and a second portion of data from a second physical address and transfer the first portion of data and the second portion of data to host device 305. The combined length of the first portion of data and the second portion of data may be associated with (e.g., equal to or correspond to) the indicated data transfer length. For example, if the indicated data transfer length is two, the combined length of the first portion of data and the second portion of data may be two pages (e.g., 8kB for a memory device having 4kB pages).

FIG. 4 illustrates an example of a set of entries 400 that support dual address encoding for logical to physical mapping in accordance with examples disclosed herein. Entry set 400 may represent an L2P table generated by a memory device (e.g., memory device 310) for mapping LBAs to physical addresses. In some cases, the set of entries 400 may be generated by a memory device, transmitted to a host device, such as the host device 305 described with reference to fig. 3, and stored in memory residing on the host device.

In some cases, the memory device may generate the entry set 400 based on receiving a plurality of write commands from the host device specifying a plurality of consecutive LBAs (e.g., LBA1, LBA 2, LBA 3, etc.) for writing data to the memory device. Based on receiving the write command, the memory device may select a physical address for writing data, write the data to the physical address, and generate one or more entries in the set of entries 400 that map the LBAs generated by the host device to the corresponding physical addresses at which the data was written. The entries in entry set 400 may be ordered by the index of the LBA; for example, a first entry associated with LBA 0, a second entry associated with LBA1, etc. The physical addresses corresponding to LBAs and stored in entry set 400 may be non-contiguous. In some cases, the memory device may contain an accelerator for more efficiently building the set of entries 400, as described with reference to FIG. 5.

In some cases, each entry in the set of entries 400 consumes eight (8) bytes and each LBA can be mapped to a physical address page on the memory device. The memory pages may be, for example, 4kB of memory, 8kB, or other sizes. For a 4kB page, a LBA can be mapped to a physical address of up to 4MB of memory using a set of entries (e.g., set of entries 400) that contains 1024 entries. In some cases, each entry in the set of entries 400 may be accessed (e.g., by a host device) based on the LBA index of the first portion of each entry.

The set of entries 400 includes a first entry 410 and a second entry 415, as well as other entries. The first entry 410 includes a first portion 410-a that includes a first physical address corresponding to LBA 0 and a second portion 410-b that includes a second physical address corresponding to LBA 1. As previously suggested, the first and second physical addresses may be non-contiguous, but may be contiguous in some cases.

The second entry 415 includes a first portion 415-a that includes a second physical address corresponding to LBA1 and a second portion 415-b that includes a third physical address corresponding to LBA 2. Thus, the physical address corresponding to LBA1 is repeated in second portion 410-b and first portion 415-a. In a broader sense, the physical addresses corresponding to LBAs 1-1023 repeat across the entry to enable each physical address to be retrieved separately based on the LBA index of the first portion of the entry.

In some cases, the set of entries 400 may contain entries that contain a single physical address. For example, the final entry 420 in the set of entries 400 may contain a single physical address, and there may be other entries in the set of entries 400 that contain a single physical address.

In some cases, an entry in the set of entries may encode additional information (e.g., in addition to one or more physical addresses). For example, an entry may include data validation information for one or more physical addresses. For example, when the memory device generates a set of entries, the memory device may determine an error detection value (e.g., a checksum or exclusive-or (XOR) value) for one or more physical addresses and store the error detection value in an entry having the one or more physical addresses.

Although the set of entries 400 depicts each entry (e.g., entries 410, 415) as including two physical addresses (corresponding to two consecutive LBAs), in some cases, the set of entries may include three or more physical addresses (corresponding to three or more consecutive LBAs).

Further, although entry set 400 contains 1024 entries of eight bytes (each divided into two portions of four bytes), other numbers of entries, entry lengths, and/or portion lengths may be used without departing from the scope of the present disclosure.

The implementation of the set of entries 400 depicted in fig. 4 may enable a host device to read data for multiple LBAs based on retrieving a single entry from the set of entries 400, thereby reducing the overhead and latency associated with reading multiple blocks of data.

For example, if the host device is intended to read data corresponding to LBA1 and LBA 2, the host device may retrieve the second entry 415. The host device may include two physical addresses (e.g., a first physical address in the first portion 415-a and a second physical address in the second portion 415-b) in the read command, as well as a first LBA (LBA 1). The host device may also include an indication in the read command that the data transfer length is 2 (corresponding to reading data at two physical addresses). For example, a read operation of 4kB may correspond to reading a single physical address associated with a logical block address, while a read operation of 8kB may correspond to reading two physical addresses associated with a logical block address.

The memory device may receive the read command and may extract a first physical address (e.g., in the first portion 415-a), a second physical address (e.g., in the second portion 415-b), and an indication of a data transfer length of 2. The memory device may retrieve a first portion of data stored at a first physical address and a second portion of data stored at a second physical address based on the read command and the indication of the data transfer length, and may transmit the first portion of data and the second portion of data to the host device.

Fig. 5 illustrates an example of a process 500 to support dual address encoding for logical to physical mapping in accordance with examples disclosed herein. Process 500 may be used to efficiently establish a set of entries (e.g., set of entries 400) for mapping LBAs to physical addresses by encoding multiple physical addresses in a single L2P entry. That is, process 500 may be used to translate an L2P table having one physical address per entry into an L2P table having two physical addresses per entry, as depicted in FIG. 4.

In some cases, process 500 may be implemented using a hardwired hardware accelerator, such as accelerator 345 depicted in fig. 3. In some cases, process 500 may be implemented using firmware or software. In the description below, process 500 is described as being implemented by an accelerator; this description is not to be taken in a limiting sense.

At 505, an accelerator (e.g., accelerator 345) of the memory device may begin building a set of entries (e.g., an L2P table) that encode a plurality of physical addresses in one or more entries in a set of entries to map LBAs generated by a host device to physical addresses of the memory device.

At 510, the accelerator may initialize a first pointer to a first value, where the first pointer points to a location of a source memory region. The accelerator may initialize a second pointer to the first value, where the second pointer points to a location of the target memory region. In some cases, the source memory region may contain a previously generated L2P table with a single physical address in each entry. The source memory region may comprise one region of SRAM memory on the memory device (e.g., one region of SRAM 340), and the target memory region may comprise another region of SRAM memory on the memory device (e.g., another region of SRAM 340).

At 515, the accelerator may read the value of the first pointer S (e.g., the first physical address) and save this value in a first portion of the first entry of the set of entries (P0), such as first portion 410-a described with reference to FIG. 4. The accelerator may increase the value of the first pointer S from a first value to a second value, such as by incrementing the first pointer S by a value.

At 520, the accelerator may read the (incremented) value of the first pointer S (e.g., the second physical address) and save this value in a second portion of the entries of the set of entries (P1), such as second portion 410-b described with reference to FIG. 4. The accelerator may increment the first pointer S again.

At 525, the accelerator may write the value of the first portion (P0) of the first entry at the memory location in the target memory indicated by the second pointer T. The accelerator may increase the value of the second pointer T from the first value to the second value, such as by incrementing the second pointer T.

At 530, the accelerator may write the value of the second portion (P1) of the first entry at the memory location in the target memory indicated by the (incremented) second pointer T. The accelerator may increment the second pointer T again.

At 535, the accelerator may determine whether some or all of the entries stored in source memory have been read into P0 or P1; for example, whether the original L2P table has been adequately converted into a double re-encoded L2P table.

In response to determining that all of the entries have been read into P0 or P1, the accelerator may stop processing at 540. In some cases, the accelerator may stop processing based on the number of entries created meeting some threshold. The memory device may then transmit the double-coded set of entries to the host device for storage in memory on the host device.

In response to determining that some or all of the entries have not been read into P0 or P1, at 545, the accelerator may write the value of the second portion of the entry (P1) to the first portion of the next entry (P0) (e.g., repeat the physical address in the first portion of the next entry of the L2P table) and continue to the next entry of the source memory table. In some cases, the accelerator may continue processing based on the number of entries created not satisfying a certain threshold.

FIG. 6 illustrates a block diagram 600 of a memory device 605 that supports dual address encoding for logical to physical mapping according to an example disclosed herein. Memory device 605 may be an example of aspects of a memory device as described with reference to fig. 1 through 5. The memory device 605 may contain a command receiving component 610, a data transfer component 615, a data writing component 620, an entry generation component 625, an LBA identification component 630, a table transfer component 635, and a data reading component 640. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

Command receiving component 610 can receive a read command from a host device that includes a first physical address of the memory device corresponding to a first logical block address generated by the host device and a second physical address of the memory device corresponding to a second logical block address generated by the host device. In some cases, the read command includes an indication of a data transfer length, and wherein a combined length of the first page data and the second page data is associated with the data transfer length. In some cases, the first physical address and the second physical address are contained within 8 bytes of the read command. In some cases, the read command includes a first logical block address. In some cases, the first logical block address and the second logical block address are consecutive logical block addresses. In some cases, the first physical address and the second physical address are non-consecutive physical addresses.

In some examples, command receiving component 610 may receive a write command including a first logical block address from a host device at a memory device prior to receiving a read command, where the write command is associated with writing a first page of data to the memory device.

The data transfer component 615 can transfer the first page data and the second page data to the host device based on retrieving the first page data and the second page data.

The data transfer component 615 can transmit a set of entries mapping a set of logical block addresses to a corresponding set of physical addresses to the host device prior to receiving the read command, wherein a first entry in the set of entries includes a first physical address and a second physical address, and a second entry includes the second physical address and a third physical address associated with a third logical block address.

The entry generation component 625 may store a first entry of the set of entries, the first entry containing a first physical address and a second physical address, the first entry used to map a first logical block address to the first physical address and the second physical address. In some cases, each entry of the set of entries is 8 bytes in length.

In some examples, the entry generation component 625 may store a second entry of the set of entries that includes a second physical address and a third physical address associated with a third logical block address, the second entry for mapping the second logical block address to the second physical address and the third physical address. In some examples, the entry generation component 625 may store a first entry of the set of entries at the memory device based on writing a first page of data to the memory device at a first physical address and writing a second page of data to the memory device at a second physical address.

In some examples, the entry generation component 625 may retrieve the first physical address from the first memory region based on the value of the first pointer. In some instances, the entry generation component 625 may store the first physical address in the first portion of the first entry.

In some examples, the entry generation component 625 may increase the value of the first pointer to a second value of the first pointer. In some examples, the entry generation component 625 may retrieve the second physical address from the first memory region based on the second value of the first pointer. In some examples, the entry generation component 625 may store the second physical address in the second portion of the first entry.

In some examples, the entry generation component 625 may store the first physical address in the second memory region based on the first value of the second pointer. In some examples, the entry generation component 625 may increase the first value of the second pointer to the second value of the second pointer.

In some examples, the entry generation component 625 may store the second physical address in the second memory region based on the second value of the second pointer, where storing the second entry includes storing the second physical address in a first portion of the second entry. In some examples, the entry generation component 625 may determine an error detection value associated with the first physical address and the second physical address, where the first entry includes the error detection value.

LBA identification component 630 can identify a first logical block address associated with a first physical address of a memory device. In some examples, LBA identification component 630 may identify a second logical block address associated with a second physical address of the memory device.

Table transfer component 635 can transfer the set of entries to the host device.

Data write component 620 may write the first page of data to the memory device at a first physical address associated with the first logical block address based on the write command. In some examples, data writing component 620 may write the second page of data to the memory device at the second physical address based on the second write command.

The data reading component 640 can retrieve a first page of data from a first physical address of the memory device and a second page of data from a second physical address of the memory device.

Fig. 7 illustrates a flow diagram that illustrates one or more methods 700 that support dual address encoding for logical-to-physical mapping in accordance with examples disclosed herein. The operations of method 700 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 700 may be performed by a memory device as described with reference to fig. 1 through 6. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated hardware.

At 705, the memory device may receive a read command from the host device that includes a first physical address of the memory device corresponding to a first logical block address generated by the host device and a second physical address of the memory device corresponding to a second logical block address generated by the host device. The operations of 705 may be performed according to the methods described herein. In some examples, aspects of the operations of 705 may be performed by a command receiving component as described with reference to fig. 6.

At 710, the memory device may retrieve a first page of data from a first physical address of the memory device and retrieve a second page of data from a second physical address of the memory device. 710 may be performed according to the methods described herein. In some examples, aspects of the operations of 710 may be performed by a data reading component as described with reference to fig. 6.

At 715, the memory device may transmit the first page data and the second page data to the host device based on retrieving the first page data and the second page data. 715 may be performed according to the methods described herein. In some examples, aspects of the operations of 715 may be performed by a data transfer component as described with reference to fig. 6.

In some examples, a device as described herein may perform one or more methods, such as method 700. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a read command from a host device, the read command including a first physical address of the memory device corresponding to a first logical block address generated by the host device and a second physical address of the memory device corresponding to a second logical block address generated by the host device; retrieving a first page of data from a first physical address of the memory device and a second page of data from a second physical address of the memory device; and transmitting the first page data and the second page data to the host device based on retrieving the first page data and the second page data.

In some examples of the method 700 and apparatus described herein, the read command includes an indication of a data transfer length, and a combined length of the first page data and the second page data may be associated with the data transfer length.

Some examples of the methods 700 and apparatus described herein may further include transmitting, to the host device, an operation, feature, means, or instruction to map a set of logical block addresses to a set of entries of a corresponding set of physical addresses before receiving the read command, wherein a first entry of the set of entries includes the first physical address and the second physical address, and a second entry includes the second physical address and a third physical address associated with a third logical block address.

In some examples of the method 700 and apparatus described herein, each entry in the set of entries may have a length of 8 bytes.

Some examples of the method 700 and apparatus described herein may further include operations, features, means, or instructions for: receiving, at the memory device, a write command including a first logical block address from the host device prior to receiving the read command, wherein the write command may be associated with writing a first page of data to the memory device; and writing the first page data to the memory device at a first physical address associated with the first logical block address based on the write command.

Some examples of the method 700 and apparatus described herein may further include operations, features, means, or instructions for: a first entry of the set of entries is stored at the memory device based on writing a first page of data to the memory device at a first physical address and writing a second page of data to the memory device at a second physical address.

In some examples of the method 700 and apparatus described herein, the first physical address and the second physical address may be contained within 8 bytes of the read command.

In some examples of the method 700 and devices described herein, the read command includes a first logical block address.

In some examples of the method 700 and apparatus described herein, the first logical block address and the second logical block address may be consecutive logical block addresses.

In some examples of the method 700 and apparatus described herein, the first physical address and the second physical address may be non-contiguous physical addresses.

FIG. 8 illustrates a flow diagram that illustrates one or more methods 800 for supporting dual address encoding for logical-to-physical mapping in accordance with examples disclosed herein. The operations of method 800 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 800 may be performed by a memory device as described with reference to fig. 6. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware (e.g., a hardware accelerator) to perform aspects of the described functionality.

At 805, the memory device can identify a first logical block address associated with a first physical address of the memory device. 805 may be performed according to the methods described herein. In some examples, aspects of the operations of 805 may be performed by an LBA identification component as described with reference to fig. 6.

At 810, the memory device can identify a second logical block address associated with a second physical address of the memory device. The operations of 810 may be performed according to the methods described herein. In some examples, aspects of the operations of 810 may be performed by the LBA identification component as described with reference to fig. 6.

At 815, the memory device may store a first entry of a set of entries, the first entry including a first physical address and a second physical address, the first entry used to map a first logical block address to the first physical address and the second physical address. 815 may be performed according to the methods described herein. In some instances, aspects of the operation of 815 may be performed by an entry generation component as described with reference to fig. 6.

At 820, the memory device may store a second entry of the set of entries, the second entry including a second physical address and a third physical address associated with a third logical block address, the second entry for mapping the second logical block address to the second physical address and the third physical address. 820 may be performed according to the methods described herein. In some instances, aspects of the operations of 820 may be performed by an entry generation component as described with reference to fig. 6.

At 825, the memory device can transmit the set of entries to the host device. The operations of 825 may be performed according to the methods described herein. In some instances, aspects of the operations of 825 may be performed by a table transfer component as described with reference to fig. 6.

In some examples, a device as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: identifying a first logical block address associated with a first physical address of a memory device; identifying a second logical block address associated with a second physical address of the memory device; storing a first entry of a set of entries, the first entry including a first physical address and a second physical address, the first entry for mapping a first logical block address to the first physical address and the second physical address; storing a second entry of the set of entries, the second entry including a second physical address and a third physical address associated with a third logical block address, the second entry for mapping the second logical block address to the second physical address and the third physical address; and transmitting the set of entries to the host device.

In some examples of the method 800 and apparatus described herein, storing the first entry may include operations, features, means, or instructions for: retrieving a first physical address from a first memory region based on a value of a first pointer; storing the first physical address in a first portion of the first entry; increasing the value of the first pointer to a second value of the first pointer; retrieving a second physical address from the first memory region based on a second value of the first pointer; and storing the second physical address in the second portion of the first entry.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: storing the first physical address in the second memory region based on the first value of the second pointer; increasing the first value of the second pointer to a second value of the second pointer; and storing the second physical address in the second memory region based on the second value of the second pointer, wherein storing the second entry includes storing the second physical address in a first portion of the second entry.

In some examples of the method 800 and apparatus described herein, the first portion of the first entry and the second portion of the first entry each have a size of four bytes.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: an error detection value associated with the first physical address and the second physical address is determined, wherein the first entry includes the error detection value.

It should be noted that the methods described herein are possible embodiments, and that operations or steps may be rearranged or otherwise modified, and that other embodiments are possible. Furthermore, portions of two or more of the methods may be combined.

A memory device may include an array of memory cells and a controller coupled to the array of memory cells. The controller may be operable to cause the memory device to: receiving a read command from a host device, the read command having a first physical address of the memory device corresponding to a first logical block address generated by the host device and a second physical address of the memory device corresponding to a second logical block address generated by the host device; retrieving a first page of data from the first physical address of the memory device and retrieving a second page of data from the second physical address of the memory device; and transmitting the first page data and the second page data to the host device based at least in part on retrieving the first page data and the second page data.

The read command may contain an indication of the length of the data transfer. A combined length of the first page data and the second page data may be associated with the data transfer length.

The controller may be further operable to cause the memory device to: transmitting, to the host device, a set of entries mapping a set of logical block addresses to a corresponding set of physical addresses before receiving the read command. A first entry of the set of entries may contain the first physical address and the second physical address, and a second entry of the set of entries may contain the second physical address and a third physical address corresponding to a third logical block address.

Each entry of the set of entries may be eight bytes in length.

The controller may be further operable to cause the memory device to: receiving a write command from the host device including the first logical block address prior to transmitting the set of entries. The write command may be associated with writing the first page of data to the memory device. The controller may be further operable to cause the memory device to: writing the first page of data to the memory device at the first physical address corresponding to the first logical block address based at least in part on the write command.

The controller may be further operable to cause the memory device to: storing the first entry of the set of entries at the memory device based at least in part on writing the first page data to the memory device at the first physical address and writing the second page data to the memory device at the second physical address.

The first physical address and the second physical address may be contained within 8 bytes of the read command. The read command may include the first logical block address. The first logical block address and the second logical block address may be consecutive logical block addresses. The first physical address and the second physical address may be non-consecutive physical addresses.

A memory device may include an array of memory cells and a controller coupled to the array of memory cells. The controller may be operable to cause the memory device to: identifying a first logical block address associated with a first physical address of the memory device; identifying a second logical block address associated with a second physical address of the memory device; storing a first entry of a set of entries; storing a second entry of the set of entries; and transmitting the set of entries to the host device. The first entry may contain the first physical address and the second physical address, the first entry being used to map the first logical block address to the first physical address and the second physical address. The second entry may include the second physical address and a third physical address associated with a third logical block address, the second entry for mapping the second logical block address to the second physical address and the third physical address.

The controller may be further operable to store the first entry by: retrieving the first physical address from a first memory region based at least in part on a value of a first pointer; storing the first physical address in a first portion of the first entry; increasing the value of the first pointer to a second value of the first pointer; retrieving the second physical address from the first memory region based at least in part on the second value of the first pointer; and storing the second physical address in a second portion of the first entry.

The controller may be further operable to cause the memory device to: storing the first physical address in a second memory region based at least in part on a first value of a second pointer; increasing the first value of the second pointer to a second value of the second pointer; and storing the second physical address in the second memory region based at least in part on the second value of the second pointer. Storing the second entry may include storing the second physical address in the first portion of the second entry.

The first portion of the first entry and the second portion of the first entry may each have a size of four bytes.

The controller may be further operable to determine an error detection value associated with the first physical address and the second physical address. The first entry may contain the error detection value.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some of the figures may show multiple signals as a single signal; however, one of ordinary skill in the art will appreciate that the signals may represent a signal bus, where the bus may have various bit widths.

The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports signal flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact, connection, or coupling with each other) if there are any conductive paths between the components that can support signal flow between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected to or coupled to each other) may be open or closed, based on the operation of the device containing the connected components. The conductive path between connected components may be a direct conductive path between components, or the conductive path between connected components may be an indirect conductive path, which may contain intermediate components, such as switches, transistors, or other components. In some examples, signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

The term "coupled" refers to a condition that moves from an open circuit relationship between components that is not currently able to transmit signals between components through conductive paths to a closed circuit relationship between components that is able to transmit signals between components through conductive paths. When a component, such as a controller, couples other components together, the component causes a change that allows a signal to flow between the other components through a conductive path that previously did not allow a signal to flow.

Devices including memory arrays as discussed herein may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or silicon-on-sapphire (SOS) or a layer of epitaxial semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping using various chemistries including, but not limited to, phosphorous, boron, or arsenic. The doping may be performed during initial formation or growth of the substrate by ion implantation or any other doping means.

The switching components or transistors discussed herein may represent Field Effect Transistors (FETs) and include three terminal devices including a source, a drain and a gate. The terminals may be connected to other electronic components through conductive materials such as metals. The source and drain may be conductive and may comprise heavily doped, for example degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

The description set forth herein, in connection with the appended drawings, describes example configurations and is not intended to represent all examples that may be practiced or within the scope of the claims. The term "exemplary" as used herein means "serving as an example (instance ) or illustration," rather than "preferred" or "superior to other examples. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference numerals. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label irrespective of the second reference label.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software for execution by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and embodiments are within the scope of the disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of the foregoing. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein (including in the claims), "or" as used in a list of items (e.g., a list of items ending in a phrase such as "at least one of. Also, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based, at least in part, on".

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), Compact Disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes CD, laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.