阅读说明：本技术 阵列基板及显示面板 (Array substrate and display panel ) 是由 张鹏 于 2021-07-30 设计创作，主要内容包括：本申请公开了一种阵列基板及显示面板。显示面板包括显示区、开孔区、多条第一扫描线、多条第二扫描线、多条第三扫描线、多个第一移位寄存器单元、多个第二移位寄存器单元及补偿单元；第一扫描线沿第一方向穿过显示区；第二扫描线第一方向延伸至开孔区；第三扫描线沿第二方向延伸至开孔区；第一移位寄存器单元的输出端分别与对应的第一扫描线和第二扫描线连接,第二移位寄存器单元的输出端与对应的第三扫描线连接；第一扫描线穿过显示区与第二移位寄存器单元连接,补偿单元接入第二时钟信号线、第二移位寄存器单元以及第三扫描线组成的扫描信号回路。根据本申请实施例,能够对显示区两侧的走线电容差异进行补偿,降低扫描信号的延时差异。(The application discloses array substrate and display panel. The display panel comprises a display area, an opening area, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of third scanning lines, a plurality of first shift register units, a plurality of second shift register units and a compensation unit; the first scanning line passes through the display area along a first direction; the first direction of the second scanning line extends to the opening area; the third scanning line extends to the opening area along the second direction; the output end of the first shift register unit is respectively connected with the corresponding first scanning line and the second scanning line, and the output end of the second shift register unit is connected with the corresponding third scanning line; the first scanning line passes through the display area and is connected with the second shift register unit, and the compensation unit is connected with a scanning signal loop formed by the second clock signal line, the second shift register unit and the third scanning line. According to the embodiment of the application, the difference of the routing capacitors at two sides of the display area can be compensated, and the delay difference of the scanning signals is reduced.)

1. An array substrate comprises a display area and an opening area in the display area; characterized in that, the array substrate includes:

a plurality of first scan lines extending from a first side of the display area in a first direction and across the display area, the first scan lines not intersecting the aperture area;

a plurality of second scan lines extending from a first side of the display region to the open region along the first direction;

a plurality of third scan lines extending from a second side of the display area to the open area along a second direction, the first direction being opposite to the second direction;

the first shift register units are arranged on the first side of the display area, the input ends of the first shift register units are connected with a first clock signal line, the output ends of the first shift register units are respectively connected with corresponding first scanning lines and second scanning lines, and the first shift register units are sequentially connected in a cascade manner;

the second shift register units are arranged on the second side of the display area, the input ends of the second shift register units are connected with a second clock signal line, the output ends of the second shift register units are connected with corresponding third scanning lines, and the second shift register units are sequentially connected in a cascade manner;

a first scanning line, which is in a preset range of the distance between the first scanning line and the second shift register unit, penetrates through the display area and is connected with the second shift register unit;

and the compensation unit is connected to a scanning signal loop formed by the second clock signal line, the second shift register unit and the third scanning line.

2. The array substrate of claim 1, wherein the compensation value of the compensation unit is a difference between a total parasitic capacitance of all the first shift register units and a total parasitic capacitance of all the second shift register units.

3. The array substrate of claim 2, wherein the total parasitic capacitance of all first shift register cells is a product of the single-stage parasitic capacitance and the number of the first shift register cells, and the total parasitic capacitance of all second shift register cells is a product of the single-stage parasitic capacitance and the number of the second shift register cells.

4. The array substrate of claim 2, wherein the second clock signal line comprises a CK clock signal line and an XCK clock signal line, and the second shift register unit is connected to the CK clock signal line and the XCK clock signal line, respectively; the compensation unit includes:

and one first compensation capacitor is connected into the CK clock signal wire, and the other first compensation capacitor is connected into the XCK clock signal wire.

5. The array substrate of claim 2, wherein the compensation unit comprises:

and the second compensation capacitors are arranged outside the display area, and each second compensation capacitor is connected with the output end of the corresponding second shift register unit.

6. The array substrate of claim 2, wherein the compensation unit comprises:

and the third compensation capacitors are arranged on one side of the display area close to the opening area, and each third compensation capacitor is connected with the corresponding third scanning line.

7. The array substrate of claim 1, wherein the size of the second shift register unit is set to be smaller than the size of the first shift register unit, the size including the number of thin film transistors constituting a circuit structure.

8. The array substrate according to any one of claims 1 to 7, wherein, among the plurality of second shift register units which are sequentially cascaded, the first-stage second shift register unit is connected with a first scanning line whose orthogonal projection distance on the array substrate is within a first preset range.

9. The array substrate of any one of claims 1 to 7, wherein, among the plurality of second shift register units which are cascaded in sequence, the last second shift register unit is connected with the first scan line of which the orthographic projection distance on the array substrate is within a second preset range.

10. A display panel comprising the array substrate according to any one of claims 1 to 9.

Technical Field

The application belongs to the technical field of display, and particularly relates to an array substrate and a display panel.

Background

At present, as the design of electronic products is diversified, holes are usually dug in the display area of the display screen of the electronic product to form an opening area, and various electronic components are placed in the opening area. Such as a camera or watch hands, etc. The shapes of the display area and the opening area may be various.

However, in the array substrate of the electronic product, in order to bypass the opening region in the display region, the wires need to be routed in an arc shape near the opening region to avoid the opening region. And the winding wires near the opening area are too dense, so that a black edge of a non-display area is formed, and the frame of the opening area is too large. Therefore, in the conventional solution, scan lines are respectively disposed on two sides of the display area in the pixel rows corresponding to the opening area and extend to the opening area, so as to avoid winding around the opening area.

In the existing scan line setting mode for avoiding winding, because the number of scan lines will affect the capacitance value of the parasitic capacitance on this side, when the number of scan lines driven on both sides of the display area is inconsistent, the capacitance values of the parasitic capacitances on both sides will be different, so that the scan signals received by the scan lines on both sides have different delays, and a flicker phenomenon occurs during display.

Disclosure of Invention

The embodiment of the application provides an array substrate and a display panel, and the technical problem that the number of scanning lines arranged on two sides of an opening area is inconsistent, so that the received scanning signals are delayed differently can be solved.

In a first aspect, an embodiment of the present application provides an array substrate, where the array substrate includes a display area and an opening area in the display area; the array substrate includes:

a plurality of first scan lines extending from a first side of the display area in a first direction and across the display area, the first scan lines not intersecting the aperture area;

a plurality of second scan lines extending from a first side of the display region to the open region along the first direction;

a plurality of third scan lines extending from a second side of the display area to the open area along a second direction, the first direction being opposite to the second direction;

the first shift register units are arranged on the first side of the display area, the input ends of the first shift register units are connected with a first clock signal line, the output ends of the first shift register units are respectively connected with corresponding first scanning lines and second scanning lines, and the first shift register units are sequentially connected in a cascade manner;

the second shift register units are arranged on the second side of the display area, the input ends of the second shift register units are connected with a second clock signal line, the output ends of the second shift register units are connected with corresponding third scanning lines, and the second shift register units are sequentially connected in a cascade manner;

a first scanning line, which is in a preset range of the distance between the first scanning line and the second shift register unit, penetrates through the display area and is connected with the second shift register unit;

and the compensation unit is connected to a scanning signal loop formed by the second clock signal line, the second shift register unit and the third scanning line.

In a second aspect, an embodiment of the present application provides a display panel, which includes the above array substrate.

Compared with the prior art, the array substrate and the display panel provided by the embodiment of the application are provided with the first scanning line which is not crossed with the opening area in the display area, the second scanning line and the third scanning line which extend to the opening area are respectively arranged on two sides of the opening area, and the first scanning line penetrates through the display area and then is connected with the second shift register unit to provide scanning signals, so that the display effect is prevented from being influenced by a large amount of winding wires near the opening area. Because one side of the display area is provided with the first scanning line and the second scanning line, and the other side is provided with the third scanning line, if the sum of the number of the first scanning line and the second scanning line is different from the number of the third scanning line, the parasitic capacitance at two sides of the display area is different, when the scanning lines at two sides of the display area are respectively driven by adopting the clock signal line, the scanning signals received by the scanning lines at two sides generate different signal delays due to the influence of different parasitic capacitance values. When the capacitance value of the parasitic capacitor at one side of the third scanning line is lower than that of the parasitic capacitor at one side of the first scanning line and the second scanning line, the corresponding compensation units are arranged on a scanning signal loop consisting of the second clock signal line, the second shift register unit and the third scanning line, so that the wiring capacitances on the clock signal lines at two sides of the display area can be kept consistent, the signal difference caused by different numbers of the scanning lines at two sides of the display area is reduced, the delay error of the scanning signals received by the scanning lines at two sides is reduced, and the synchronism and the harmony of the scanning signals are improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a compensation unit according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a compensation unit in another embodiment of the present application;

FIG. 4 is a schematic structural diagram of a compensation unit according to another embodiment of the present application;

FIG. 5 is a partial circuit layout of a first shift register unit according to an embodiment of the present application;

FIG. 6 is a partial circuit layout of a second shift register unit according to an embodiment of the present application

Fig. 7 is a schematic structural diagram of a light-emitting control line on an array substrate according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of a scan line and a light-emitting control line according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present application.

In the drawings:

1. a display area; 2. opening the hole area; 10. a first scanning line; 11. a second scanning line; 12. a third scanning line; 20. a first shift register unit; 21. a second shift register unit; 30. a compensation unit; 31. a first compensation capacitor; 32. a second compensation capacitor; 33. a third compensation capacitor; 40. A first clock signal line; 41. a second clock signal line; 50. a first light emission control line; 51. a second light emission control line; 52. a third light emission control line; 60. a third shift register unit; 61. a fourth shift register unit; 70. a second compensation unit; 80. a third clock signal line; 81. a fourth clock signal line.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The embodiments will be described in detail below with reference to the accompanying drawings.

At present, a hole is usually dug in a display area of a display screen of an electronic product to form an opening area, and various electronic components, such as a camera or a watch pointer, are placed in the opening area to realize various functions of the electronic product. The shape of the display area and the shape of the opening area can be various.

The opening area in the display area is usually not provided with the pixel circuit, and in order to provide a setting space for the electronic element, various wirings in the display area need to be wound in an arc shape near the opening area so as to avoid the opening area. The dense winding near the opening area can form a black edge at the junction of the display area and the opening area, so that the black frame of the opening area is too large, and the normal display effect of the display area is influenced.

To solve the problem that the dense winding affects the display effect, the existing solution is to set the scan lines from both sides of the display area to extend to the opening area in the pixel rows corresponding to the opening area, so as to avoid the scan lines extending from one side from winding when passing through the opening area.

However, in the pixel rows corresponding to the opening area, the scan lines are respectively disposed on two sides of the display area, that is, the shift register units are respectively disposed correspondingly, and the number of the shift register units is equal. In the pixel rows not corresponding to the opening area, the scanning lines are extended from one side of the display area, and the shift register units corresponding to the scanning lines are only arranged on one side of the display area. Therefore, the number of scan lines driven on one side of the display area is greater than the number of scan lines driven on the other side of the display area, and accordingly, the number of shift register units respectively disposed on both sides of the display area is different. When the clock signal lines on two sides of the display area are connected with the shift register units on two sides, corresponding routing capacitors are generated, the routing capacitors are related to the series of the shift register units connected on the clock signal lines, and because the number of the shift register units on two sides of the display area is not consistent, the routing capacitors on the clock signal lines on two sides of the display area are also not the same, so that the waveform delay of the scanning signals output on two sides of the display area is different, and the display effect is influenced.

In order to solve the above technical problem, an embodiment of the present application provides an array substrate and a display panel. First, the array substrate provided in the embodiments of the present application will be described.

Fig. 1 shows a schematic structural diagram of an array substrate according to an embodiment of the present application. The array substrate comprises a display area 1 and an opening area 2 in the display area 1, and further comprises a plurality of first scanning lines 10, a plurality of second scanning lines 11, a plurality of third scanning lines 12, a plurality of first shift register units 20, a plurality of second shift register units 21 and a compensation unit 30.

As shown in fig. 1, the first side and the second side of the display area 1 are two oppositely disposed side edges. The first scan line 10 extends from a first side of the display area 1 in a first direction and passes through the display area 1, and the first scan line 10 does not cross the open area 2 in the display area 1 when passing through the display area 1. That is, the projection of the first scan line 10 perpendicular to the array substrate does not overlap with the projection of the opening region 2 perpendicular to the array substrate.

The second scan line 11 extends from the first side of the display region 1 to the open region 2 along a first direction, and the third scan line 12 extends from the second side of the display region 1 to the open region 2 along a second direction, wherein the first direction is opposite to the second direction. That is, the second scan line 11 and the third scan line 12 are both located in the pixel row corresponding to the opening region 2, the opening region 2 divides the corresponding pixel row into two segments, the second scan line 11 is connected to the same row of pixels from the first side of the display region 1 to the opening region 2, and the third scan line 12 is connected to the same row of pixels from the second side of the display region 1 to the opening region 2. It can be understood that, since the open region 2 separates each row of pixels passing through the open region 2, the number of pixel rows on both sides of the open region 2 is the same, and the number of the second scanning lines 11 and the number of the third scanning lines 12 correspond to the number of the pixel rows on both sides of the open region 2 one to one, so that the number of the second scanning lines 11 is the same as the number of the third scanning lines 12.

The first shift register unit 20 is disposed at a first side of the display area 1, an input terminal of the first shift register unit 20 is connected to the first clock signal line 40, and an output terminal of the first shift register unit 20 can provide a scan signal for a scan line extending from the first side of the display area 1. And the first scan line 10 and the second scan line 11 both extend from the first side of the display area 1, the first shift register unit 20 may be connected to the first scan line 10 and the second scan line 11, respectively, to provide corresponding scan signals. It is understood that the number of the first shift register units 20 is the sum of the number of the first scan lines 10 and the second scan lines 11.

The first shift register units 20 may also be connected in series, and when the scan signal is set to be the positive scan, the scan signal output by each first shift register unit 20 is further sent to the next first shift register unit 20, so that the next first shift register unit 20 generates the scan signal according to the clock signal of the first clock signal line 40 and outputs the scan signal to the corresponding scan line. Similarly, when the scan signal is set to be the reverse scan, the scan signal output from each first shift register unit 20 is sent to the previous first shift register unit 20, so that the previous first shift register unit 20 outputs the corresponding scan signal.

The second shift register unit 21 is disposed at the second side of the display area 1, the input terminal of the second shift register unit 21 is connected to the second clock signal line 41, the output terminal of the second shift register unit 21 can provide the scan signal for the scan line extending from the second side of the display area 1, and the third scan line 12 extends from the second side of the display area 1. Therefore, the second shift register unit 21 can be connected to the corresponding third scanning line 12 to provide the pixels on the third scanning line 12 with the corresponding scanning signals. It is understood that the number of the second shift register units 21 may be equal to the number of the third scanning lines 12.

The second shift register units 21 may also be sequentially arranged in a cascade manner, and may be sent to the adjacent second shift register unit 21 when outputting the scan signal according to whether the scan signal is in a forward scan setting or a reverse scan setting, so as to trigger the adjacent second shift register unit 21 to generate the scan signal.

In the plurality of first shift register units 20, each first shift register unit 20 may receive the scan signal output from the adjacent first shift register unit 20 and generate the scan signal by the clock signal output from the first clock signal line 40. After the scan signal output by the first shift register unit 20 passes through the first scan line 10 from the first side of the display area 1 to the second side of the display area 1 through the display area 1, the first scan line 10 may be connected to the second shift register unit 21, so that the second shift register unit 21 receives the scan signal, and the second shift register unit 21 is triggered to generate a corresponding scan signal according to the clock signal on the second clock signal line 41. That is, in the plurality of second shift register units 21, the scan signal received by a first second shift register unit 21 is the scan signal sent by the first shift register unit 20 to the first scan line 10, and the first scan line 10 passes through the display area 1 and then is sent to the second shift register unit 21, and after the second shift register unit 21 outputs the scan signal, the scan signal can be sent to the adjacent second shift register unit 21 through the second shift register units 21 which are sequentially cascaded, so that all the second shift register units 21 sequentially receive the scan signal.

It can be understood that the second scan lines 11 only extend to the opening region 2 and cannot completely pass through the display region 1, and therefore the scan signals received by the second shift register unit 21 are sent by the first scan lines 10. The first scan line 10 may be a first scan line 10 having a distance from the second shift register unit 21 within a predetermined range. The second shift register unit 21 may receive the scan signal through the first scan line 10, thereby triggering the second shift register units 21, which are sequentially cascaded, to generate the scan signal.

The first shift register unit 20 receives a clock signal through a first clock signal line 40 to generate a scan signal, and the second shift register unit 21 receives a clock signal through a second clock signal line 41 to generate a scan signal. The number of first shift register cells 20 on the first clock signal line 40 is greater than the number of second shift register cells 21 on the second clock signal line 41. Since each shift register unit generates a corresponding parasitic capacitance, and the trace capacitance on the clock signal line is associated with the parasitic capacitance of each shift register unit, when the number of the first shift register unit 20 is larger than that of the second shift register unit 21, the trace capacitance on the first clock signal line 40 is also larger than that on the second clock signal line 41. The trace capacitance on the clock signal line affects the output delay of the scan signal output by the shift register unit, and when the trace capacitance on the first clock signal line 40 is different from that on the second clock signal line 41, the delay difference between the scan signal output by the first shift register unit 20 and the scan signal output by the second shift register unit 21 will be caused.

The compensation unit 30 is connected to a scan signal loop formed by the second clock signal line 41, the second shift register unit 21 and the third scan line 12, and the compensation unit 30 can compensate the whole trace capacitance on the second clock signal line 41, so that the trace capacitance on the second clock signal line 41 is equal to or similar to the trace capacitance on the first clock signal line 40.

In this embodiment, the first scanning line 10 is disposed in the pixel row outside the opening region 2, and the second scanning line 11 and the third scanning line 12 are disposed on both sides of the pixel row corresponding to the opening region 2, so that a black edge surrounding the opening region 2 due to winding near the opening region 2 can be avoided, and the width of the border between the display region 1 and the opening region 2 can be reduced. The first shift register unit 20 may output corresponding scan signals to the first scan line 10 and the second scan line 11, and the first scan line 10 may be further connected to the second shift register unit 21 after extending through the display area 1 to transmit the scan signals to the second shift register unit 21 at the other side of the display area 1, so that the second shift register unit 21 can transmit the scan signals to the third scan line 12. Because the number of the first shift register unit 20 and the second shift register unit 21 is different, a compensation unit 30 may be further disposed on a scan signal loop formed by the second clock signal line 41, the second shift register unit 21 and the third scan line 12 to compensate for a capacitance difference generated by the number difference of the shift register units at both sides of the display area 1, so that the shift register units at both sides of the display area 1 can generate scan signals with the same or similar waveforms through the first clock signal line 40 and the second clock signal line 41, respectively, and a flicker phenomenon generated during display due to a delay difference of the scan signals is avoided.

In some embodiments, the compensation value of the compensation unit 30 may be a difference between a total parasitic capacitance of all the first shift register units 20 and a total parasitic capacitance of all the second shift register units 21.

The capacitance value of the trace capacitor on the first clock signal line 40 is related to the number of stages of the first shift register units 20 driven by the trace capacitor, and for a plurality of sequentially cascaded first shift register units 20, the capacitance value of the parasitic capacitor formed by each first shift register unit 20 is a, the number of the first shift register units 20 is n, and then the total parasitic capacitance of all the first shift register units 20 is the product of the single-stage parasitic capacitor of each first shift register unit 20 and the number of the first shift register units 20, that is, n × a.

The number of the second scan lines 11 is the same as the number of the third scan lines 12, and the sum of the numbers of the second scan lines 11 and the first scan lines 10 is the same as the number of the first shift register units 20. If the number of the second scan lines 11 is m, the number of the first scan lines 10 is (n-m), the number of the third scan lines 12 is m, and the number of the second shift register units 21 is also m. When the parasitic capacitance formed by the first shift register unit 20 is equal to the parasitic capacitance formed by the second shift register unit 21, the total parasitic capacitance of all the second shift register units 21 is the product of the single-stage parasitic capacitance and the number of the second shift register units 21, i.e., m × a.

The compensation value of the compensation unit 30 may be an equivalent capacitance value of the compensation unit 30, and the equivalent capacitance value may be set as a difference between a total parasitic capacitance of all the first shift register units 20 and a total parasitic capacitance of all the second shift register units 21, i.e., (n-m) × a. After the trace capacitance on the second clock signal line 41 is compensated, the actual capacitance on the second clock signal line 41 is the same as the trace capacitance on the first clock signal line 40, and at this time, the delays of the scan signals output by the first shift register unit 20 and the second shift register unit 21 are equal.

It should be noted that the compensation unit 30 may be disposed in a scanning signal loop composed of the second clock signal line 41, the second shift register unit 21, and the third scanning line 12, and the disposed positions may be respective nodes in the scanning signal loop.

Referring to fig. 2, in some embodiments, the second clock signal line 41 may include a CK clock signal line and an XCK clock signal line, and the second shift register unit 21 is connected to the CK clock signal line and the XCK clock signal line, respectively. The compensation unit 30 may include:

two first compensation capacitors 31, one first compensation capacitor 31 is connected to the CK clock signal line, and the other first compensation capacitor 31 is connected to the XCK clock signal line.

When receiving the scan signal transmitted from the first scan line 10 or the scan signal transmitted from the adjacent second shift register unit 21, the second shift register unit 21 may generate a corresponding scan signal from the CK clock signal and the XCK clock signal output from the CK clock signal line and the XCK clock signal line, and output the scan signal to the third scan line 12 connected to the second shift register unit 21.

For the CK clock signal line, it is necessary to access the CK clock signal line through the first compensation capacitor 31 to compensate for the difference between the parasitic capacitances of the first shift register unit 20 and the second shift register unit 21. One end of the first compensation capacitor 31 is connected to the CK clock signal line, and the other end thereof can be grounded or connected to the power signal line. Similarly, another first compensation capacitor 31 may be provided for the XCK clock signal line to compensate for the difference between the parasitic capacitances of the first shift register unit 20 and the second shift register unit 21. It is understood that the capacitance values of the two first compensation capacitors 31 are equal, and the capacitance value is equal to the difference between the total parasitic capacitance of all the first shift register units 20 and the total parasitic capacitance of all the second shift register units 21.

Referring to fig. 3, in some embodiments, the compensation unit 30 may further include:

a plurality of second compensation capacitors 32, the second compensation capacitors 32 may be disposed outside the display area 1, and each second compensation capacitor 32 is connected to the output end of the corresponding second shift register unit 21.

The second shift register unit 21 has an input terminal connected to the second clock signal line 41 and an output terminal connected to the third scan line 12. The third scan line 12 is located in the display region 1, the second shift register unit 21 is located outside the display region 1, and the second compensation capacitor 32 can be disposed outside the display region 1 and connected to the output terminal of the second shift register unit 21.

The number of the second compensation capacitances 32 may be set to be equal to the number of the second shift register units 21. The capacitance values of each of the second compensation capacitors 32 may be set to be equal or unequal, and the equivalent capacitance value of all the second compensation capacitors 32 is equal to the difference between the total parasitic capacitance of all the first shift register units 20 and the total parasitic capacitance of all the second shift register units 21. One end of each second compensation capacitor 32 is connected to the output terminal of the corresponding second shift register unit 21, and the other end thereof may be connected to ground or a power supply signal line.

Referring to fig. 4, in some embodiments, the compensation unit 30 may further include:

and a plurality of third compensation capacitors 33, wherein the third compensation capacitors 33 are disposed on one side of the display region 1 close to the opening region 2, and each third compensation capacitor 33 is connected to a corresponding third scan line 12.

The number of the third compensation capacitors 33 may be set to be equal to the number of the third scan lines 12, the capacitance value of each third compensation capacitor 33 may be set to be equal or unequal, and the sum of the equivalent capacitances of all the third compensation capacitors 33 is equal to the difference between the total parasitic capacitances of all the first shift register units 20 and the total parasitic capacitances of all the second shift register units 21. The third compensation capacitor 33 may be disposed on a side of the display region 1 near the opening region 2, so as to be disposed by using a boundary region between the display region 1 and the opening region 2. One end of the third compensation capacitor 33 may be connected to the corresponding third scan line 12, and the other end may be connected to ground or a power signal line.

In the above embodiments, the compensation units 30 may be respectively disposed on the second clock signal line 41, between the output terminal of the second shift register unit 21 and the display area 1, and on the third scan line 12 on the side close to the aperture area 2. When the compensation capacitors are arranged at different positions, the number of the compensation capacitors can be adjusted adaptively. The difference value of the wiring capacitance on the clock signal lines at two sides of the display can be compensated through the compensation capacitors, so that the delay difference of scanning signals output by the shift register units at two sides of the display is avoided.

In some embodiments, the size of the second shift register unit 21 may be set smaller than the size of the first shift register unit 20. The size of the shift register cell may include the number of thin film transistors constituting the circuit structure. As shown in fig. 5, the first shift register unit 20 may have a circuit structure including 16 thin film transistors. As shown in fig. 6, the second shift register unit 21 may be configured as a circuit structure composed of 12 thin film transistors.

It can be understood that as the number of thin film transistors constituting the shift register unit is decreased, the delay of the scan signal output from the shift register unit is increased accordingly. Because the trace capacitance and the trace resistance on the clock signal line will generate an equivalent delay circuit, when the trace capacitance on the first clock signal line 40 is greater than the trace capacitance on the second clock signal line 41, the delay of the signal waveform on the first clock signal line 40 is also greater than the delay of the second waveform on the second clock signal line 41. By reducing the size of the second shift register unit 21 with respect to the first shift register unit 20, the waveform delay of the scanning signal output from the second shift register unit 21 can be increased, and the delay of the scanning signal output from the second shift register unit 21 can be increased to match the delay of the scanning signal output from the first shift register unit 20.

It should be noted that, by setting the size of the second shift register unit 21 smaller than the size of the first shift register unit 20, the delay increase of the scanning signal output by the second shift register unit 21 can be achieved independently. Setting the size of the second shift register unit 21 to be smaller than the size of the first shift register unit 20 may also be combined with the compensation unit 30, for example, the compensation unit 30 only partially compensates for the difference between the routing capacitances of the first clock signal line 40 and the second clock signal line 41, at this time, the waveform delay of the scan signal output by the second shift register unit 21 is still smaller than the waveform delay of the scan signal output by the first shift register unit 20, and by adjusting the size of the second shift register unit 21, the scan signal output by the second shift register unit 21 may be further adjusted in a delayed manner, so as to achieve the waveform delays of the scan signals output by the two shift register units to be consistent. It can be understood that when the compensation unit 30 is not provided, and the sizes of the first shift register unit 20 and the second shift register unit 21 are not adjusted, the scanning signals on both sides of the display area 1 have a delay difference, thereby affecting the actual display effect.

In some embodiments. When the pixel circuits in the array substrate are arranged in an array, the length of the scan line is positively correlated to the number of the pixel circuits on the scan line, and since the first scan line 10 can pass through the display area 1 and the second scan line 11 can only extend to the open area 2, the number of the pixel circuits on the first scan line 10 close to the open area 2 is greater than the number of the pixel circuits on the second scan line 2.

After sampling of scanning signal waveforms is performed on a plurality of scanning lines with different numbers of pixel circuits, it can be determined that when the ratio of the number of the pixel circuits on the two scanning lines reaches 0.7 times, the delay difference generated by the scanning signals on the two scanning lines reaches 30 nanoseconds, the luminance difference reaches 2.86%, and at this time, the pixel circuits on the two scanning lines have obvious luminance difference, so that the overall display effect of the display panel is affected. Further, when the difference in the number of pixel circuits on the two scanning lines gradually increases, the difference in delay and the difference in light emission luminance of the two scanning signals further increase. Among them, the Gate Delay time Gate Delay of the scanning signal on the scanning line with a lower number of pixel circuits is smaller, and the Gate Delay time of the scanning signal on the scanning line with a higher number of pixel circuits is larger.

When the gate delay time of the scanning signal received by the pixel circuit is increased, the feed-through voltage of the pixel circuit is reduced, the pixel voltage and the feed-through voltage are in positive correlation, namely the pixel voltage is also reduced, so that the light emitting brightness of the pixel circuit is reduced due to the reduction of the pixel voltage. After the luminance tests are performed on the scanning lines with different numbers of pixel circuits, the corresponding relationship between the number of pixel circuits on the scanning lines and the luminance difference is obtained as shown in the following table:

number of pixel circuits	Luminous current	Difference in brightness
			0.5*n	-1.7E-09	5.60％
0.6*n	-1.6E-09	3.33％
			0.7*n	-1.6E-09	2.86％
0.8*n	-1.6E-09	1.06％
			0.9*n	-1.6E-09	1.08％
n	-1.6E-09	0.00％

As shown in the above table, when the number of pixel circuits on one scanning line is n, the light emission current is-1.6E-09, and the luminance difference is 0 with the light emission luminance of the pixel circuits at this time as a reference. When the number of the pixel circuits on the scan line is gradually reduced, the light emitting current of the pixel circuits is also continuously increased, and when the number of the pixel circuits is gradually reduced to 0.7 times or less, the luminance difference is obvious, which will affect the overall display effect of the display panel. Therefore, when there is a large difference in the number of pixel circuits on a scan line, corresponding pixel compensation is required to avoid that the overall display effect is affected by the large difference in the brightness of the pixel circuits on different scan lines. The pixel compensation mode may be that a corresponding equivalent compensation capacitor is connected in series to one side of the scan line close to the opening region, so that the equivalent delay circuit on the compensated scan line is consistent with the equivalent delay circuit of the scan line as the compensation target. The equivalent compensation capacitor may be disposed at other positions besides the side close to the opening region, which is not limited herein.

When the number of the pixel circuits is compensated to be within the range of 0.8n to n, namely, the number of the pixel circuits is compensated to be 0.8 to 1 time, the brightness difference is small at the moment, and the brightness can be regarded as consistent, so that the brightness of the pixel circuits on different scanning lines is prevented from being greatly different through pixel compensation.

It is understood that the above-mentioned embodiment of performing pixel compensation on the scan lines with large difference in the number of pixel circuits can be implemented separately, or can be combined with at least two of the above-mentioned embodiment of adjusting the size of the shift register unit and the embodiment of setting the compensation unit 30, for example, the compensation unit 30 is combined with pixel compensation, the compensation unit 30 is combined with shift register unit size adjustment, pixel compensation is combined with shift register unit size adjustment, and the like, so as to compensate the difference in the number of pixel circuits on the scan lines and the waveform delay of the scan signal, and ensure the display effect of the display panel.

In some embodiments, the plurality of second shift register units 21 cascaded in sequence may include the first-stage second shift register unit 21. For the first stage shift register unit, the first scan line 10 meeting the first preset condition may be determined, and the first scan line 10 passes through the display area 1 and then is connected to the first stage shift register unit. The first preset condition may be that a distance between an orthogonal projection of the first stage shift register unit on the array substrate and an orthogonal projection of the first scan line 10 on the array substrate is within a first preset range.

In some embodiments, the plurality of sequentially cascaded second shift registers may further include a last-stage second shift register unit 21, and for the last-stage shift register unit, the first scan line 10 satisfying the second preset condition may be determined, and the first scan line 10 may be connected to the last-stage shift register unit after passing through the display area 1. The second preset condition may be that a distance between an orthogonal projection of the last stage shift register unit on the array substrate and an orthogonal projection of the first scan line 10 on the array substrate is within a second preset range.

It is understood that, if there are a plurality of first scan lines 10 satisfying the first predetermined condition, any one of the first scan lines 10 may be selected to be connected to the first-stage second shift register unit 21. Similarly, if there are a plurality of first scan lines 10 satisfying the second predetermined condition, any one of the first scan lines 10 may be selected to be connected to the last-stage second shift register unit 21.

After receiving a scanning signal output by the first shift register unit 20, the first scanning line 10 meeting the first preset condition transmits the scanning signal to the first-stage second shift register unit 21, the first-stage second shift register unit 21 sequentially transmits the scanning signal to other second shift register units 21 connected in cascade, after receiving the scanning signal, the last-stage shift register unit can transmit the scanning signal to the first scanning line 10 meeting the second preset condition, and the first scanning line 10 meeting the second preset condition can realize scanning signal bilateral driving by corresponding to the first shift register unit 20 and the last-stage shift register unit.

In the above embodiment, the first preset condition may also be the first scan line 10 closest to the first-stage shift register unit, that is, closest to the opening region 2 and close to one side of the first-stage shift register unit. The second preset condition may also be the first scan line 10 closest to the last stage shift register unit, i.e., closest to the opening region 2 and near a side of the last stage shift register unit.

In some embodiments, the array substrate may further include light emission control lines, the number of the light emission control lines is the same as the number of the scan lines, and each light emission control line and the corresponding scan line are connected to the same pixel row. The pixels in the same row can receive the light-emitting control signal of the light-emitting control line and the scanning signal of the scanning line, and the pixels in the row are controlled to emit light by the light-emitting control signal and the scanning signal together. The extending direction of the light emitting control lines may be opposite to that of the scan lines to realize bilateral driving of the pixels in the same row.

Referring to fig. 7, in the above embodiment, the light emission control lines may include a first light emission control line 50, a second light emission control line 51, and a third light emission control line 52. The first emission control line 50 extends from the second side of the display area 1 in the second direction and passes through the display area 1, the first emission control line 50 not crossing the aperture area 2. The second light emission control line 51 extends from the second side of the display area 1 to the open area 2 in the second direction. The third emission control line 52 extends from the first side of the display region 1 to the opening region 2 along a first direction, which is opposite to the second direction. It is understood that the numbers of the first light emission control line 50, the second light emission control line 51, and the third light emission control line 52 correspond one-to-one to the numbers of the first scan line 10, the second scan line 11, and the third scan line 12, respectively.

The array substrate may further include a plurality of third shift register units 60, a plurality of fourth shift register units 61, and a second compensation unit 70.

The third shift register unit 60 is disposed on the second side of the display region 1, an input end of the third shift register unit 60 is connected to the third clock signal line 80, an output end of the third shift register unit 60 is connected to the corresponding first light-emitting control line 50 and the second light-emitting control line 51, and the plurality of third shift register units 60 are sequentially connected in cascade.

The fourth shift register unit 61 is disposed on the first side of the display region 1, an input end of the fourth shift register unit 61 is connected to the fourth clock signal line 81, an output end of the fourth shift register unit 61 is connected to the corresponding third light-emitting control line 52, and the plurality of fourth shift register units 61 are sequentially connected in cascade.

The number of the third shift register units 60 is equal to the sum of the first light emission control lines 50 and the second light emission control lines 51, and the number of the fourth shift register units 61 is equal to the number of the third light emission control lines 52.

Among the plurality of first light emission control lines 50, the first light emission control line 50 having a distance from the fourth shift register unit 61 within a preset range may be connected to the fourth shift register unit 61 after passing through the display region 1 to transmit a light emission control signal to the fourth shift register unit 61, so that the fourth shift register unit 61 located at the first side of the display region 1 can output the corresponding light emission control signal.

It can be understood that the wiring connection mode of the light-emitting control line and the wiring connection direction of the scan line are mirror images of each other, the two wiring modes are axisymmetric along a third direction, and the third direction is perpendicular to the first direction and the second direction. Therefore, the number of the third shift register units 60 on the third clock signal line 80 is greater than the number of the fourth shift register units 61 on the fourth clock signal line 81, and the second compensation unit 70 is arranged to compensate the trace capacitance on the fourth clock signal line 81, so that the signal delays of the light-emitting control signals output from the two sides of the display area 1 are kept consistent, thereby avoiding the delay difference of the light-emitting control signals.

Referring to fig. 8, fig. 8 is a schematic structural diagram illustrating that the scanning lines and the light-emitting control lines control the pixels in the same row together, and each row of pixels is connected to one scanning line and one light-emitting control line respectively and controls the light-emitting device to emit light according to the received scanning signals and light-emitting control signals. .

The technical features corresponding to the embodiments of the compensation unit 30, the scan line, the first shift register unit 20, and the second shift register unit 21 can be applied to the second compensation unit 70, the emission control line, the third shift register unit 60, and the fourth shift register unit 61, respectively, and the same technical effects can be achieved. The details are not repeated.

Based on the same inventive concept, as shown in fig. 9, an embodiment of the present application further provides a display panel including any one of the array substrates provided by the embodiments of the present application.

Since the display panel provided in the embodiment of the present application includes any one of the array substrates provided in the embodiment of the present application, the display panel has technical features corresponding to the array substrate included in the display panel, and can achieve the same effect, which is not described herein again.

The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

The principles and embodiments of the present application are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present application. It should be noted that there are no specific structures in the above description, and it will be apparent to those skilled in the art that various modifications, decorations, or changes can be made without departing from the principle of the present application, and the technical features can be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the invention in other contexts without modification may be viewed as within the scope of the present application.