阅读说明：本技术 一种阵列基板及显示面板 (Array substrate and display panel ) 是由 黄冠儒 于 2021-06-21 设计创作，主要内容包括：本发明实施例涉及显示技术领域,公开了一种阵列基板及显示面板。本发明中,阵列基板包括：衬底、依次叠设于衬底上的底栅、底栅绝缘层、有源层、顶栅绝缘层以及顶栅；阵列基板还包括：源极和漏极,源极和漏极均与有源层电连接；顶栅包括：位于顶栅绝缘层远离衬底一侧的第一部分、以及自第一部分的边缘延伸并与底栅接触的第二部分；在沿源极指向漏极的方向上,第二部分的宽度大于或等于第一部分的宽度。本发明还提供了一种显示面板。本发明提供的阵列基板及显示面板,能够改善环境电场以及环境光源对显示面板的干扰,提高显示面板的稳定性。(The embodiment of the invention relates to the technical field of display, and discloses an array substrate and a display panel. In the present invention, the array substrate includes: the device comprises a substrate, a bottom gate insulating layer, an active layer, a top gate insulating layer and a top gate, wherein the bottom gate, the bottom gate insulating layer, the active layer, the top gate insulating layer and the top gate are sequentially stacked on the substrate; the array substrate further includes: the source electrode and the drain electrode are electrically connected with the active layer; the top gate includes: the first part is positioned on one side of the top gate insulating layer, which is far away from the substrate, and the second part extends from the edge of the first part and is in contact with the bottom gate; the width of the second portion is greater than or equal to the width of the first portion in a direction along the source to the drain. The invention also provides a display panel. The array substrate and the display panel provided by the invention can improve the interference of an environmental electric field and an environmental light source to the display panel and improve the stability of the display panel.)

1. An array substrate, comprising: the device comprises a substrate, a bottom gate insulating layer, an active layer, a top gate insulating layer and a top gate, wherein the bottom gate, the bottom gate insulating layer, the active layer, the top gate insulating layer and the top gate are sequentially stacked on the substrate;

the array substrate further includes: a source electrode and a drain electrode, both of which are electrically connected to the active layer;

the top gate comprises a first part and a second part, wherein the first part is positioned on one side, far away from the substrate, of the top gate insulating layer, and the second part extends from the edge of the first part and is in contact with the bottom gate;

the width of the second portion is greater than or equal to the width of the first portion in a direction pointing along the source to the drain.

2. The array substrate of claim 1, wherein the top gate further comprises a third portion attached to the bottom gate, and the third portion is connected to an end of the second portion away from the first portion.

3. The array substrate of claim 1, further comprising a connection trench penetrating the bottom gate insulating layer, wherein a width of the connection trench is greater than or equal to a width of the first portion in a direction along the source electrode toward the drain electrode;

the top gate further comprises a third part attached to the bottom gate insulating layer, the second part fills the connecting groove to be in contact with the bottom gate, and the third part is connected with the second part.

4. The array substrate of claim 1, further comprising a connection trench penetrating the bottom gate insulating layer and the top gate insulating layer, wherein a width of the connection trench is greater than or equal to a width of the first portion in a direction pointing to the drain electrode along the source electrode;

the top gate further comprises a third part attached to the top gate insulating layer, the second part fills the connecting groove to be in contact with the bottom gate, and the third part is connected with the second part.

5. The array substrate of any one of claims 2 to 4, wherein the top gate insulating layer comprises a fourth portion located on a side of the active layer away from the substrate and a fifth portion connected to the fourth portion, the fifth portion is in contact with a surface of the bottom gate insulating layer facing away from the substrate, and the second portion is attached to the fifth portion and the bottom gate insulating layer.

6. The array substrate of claim 1, wherein the top gate insulating layer is further attached to a surface of the source electrode on a side away from the substrate and/or a surface of the drain electrode on a side away from the substrate.

7. The array substrate of claim 6, wherein the first portion has an avoiding hole;

the orthographic projection of the source electrode on the substrate is positioned in the orthographic projection of the edge of the avoidance hole on the substrate, and the orthographic projection of the first part on the substrate and the orthographic projection of the source electrode on the substrate are arranged at intervals;

and/or the orthographic projection of the drain electrode on the substrate is positioned in the orthographic projection of the edge of the avoidance hole on the substrate, and the orthographic projection of the first part on the substrate and the orthographic projection of the drain electrode on the substrate are arranged at intervals.

8. The array substrate of claim 7, wherein a distance between an inner wall of the avoiding hole and an edge of the source electrode in a stacking direction perpendicular to the substrate and the bottom gate is greater than or equal to 2 mm;

and/or in the stacking direction vertical to the substrate and the bottom gate, the distance range between the inner wall of the avoiding hole and the edge of the drain electrode is larger than or equal to 2 mm.

9. The array substrate of claim 1, wherein the width of the second portion in a direction along the source to the drain ranges from 7 microns to 8 microns.

10. A display panel, comprising: an array substrate as claimed in any one of claims 1 to 9, and an organic light emitting layer disposed on the array substrate.

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to an array substrate and a display panel.

Background

In the field of display technology, flat panel display devices have advantages such as high image quality, power saving, and thin body, and are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and are becoming the mainstream of display devices.

The currently common flat panel display device mainly includes: liquid Crystal Display (LCD) panels and Organic electroluminescent Display (AMOLED) panels. Thin Film Transistors (TFTs) are the main driving elements of LCD display panels and AMOLED display panels, and a plurality of TFTs are arranged in an array on an array substrate.

The inventor finds that at least the following problems exist in the prior art: the leakage current and the electrical property of the active layer in the display panel are easily interfered by the environmental electric field and the environmental light source, so that the stability of the display panel is poor.

Disclosure of Invention

An object of embodiments of the present invention is to provide an array substrate and a display panel, which can improve the interference of an environmental electric field and an environmental light source to the display panel, and improve the stability of the display panel.

In order to solve the above technical problem, an embodiment of the present invention provides an array substrate, including: the device comprises a substrate, a bottom gate insulating layer, an active layer, a top gate insulating layer and a top gate, wherein the bottom gate, the bottom gate insulating layer, the active layer, the top gate insulating layer and the top gate are sequentially stacked on the substrate; the array substrate further includes: a source electrode and a drain electrode, both of which are electrically connected to the active layer; the top gate comprises a first part and a second part, wherein the first part is positioned on one side, far away from the substrate, of the top gate insulating layer, and the second part extends from the edge of the first part and is in contact with the bottom gate; the width of the second portion is greater than or equal to the width of the first portion in a direction pointing along the source to the drain.

Embodiments of the present invention also provide a display panel including: the array substrate comprises the array substrate and an organic light emitting layer arranged on the array substrate.

In addition, the top gate further comprises a third part attached to the bottom gate, and the third part is connected with one end, far away from the first part, of the second part. Because the third part is attached to the bottom gate, namely, the bottom gate insulating layer and the top gate insulating layer on the other areas of the surface of the bottom gate except the area facing the active layer are removed, the contact area between the top gate and the bottom gate is larger, and the connection is more reliable.

In addition, the bottom gate insulating layer is provided with a connecting groove penetrating through the bottom gate insulating layer, and the width of the connecting groove is larger than or equal to that of the first part in the direction pointing to the drain electrode along the source electrode; the top gate further comprises a third part attached to the bottom gate insulating layer, the second part fills the connecting groove to be in contact with the bottom gate, and the third part is connected with the second part.

In addition, the semiconductor device further comprises a connecting groove penetrating through the bottom gate insulating layer and the top gate insulating layer, and the width of the connecting groove is larger than or equal to that of the first part in the direction pointing to the drain electrode along the source electrode; the top gate further comprises a third part attached to the top gate insulating layer, the second part fills the connecting groove to be in contact with the bottom gate, and the third part is connected with the second part.

In addition, the top gate insulating layer comprises a fourth part and a fifth part, the fourth part is located on one side, far away from the substrate, of the active layer, the fifth part is connected with the fourth part, the fifth part is in surface contact with one side, far away from the substrate, of the bottom gate insulating layer, and the second part is attached to the fifth part and the bottom gate insulating layer.

In addition, the top gate insulating layer is also attached to the surface of one side of the source electrode, which is far away from the substrate, and/or the surface of one side of the drain electrode, which is far away from the substrate. By the arrangement, the top gate can be prevented from being in error contact with the source electrode and/or the drain electrode in the preparation process of the top gate.

In addition, the first part is provided with an avoidance hole; the orthographic projection of the source electrode on the substrate is positioned in the orthographic projection of the edge of the avoidance hole on the substrate, and the orthographic projection of the first part on the substrate and the orthographic projection of the source electrode on the substrate are arranged at intervals; and/or the orthographic projection of the drain electrode on the substrate is positioned in the orthographic projection of the edge of the avoidance hole on the substrate, and the orthographic projection of the first part on the substrate and the orthographic projection of the drain electrode on the substrate are arranged at intervals. Because the orthographic projection of the first part on the substrate and the orthographic projection of the source electrode on the substrate are arranged at intervals, the top gate is not easily touched by mistake when an external power supply is connected with the source electrode, and the reliability is improved; similarly, the orthographic projection of the first part on the substrate and the orthographic projection of the drain electrode on the substrate are arranged at intervals, so that the top grid is not easily touched by mistake when an external power supply is connected with the drain electrode, and the reliability is improved.

In addition, in the stacking direction perpendicular to the substrate and the bottom gate, the distance range between the inner wall of the avoidance hole and the edge of the source electrode is greater than or equal to 2 millimeters; and/or in the stacking direction vertical to the substrate and the bottom gate, the distance range between the inner wall of the avoiding hole and the edge of the drain electrode is larger than or equal to 2 mm. According to the arrangement, the area of the top gate can be guaranteed to be large enough, the influence of an environment electric field and an environment light source above the top gate on an active layer can be well prevented, and the sufficient distance between the edge of the top gate and the source/drain electrode can be guaranteed, so that the problem of misconduction between the top gate and the source/drain electrode is avoided.

In addition, the width of the second portion in a direction along the source to the drain ranges from 7 micrometers to 8 micrometers. According to the arrangement, the influence of an environmental electric field and an environmental light source on the active layer can be improved, and the problem of misconduction caused by too short distance between the top gate and the source electrode and the drain electrode can be avoided.

Compared with the prior art, the array substrate of the embodiment of the invention comprises: the active layer is covered by the top gate and the bottom gate, and the influence of an environmental electric field in the vertical direction and an environmental light source on the active layer is improved by utilizing the top gate and the bottom gate; and because the top gate includes: the width of the second part is larger than or equal to that of the first part in the direction pointing to the drain electrode along the source electrode, namely, the second part of the top gate is widened to better shield the left side and the right side of the active layer, so that the influence of a lateral environment electric field and an environment light source on the active layer is improved; and the second part of the top gate is contacted with the bottom gate, so that the top gate and the bottom gate are in seamless connection, namely, the structure formed by the top gate and the bottom gate completely comprises the active layer from the side (the side is the surface vertical to the direction from the source electrode to the drain electrode), the influence of an environmental electric field and an environmental light source on the active layer is improved, and the stability of the display panel is further improved.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1 is a top view of an array substrate according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view of an array substrate taken along the A-A direction according to an embodiment of the present invention;

FIG. 3 is a cross-sectional view of an array substrate taken along the direction A-A according to another embodiment of the present invention;

FIG. 4 is a cross-sectional view of an array substrate taken along the A-A direction according to another embodiment of the present invention;

FIG. 5 is a cross-sectional view of an array substrate taken along the A-A direction according to another embodiment of the present invention;

fig. 6 is a top view of another array substrate with a top gate removed according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

An embodiment of the present invention relates to an array substrate, as shown in fig. 1 and 2, including: the structure comprises a substrate 11, a bottom gate 12, a bottom gate insulating layer 13, an active layer 14, a top gate insulating layer 15 and a top gate 16 which are sequentially stacked on the substrate 11; the array substrate further includes: a source electrode 17 and a drain electrode 18, wherein the source electrode 17 and the drain electrode 18 are electrically connected with the active layer 14, and specifically, the source electrode 17 and the drain electrode 18 can be attached to one side of the active layer 14 away from the substrate 11; the top gate 16 includes: a first portion 161 located on a side of the top gate insulating layer 15 away from the substrate 11, and a second portion 162 extending from an edge of the first portion 161 and contacting the bottom gate 12; the width of the second portion 162 is greater than or equal to the width of the first portion 161 in a direction X along the source 17 towards the drain 18.

Because the top gate 16 and the bottom gate 12 are respectively located at the upper side and the lower side of the active layer 14, the influence of the environmental electric field in the up-down direction and the environmental light source on the active layer 14 is improved by using the blocking effect of the top gate 16 and the bottom gate 12 on the upper side and the lower side of the active layer 14.

Since the width of the second portion 162 in the direction X along the source 17 toward the drain 18 is greater than or equal to the width of the first portion 161, that is, the second portion 162 of the top gate 16 is widened to better shield the left and right sides of the active layer 14, the influence of the side ambient electric field and the ambient light source on the active layer 14 is improved.

Moreover, the second portion 162 of the top gate 16 is in contact with the bottom gate 12, so that the top gate 16 and the bottom gate 12 are in seamless connection, that is, the top gate 16 and the bottom gate 12 together form a structure that completely encloses the active layer 14 from the side (the side is the surface perpendicular to the direction X from the source 17 to the drain 18), that is, the top gate 16 and the bottom gate 12 do not shield the active layer 14 from the upper, lower, left and right directions, so that the influence of the environmental electric field and the environmental light source on the active layer 14 is improved, and the stability of the display panel is further improved.

Regarding the size of the second portion 162, specifically, the width of the second portion 162 in the direction X along the source 17 toward the drain 18 ranges from 7 micrometers to 8 micrometers, which can improve the influence of the ambient electric field and the ambient light source on the active layer 14, and avoid the problem of mis-conduction caused by the top gate 16 being too close to the source 17 and the drain 18.

Wherein the second portion 162 may include: the first extension portion and the second extension portion respectively extend from two opposite sides of the first portion 161 toward the direction close to the substrate 11, both the first extension portion and the second extension portion are in contact with the bottom gate 12, and the size setting of both the first extension portion and the second extension portion can be referred to the size setting of the second portion 162.

As to the specific structure of the "second portion 162 is in contact with the bottom gate 12", the following scheme may be included:

in scheme 1, as shown in fig. 2, the top gate 16 may further include: and a third portion 163 extending from an end of the second portion 162 away from the first portion 161 toward a side away from the active layer 14, wherein the third portion 163 is attached to the bottom gate 12. In other words, the insulating layer (referred to as the bottom gate insulating layer 13 and/or the top gate insulating layer 15) is etched away in other directions except for the insulating layer still covering the drain/source extension direction, and the top gates 16 on both sides are directly located on the bottom gate 12.

In the embodiment 2, as shown in fig. 3, the array substrate may further include: the connection groove 19 penetrating the bottom gate insulating layer 13, a width of the connection groove 19 being greater than or equal to a width of the first portion 161 in a direction X along the source electrode 17 toward the drain electrode 18, the top gate 16 may further include: a third portion 163 attached on the bottom gate insulating layer 13, the second portion 162 filling up the connection groove 19 to contact the bottom gate 12, the third portion 163 being connected to a middle portion of the second portion 162.

In scheme 3, as shown in fig. 4, the array substrate may further include: the connection groove 19 penetrating through the bottom gate insulating layer 13 and the top gate insulating layer 15, a width of the connection groove 19 being greater than or equal to a width of the first portion 161 in a direction X along the source electrode 17 toward the drain electrode 18, and the top gate 16 may further include: the third portion 163 attached on the top gate insulating layer 15, the second portion 162 fills the connection groove 19 to contact the bottom gate 12, and the third portion 163 is connected to a middle portion of the second portion 162.

There are also various arrangements for the top gate insulating layer 15, such as:

in this embodiment, the top gate insulating layer 15 covers only the top surface and the side surface of the active layer 14, and specifically, the top gate insulating layer 15 may include: a fourth portion 151 located on the side of the active layer 14 away from the substrate 11, and a fifth portion 152 connected to the fourth portion 151, wherein the fifth portion 152 is in contact with the surface of the bottom gate insulating layer 13 away from the substrate 11, and the second portion 162 is attached to the fifth portion 152 and the bottom gate insulating layer 13 and is in contact with the bottom gate 12, as can be seen in fig. 2.

In another embodiment, the top gate insulating layer 15 covers the top surface and the side surfaces of the active layer 14 and the side surfaces of the bottom gate insulating layer 13, specifically, the fifth portion 152 contacts the surface of the bottom gate 12 on the side away from the substrate 11, and the second portion 162 is attached on the fifth portion 152 and contacts the bottom gate 12, as can be seen in fig. 5.

Regarding the insulating layer on the surface of the source electrode 17/the drain electrode 18, there are at least the following two schemes:

first, the insulation of the source 17/drain 18 surfaces may be achieved by the top gate insulating layer 15, that is, as shown in fig. 6, the top gate insulating layer 15 may also be attached on the surface of the source 17 on the side away from the substrate 11 and on the surface of the drain 18 on the side away from the substrate 11. Of course, the top gate insulating layer 15 may also be attached only to the surface of the source 17 on the side away from the substrate 11 (and not to the surface of the drain 18 on the side away from the substrate 11), or only to the surface of the drain 18 on the side away from the substrate 11 (and not to the surface of the source 17 on the side away from the substrate 11).

Since the top gate insulating layer 15 is provided between the first portion 161 of the top gate 16 and the source/drain electrodes 17 and 18 to avoid electrical connection between the top gate 16 and the source/drain electrodes 17 and 18, the first portion 161 of the top gate 16 may be provided with a larger width. Preferably, the first portion 161 may have an avoidance hole 20, an orthographic projection of the source 17 on the substrate 11 is located within an orthographic projection of an edge of the avoidance hole 20 on the substrate 11, and an orthographic projection of the first portion 161 on the substrate 11 is spaced from an orthographic projection of the source 17 on the substrate 11, and/or an orthographic projection of the drain 18 on the substrate 11 is located within an orthographic projection of an edge of the avoidance hole 20 on the substrate 11, and an orthographic projection of the first portion 161 on the substrate 11 is spaced from an orthographic projection of the drain 18 on the substrate 11. Since the orthographic projection of the first part 161 on the substrate 11 and the orthographic projection of the source electrode 17 on the substrate 11 are arranged at intervals, the top grid 16 is not easily touched by mistake when an external power supply is connected with the source electrode 17, and the reliability is improved; similarly, the orthographic projection of the first portion 161 on the substrate 11 and the orthographic projection of the drain 18 on the substrate 11 are arranged at intervals, so that the top grid 16 is not easily touched by mistake when an external power supply is connected with the drain 18, and the reliability is improved.

Further, in the stacking direction Y perpendicular to the substrate 11 and the bottom gate 12, the range of the distance w between the inner wall of the avoiding hole 20 and the edge of the source 17 is greater than or equal to 2 mm, and optionally, may be 2 mm to 3 mm, so that not only can the area of the top gate 16 be ensured to be large enough to well block the influence of an above ambient electric field and an ambient light source on the active layer 14, but also a large enough distance can be ensured between the edge of the top gate 16 and the source 17, thereby avoiding the problem of mis-conduction between the top gate 16 and the source 17; and/or, in the stacking direction Y perpendicular to the substrate 11 and the bottom gate 12, a distance range between an inner wall of the avoiding hole 20 and an edge of the drain 18 is greater than or equal to 2 mm, optionally, may be 2 mm to 3 mm, and the specific technical effects are similar and will not be described herein again.

Of course, the first portion 161 of the narrower top gate 16 may be provided, in which case the first portion 161 does not extend to the source 17/drain 18, and the first portion 161 and the source 17/drain 18 are spaced apart, so that the electrical connection between the first portion 161 and the source 17/drain 18 may also be avoided.

Secondly, the insulation of the surface of the source electrode 17/the drain electrode 18 may be achieved by an additional passivation layer (not shown), that is, the array substrate may further include: and the passivation layer is positioned on the side of the top gate 16, which is far away from the substrate 11, and is also attached to the side of the source electrode 17, which is far away from the substrate 11, and the side of the drain electrode 18, which is far away from the substrate 11.

Specifically, as shown in fig. 1, a narrower first portion 161 of the top gate 16 may be provided to avoid electrical connection between the top gate 16 and the source 17/drain 18, in which case the first portion 161 does not extend to the source 17/drain 18, and the first portion 161 is spaced apart from the source 17/drain 18.

Specifically, the top gate 16 is a transparent electrode, the transparent electrode is an ITO electrode, an IZO electrode or a thin metal electrode, the active layer 14 is made of one or a combination of amorphous silicon-based semiconductor, polysilicon-based semiconductor and zinc oxide-based semiconductor, the bottom gate 12 and the source/drain 18 are made of one or a combination of molybdenum, titanium, aluminum and copper, the bottom gate insulating layer 13 is made of silicon nitride, silicon oxide or a combination of silicon nitride and silicon oxide, and the top gate insulating layer 15 or the passivation layer is made of silicon nitride, silicon oxide or a combination of silicon nitride and silicon oxide.

A second embodiment of the present invention provides a display panel including: the array substrate comprises the array substrate and an organic light emitting layer arranged on the array substrate.

Specifically, the display panel may further include: the array substrate comprises a planarization layer, an anode, a pixel defining layer and a cathode, wherein the planarization layer is arranged on the array substrate, the anode is arranged on the planarization layer and penetrates through the planarization layer to be connected with the array substrate, an organic light emitting layer is arranged on the anode, the pixel defining layer is arranged around the organic light emitting layer, the cathode is arranged on the organic light emitting layer and the pixel defining layer, and the anode and the cathode drive the organic light emitting layer to emit light together.

A third embodiment of the present invention provides a display device including: the display panel, the color filter and the packaging layer are sequentially stacked on the display panel.

Compared with the prior art, the top gate 16 and the bottom gate 12 are respectively positioned at the upper side and the lower side of the active layer 14, and the influence of an environmental electric field in the upper-lower direction and an environmental light source on the active layer 14 is improved by utilizing the blocking effect of the top gate 16 and the bottom gate 12 on the upper side and the lower side of the active layer 14; since the width of the second portion 162 in the direction X along the source 17 toward the drain 18 is greater than or equal to the width of the first portion 161, that is, the second portion 162 of the top gate 16 is widened to better shield the left and right sides of the active layer 14, the influence of the side ambient electric field and the ambient light source on the active layer 14 is improved; moreover, since the second portion 162 of the top gate 16 is in contact with the bottom gate 12, the top gate 16 and the bottom gate 12 are seamlessly connected, i.e., the active layer 14 is completely enclosed from the side, and the stability of the display panel is further improved.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.