阅读说明：本技术 三态存储器寻址电路、读取电路、装置及存储器 (Addressing circuit, reading circuit and device of tri-state memory and memory ) 是由 赵巍胜 魏少芊 邓尔雅 康旺 于 2021-01-26 设计创作，主要内容包括：本发明提供三态存储器寻址电路、读取电路、装置及存储器,本发明采用PDM的方式选择数据匹配的最优结果,避免了传统TCAM中由PE模块带来的大量不必要的能量消耗。同时将X态与参考单元结合,节省了数据长度信息存储单元带来的面积消耗,又能够快速的判断出数据的最优匹配结果。最后由于数据最优匹配结果是通过判断‘X’态的位数,因此,数据存储中‘X’态的位置不受限。(The invention provides a addressing circuit, a reading circuit, a device and a memory of a ternary memory, which adopt a PDM mode to select an optimal result of data matching and avoid a large amount of unnecessary energy consumption brought by a PE module in the traditional TCAM. Meanwhile, the X state is combined with the reference unit, so that the area consumption caused by the data length information storage unit is saved, and the optimal matching result of the data can be rapidly judged. Finally, the data optimal matching result is obtained by judging the number of the bits of the 'X' state, so that the position of the 'X' state in the data storage is not limited.)

1. A tri-state memory addressing circuit, comprising:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

and the ends of the other first MTJ and the other second MTJ far away from the corresponding connecting line are coupled with an external reading circuit.

2. A tri-state memory addressing apparatus comprising a tri-state memory addressing circuit, said tri-state memory addressing circuit comprising:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

and the ends of the other first MTJ and the other second MTJ far away from the corresponding connecting line are coupled with an external reading circuit.

3. A tri-state memory addressing read circuit comprising a tri-state memory addressing circuit and a read circuit, the tri-state memory addressing circuit comprising:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

the reading circuit is coupled with one end of the other first MTJ and the other second MTJ far away from the corresponding connecting line.

4. The tri-state memory addressed read circuit according to claim 3, wherein the read circuit comprises:

the input ends of two first transistors in the first transistor pair are both coupled with a high-level line, the output ends of the two first transistors in the first transistor pair are both coupled with a first node, and the control end of one first transistor in the first transistor pair is coupled with a pre-charging voltage line;

the input ends of two second transistors in the second transistor pair are coupled with the output end of the first single transistor, the input end of the first single transistor is coupled with a second node, and the control end of one second transistor is coupled with the other precharging voltage line;

a third transistor pair, wherein an output terminal of one of the third transistors is coupled to the second node, and an output terminal of the other third transistor is coupled to a third node;

a second single transistor, wherein an output terminal of the second single transistor is coupled to the first node, and a control terminal of the second single transistor is coupled to a control terminal of the first single transistor;

a fourth transistor pair, wherein an output terminal of one of the fourth transistors of the fourth transistor pair is coupled to the second node, an output terminal of the other fourth transistor of the fourth transistor pair is coupled to the third node, and a control terminal of the one of the fourth transistors and a control terminal of the other third transistor of the fourth transistor pair are both coupled to a low-level line;

the input ends of the two third transistors are coupled with the output end of the storage unit, and the input ends of the two fourth transistors are coupled with the output end of the reference unit;

the first node is coupled to control terminals of the other of the first transistors and the other of the second transistors.

5. The tri-state memory addressed read circuit as claimed in claim 4, wherein the transistor is a PMOS transistor or an NMOS transistor.

6. A tri-state memory addressed read apparatus, comprising: a tri-state memory addressing circuit and a read circuit, the tri-state memory addressing circuit comprising:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

the reading circuit is coupled with one end of the other first MTJ and the other second MTJ far away from the corresponding connecting line.

7. The tri-state memory addressed read device according to claim 6, wherein the read circuit comprises:

the input ends of two first transistors in the first transistor pair are both coupled with a high-level line, the output ends of the two first transistors in the first transistor pair are both coupled with a first node, and the control end of one first transistor in the first transistor pair is coupled with a pre-charging voltage line;

the input ends of two second transistors in the second transistor pair are coupled with the output end of the first single transistor, the input end of the first single transistor is coupled with a second node, and the control end of one second transistor is coupled with the other precharging voltage line;

a third transistor pair, wherein an output terminal of one of the third transistors is coupled to the second node, and an output terminal of the other third transistor is coupled to a third node;

a second single transistor, wherein an output terminal of the second single transistor is coupled to the first node, and a control terminal of the second single transistor is coupled to a control terminal of the first single transistor;

a fourth transistor pair, wherein an output terminal of one of the fourth transistors of the fourth transistor pair is coupled to the second node, an output terminal of the other fourth transistor of the fourth transistor pair is coupled to the third node, and a control terminal of the one of the fourth transistors and a control terminal of the other third transistor of the fourth transistor pair are both coupled to a low-level line;

the input ends of the two third transistors are coupled with the output end of the storage unit, and the input ends of the two fourth transistors are coupled with the output end of the reference unit;

the first node is coupled to control terminals of the other of the first transistors and the other of the second transistors.

8. The tri-state memory addressed reading apparatus according to claim 7, wherein the transistor is a PMOS transistor or an NMOS transistor.

9. A tri-state memory, comprising: the device comprises a tristate memory addressing circuit, a tristate memory addressing reading circuit and a peripheral circuit;

the tri-state memory addressing circuit comprises:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

the reading circuit is coupled with one end of the other first MTJ and the other second MTJ far away from the corresponding connecting line;

the peripheral circuit is used for processing and transmitting the matching result.

10. The tri-state memory of claim 9, wherein the read circuit comprises:

the input ends of two first transistors in the first transistor pair are both coupled with a high-level line, the output ends of the two first transistors in the first transistor pair are both coupled with a first node, and the control end of one first transistor in the first transistor pair is coupled with a pre-charging voltage line;

the input ends of two second transistors in the second transistor pair are coupled with the output end of the first single transistor, the input end of the first single transistor is coupled with a second node, and the control end of one second transistor is coupled with the other precharging voltage line;

a third transistor pair, wherein an output terminal of one of the third transistors is coupled to the second node, and an output terminal of the other third transistor is coupled to a third node;

a second single transistor, wherein an output terminal of the second single transistor is coupled to the first node, and a control terminal of the second single transistor is coupled to a control terminal of the first single transistor;

a fourth transistor pair, wherein an output terminal of one of the fourth transistors of the fourth transistor pair is coupled to the second node, an output terminal of the other fourth transistor of the fourth transistor pair is coupled to the third node, and a control terminal of the one of the fourth transistors and a control terminal of the other third transistor of the fourth transistor pair are both coupled to a low-level line;

the input ends of the two third transistors are coupled with the output end of the storage unit, and the input ends of the two fourth transistors are coupled with the output end of the reference unit;

the first node is coupled to control terminals of the other of the first transistors and the other of the second transistors.

Technical Field

The present invention relates to the field of semiconductors, and more particularly, to a tri-state memory addressing circuit, a read circuit, a device, and a memory.

Background

A Ternary Content Addressable Memory (TCAM) is a Memory capable of storing three states, namely logic '0', logic '1' and unknown state 'X'. The method is widely applied to the occasions needing accurate matching or fuzzy matching, such as router address storage, lookup table deep packet inspection (deep packet inspection), network intrusion inspection/protection systems, the Internet of things, wireless sensor networks (wireless sensor networks), face recognition (face recognition), vehicle license plate recognition (vehicle license plate recognition), and the like.

The conventional memory only stores two data states, logic '0' and logic '1', while the TCAM has an 'X' state. So TCAM needs to determine the optimal matching result by using a Priority Encoder (PE) after matching to multiple correct results. However, the PE has many problems, such as that in the TCAM structure using the PE, a large amount of power consumption is wasted on rearrangement of contents, thereby reducing the operation speed and increasing the operation power consumption. And with the increasing capacity of TCAMs, the area and power consumption consumed by PE modules has become non-negligible. In response to the various problems of PE, designers propose a Priority-Decision in Memory (PDM) structure. The PDM determines the optimal solution by three steps: finding out a plurality of matched data; comparing the lengths of the data S to obtain the longest length information; finding out the data corresponding to the longest length and outputting the address. However, besides storing data, the PDM approach also needs to store length information of data, which causes additional area consumption.

Disclosure of Invention

The invention provides a addressing circuit, a reading circuit, a device and a memory of a three-state memory, wherein the addressing circuit of the three-state memory comprises: the device comprises a reference unit, a storage unit and an X-state judgment unit; the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction; one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not; one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled; and the ends of the other first MTJ and the other second MTJ far away from the corresponding connecting line are coupled with an external reading circuit. The invention adopts the PDM mode to select the optimal result of data matching, thereby avoiding a great deal of unnecessary energy consumption brought by a PE module in the traditional TCAM. Meanwhile, the X state is combined with the reference unit, so that the area consumption caused by the data length information storage unit is saved, and the optimal matching result of the data can be rapidly judged. Finally, the data optimal matching result is obtained by judging the number of the bits of the 'X' state, so that the position of the 'X' state in the data storage is not limited.

A first aspect of the invention provides a tristate memory addressing circuit comprising:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

and the ends of the other first MTJ and the other second MTJ far away from the corresponding connecting line are coupled with an external reading circuit.

A second aspect of the invention provides a tristate memory addressing arrangement comprising a tristate memory addressing circuitry, said tristate memory addressing circuitry comprising:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

and the ends of the other first MTJ and the other second MTJ far away from the corresponding connecting line are coupled with an external reading circuit.

A third aspect of the present invention provides a tristate memory addressing and reading circuit, comprising a tristate memory addressing circuit and a reading circuit, wherein the tristate memory addressing circuit comprises:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

the reading circuit is coupled with one end of the other first MTJ and the other second MTJ far away from the corresponding connecting line.

In a preferred embodiment, the read circuit comprises:

the input ends of two first transistors in the first transistor pair are both coupled with a high-level line, the output ends of the two first transistors in the first transistor pair are both coupled with a first node, and the control end of one first transistor in the first transistor pair is coupled with a pre-charging voltage line;

the input ends of two second transistors in the second transistor pair are coupled with the output end of the first single transistor, the input end of the first single transistor is coupled with a second node, and the control end of one second transistor is coupled with the other precharging voltage line;

a third transistor pair, wherein an output terminal of one of the third transistors is coupled to the second node, and an output terminal of the other third transistor is coupled to a third node;

a second single transistor, wherein an output terminal of the second single transistor is coupled to the first node, and a control terminal of the second single transistor is coupled to a control terminal of the first single transistor;

a fourth transistor pair, wherein an output terminal of one of the fourth transistors of the fourth transistor pair is coupled to the second node, an output terminal of the other fourth transistor of the fourth transistor pair is coupled to the third node, and a control terminal of the one of the fourth transistors and a control terminal of the other third transistor of the fourth transistor pair are both coupled to a low-level line;

the input ends of the two third transistors are coupled with the output end of the storage unit, and the input ends of the two fourth transistors are coupled with the output end of the reference unit;

the first node is coupled to control terminals of the other of the first transistors and the other of the second transistors.

In a preferred embodiment, the transistor is a PMOS transistor or an NMOS transistor.

The fourth aspect of the present invention provides a tri-state memory addressing and reading apparatus, comprising: a tri-state memory addressing circuit and a read circuit, the tri-state memory addressing circuit comprising:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

the reading circuit is coupled with one end of the other first MTJ and the other second MTJ far away from the corresponding connecting line.

In a preferred embodiment, the read circuit comprises:

the input ends of two first transistors in the first transistor pair are both coupled with a high-level line, the output ends of the two first transistors in the first transistor pair are both coupled with a first node, and the control end of one first transistor in the first transistor pair is coupled with a pre-charging voltage line;

the input ends of two second transistors in the second transistor pair are coupled with the output end of the first single transistor, the input end of the first single transistor is coupled with a second node, and the control end of one second transistor is coupled with the other precharging voltage line;

a third transistor pair, wherein an output terminal of one of the third transistors is coupled to the second node, and an output terminal of the other third transistor is coupled to a third node;

a second single transistor, wherein an output terminal of the second single transistor is coupled to the first node, and a control terminal of the second single transistor is coupled to a control terminal of the first single transistor;

a fourth transistor pair, wherein an output terminal of one of the fourth transistors of the fourth transistor pair is coupled to the second node, an output terminal of the other fourth transistor of the fourth transistor pair is coupled to the third node, and a control terminal of the one of the fourth transistors and a control terminal of the other third transistor of the fourth transistor pair are both coupled to a low-level line;

the input ends of the two third transistors are coupled with the output end of the storage unit, and the input ends of the two fourth transistors are coupled with the output end of the reference unit;

the first node is coupled to control terminals of the other of the first transistors and the other of the second transistors.

In a preferred embodiment, the transistor is a PMOS transistor or an NMOS transistor.

A fifth aspect of the present invention provides a tri-state memory comprising: the device comprises a tristate memory addressing circuit, a tristate memory addressing reading circuit and a peripheral circuit;

the tri-state memory addressing circuit comprises:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

the reading circuit is coupled with one end of the other first MTJ and the other second MTJ far away from the corresponding connecting line;

the peripheral circuit is used for processing and transmitting the matching result.

In a preferred embodiment, the read circuit comprises:

the input ends of two first transistors in the first transistor pair are both coupled with a high-level line, the output ends of the two first transistors in the first transistor pair are both coupled with a first node, and the control end of one first transistor in the first transistor pair is coupled with a pre-charging voltage line;

the input ends of two second transistors in the second transistor pair are coupled with the output end of the first single transistor, the input end of the first single transistor is coupled with a second node, and the control end of one second transistor is coupled with the other precharging voltage line;

a third transistor pair, wherein an output terminal of one of the third transistors is coupled to the second node, and an output terminal of the other third transistor is coupled to a third node;

a second single transistor, wherein an output terminal of the second single transistor is coupled to the first node, and a control terminal of the second single transistor is coupled to a control terminal of the first single transistor;

a fourth transistor pair, wherein an output terminal of one of the fourth transistors of the fourth transistor pair is coupled to the second node, an output terminal of the other fourth transistor of the fourth transistor pair is coupled to the third node, and a control terminal of the one of the fourth transistors and a control terminal of the other third transistor of the fourth transistor pair are both coupled to a low-level line;

the input ends of the two third transistors are coupled with the output end of the storage unit, and the input ends of the two fourth transistors are coupled with the output end of the reference unit;

the first node is coupled to control terminals of the other of the first transistors and the other of the second transistors.

The invention has the beneficial effects that:

the invention provides a addressing circuit, a reading circuit, a device and a memory of a three-state memory, wherein the addressing circuit of the three-state memory comprises: the device comprises a reference unit, a storage unit and an X-state judgment unit; the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction; one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not; one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled; and the ends of the other first MTJ and the other second MTJ far away from the corresponding connecting line are coupled with an external reading circuit. The invention adopts the PDM mode to select the optimal result of data matching, thereby avoiding a great deal of unnecessary energy consumption brought by a PE module in the traditional TCAM. Meanwhile, the X state is combined with the reference unit, so that the area consumption caused by the data length information storage unit is saved, and the optimal matching result of the data can be rapidly judged. Finally, the data optimal matching result is obtained by judging the number of the bits of the 'X' state, so that the position of the 'X' state in the data storage is not limited.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a diagram illustrating a prior art tri-state memory structure according to an embodiment of the present invention;

FIG. 2 is a second schematic diagram of a prior art tri-state memory structure according to an embodiment of the present invention;

FIG. 3 is a third schematic diagram of a prior art tri-state memory structure according to an embodiment of the present invention;

FIG. 4 is a fourth schematic diagram of a prior art tri-state memory structure according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a reading circuit of a tri-state memory addressing circuit according to an embodiment of the present invention;

fig. 6 is a schematic circuit diagram of a memory according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

A Ternary Content Addressable Memory (TCAM) is a Memory capable of storing three states, namely logic '0', logic '1' and unknown state 'X'. The method is widely applied to the occasions needing accurate matching or fuzzy matching, such as router address storage, lookup table deep packet inspection (deep packet inspection), network intrusion inspection/protection systems, the Internet of things, wireless sensor networks (wireless sensor networks), face recognition (face recognition), vehicle license plate recognition (vehicle license plate recognition), and the like.

The conventional memory only stores two data states, logic '0' and logic '1', while the TCAM has an 'X' state. So TCAM needs to determine the optimal matching result by using a Priority Encoder (PE) after matching to multiple correct results. However, the PE has many problems, such as that in the TCAM structure using the PE, a large amount of power consumption is wasted on rearrangement of contents, thereby reducing the operation speed and increasing the operation power consumption. And with the increasing capacity of TCAMs, the area and power consumption consumed by PE modules has become non-negligible. In response to the various problems of PE, designers propose a Priority-Decision in Memory (PDM) structure. As shown in fig. 1, the PDM determines the optimal solution by three steps: finding out a plurality of matched data; comparing the lengths of the data S to obtain the longest length information; finding out the data corresponding to the longest length and outputting the address. However, besides storing data, the PDM approach also needs to store length information of data, which causes additional area consumption.

Fig. 2 shows a first prior art solution, as shown in fig. 2, in which the data state in the TCAM circuit is stored in two MTJs. When a logic '1' is sought and the data stored in the device is '1' (i.e., the left MTJ is the AP state and the right MTJ is the P state), SL is high ('1'), \\ SL is low ('0'), and SrL is low. By dividing the voltage of the branch (devices 205, M3, M5), the voltage at the node X1 is low, the voltage at the node X2 is 'GND', the M1 transistor and the M2 transistor are both turned off, and ML maintains high level, indicating data matching. When a logic '1' is found and the stored data is '0' (i.e. the MTJ state on the left is P and the MTJ state on the right is AP), the voltage at the node X1 is high due to the voltage division of the branch (the devices 205, M3, M5), the M1 transistor is turned on, and ML discharges through the M1 transistor, indicating data mismatch.

As shown in fig. 3, another prior art is a non-volatile TCAM structure consisting of 15 transistors and 4 MTJs. The three states of logic '0', logic '1', and 'X' are represented by using 4 different state combinations of MTJs. Reading three states is accomplished by configuring the voltage states of both SL and SLB lines. The N6 and N7 transistors are used in the write operation.

Third, the prior art improves the power consumption and speed problem in TCAM by adding data length search operation in a decision-making manner using PIM, as shown in fig. 4. Three data states are stored in the m1-4 four MTJs. m5 and m6 are used to store data length information. By configuring the SL, SLB and SM voltages, three steps of PDM operation are achieved, as shown in fig. 4.

However, the three solutions have the following disadvantages:

the first disadvantage of the scheme is that: since the read margin (sensing margin) is small, the M2 and M3 threshold voltages need to be precisely controlled, and reliability is not high.

The second scheme has the following defects: after the reading operation of the three states is completed, the optimal matching result still needs to be selected by one PE module. The power consumption and speed problems caused by the PE module itself are not solved.

The three disadvantages of the scheme are as follows: the three data states and data lengths are represented by 6 MTJs, which occupy too much area.

In this regard, the present invention provides a tri-state memory addressing circuit, e.g., 5, comprising:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

and the ends of the other first MTJ and the other second MTJ far away from the corresponding connecting line are coupled with an external reading circuit.

The invention provides a addressing circuit of a ternary memory, which selects the optimal result of data matching by adopting a PDM mode and avoids a large amount of unnecessary energy consumption brought by a PE module in the traditional TCAM. Meanwhile, the X state is combined with the reference unit, so that the area consumption caused by the data length information storage unit is saved, and the optimal matching result of the data can be rapidly judged. Finally, the data optimal matching result is obtained by judging the number of the bits of the 'X' state, so that the position of the 'X' state in the data storage is not limited.

It is to be understood that "coupled" in the context of embodiments of the present invention may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements may not be in direct contact.

Transistors of the present invention include, but are not limited to, conventional transistors, tunneling field effect transistors, finfets, vertical full-ring gate transistors.

The MTJ is referred to herein as a magnetic tunnel junction whose shape includes, but is not limited to, square, rectangular, circular, or elliptical.

The switch element and the transistor in the invention can be selected from NMOS selection transistor and/or PMOS selection transistor, and the PMOS selection transistor and the NMOS selection transistor are metal oxide semiconductor transistors.

In some embodiments, the X-state determining unit includes: and the PMOS tube and the NMOS tube form an inverter.

In a second aspect, an embodiment of the present invention provides a tri-state memory addressing apparatus, including a tri-state memory addressing circuit, as shown in fig. 5, the tri-state memory addressing circuit includes:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

and the ends of the other first MTJ and the other second MTJ far away from the corresponding connecting line are coupled with an external reading circuit.

In some embodiments, the X-state determining unit includes: and the PMOS tube and the NMOS tube form an inverter.

The invention provides a ternary memory addressing reading circuit, which adopts a PDM mode to select the optimal result of data matching, and avoids a large amount of unnecessary energy consumption brought by a PE module in the traditional TCAM. Meanwhile, the X state is combined with the reference unit, so that the area consumption caused by the data length information storage unit is saved, and the optimal matching result of the data can be rapidly judged. Finally, the data optimal matching result is obtained by judging the number of the bits of the 'X' state, so that the position of the 'X' state in the data storage is not limited.

An embodiment of the third aspect of the present invention provides a tri-state memory addressing and reading circuit, as shown in fig. 5, including a tri-state memory addressing circuit and a reading circuit, where the tri-state memory addressing circuit includes:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

the reading circuit is coupled with one end of the other first MTJ and the other second MTJ far away from the corresponding connecting line.

In some embodiments, the X-state determining unit includes: and the PMOS tube and the NMOS tube form an inverter.

In some embodiments, the read circuit comprises: a differential amplifier circuit.

The input ends of two first transistors in the first transistor pair are both coupled with a high-level line, the output ends of the two first transistors in the first transistor pair are both coupled with a first node, and the control end of one first transistor in the first transistor pair is coupled with a pre-charging voltage line;

the input ends of two second transistors in the second transistor pair are coupled with the output end of the first single transistor, the input end of the first single transistor is coupled with a second node, and the control end of one second transistor is coupled with the other precharging voltage line;

a third transistor pair, wherein an output terminal of one of the third transistors is coupled to the second node, and an output terminal of the other third transistor is coupled to a third node;

a second single transistor, wherein an output terminal of the second single transistor is coupled to the first node, and a control terminal of the second single transistor is coupled to a control terminal of the first single transistor;

a fourth transistor pair, wherein an output terminal of one of the fourth transistors of the fourth transistor pair is coupled to the second node, an output terminal of the other fourth transistor of the fourth transistor pair is coupled to the third node, and a control terminal of the one of the fourth transistors and a control terminal of the other third transistor of the fourth transistor pair are both coupled to a low-level line;

the input ends of the two third transistors are coupled with the output end of the storage unit, and the input ends of the two fourth transistors are coupled with the output end of the reference unit;

the first node is coupled to control terminals of the other of the first transistors and the other of the second transistors.

In a preferred embodiment, the transistor is a PMOS transistor or an NMOS transistor.

As shown in connection with fig. 4, the data reading process: PRE is a precharge signal, and simultaneously precharges the nodes OUTB and OUT through P1 and P2, respectively, when the entire system precharges the ML. As shown in fig. 2, when the MTJ state of the reference cell is AP + P (top to bottom), the data of the memory cell needs to be compared with the input data, XL voltage is low, and the read circuit normally reads the data. When the reference cell resistance is in the P + AP state, denoted as the X state, as shown in FIG. 2, i.e., the cell's stored data does not need to be compared to the input data, the XL voltage is high. XL controls ML to remain high through the peripheral circuitry.

As shown in Table 1, the data in Table 1 is looked up

As shown in table 1, the circuit provided by the present invention can implement the above data lookup, the reference cell is composed of M0 and M1 in fig. 2 connected in series, the memory cell is composed of M2 and M3 in fig. 2 connected in series, care: represents data of ' 0 ' or ' 1 ', don't care: represents ' X ', ML ═ 1 ': representing data match, ML ═ 0': representing a data mismatch.

The invention provides a ternary memory addressing reading circuit, which adopts a PDM mode to select the optimal result of data matching, and avoids a large amount of unnecessary energy consumption brought by a PE module in the traditional TCAM. Meanwhile, the X state is combined with the reference unit, so that the area consumption caused by the data length information storage unit is saved, and the optimal matching result of the data can be rapidly judged. Finally, the data optimal matching result is obtained by judging the number of the bits of the 'X' state, so that the position of the 'X' state in the data storage is not limited.

A fourth aspect of the present invention provides a tri-state memory addressing and reading apparatus, as shown in fig. 5, including: a tri-state memory addressing circuit and a read circuit, the tri-state memory addressing circuit comprising:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

the reading circuit is coupled with one end of the other first MTJ and the other second MTJ far away from the corresponding connecting line.

In some embodiments, the read circuit comprises: a differential amplifier circuit.

The input ends of two first transistors in the first transistor pair are both coupled with a high-level line, the output ends of the two first transistors in the first transistor pair are both coupled with a first node, and the control end of one first transistor in the first transistor pair is coupled with a pre-charging voltage line;

the input ends of two second transistors in the second transistor pair are coupled with the output end of the first single transistor, the input end of the first single transistor is coupled with a second node, and the control end of one second transistor is coupled with the other precharging voltage line;

a third transistor pair, wherein an output terminal of one of the third transistors is coupled to the second node, and an output terminal of the other third transistor is coupled to a third node;

a second single transistor, wherein an output terminal of the second single transistor is coupled to the first node, and a control terminal of the second single transistor is coupled to a control terminal of the first single transistor;

a fourth transistor pair, wherein an output terminal of one of the fourth transistors of the fourth transistor pair is coupled to the second node, an output terminal of the other fourth transistor of the fourth transistor pair is coupled to the third node, and a control terminal of the one of the fourth transistors and a control terminal of the other third transistor of the fourth transistor pair are both coupled to a low-level line;

the input ends of the two third transistors are coupled with the output end of the storage unit, and the input ends of the two fourth transistors are coupled with the output end of the reference unit;

the first node is coupled to control terminals of the other of the first transistors and the other of the second transistors.

An embodiment of a fifth aspect of the present invention provides a tri-state memory, as shown in fig. 6, including: the device comprises a tristate memory addressing circuit, a tristate memory addressing reading circuit and a peripheral circuit;

the tri-state memory addressing circuit comprises:

the device comprises a reference unit, a storage unit and an X-state judgment unit;

the reference unit comprises two first MTJs connected in series, the storage unit comprises two second MTJs connected in series, and the two first MTJs are opposite in magnetization direction;

one end of the X-state judging unit is coupled to a connecting line between the two first MTJs, and the other end of the X-state judging unit is coupled to a connecting line between the two second MTJs and used for informing an external processing system whether bit corresponding to the addressing circuit is in fuzzy matching or not;

one end of one of the first MTJ and one end of one of the second MTJ, which are far away from the corresponding connecting line, are respectively coupled with an input end of a switch element, an output end of the switch element is grounded, and control ends of the two switch elements are mutually coupled;

the reading circuit is coupled with one end of the other first MTJ and the other second MTJ far away from the corresponding connecting line;

the peripheral circuit is used for processing and transmitting the matching result.

The invention adopts the PDM mode to select the optimal result of data matching, thereby avoiding a great deal of unnecessary energy consumption brought by a PE module in the traditional TCAM. Meanwhile, the X state is combined with the reference unit, so that the area consumption caused by the data length information storage unit is saved, and the optimal matching result of the data can be rapidly judged. Finally, the data optimal matching result is obtained by judging the number of the bits of the 'X' state, so that the position of the 'X' state in the data storage is not limited.

In the description of the present specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present specification. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.

Furthermore, the various embodiments or examples and features of the various embodiments or examples described in this specification can be combined and combined by those skilled in the art without contradiction. The above description is only an embodiment of the present disclosure, and is not intended to limit the present disclosure. Various modifications and changes may occur to those skilled in the art to which the embodiments of the present disclosure pertain. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present specification should be included in the scope of the claims of the embodiments of the present specification.