阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 菅原昭雄 今本哲広 渡邉稔史 栫真己 増田考平 吉原正浩 安彦尚文 于 2018-11-06 设计创作，主要内容包括：实施方式的半导体存储装置包含多个平面与定序器。多个平面分别具有多个作为存储单元的集合的块。定序器执行第1动作、及比第1动作短的第2动作。定序器当接收指示第1动作的执行的第1指令集时执行所述第1动作。定序器在执行第1动作的期间接收指示第2动作的执行的第2指令集时,基于作为第1动作对象的块的地址与作为第2动作对象的块的地址,暂停第1动作而执行第2动作或与第1动作并行地执行第2动作。(The semiconductor memory device of an embodiment includes a plurality of planes and a sequencer. The planes each have a plurality of blocks as a set of storage units. The sequencer performs action 1 and action 2, which is shorter than action 1. The sequencer performs the 1 st action when receiving the 1 st instruction set indicating execution of the 1 st action. When the sequencer receives a 2 nd instruction set instructing execution of a 2 nd action while executing the 1 st action, the sequencer suspends the 1 st action and executes the 2 nd action or executes the 2 nd action in parallel with the 1 st action, based on an address of a block to be operated 1 and an address of a block to be operated 2.)

1. A semiconductor memory device includes:

a plurality of planes having a plurality of blocks each being a set of storage units; and

a sequencer that executes a 1 st action and a 2 nd action shorter than the 1 st action;

the sequencer executes the 1 st action upon receiving a 1 st instruction set instructing execution of the 1 st action, and when receiving a 2 nd instruction set instructing execution of the 2 nd action during execution of the 1 st action, suspends the 1 st action and executes the 2 nd action or executes the 2 nd action in parallel with the 1 st action based on an address of a block to which the 1 st action is to be directed and an address of a block to which the 2 nd action is to be directed.

2. The semiconductor storage device according to claim 1, further provided with a voltage generation circuit including 1 st and 2 nd driver modules,

the plurality of planes includes 1 st and 2 nd planes powered by the 1 st driver module and 3 rd and 4 th planes powered by the 2 nd driver module,

the sequencer is configured to execute the 1 st action for targeting the block included in the 1 st plane,

upon receiving a 2 nd instruction set that targets a block included in the 1 st plane, suspending the 1 st action and executing the 2 nd action,

and a step of executing the 2 nd action in parallel with the 1 st action when receiving a 2 nd instruction set that targets a block included in any one of the 2 nd plane, the 3 rd plane, and the 4 th plane.

3. The semiconductor storage device of claim 2, wherein the plurality of planes further includes a 5 th plane, the 5 th plane being powered by the 1 st driver module and sharing a portion of a power supply circuit with the 1 st plane,

the sequencer suspends the 1 st action and executes the 2 nd action when receiving a 2 nd instruction set that targets a block included in the 5 th plane while executing the 1 st action that targets a block included in the 1 st plane.

4. The semiconductor memory device according to claim 2, wherein the action 1 is an erase action, and

the 2 nd operation is a read operation.

5. The semiconductor storage device of claim 4, wherein when the 2 nd instruction set is received during execution of the 1 st action, a time at which the sequencer executes the 2 nd action varies according to a time at which the 2 nd instruction set is received.

6. The semiconductor memory device according to claim 5, further comprising a plurality of well lines provided in each of the plurality of planes,

the block includes a plurality of string components,

the erase action includes: a boosting period in which the voltage of a well line corresponding to a block in which the 1 st or 2 nd driver module is selected is raised from a 1 st voltage to an erase voltage; during erase, the 1 st or 2 nd driver module applying the erase voltage to the corresponding well line; during a step-down, the 1 st or 2 nd driver module dropping a voltage of the corresponding well line from the erase voltage to the 1 st voltage; and during erase verification, the sequencer performing erase verification in units of the string components; and is

The sequencer's timing of the 2 nd action when receiving the 2 nd instruction set during the 1 st action is different for the case where the 2 nd instruction set is received during the boosting, the case where the 2 nd instruction set is received during the erasing, the case where the 2 nd instruction set is received during the dropping, and the case where the 2 nd instruction set is received during the erase verifying.

7. The semiconductor storage device according to claim 6, wherein in a case where a 1 st action targeting a block included in the 1 st plane is performed, when the sequencer receives a 2 nd instruction set targeting a block included in the 2 nd plane during the boosting, the boosting of the corresponding well line is stopped and the 2 nd action is performed, and the boosting of the corresponding well line is restarted after the 2 nd action is ended.

8. The semiconductor storage device according to claim 6, wherein in a case where a 1 st action targeting a block included in the 1 st plane is performed, the sequencer starts the 2 nd action based on a case where the boosting period has ended when receiving a 2 nd instruction set targeting a block included in the 2 nd plane during the boosting period.

9. The semiconductor storage device according to claim 6, wherein in a case where the sequencer performs a 1 st action that targets a block included in the 1 st plane,

the 1 st driver module raises and applies the erase voltage for the corresponding well line during the erase, an

The sequencer, when receiving a 2 nd instruction set that targets a block included in the 2 nd plane during the erasing, stops rising of the erase voltage applied to the corresponding well line and executes the 2 nd action, and restarts rising of the erase voltage after the 2 nd action ends.

10. The semiconductor storage device according to claim 6, wherein in a case where a 1 st action targeting a block included in the 1 st plane is performed, the sequencer starts the 2 nd action based on a case where the erase period has ended when receiving a 2 nd instruction set targeting a block included in the 2 nd plane during the erase period.

11. The semiconductor storage device according to claim 6, wherein in a case where a 1 st action targeting a block included in the 1 st plane is performed, the sequencer starts the 2 nd action based on a case where the step-down period has ended when receiving a 2 nd instruction set targeting a block included in the 2 nd plane during the step-down period.

12. The semiconductor storage device according to claim 6, wherein in a case where a 1 st action targeting a block included in the 1 st plane is performed, the sequencer receives a 2 nd instruction set targeting a block included in the 2 nd plane during the erase verification, suspends the erase verification to start the 2 nd action based on a case where a decision action in the erase verification in units of the string elements has ended, and resumes the erase verification of a next string element when the 2 nd action ends.

13. The semiconductor storage device according to claim 6, wherein in a case where a 1 st action targeting a block included in the 1 st plane is performed, the sequencer starts the 2 nd action by dropping the voltage of the corresponding well line from the erase voltage to the 1 st voltage when receiving a 2 nd instruction set targeting a block included in the 1 st plane during the erase.

14. The semiconductor storage device according to claim 13, wherein the 1 st driver module raises the voltage of the corresponding well line from the 1 st voltage to the erase voltage again after the 2 nd action is ended.

15. The semiconductor storage device according to claim 6, wherein in a case of performing a 1 st action targeting a block included in the 1 st plane, the sequencer interrupts erase verification in units of the string component to start the 2 nd action when receiving a 2 nd instruction set targeting a block included in the 1 st plane during the erase verification, and re-performs the interrupted erase verification of the string component when the 2 nd action ends.

16. The semiconductor memory device according to claim 4, wherein after data read in the action 2 is output, the action 1 is restarted without a command from an external memory controller.

17. The semiconductor memory device according to claim 4, wherein the 1 st action is restarted based on an instruction received from outside after data read by the 2 nd action is output.

18. The semiconductor memory device according to claim 1, wherein the sequencer causes the semiconductor memory device to transition from a ready state to a busy state to start the 1 st action when receiving the 1 st instruction set, and causes the semiconductor memory device to transition from the busy state to the ready state after starting the 1 st action, and performs the 1 st action in the ready state.

19. The semiconductor memory device according to claim 18, wherein the sequencer starts the 2 nd action by causing the semiconductor memory device to transition from a ready state to a busy state when receiving the 2 nd instruction set during execution of the 1 st action, and causes the semiconductor memory device to transition from the busy state to the ready state after the 2 nd action is finished.

20. The semiconductor storage device of claim 18, wherein the sequencer transitions the semiconductor storage device from a ready state to a busy state upon receiving the 2 nd instruction set during performance of the 1 st action,

when the 2 nd instruction set includes a 1 st instruction, suspending the 1 st action and starting the 2 nd action before the 1 st action is completed, and making the semiconductor memory device transition from a busy state to a ready state after the 2 nd action is completed,

when the 2 nd instruction set includes a 2 nd instruction different from the 1 st instruction, the 1 st action is continued, the 2 nd action is started after the 1 st action is completed, and the semiconductor memory device is transitioned from a busy state to a ready state after the 2 nd action is completed.

Technical Field

Embodiments relate to a semiconductor memory device.

Background

A NAND (Not AND) type flash memory capable of nonvolatile storage of data is known.

Background of the invention

Patent document

Patent document 1: japanese patent laid-open No. 2004-348788

Disclosure of Invention

[ problems to be solved by the invention ]

The latency of the semiconductor memory device is improved.

[ means for solving problems ]

The semiconductor memory device of an embodiment includes a plurality of planes and a sequencer. The planes each have a plurality of blocks as a set of storage units. The sequencer performs action 1 and action 2, which is shorter than action 1. The sequencer performs the 1 st action when receiving the 1 st instruction set indicating execution of the 1 st action. When the sequencer receives a 2 nd instruction set instructing execution of a 2 nd action while executing the 1 st action, the sequencer suspends the 1 st action and executes the 2 nd action or executes the 2 nd action in parallel with the 1 st action, based on an address of a block to be operated 1 and an address of a block to be operated 2.

Drawings

Fig. 1 is a block diagram showing an example of the configuration of the semiconductor memory device according to embodiment 1.

Fig. 2 is a block diagram showing an example of the configuration of a plane group included in the semiconductor memory device according to embodiment 1.

Fig. 3 is a block diagram showing an example of a planar configuration in the semiconductor memory device according to embodiment 1.

Fig. 4 is a circuit diagram showing an example of a circuit configuration of a memory cell array in the semiconductor memory device according to embodiment 1.

Fig. 5 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array in the semiconductor memory device according to embodiment 1.

Fig. 6 is a cross-sectional view showing an example of a cross-sectional structure of a memory pillar in the semiconductor memory device according to embodiment 1.

Fig. 7 is a threshold distribution diagram showing an example of the distribution of threshold voltages of memory cell transistors in the semiconductor memory device according to embodiment 1.

Fig. 8 is a circuit diagram showing an example of a circuit configuration of a row decoder module in the semiconductor memory device according to embodiment 1.

Fig. 9 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module in the semiconductor memory device according to embodiment 1.

Fig. 10 is a circuit diagram showing an example of the circuit configuration of the determination circuit in the semiconductor memory device according to embodiment 1.

Fig. 11 is a command sequence and timing chart for explaining an example of a read operation in the semiconductor memory device according to embodiment 1.

Fig. 12 is a command sequence and timing chart for explaining an example of an erasing operation in the semiconductor memory device according to embodiment 1.

Fig. 13 is a block diagram showing an example of the relationship between a selected plane and another plane in the erasing operation of the semiconductor memory device according to embodiment 1.

Fig. 14 is a block diagram showing an example of the relationship between a selected plane and another plane in the erasing operation of the semiconductor memory device according to embodiment 1.

Fig. 15 is a block diagram showing an example of the relationship between a selected plane and another plane in the erasing operation of the semiconductor memory device according to embodiment 1.

Fig. 16 is a sequence and timing chart for explaining an erase operation and a background read operation for selecting a plane of the same power pack in the semiconductor memory device according to embodiment 1.

Fig. 17 is a timing chart for explaining an example of more detailed execution time of background reading for selecting a plane of the same power pack in the semiconductor memory device according to embodiment 1.

Fig. 18 is a timing chart for explaining an example of more detailed execution time of background reading for selecting a plane of the same power pack in the semiconductor memory device according to embodiment 1.

Fig. 19 is a timing chart for explaining an example of more detailed execution time of background reading for selecting a plane of the same power pack in the semiconductor memory device according to embodiment 1.

Fig. 20 is a timing chart for explaining an example of more detailed execution time of background reading for selecting a plane of the same power pack in the semiconductor memory device according to embodiment 1.

Fig. 21 is a timing chart for explaining an example of more detailed execution time of background reading for selecting a plane of the same power pack in the semiconductor memory device according to embodiment 1.

Fig. 22 is a timing chart for explaining an example of more detailed execution time of background reading for selecting a plane of the same power pack in the semiconductor memory device according to embodiment 1.

Fig. 23 is a timing chart for explaining an example of more detailed execution time of background reading for selecting a plane of the same power pack in the semiconductor memory device according to embodiment 1.

Fig. 24 is a timing chart for explaining an example of more detailed execution time of background reading for selecting a plane of the same power pack in the semiconductor memory device according to embodiment 1.

Fig. 25 is a sequence and timing chart for explaining an erase operation and a background read operation for selecting a plane of a different power pack in the semiconductor memory device according to embodiment 1.

Fig. 26 is a command sequence and timing chart for explaining a suspend read operation for selecting the same pair of planes and an erase operation in the semiconductor memory device according to embodiment 1.

Fig. 27 is a timing chart for explaining an example of a more detailed execution time of the suspend reading for selecting the same pair of planes in the semiconductor memory device according to embodiment 1.

Fig. 28 is a timing chart for explaining an example of a more detailed execution time of the suspend reading for selecting the same pair of planes in the semiconductor memory device according to embodiment 1.

Fig. 29 is a timing chart for explaining an example of a more detailed execution time of the suspend reading for selecting the same pair of planes in the semiconductor memory device according to embodiment 1.

Fig. 30 is a timing chart for explaining an example of a more detailed execution time of the suspend reading for selecting the same pair of planes in the semiconductor memory device according to embodiment 1.

Fig. 31 is a timing chart for explaining an example of a more detailed execution time of the suspend reading for selecting the same pair of planes in the semiconductor memory device according to embodiment 1.

Fig. 32 is a timing chart for explaining an example of a more detailed execution time of the suspend reading for selecting the same pair of planes in the semiconductor memory device according to embodiment 1.

Fig. 33 is a timing chart for explaining an example of a more detailed execution time of the suspend reading for selecting the same pair of planes in the semiconductor memory device according to embodiment 1.

Fig. 34 is a command sequence and timing chart for explaining an erase operation and a pause read in a comparative example of embodiment 1.

Fig. 35 is a command sequence and timing chart for explaining an example of an erasing operation in the semiconductor memory device according to embodiment 2.

Fig. 36 is a timing chart for explaining an example of more detailed execution time of background reading for selecting a plane of the same power pack in the semiconductor memory device according to embodiment 2.

Fig. 37 is a command sequence and timing chart for explaining a suspend read operation for selecting the same pair of planes and an erase operation in the semiconductor memory device according to embodiment 3.

Fig. 38 is a sequence and timing chart for explaining a command sequence of a suspend read for erasing and selecting the same pair of planes in the semiconductor memory device according to embodiment 3.

Fig. 39 is a block diagram showing an example of a memory system including the semiconductor memory device according to embodiment 1.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. Each embodiment exemplifies an apparatus and a method for embodying the technical idea of the invention. The drawings are schematic or conceptual drawings, and the dimensions, ratios, and the like of the drawings are not necessarily the same as actual ones. The technical idea of the present invention is not specified by the shape, structure, arrangement, and the like of the constituent elements.

In the following description, components having substantially the same function and configuration are denoted by the same reference numerals. The numerals following the letters constituting the reference symbols are used to distinguish elements having the same configuration from each other, which are referred to as reference symbols including the same letters. In the case where elements denoted by reference symbols including the same letter are not necessarily distinguished from each other, the elements are referred to by reference symbols including only the same letter.

In this specification, the "H (High)" level corresponds to a voltage at which an NMOS (N-channel Metal Oxide Semiconductor) transistor is in an on state and a PMOS (P-channel Metal Oxide Semiconductor) transistor is in an off state. The "L (Low)" level corresponds to a voltage at which the NMOS transistor becomes an off state and the PMOS transistor becomes an on state.

[1] Embodiment 1

The semiconductor memory device according to the embodiment described below is a NAND flash memory capable of nonvolatile storage of data. First, the semiconductor memory device 10 according to embodiment 1 will be described.

[1-1] constitution

[1-1-1] Overall configuration of semiconductor memory device 10

Fig. 1 shows an example of the structure of a semiconductor memory device 10 according to embodiment 1. As shown in fig. 1, the semiconductor memory device 10 according to embodiment 1 includes, for example, an input/output circuit 11, a register group 12, a logic controller 13, a sequencer 14, a ready/busy control circuit 15, a voltage generation circuit 16, and plane groups PG1 and PG 2.

The input/output circuit 11 transmits and receives, for example, 8-bit wide input/output signals I/O1 to I/O8 to and from an external memory controller. The input/output signals I/O may contain data DAT, status information STS, address information ADD, commands CMD, etc. Data DAT is transmitted and received between the input/output circuit 11 and each plane group PG via a data bus.

The register set 12 includes a status register 12A, an address register 12B, and an instruction register 12C. The status register 12A, the address register 12B, and the command register 12C hold status information STS, address information ADD, and a command CMD, respectively.

The status information STS is updated based on, for example, the operation status of the sequencer 14. In addition, the status information STS is transferred from the status register 12A to the input-output circuit 11 based on an instruction from the memory controller, and is output to the memory controller. The address information ADD is transferred from the input-output circuit 11 to the address register 12B, and may include, for example, a block address, a page address, a column address, and the like. The command CMD is transmitted from the input/output circuit 11 to the command register 12C, and includes commands related to various operations of the semiconductor memory device 10.

The logic controller 13 controls the input/output circuit 11 and the sequencer 14 based on a control signal received from an external memory controller. As such control signals, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a write protect signal WPn are used.

The chip enable signal CEn is a signal for enabling the semiconductor memory apparatus 10. The command latch enable signal CLE is a signal for notifying the input/output circuit 11 that the received input/output signal I/O is the command CMD. The address latch enable signal ALE is a signal for notifying the input-output circuit 11 that the received input-output signal I/O is the address information ADD. The write enable signal WEn is a signal for instructing the input/output circuit 11 to input the input/output signal I/O. The sense enable signal REn is a signal for instructing the input-output circuit 11 to output the input-output signal I/O. The write protect signal WPn is a signal for protecting the semiconductor memory device 10 when the power supply is turned on or off.

The sequencer 14 controls the operation of the entire semiconductor memory device 1. For example, the sequencer 14 executes a read operation, a write operation, an erase operation, and the like based on the command CMD stored in the command register 12C and the address information ADD stored in the address register 12B. In addition, the sequencer 14 includes a determination circuit DC.

The decision circuit DC has a function as an address decoder. The determination circuit DC generates a specific control signal based on the address information ADD and the command CMD. The control signal is referred to when, for example, the semiconductor memory device 10 receives a command instructing execution of an interrupt process during an erase operation. Details of the determination circuit DC will be described later.

Ready/busy control circuit 15 generates ready/busy signal RBn based on the action state of sequencer 14. The ready/busy signal RBn is a signal for informing the external memory controller whether the semiconductor memory apparatus 10 is in a ready state or a busy state. In this specification, the "ready state" indicates a state in which the semiconductor memory device 10 receives a command from the memory controller, and the "busy state" indicates a state in which the semiconductor memory device 10 does not receive a command from the memory controller.

The voltage generation circuit 16 generates a voltage used for a read operation, a write operation, an erase operation, and the like. The voltage generation circuit 16 includes, for example, driver modules DRM1 and DRM 2. The driver module DRM1 supplies a voltage to the plane group PG1, and the driver module DRM2 supplies a voltage to the plane group PG 2. That is, the plane groups PG1 and PG2 are connected to different power sources.

The plane group PG includes a plurality of planes PL. Plane PL contains a collection of memory cell transistors that nonvolatilely store data. Details of the plane PL will be described later. Plane groups PG1 and PG2 may be independently controlled by sequencer 14.

Fig. 2 shows an example of the configuration of the plane group PG included in the semiconductor memory device 10 according to embodiment 1. As shown in fig. 2, for example, plane group PG1 includes planes PL0 to PL7, and plane group PG2 includes planes PL8 to PL 15.

In the plane group PG1, for example, a group of planes PL0 and PL1, a group of planes PL2 and PL3, a group of planes PL4 and PL5, and a group of planes PL6 and PL7 constitute pairs of planes PP0 to PP3, respectively.

In the plane group PG2, for example, a group of planes PL8 and PL9, a group of planes PL10 and PL11, a group of planes PL12 and PL13, and a group of planes PL14 and PL15 constitute pairs of planes PP14 to PP15, respectively.

Each pair of planes PP may be independently controlled by sequencer 14. In addition, a common circuit SC is provided in each pair of planes PP. The shared circuit SC is a circuit shared by 2 planes PL included in the plane PP. For example, the shared circuit SC includes a power supply circuit that supplies a voltage to the components included in each plane PL.

The number of planes PL and PP included in the plane group PG may be set to any number. The common circuit CS that is common to the 2 planes PL constituting the plane PP is not limited to the power supply circuit, and may include a circuit having an arbitrary function.

Fig. 3 shows an example of the structure of the plane PL in the semiconductor memory device 10 according to embodiment 1. As shown in fig. 3, each plane PL includes, for example, a memory cell array 20, a row decoder block 21, and a sense amplifier block 22.

The memory cell array 20 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). The block BLK is a set of a plurality of memory cell transistors capable of nonvolatile storage of data, and is used as an erase unit of data, for example. In the memory cell array 20, a plurality of bit lines BL0 to BLm (m is an integer of 1 or more), a plurality of word lines, source lines, and well lines are provided. Each memory cell transistor is associated with 1 bit line and 1 word line. The detailed structure of the memory cell array 20 will be described later.

The row decoder module 21 selects the block BLK that performs various actions based on the block address. Then, the row decoder block 21 transfers the voltage supplied from the voltage generation circuit 16 to various wirings within the selected block BLK. For example, the row decoder module 21 includes a plurality of row decoders RD0 RDn. The row decoders RD 0-RDn are associated with the blocks BLK 0-BLKn, respectively. The detailed circuit configuration of the row decoder RD will be described later.

In the read operation, the sense amplifier module 22 reads data from the memory cell array 20 and transfers the read data to the input/output circuit 11. In addition, the sense amplifier module 22 applies a desired voltage to the bit line BL in the write operation based on the data received from the input/output circuit 11. For example, the sense amplifier module 22 includes a plurality of sense amplifier elements SAU0 SAUm. The sense amplifier elements SAU 0-SAUm are respectively associated with the bit lines BL 0-BLm. The detailed circuit configuration of the sense amplifier unit SAU will be described later.

The plane PL described above may include at least the memory cell array 20. In this case, the row decoder module 21 or the sense amplifier module 22 may be included in the common circuit SC within each pair of planes PP.

[1-1-2] constitution of memory cell array 20

Next, a detailed configuration of the memory cell array 20 in the semiconductor memory device 10 according to embodiment 1 will be described.

(Circuit constitution of memory cell array 20)

Fig. 4 shows an example of the circuit configuration of the memory cell array 20 in the semiconductor memory device 10 according to embodiment 1, with 1 block BLK being decimated. As shown in fig. 4, the block BLK includes, for example, 4 string components SU0 to SU 3.

Each string component SU includes a plurality of NAND strings NS associated with bit lines BL0 BLm, respectively. The NAND string NS includes, for example, memory cell transistors MT 0-MT 7 and select transistors ST1 and ST 2.

The memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. The selection transistors ST1 and ST2 are used to select the string unit SU in various operations.

In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. A selection transistor ST1 is connected between one end of the memory cell transistors MT0 to MT7 connected in series and the bit line BL for establishing the association. The drain of the selection transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the selection transistor ST2 is connected to each of the source line CELSRC and the well line CPWELL.

In the same block BLK, the gates of the plurality of select transistors ST1 included in the string elements SU0 to SU3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. The control gates of the memory cell transistors MT0 to MT7 are commonly connected to word lines WL0 to WL7, respectively. The gates of the plurality of selection transistors ST2 are commonly connected to the selection gate line SGS.

The bit lines BL0 to BLm are shared among the blocks BLK. The same bit line BL is connected to the NAND string NS corresponding to the same column address. Word lines WL0 to WL7 are provided for each block BLK, respectively. The source line CELSRC and the well line CPWELL are shared by a plurality of blocks BLK, for example.

The set of the plurality of memory cell transistors MT connected to the common word line WL in the 1 string unit SU is referred to as a cell unit CU, for example. For example, the storage capacity of the cell unit CU including the memory cell transistors MT each storing 1-bit data is defined as "1-page data". The cell unit CU may have a storage capacity of 2 pages of data or more according to the number of bits of data stored in the memory cell transistor MT.

The circuit configuration of the memory cell array 20 described above is merely an example, and is not limited thereto. For example, the number of string components SU included in each block BLK may be designed to be any number. The number of memory cell transistors MT and the number of selection transistors ST1 and ST2 included in each NAND string NS can be set to any number. The number of word lines WL and the number of select gate lines SGD and SGS are designed to correspond to the number of memory cell transistors MT and the number of select transistors ST1 and ST2 included in each NAND string NS.

(regarding the cross-sectional structure of the memory cell array 20)

Fig. 5 shows an example of the cross-sectional structure of the memory cell array 20 in the semiconductor memory device 10 according to embodiment 1, in which structures corresponding to 1 block BLK are sampled and shown. In the cross-sectional views referred to below, components such as an interlayer insulating film, wirings, and contacts are appropriately omitted to make the drawings understandable. The X direction corresponds to the extending direction of the bit line BL. The Y direction corresponds to the extending direction of the word lines WL. The Z direction corresponds to a vertical direction with respect to the surface of the semiconductor substrate.

As shown in fig. 5, the region for forming the memory cell array 20 includes, for example, a P-type well region 30, an insulator layer 33, a 4-layer conductor layer 34, an 8-layer conductor layer 35, a 4-layer conductor layer 36, a plurality of memory pillars MP, conductor layers 37, 38, and 39, and a plurality of contacts CP.

The P-type well region 30 is disposed near the surface of the semiconductor substrate. The P-type well region 30 includes n arranged separately from each other⁺Impurity diffusion region 31 and p⁺An impurity diffusion region 32. n is⁺Impurity diffusion region 31 and p⁺Impurity diffusion regions 32 are respectively provided in the vicinity of the surfaces of the P-type well regions 30.

An insulator layer 33 is provided on the P-type well region 30. 4 conductive layers 34 are provided on the insulator layer 33 so as to be separated from each other. The lowermost conductor layer 34 and insulator layer 33 are provided to n⁺The vicinity of the impurity diffusion region 31. Above the uppermost conductor layer 34, 8 conductor layers 35 are provided, which are separately stacked. Above the uppermost conductor layer 35, 4 conductor layers 36 are provided, which are separately laminated. An electrical conductor layer 37 is provided above the uppermost electrical conductor layer 36.

The conductor layer 34 has a structure extending along the XY plane and functions as the selection gate line SGS. The conductor layer 35 has a structure extending along the XY plane, and 8 conductor layers 35 serve as word lines WL0 to WL7 in this order from the lower layer. The conductor layer 36 has a structure extending in the Y direction, and is separated for each string unit SU corresponding to each wiring layer. The conductor layer 36 serves as a select gate line SGD. The conductor layer 37 has a structure extending in the X direction, and in an area not shown, the plurality of conductor layers 37 are arranged in the Y direction. The conductor layer 37 functions as a bit line BL.

Conductive layers 38 and 39 are disposed in wiring layers between conductive layer 36 and conductive layer 37, for example, in the uppermost layer. The conductor layer 38 functions as a source line CELSRC, and the conductor layer 39 functions as a well line CPWELL. Contacts CP are provided on the conductor layer 38 and n, respectively⁺Between impurity diffusion regions 31, and conductor layers 39 and p⁺Between the impurity diffusion regions 32. Conductive layers 38 and 39 are electrically connected to n through contacts CP⁺Impurity diffusion region 31 and p⁺An impurity diffusion region 32.

The plurality of memory pillars MP penetrate (pass) the insulator layer 33, the 4-layer conductor layer 34, the 8-layer conductor layer 35, and the 4-layer conductor layer 36, respectively. The plurality of memory pillars MP include, for example, a semiconductor member 40 and a laminate film 41.

The semiconductor member 40 is formed in a columnar shape extending in the Z direction, for example. The side surface of the semiconductor component 40 is covered with the laminate film 41. The lower portion of the semiconductor component 40 is in contact with the P-type well region 30. The upper portion of the semiconductor component 40 is in contact with the conductor layer 37 via, for example, a contact CH. The semiconductor parts 40 in the memory pillars MP corresponding to the same column address are electrically connected to the same conductor layer 37. The semiconductor component 40 and the conductor layer 37 may be electrically connected to each other through a contact, a wiring, or the like.

Fig. 6 is a cross-sectional view taken along line VI-VI in fig. 5, showing an example of a cross-sectional structure of the memory pillar MP in the wiring layer including the conductor layer 35. As shown in fig. 6, the laminated film 41 includes, for example, a tunnel oxide film 42, an insulating film 43, and a barrier insulating film 44.

The tunnel oxide film 42 surrounds the side surfaces of the semiconductor component 40. An insulating film 43 is provided on the side surface of the tunnel oxide film 42. A barrier insulating film 44 is provided on the side surface of the insulating film 43. The conductive layer 35 is in contact with the side surface of the barrier insulating film 44. In addition, an insulator whose side surface is surrounded by the semiconductor member 40 may be provided in the central portion of the memory pillar MP.

In the structure of the memory cell array 20 described above, the portion where the memory pillar MP intersects with the conductor layer 34 functions as the selection transistor ST 2. The portion where the memory pillar MP intersects the conductor layer 35 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects the conductor layer 25 functions as a selection transistor ST 1.

That is, in this example, 1 memory pillar MP functions as 1 NAND string NS. The string unit SU is formed of a set of a plurality of memory pillars MP arranged in the Y direction. As a current path of the transistor included in the NAND string NS, the semiconductor member 40 is used. When the select transistor ST2 is turned on, the NAND string NS and the source line CELSRC are electrically connected to each other through a channel formed in the vicinity of the surface of the P-type well region 30.

The structure of the memory cell array 20 described above is merely an example, and can be changed as appropriate. For example, the number of layers of the conductor layer 35 is designed based on the number of word lines WL. The number of layers of the conductor layer 34 serving as the selection gate line SGS can be designed to be any number of layers. The number of layers of the conductor layer 36 serving as the selection gate line SGD may be designed to be any number of layers.

(threshold distribution of memory cell transistor MT)

Fig. 7 shows an example of the threshold distribution of the memory cell transistor MT in the semiconductor memory device 10 according to embodiment 1. The vertical axis of the graph shown in fig. 7 corresponds to the number of memory cell transistors MT, and the horizontal axis corresponds to the threshold voltage of the memory cell transistors MT.

As shown in fig. 7, in the semiconductor memory device 10 according to embodiment 1, 4 kinds of threshold distributions can be formed according to the threshold voltages of the plurality of memory cell transistors MT included in 1 cell unit CU. That is, the memory Cell transistor MT in the semiconductor memory device 10 according to embodiment 1 is an MLC (Multi Level Cell) capable of storing 2 bits (4 values) of data. These 4 threshold distributions are referred to as an "ER" state, an "a" state, a "B" state, and a "C" state, for example, in order of a threshold voltage from low to high. Note that although the memory Cell transistor MT is an MLC example, the memory Cell transistor MT may be an SLC (Single Level Cell) capable of storing 1 bit (2 value) of data. In this case, for example, the number of latch circuits in the sense amplifier module 22 described below can be reduced.

Verify voltages used for the write operation are set for each of adjacent threshold distributions. For example, the verify voltage AV corresponding to the "a" state is set between the "ER" state and the "a" state and in the vicinity of the "a" state. Similarly, the verify voltages BV and CV are set corresponding to the "B" state and the "C" state, respectively. In the write operation, the sequencer 14 completes the program of the memory cell transistor MT when detecting that the threshold voltage of the memory cell transistor MT storing certain data exceeds the verify voltage corresponding to the data.

The read voltages used for the read operation are also set for each of the adjacent threshold distributions. For example, the read voltage AR is set between the "ER" state and the "a" state. Similarly, the read voltage BR is set between the "a" state and the "B" state, and the read voltage CR is set between the "B" state and the "C" state. For example, the readout voltages AR, BR, and CR are set to voltages lower than the verify voltages AV, BV, and CV, respectively. The memory cell transistor MT is turned on or off according to data to be stored when a read voltage is applied to a gate.

The read-on voltage Vread is set to a higher voltage than the highest threshold distribution. Specifically, the read pass voltage Vread is set to a voltage higher than the maximum threshold voltage in the "C" state. When a read-on voltage Vread is applied to the gate, the memory cell transistor MT is turned on regardless of stored data.

In addition, 2-bit data that is different from each other is allocated to the 4 kinds of threshold distributions described above. An example of data allocation to the threshold distribution is listed below.

"ER" status: "11 (upper bit/lower bit)" data

The "A" state: data of "01

The "B" state: "00" data

The "C" state: the "10" data.

In the case where such data allocation is applied, 1-page data (lower page data) composed of lower bits is determined by a readout process using the readout voltage BR. The 1-page data (upper page data) composed of the upper bits is determined by the read processing using the read voltages AR and CR.

[1-1-3] Circuit constitution of Row decoder Module 21

Fig. 8 shows an example of the circuit configuration of the row decoder module 21 in the semiconductor memory device 10 according to embodiment 1, and also shows the relationship between the driver module DRM and the memory cell array 20. As shown in fig. 8, the row decoder module 21 is connected to the driver module DRM via a plurality of signal lines.

Hereinafter, a detailed circuit configuration of the row decoder RD will be described with attention paid to the row decoder RD0 corresponding to the block BLK 0. The row decoder RD includes, for example, a block decoder BD and transistors TR0 to TR 17.

The block decoder BD decodes the block address, and applies a specific voltage to each of the transfer gate lines TG and bTG based on the decoding result. The transmission gate line TG is commonly connected to the gates of the transistors TR0 to TR 12. The transfer gate line bTG receives an inverted signal of the transfer gate line TG, and the transfer gate line bTG is commonly connected to the gates of the transistors TR13 to TR 17.

Each of the transistors TR0 to TR17 is a high-voltage n-channel MOS (Metal Oxide Semiconductor) transistor. The transistor TR is connected between a signal line wired from the driver module DRM and a wiring provided at the corresponding block BLK.

Specifically, the drain of the transistor TR0 is connected to the signal line SGSD. A source of the transistor TR0 is connected to the select gate line SGS. Drains of the transistors TR1 to TR8 are connected to the signal lines CG0 to CG7, respectively. The sources of the transistors TR1 to TR8 are connected to word lines WL0 to WL7, respectively. Drains of the transistors TR9 to TR12 are connected to the signal lines SGDD0 to SGDD3, respectively. Sources of the transistors TR9 to TR12 are connected to the select gate lines SGD0 to SGD3, respectively.

The drain of the transistor TR13 is connected to the signal line USGS. A source of the transistor TR13 is connected to the select gate line SGS. The drains of the transistors TR14 to TR17 are commonly connected to the signal line USGD. Sources of the transistors TR14 to TR17 are connected to the select gate lines SGD0 to SGD3, respectively.

With the above configuration, the row decoder module 21 can select the block BLK. For example, in various operations, the block decoder BD corresponding to the selected block BLK applies the voltages of the "H" level and the "L" level to the transmission gate lines TG and bTG, respectively, and the block decoder BD corresponding to the non-selected block BLK applies the voltages of the "L" level and the "H" level to the transmission gate lines TG and bTG, respectively.

The circuit configuration of the row decoder block 21 described above is merely an example, and may be changed as appropriate. For example, the number of transistors TR included in the row decoder block 21 may be designed to be based on the number of pieces of wiring provided in each block BLK. The driver module DRM shown in fig. 8 may apply a voltage to each of the source line CELSRC and the well line CPWELL provided in the memory cell array 20.

[1-1-4] Circuit configuration of sense Amplifier Module 22

Fig. 9 shows an example of the circuit configuration of the sense amplifier module 19 in the semiconductor memory device 10 according to embodiment 1, in which circuit configurations corresponding to 1 sense amplifier unit SAU are extracted and shown. As shown in fig. 9, the sense amplifier unit SAU includes, for example, a sense amplifier unit SA and latch circuits SDL, ADL, BDL, and XDL.

The sense amplifier unit SA determines whether read data is "0" or "1" based on the voltage of the corresponding bit line BL, for example, in a read operation. In other words, the sense amplifier section SA senses data read out to the corresponding bit line BL, and determines data stored in the selected memory cell.

Each of the latch circuits SDL, ADL, BDL, and XDL temporarily holds read data, write data, and the like. For example, the latch circuit XDL may be used for input and output of data DAT between the sense amplifier component SAU and the input and output circuit 11. That is, the latch circuit XDL may be used as a cache memory of the semiconductor memory device 10. On the other hand, the latch circuits SDL, ADL, and BDL are disposed in a region closer to the sense amplifier unit SA than the latch circuit XDL, and can be used preferentially in the read operation, the write operation, and the erase operation. On the other hand, the latch circuits SDL, ADL, and BDL are disposed in a region closer to the sense amplifier unit SA than the latch circuit XDL, and can be used preferentially in the read operation, the write operation, and the erase operation. For example, when the memory cell transistor MT is SLC, the latch circuits ADL and BDL may not be provided. In this case, the 1 sense amplifier module SAU includes only the sense amplifier unit SA, the latch circuit SDL arranged in the vicinity thereof, and the latch circuit XDL for inputting and outputting data DAT to and from the input/output circuit 11.

For example, with the semiconductor memory device 10, even if the latch circuits SDL, ADL, and BDL are in use, the latch circuit XDL (cache memory) can be brought into a ready state as long as it is idle. Defining the ready state in association with the state of the latch circuit XDL (cache memory) is referred to as "cache ready". As for "cache ready", compared with the case where the ready state is defined in association with the operation of the internal circuit other than the latch circuit XDL, the condition for bringing the semiconductor memory device 10 into the ready state is relaxed, and therefore, the period until the semiconductor memory device is brought into the ready state again after the start of the operation and the transition to the busy state can be shortened.

Hereinafter, an example of a detailed circuit configuration of each of the sense amplifier unit SA and the latch circuits SDL, ADL, BDL, and XDL will be described. For example, the sense amplifier section SA includes transistors 50 to 58 and a capacitor 59, and the latch circuit SDL includes transistors 60 and 61 and inverters 62 and 63.

The transistor 50 is a PMOS transistor. Each of the transistors 51, 52, 54-58, 60 and 61 is an NMOS transistor. The transistor 53 is an NMOS transistor with high withstand voltage.

One terminal of the transistor 50 is connected to a power supply line. A power supply voltage Vdd, for example, is applied to a power supply line connected to one end of the transistor 50. The gate of the transistor 50 is connected to the node inv (SDL) of the latch circuit SDL. One end of the transistor 51 is connected to the other end of the transistor 50. The other end of the transistor 51 is connected to the node COM. The control signal BLX is input to the gate of the transistor 51. The other end of the transistor 51 is connected to the node COM. One end of the transistor 52 is connected to the node COM. The control signal BLC is input to the gate of the transistor 52. One end of the transistor 53 is connected to the other end of the transistor 52. The other end of the transistor 53 is connected to the corresponding bit line BL. The control signal BLS is input to the gate of the transistor 53.

One end of the transistor 54 is connected to the node COM. The other terminal of transistor 54 is connected to node SRC. The node SRC is applied with, for example, the ground voltage Vss. The gate of the transistor 54 is connected to the node inv (SDL) of the latch circuit SDL. One terminal of the transistor 55 is connected to the other terminal of the transistor 50. The other end of transistor 55 is connected to node SEN. The control signal HLL is input to the gate of the transistor 55. One terminal of transistor 56 is connected to node SEN. The other end of the transistor 56 is connected to the node COM. A control signal XXL is input to a gate of the transistor 56.

One terminal of the transistor 57 is grounded. The gate of transistor 57 is connected to node SEN. One terminal of the transistor 58 is connected to the other terminal of the transistor 57. The other terminal of transistor 58 is connected to bus LBUS. The control signal STB is input to the gate of the transistor 58. One end of the capacitor 59 is connected to the node SEN. The other end of the capacitor 59 is inputted with a clock CLK.

In the latch circuit SDL, one end of each of the transistors 60 and 61 is connected to the bus line LBUS. The other ends of the transistors 60 and 61 are connected to nodes INV and LAT, respectively. The gates of the transistors 60 and 61 are supplied with control signals STI and STL, respectively. An input node of the inverter 62 and an output node of the inverter 63 are connected to the node LAT, respectively. An output node of the inverter 62 and an input node of the inverter 63 are connected to the node INV, respectively.

The circuit configuration of the latch circuits ADL, BDL, and XDL is the same as that of the latch circuit SDL, for example. On the other hand, a control signal different from that of the latch circuit SDL is input to each of the transistors 60 and 61. For example, in the latch circuit ADL, control signals ATI and ATL are input to gates of the transistors 60 and 61, respectively. In addition, the nodes INV and LAT of the latch circuits SDL, ADL, BDL, and XDL are independently provided.

The control signals BLX, BLC, BLS, HLL, XXL, STB, STI, STL, ATI, and ATL described above are generated by the sequencer 14, for example. The timing at which the sense amplifier section SA determines that the data is read out to the bit line BL is based on the timing at which the sequencer 14 asserts the control signal STB. In the following description, "asserting the control signal STB" corresponds to the sequencer 14 temporarily changing the control signal STB from the "L" level to the "H" level.

The circuit configuration of the sense amplifier module 22 described above is merely an example, and is not limited thereto. For example, the number of latch circuits included in the sense amplifier unit SAU may be changed as appropriate based on the number of bits of data to be stored in the memory cell transistor MT. Depending on the circuit configuration of the sense amplifier module SAU, an operation corresponding to "enable the control signal STB" may correspond to an operation in which the sequencer 14 temporarily changes the control signal STB from the "H" level to the "L" level.

[1-1-5] Circuit constitution of decision Circuit DC

Fig. 10 shows an example of the circuit configuration of the determination circuit DC in the semiconductor memory device 10 according to embodiment 1. As shown in fig. 10, addresses EPG1 and EPG2, addresses RPG1 and RPG2, addresses EPP0 to EPP7, and addresses RPP0 to RPP7 are input to the determination circuit DC. The determination circuit DC includes AND circuits AC0 to AC14, OR circuits OC0 AND OC1, inverters INV0 to INV2, AND flip-flop circuits FF0 to FF 2.

Each of the addresses EPG1 and EPG2 is address information indicating a plane group PG in which the semiconductor memory device 10 performs an erase operation in the foreground. Addresses EPG1 and EPG2 correspond to plane sets PG1 and PG2, respectively.

Each of the addresses RPG1 and RPG2 is address information indicating a plane group PG on which the semiconductor memory device 10 performs a read operation in an interrupt process. Addresses RPG1 and RPG2 correspond to plane sets PG1 and PG2, respectively.

Each of the addresses EPG1, EPG2, RPG1, and RPG2 is, for example, a signal of "H" level when corresponding to the selected plane group PG, and a signal of "L" level when corresponding to the non-selected plane group PG.

The addresses EPP0 to EPP7 are address information on the plane PP indicating that the semiconductor memory device 10 performs an erase operation in the foreground. Addresses EPP 0-EPP 7 correspond to the pairs of planes PP 0-PP 7, respectively.

The addresses RPP0 to RPP7 are address information indicating the plane PP on which the semiconductor memory device 10 performs the read operation in the interrupt process. Addresses RPP 0-RPP 7 correspond to the pairs of planes PP 0-PP 7, respectively.

The addresses EPP0 to EPP7 and RPP0 to RPP7 are, for example, signals at "H" level when corresponding to the selected counter plane PP, and signals at "L" level when corresponding to the non-selected counter plane PP.

Addresses EPG1 AND RPG1 are input to the AND circuit AC 0. Addresses EPG2 AND RPG2 are input to the AND circuit AC 1. The OR circuit OC0 receives respective output signals of the AND circuits AC0 AND AC 1.

Addresses EPP0 AND RPP0 are input to the AND circuit AC 2. Addresses EPP1 AND RPP1 are input to the AND circuit AC 3. Addresses EPP2 AND EPP2 are input to the AND circuit AC 4. Addresses EPP3 AND RPP3 are input to the AND circuit AC 5. Addresses EPP4 AND RPP4 are input to the AND circuit AC 6. Addresses EPP5 AND RPP5 are input to the AND circuit AC 7. Addresses EPP6 AND RPP6 are input to the AND circuit AC 8. Addresses EPP7 AND RPP7 are input to the AND circuit AC 9. The OR circuit OC1 receives the output signals of the AND circuits AC2 to AC9, respectively.

An output signal of the OR circuit OC0 via the inverter INV0 AND an output signal of the OR circuit OC1 via the inverter INV1 are input to the AND circuit AC 10. The output signal of the OR circuit OC0 AND the output signal of the OR circuit OC1 via the inverter INV2 are input to the AND circuit AC 11.

The output signal of the AND circuit AC10 is input to the AND circuit AC 12. The output signal of the AND circuit AC11 is input to the AND circuit AC 13. The output signal of the OR circuit OC1 is input to the AND circuit AC 14. Further, commands CMD are input to the AND circuits AC12 to AC 14. The command CMD is a signal of "H" level when a specific command is stored in the command register 12C, for example.

An input D to the flip-flop circuit FF0 is input with an output signal of the AND circuit AC 12. An input D to the flip-flop circuit FF1 is input with an output signal of the AND circuit AC 13. An input D to the flip-flop circuit FF2 is input with an output signal of the AND circuit AC 14. For example, a write enable signal WEn is input to each of the clocks of the flip-flop circuits FF0 to FF 2.

The flip-flop circuits FF0 to FF2 output control signals from the output Q based on the signal input to the input D and the signal input to the clock. Specifically, the control signal DIFFVG is output from the output Q of the flip-flop circuit FF 0. The control signal SAMEVG is output from the output Q of the flip-flop circuit FF 1. The control signal sampp is output from the output Q of the flip-flop circuit FF 2.

The control signal DIFFVG is a control signal indicating that the plane group PG is different between the plane PL in which the erase operation is performed in the foreground and the plane PL in which the read operation is performed in the interrupt processing.

The control signal SAMEVG is a control signal indicating that the plane group PG is the same and different for the planes PP between the plane PL in which the erase operation is performed in the foreground and the plane PL in which the read operation is performed in the interrupt process.

The control signal sampp is a control signal indicating that the pair plane PP including the plane PL in which the erase operation is performed in the foreground is the same as the pair plane PP including the plane PL in which the read operation is performed in the interrupt processing.

In the circuit configuration of the determination circuit DC described above, when the semiconductor memory device 10 receives an interrupt processing command during the erase operation, any one of the control signals DIFFVG, SAMEVG, and sampp is set to the "H" level based on the address of the plane PL on which the erase operation is performed on the foreground and the address of the plane PL on which the read operation is performed during the interrupt operation.

The circuit configuration of the determination circuit DC is not limited to this, and may be designed to have any circuit configuration. The determination circuit DC may be configured to output information indicating a relationship between the plane PL for executing the operation in the foreground and the plane PL for executing the operation in the interrupt processing based on at least 2 address information.

[1-2] actions

Next, the interrupt processing in the read operation, the erase operation, and the erase operation in the semiconductor memory device 10 according to embodiment 1 will be described in order.

In the following description, the selected block BLK is referred to as a selected block BLKsel, and the unselected block BLK is referred to as an unselected block BLKusel. The voltage generation circuit 16 applying a voltage to the word line WL corresponds to the voltage generation circuit 16 applying a voltage to the word line WL via the signal line CG and the row decoder module 21.

[1-2-1] read operation

Fig. 11 is a timing chart showing an example of the reading operation of the upper page in the semiconductor memory device 10 according to embodiment 1. As shown in fig. 11, in the read operation of the upper page, the external memory controller sequentially transmits, for example, a command "00 h", address information "ADD", and a command "30 h" to the semiconductor memory device 10.

The command "00 h" is a command for specifying a read operation. The command "30 h" is a command for instructing the execution of the read operation. When receiving the command "30 h", the sequencer 14 changes the semiconductor memory device 10 from the ready state to the busy state, and starts the read operation based on the received command and address information.

When the read operation starts, the voltage generation circuit 16 applies a read pass voltage Vread to the unselected word line WL, and sequentially applies the read voltages AR and CR to the selected word line WL. In addition, while the read voltages AR and CR are applied to the selected word line WLsel, the sequencer 14 asserts the control signal STB, respectively.

In each sense amplifier unit SAU, a readout result based on the readout voltage AR is held in, for example, a latch circuit ADL. Then, the read data of the upper page is calculated based on the read result based on the read voltage CR and the read result based on the read voltage AR stored in the latch circuit ADL, and the calculation result is stored in the latch circuit XDL, for example.

When the read data of the upper page is determined, the sequencer 14 ends the read operation, and causes the semiconductor memory device 10 to transition from the busy state to the ready state. Then, the read result held in the latch circuit XDL of each sense amplifier module SAU is output to the memory controller (fig. 11, "Dout") based on an instruction from the memory controller.

In the reading operation of the lower page, the semiconductor memory device 10 may be executed in the same manner as the reading operation of the upper page. The type and number of voltages applied in the read operation can be changed as appropriate according to the number of bits of data stored in the memory cell transistor MT or the distribution of data. The command used in the read operation can be changed as appropriate.

[1-2-2] Erase action

Fig. 12 is a timing chart showing an example of an erasing operation in the semiconductor memory device 10 according to embodiment 1. As shown in fig. 12, in the erasing operation, the external memory controller sequentially transmits, for example, a command "60 h", address information "ADD", and a command "D0 h" to the semiconductor memory device 10.

The instruction "60 h" is an instruction to specify an erase operation. The instruction "D0 h" is an instruction that instructs execution of a normal erase action. When receiving the instruction "D0 h", the sequencer 14 makes the semiconductor memory apparatus 10 transit from the ready state to the busy state, and starts the erasing action based on the received instruction and address information.

In the erase operation, the voltage generation circuit 16 applies Vss to the word line WL in the selection block BLKsel and applies Vera to the well line CPWELL. Vera is a high voltage used as an erase voltage. In this way, a potential difference is generated between the channel and the control gate in the NAND string NS in the selection block BLKsel, and electrons stored in the charge storage layer are extracted to the channel. As a result, the threshold voltage of the memory cell transistor MT in the selection block BLKsel is lowered and distributed at the "ER" level.

Sequencer 14 then performs erase verification. Specifically, the sequencer 14 performs a read operation using Vevf on the selection block BLKsel after dropping the voltage of the well line CPWELL from Vera to Vss. Vevf is set to a voltage between the "ER" state and the "A" state. The threshold voltage of the memory cell transistor MT for which the erase verification is successful is distributed in the "ER" state. Vevf is applied to all word lines WL corresponding to the selected block BLKsel, for example.

If the erase verification is successful, the sequencer 14 ends the erase action, causing the semiconductor memory apparatus 10 to transition from the busy state to the ready state. Further, the erase verification may be performed in units of blocks BLK, or in units of string components SU. In the case where the erase verification fails, the sequencer 14 may also perform the erase action of selecting the same block BLK again.

The erase operation described above can be classified into, for example, a boosting period, an erase period, a step-down period, and an erase verify period. The boosting period corresponds to a period between times t0 and t1 (fig. 12, (1)), and is a period during which the voltage of the well line CPWELL rises from Vss to Vera. The erase period corresponds to a period between times t1 and t2 (fig. 12 and 2), and is a period in which electrons stored in the charge storage layer are mainly extracted. The step-down period corresponds to a period between times t2 and t3 (fig. 12 and 3), and is a period during which the voltage of the well line CPWELL falls from Vera to Vss. The erase verify period corresponds to a period between times t3 and t4 (fig. 12 and (4)), and is a period during which erase verify is performed. These periods are used for explaining the execution time of the interrupt processing described below.

[1-2-3] interruption processing in Erase action

The semiconductor memory device 10 according to embodiment 1 appropriately interrupts the erase operation and executes the interrupt processing when receiving an instruction of the read operation from the external memory controller during the erase operation. The execution time of the interrupt processing may be variously considered based on the relationship between the plane PL for executing the erase operation and the plane PL for executing the read operation.

For example, in the interrupt processing, the planes PL0 to PL15 are classified into, for example, the same power supply group, different power supply groups, and the same pair of planes. The same power group is a set of planes PL contained in the same plane group PG as the selected plane PL and being different pairs of planes PP. A different power pack is a collection of planes PL contained in a different plane group PG than the selected plane PL. The same pair of planes is a set of planes PL contained in the same pair of planes PP.

Fig. 13, 14, and 15 show examples of the relationship between the selected plane PL and other planes PL in the erasing operation of the semiconductor memory device 10 according to embodiment 1. Fig. 13, 14, and 15 correspond to the case where 1 plane PL, 2 planes PL, and 4 planes PL are selected, respectively.

In the example shown in fig. 13, the plane PL0 is selected as the erasing target. In this case, the planes PL2 to PL7 are included in the same power pack. The planes PL 8-PL 15 are included in different power packs. Planes PL0 and PL1 are contained in the same pair of planes.

In the example shown in fig. 14, planes PL0 and PL1, i.e., the counter plane PP0, are selected as the objects to be erased. In this case, the planes PL2 to PL7 are included in the same power pack. The planes PL 8-PL 15 are included in different power packs. Planes PL0 and PL1 are contained in the same pair of planes.

In the example shown in fig. 15, planes PL0, PL1, PL8, and PL9, that is, the counter planes PP0 and PP4 are selected as objects to be erased. In this case, the planes PL2 to PL7 and PL10 to PL15 are included in the same power group. Planes PL0, PL1, PL8 and PL9 are contained in the same pair of planes. In this example, there is no plane PL contained in a different power pack.

As described above, in the semiconductor memory device 10 according to embodiment 1, grouping is performed appropriately according to the number and the location of the selected planes PL. The number and combination of planes PL for performing the erase operation are not limited to the combinations described above, and may be set to any number and combination.

In addition, the semiconductor memory device 10 according to embodiment 1 executes an erase operation using a command different from the erase operation described with reference to fig. 12 in order to execute an interrupt process at high speed. In this erasing operation, the sequencer 14 starts the erasing operation, and then the semiconductor memory device 10 is brought into the ready state, and the semiconductor memory device 10 performs the erasing operation in the ready state. Such an erase operation can shorten the period after the transition to the busy state and before the transition to the ready state again like the "cache ready", for example, referred to as a cache erase operation. The semiconductor memory device 10 according to embodiment 1 executes interrupt processing as appropriate based on the packet and the time when the read command is received in the cache erase operation.

Hereinafter, the interrupt processing for selecting the same power supply group, the interrupt processing for selecting a different power supply group, and the interrupt processing for selecting the same pair of planes will be described in order. In the following, as the interrupt processing, the read operation executed in parallel with the erase operation is referred to as background read, and the read operation executed by interrupting the erase operation is referred to as pause read.

[1-2-3-1] interrupt handling to select the same power pack

Fig. 16 shows an example of a command sequence and a timing chart of the cache erase operation and the interrupt processing for selecting the plane of the same power pack in the semiconductor memory device 10 according to embodiment 1. The control signals DIFFVG, SAMEVG, and sampp before various operations are at the "L" level, respectively.

As shown in fig. 16, first, the memory controller sequentially sends, for example, a command "60 h", address information "ADD", and a command "D3 h" to the semiconductor memory device 10. Instruction "D3 h" is an instruction that instructs the execution of a cache scrubbing action.

Upon receiving the instruction "D3 h", the sequencer 14 causes the semiconductor memory apparatus 10 to transition from the ready state to the busy state. Then, based on the received command and address information, the sequencer 14 starts the Erase operation (fig. 16, "Erase") similar to the operation described with reference to fig. 12.

When the erasing operation is started, the sequencer 14 makes the semiconductor memory device 10 transition from the busy state to the ready state. In this way, the semiconductor memory device 10 sequentially executes the processes corresponding to the periods (1) to (4) shown in fig. 12 in the ready state.

Before the semiconductor memory device 10 is in the ready state and the erasing operation is ended, the memory controller sequentially transmits, for example, a command "00 h", address information "ADD", and a command "30 h" to the semiconductor memory device 10. The address information "ADD" includes information specifying the plane PL of the same power supply group as the plane PL on which the erase operation is performed.

Upon receiving the instruction "30 h", the sequencer 14 causes the semiconductor memory apparatus 10 to transition from the ready state to the busy state. Then, the sequencer 14 starts a Read operation (fig. 16, "Read") of the interrupt processing based on the received command and address information and the control signal generated by the determination circuit DC.

In this example, address information specifying the plane PL of the same power supply group is input to the determination circuit DC. Therefore, control signal SAMEVG becomes "H" level, and control signals DIFFVG and sampp maintain "L" level.

That is, the sequencer 14 executes background reading for selecting the plane PL of the same power supply group in parallel with the erase operation based on the fact that the control signal SAMEVG is at the "H" level. The detailed operation of the background reading is the same as the reading operation described with reference to fig. 11, for example, and therefore, the description thereof is omitted.

At the end of the background read, sequencer 14 causes semiconductor memory device 10 to transition from the busy state to the ready state. At this time, the control signal SAMEVG output from the determination circuit DC is returned to the "L" level based on, for example, completion of the processing related to the reading operation. The memory controller causes the semiconductor memory device 10 to output read data (fig. 16, "Dout") when detecting that the semiconductor memory device 10 has become the ready state after instructing a read operation.

After receiving the read data, the memory controller transmits, for example, a command "48 h" to the semiconductor memory device 10. The instruction "48 h" is an instruction to notify the semiconductor memory device 10 of the end of the interrupt processing. When instruction "48 h" is received, sequencer 14 continues to perform the erase action.

Since the semiconductor memory device 10 performs the erase operation in the ready state, the ready state is maintained and does not change even after the erase operation is completed. In contrast, the memory controller performs the status read when performing the write operation, the erase operation for the other block BLK, or the like. At the time of status reading, the memory controller sends, for example, an instruction "70 h" to the semiconductor storage device 10. When receiving the command "70 h", the semiconductor memory device 10 outputs status information STS including information indicating whether the erase operation is completed or not to the memory controller. Thus, the memory controller can confirm whether or not the erasing operation of the semiconductor memory device 10 is completed.

The time for performing the background read-out described above may vary based on the progress of the erase operation. Hereinafter, various cases will be described with respect to an example of the time for executing the background read in the semiconductor memory device 10 according to embodiment 1.

(case where a read command is received during boosting)

Fig. 17, 18, and 19 each show an example of execution time of background reading for selecting the plane PL of the same power supply group in the semiconductor memory device 10 according to embodiment 1, and correspond to an operation of the semiconductor memory device 10 when receiving a read command during a boosting period of an erase operation.

In the same drawings referred to below, an example of a period of a foreground operation corresponding to an erase operation, a period of a background operation corresponding to a read operation in an interrupt process, and a voltage applied to the well line CPWELL of the plane PL in which the erase operation is performed is shown.

In the example shown in fig. 17, the semiconductor memory device 10 starts the background read immediately when it receives a read command (for example, "30 h") during the boosting period (fig. 17, (1)). In other words, after receiving the read command, the semiconductor memory device 10 starts background reading without suspending the erase operation. That is, in this example, the process of the boosting period and the process of the background read in the erase operation of the foreground are executed in parallel.

In the example shown in fig. 18, when the semiconductor memory device 10 receives a read command (for example, "30 h") during the boosting period (fig. 18, (1)), the boosting of the well line CPWELL is stopped and the background read is immediately started. During the execution of the background readout, the voltage of the well line CPWELL is maintained in a state at the time point when boosting is stopped, for example. Then, when the background readout ends, the semiconductor memory apparatus 10 restarts the boosting of the well line CPWELL. That is, in this example, the process of the boosting period in the erase operation of the foreground is stopped during the execution of the process of the background read, and is restarted based on the completion of the process of the background read.

In the example shown in fig. 19, when the semiconductor memory device 10 receives a read command (for example, "30 h") during the step-up period (fig. 19, (1)), the semiconductor memory device starts background reading after waiting for the end of the step-up period. In other words, after receiving the read instruction, the semiconductor memory device 10 suspends the background read during the boosting period, and starts the background read based on the fact that the boosting period has ended. That is, in this example, the process in the boosting period in the erase operation of the foreground and the process of the background read are executed so as not to overlap.

(case where a read instruction is received during erasing)

Fig. 20 and 21 each show an example of execution time of background reading for selecting the plane PL of the same power supply group in the semiconductor memory device 10 according to embodiment 1, and correspond to an operation of the semiconductor memory device 10 when receiving a read command during an erase period of an erase operation.

In the example shown in fig. 20, the semiconductor memory device 10 starts background reading immediately when it receives a read command (for example, "30 h") during the erase period (fig. 20, (2)). In other words, after receiving the read command, the semiconductor memory device 10 starts background reading without suspending the erase operation. That is, in this example, the process of the erase period and the process of the background read out in the erase operation of the foreground are executed in parallel.

In the example shown in fig. 21, when the semiconductor memory device 10 receives a read command (for example, "30 h") during the erase period (fig. 21 and (2)), it waits for the end of the erase period and then starts background reading. In other words, the semiconductor memory device 10 suspends background readout during erasing after receiving the readout instruction, and starts background readout based on the fact that the erasing period has ended. That is, in this example, the process in the erase period in the erase operation of the foreground and the process of the background read are executed so as not to overlap.

(case where a read instruction is received during step-down)

Fig. 22 and 23 each show an example of execution time of background reading for selecting the plane PL of the same power supply group in the semiconductor memory device 10 according to embodiment 1, and correspond to an operation of the semiconductor memory device 10 when receiving a read command during a step-down period of an erase operation.

In the example shown in fig. 22, the semiconductor memory device 10 starts background reading immediately when it receives a read command (for example, "30 h") during the step-down period (fig. 22, (3)). In other words, after receiving the read command, the semiconductor memory device 10 starts background reading without suspending the erase operation. That is, in this example, the step-down period processing and the background read processing in the erase operation of the foreground are executed in parallel.

In the example shown in fig. 23, when the semiconductor memory device 10 receives a read instruction (for example, "30 h") during the step-down period (fig. 23 and 3), it waits for the end of the step-down period and then starts background reading. In other words, after the semiconductor memory device 10 receives the readout instruction, the background readout in the step-down period is suspended, and the background readout is started based on the fact that the step-down period has ended. That is, in this example, the process in the step-down period in the erase operation of the foreground is executed so as not to overlap with the process of the background read.

(case where a read instruction is received during erase verification)

Fig. 24 and 25 each show an example of execution time of background reading for selecting the plane PL of the same power supply group in the semiconductor memory device 10 according to embodiment 1, and correspond to an operation of the semiconductor memory device 10 when receiving a read command during an erase verification period of an erase operation.

In addition, in the same drawings referred to below, an operation when the erase verification is performed in units of the string component SU during the erase verification is exemplified. For example, in a certain block BLK, the erase verification is performed in the order of string components SU 0-SU 3. In addition, the read operation in the 1-cycle erase verify is denoted as "Evfy", and the detect operation is denoted as "Edet". In the detecting operation, it is determined whether the erase verification of the string of elements SU is successful based on the result of the read operation in the erase verification performed before.

In the example shown in fig. 24, the semiconductor memory device 10 starts background read immediately when it receives a read instruction (for example, "30 h") during the erase verification period (fig. 24, (4)). In other words, after receiving the read command, the semiconductor memory device 10 starts background reading without suspending the erase operation. That is, in this example, the process in the erase verification period and the process in the background read out in the erase operation of the foreground are executed in parallel.

In the example shown in fig. 25, when the semiconductor memory device 10 receives a read instruction (for example, "30 h") during the erase verification period (fig. 25 and (4)), it waits for 1-cycle erase verification to end and then starts background reading. In other words, the semiconductor storage device 10 suspends background readout during execution of 1-cycle erase verification executed at the time point of receiving the readout instruction. Then, the semiconductor memory device 10 starts background readout based on the case where the 1-cycle erase verification has ended. When the background readout ends, the semiconductor memory apparatus 10 restarts the erase verification for the next string component SU.

Specifically, for example, when a read instruction is received during execution of erase verification for string element SU1, semiconductor memory device 10 suspends background read until end of erase verification for string element SU1 (that is, the set of read action "Evfy" and sense action "Edet").

Then, the semiconductor memory device 10 starts background reading based on the fact that the detection operation of the erase verification in the string unit SU1 has ended. Then, the semiconductor memory device 10 starts the erase verification for the string component SU2 based on the fact that the background readout has ended. As described above, in this example, the process of 1-cycle erase verification in the foreground erase operation is executed so as not to overlap the process of background read.

[1-2-3-2] selection of interrupt handling for different power packs

Fig. 26 shows an example of a command sequence and a timing chart of the cache erase operation and the interrupt processing for selecting a plane of a different power supply group in the semiconductor memory device 10 according to embodiment 1.

As shown in fig. 26, the operation in the interrupt processing for selecting planes of different power packs differs in the kind of the control signal at the "H" level from the operation in the interrupt processing for selecting planes of the same power pack described with reference to fig. 16.

Specifically, in this example, address information specifying the plane PL of the different power supply group is input to the determination circuit DC. Therefore, control signal DIFFVG becomes "H" level, and control signals SAMEVG and sampp maintain "L" level, respectively.

If a readout instruction (e.g., "30H") is received in the erase operation, the sequencer 14 performs background readout of selecting the planes PL of different power supply groups in parallel with the erase operation based on the fact that the control signal DIFFVG is at the "H" level.

Then, when the background readout ends, sequencer 14 causes semiconductor memory device 10 to transition from the busy state to the ready state. At this time, the control signal DIFFVG output from the determination circuit DC is returned to the "L" level based on, for example, completion of the processing related to the reading operation. The other operations in fig. 26 are the same as the instruction sequence and the timing chart described with reference to fig. 16, for example, and therefore, the description thereof is omitted.

Furthermore, background readout that selects a different power pack may also be performed without suspension. That is, background readout to select a different power pack can be performed immediately during any period of the foreground erase operation. The background readout selecting a different power pack may be performed at the same time as the background readout selecting the same power pack.

[1-2-3-3] interrupt processing for selecting the same pair of planes

Fig. 27 shows an example of a command sequence and a timing chart of an interrupt process for performing a cache erase operation and selecting the same pair of planes in the semiconductor memory device 10 according to embodiment 1.

As shown in fig. 27, the operation in the interrupt process for selecting the same pair of planes differs from the operation in the interrupt process for selecting the same power supply group described with reference to fig. 16 in the period for which the control signal at the "H" level is set to the "H" level and the period for which the erase operation is performed.

Specifically, in this example, address information specifying the same pair of planes is input to the determination circuit DC. Therefore, control signal SAMEPP becomes "H" level, and control signals DIFFVG and SAMEVG maintain "L" level, respectively.

If a read instruction (for example, "30H") is received in the erase operation, sequencer 14 interrupts the erase operation of the previous stage based on the fact that control signal samppp is at the "H" level, and performs the pause read for selecting the same pair of planes. The detailed operation of the pause reading is the same as the reading operation described with reference to fig. 11, for example, and therefore, the description thereof is omitted.

At the end of the suspended reading, the sequencer 14 causes the semiconductor memory device 10 to transition from the busy state to the ready state. At this time, the control signal sampp output from the determination circuit DC is returned to the "L" level based on, for example, completion of the processing related to the reading operation. The memory controller causes the semiconductor memory device 10 to output read data (fig. 27, "Dout") when the semiconductor memory device 10 is in the ready state after the instruction of the read operation.

After receiving the read data, the memory controller transmits, for example, a command "48 h" to the semiconductor memory device 10. When receiving instruction "48 h", sequencer 14 resumes the erase operation.

The time for performing the suspend readout described above may vary based on the progress status of the erase operation. Hereinafter, various cases will be described with respect to an example of the time for which the semiconductor memory device 10 according to embodiment 1 performs the suspend reading.

(case where a read instruction is received during erasing)

Fig. 28, 29, 30, and 31 each show an example of the execution time of the suspend reading for selecting the planes PL of the same pair in the semiconductor memory device 10 according to embodiment 1, and correspond to the operation of the semiconductor memory device 10 when receiving a read command during the erase period of the erase operation.

Fig. 28, 29, 30, and 31 show the number of steps in the erase period. In this example, the semiconductor memory device 10 ends the erase period based on the fact that the steps "0" to "9" have been executed in the erase period. In the example shown in fig. 29, 30, and 31, the interrupt process is executed 1 time during the erase period, and the erase operation is divided into the 1 st period and the 2 nd period.

In the example shown in fig. 28, when the semiconductor memory device 10 receives a read command (for example, "30 h") during the erase period (fig. 28, 1 st period (2)), the erase period is first executed until a specific step is performed, and the erase process is completed. Then, the semiconductor memory device 10 starts suspending the readout based on the fact that the voltage of the well line CPWELL has been dropped to Vss. When the suspend reading ends, the memory controller sends an instruction "48 h". When the semiconductor memory device 10 receives the command "48 h", the sequencer 14 restarts the erase operation and starts the process during the erase verification period. In other words, when the semiconductor memory device 10 receives the read instruction, the suspend read is performed after the end of the process during erase and the process during step-down and before the erase verification period.

In the example shown in fig. 29, when the semiconductor memory device 10 receives a read command (for example, "30 h") during the erase period (fig. 29, 1 st period (2)), the erase operation is immediately interrupted to start the pause of the read. Specifically, for example, when the semiconductor memory device 10 receives a read command in the middle of the process of the "5" step in the erase period, the voltage of the well line CPWELL is immediately lowered (fig. 29, 1 st period (3)). Then, when the voltage of the well line CPWELL falls to Vss, the semiconductor memory apparatus 10 performs the suspend readout for the same pair of planes.

When the suspend reading ends, the memory controller sends an instruction "48 h". When the semiconductor memory device 10 receives the command "48 h", the sequencer 14 restarts the erase operation to increase the voltage of the well line CPWELL (fig. 29, period (1) 2). When the voltage of the well line CPWELL rises to Vera, the sequencer 14 restarts counting during erasing from the counting of the time point at which the erasing action is interrupted. That is, in this example, sequencer 14 restarts the processing during erasing from the processing of "5" step. Then, sequencer 14 ends the process during erase based on the fact that the process at step "9" during erase has been completed, and moves to the process during erase verification.

In the example shown in fig. 30, when the semiconductor memory device 10 receives a read command (for example, "30 h") during the erase period (2) in fig. 30 and 1), the erase operation is interrupted and the background read is started based on the completion of the processing in the step at the time of receiving the read command. In other words, when the semiconductor memory device 10 receives the read instruction, the interrupt processing is suspended before the end of the processing of the erase period 1 step, and then the suspension of the read is started.

Specifically, for example, when the semiconductor memory device 10 receives a read command in the middle of the process of "5" step in the erase period, the process period is continued until the process of "5" step is completed. Then, when the process of step "5" is completed, the semiconductor memory device 10 lowers the voltage of the well line CPWELL (fig. 30, period (3) 1). When the voltage of the well line CPWELL falls to Vss, the semiconductor memory apparatus 10 performs the suspended readout for the same pair of planes.

When the suspend reading ends, the memory controller sends an instruction "48 h". When the semiconductor memory device 10 receives the command "48 h", the sequencer 14 restarts the erase operation to raise the voltage of the well line CPWELL (fig. 30, period (1) 2). When the voltage of the well line CPWELL rises to Vera, the sequencer 14 resumes the process during erase from the last cycle in period 1. That is, in this example, sequencer 14 restarts from the processing of the next "6" step of the "5" step. Then, sequencer 14 ends the process during erase based on the fact that the process at step "9" during erase has been completed, and shifts to the process during erase verification.

In the example shown in fig. 31, when the semiconductor memory device 10 receives a read command (for example, "30 h") during the erase period (fig. 31, period (2) 1), the erase operation is interrupted and the background read operation is started based on the fact that the processing for the next step of the step at the time of reception of the read command has ended. In other words, when the semiconductor memory device 10 receives the read instruction, the interrupt processing is suspended before the end of the processing of the erase period 2 step, and then the suspension of the read is started.

Specifically, for example, when the semiconductor memory device 10 receives a read command in the middle of the process of "5" step in the erase period, the semiconductor memory device continues the process period until the process of the next "6" step in the "5" step is completed. Then, when the process of step "6" is completed, the semiconductor memory device 10 lowers the voltage of the well line CPWELL (fig. 31, period (3) 1). When the voltage of the well line CPWELL falls to Vss, the semiconductor memory apparatus 10 performs the suspended readout for the same pair of planes.

When the suspend reading ends, the memory controller sends an instruction "48 h". When the semiconductor memory device 10 receives the command "48 h", the sequencer 14 restarts the erasing operation of the foreground and raises the voltage of the well line CPWELL (fig. 31, period (1) 2). When the voltage of the well line CPWELL rises to Vera, the sequencer 14 resumes the process during erase from the last cycle in period 1. That is, in this example, sequencer 14 restarts from the processing of the next "7" step of the "6" step. Then, sequencer 14 ends the process during erase based on the fact that "9" steps have been counted during erase, and shifts to the process during erase verification.

The number of steps before the erase operation is interrupted after the read command is received can be set to any value. In addition, the semiconductor memory device 10 may be configured such that the erase period is processed until the end of the erase period, and the interrupt processing is started, depending on the number of steps before the erase operation is interrupted and the time when the read command is received.

For example, in the example shown in fig. 30, when the semiconductor memory device 10 receives a read instruction in the middle of the processing of the "9" loop, the interrupt processing may be executed after the processing of the "9" loop is completed. In the example shown in fig. 31, when the semiconductor memory device 10 receives a read command in the middle of the processing of the "8" or "9" loop, the interrupt processing may be executed after the processing of the "9" loop is completed.

(case where a read instruction is received during erase verification)

Fig. 32 and 33 each show an example of execution time of background reading for selecting the plane PL of the same power supply group in the semiconductor memory device 10 according to embodiment 1, and correspond to an operation of the semiconductor memory device 10 when receiving a read command during an erase verification period of an erase operation.

In the example shown in fig. 32, when the semiconductor memory device 10 receives a read instruction (for example, "30 h") during the erase verification period (fig. 32, (4)), the semiconductor memory device starts an interrupt process (read operation) after the erase verification of all the string units SU to be the erase verification is completed. In other words, the semiconductor storage device 10 causes the suspend readout to be performed after the process during the erase verification performed at the time point when the readout instruction is received is completed.

Specifically, for example, when a read instruction is received during execution of the erase verification for the string component SU1, the semiconductor memory device 10 suspends the interrupt processing until the end of the erase verification for each of the string components SU1, SU2, and SU 3. Then, when the detection operation of the erase verification in the string unit SU3 is completed, the semiconductor memory device 10 starts the interrupt processing based on the reception of the instruction "48 h". In this example, since the erasing operation is ended at the time point when the interrupt processing is started, the process of restarting the erasing operation by the command "48 h" described with reference to fig. 27 can be omitted.

In the example shown in fig. 33, when the semiconductor memory device 10 receives a read command (for example, "30 h") during the erase verification period (fig. 33, (4)), the semiconductor memory device immediately starts suspending the read. In other words, the semiconductor storage device 10 interrupts the processing during the erase verification performed at the time point when the read instruction is received, and performs the suspend read. Then, when the suspend readout ends, the memory controller sends an instruction "48 h". When the semiconductor memory device 10 receives the instruction "48 h", it backs up and restarts the cycle of the interrupted erase verification. That is, the semiconductor memory apparatus 10 re-executes the cycle of the interrupted erase verification.

Specifically, for example, when a read instruction is received during execution of erase verification for the string component SU1, the semiconductor memory device 10 immediately executes suspend reading. Then, when the suspend readout ends, the semiconductor memory apparatus 10 performs the erase verification for the string component SU1 again.

The time for which the semiconductor memory device 10 performs the suspend reading for selecting the same pair of planes is not limited to the above-described example. For example, the semiconductor memory device 10 may execute the suspend read of the same pair of planes based on the case where the 1-cycle erase verification is completed as described with reference to fig. 25.

[1-3] Effect of embodiment 1

According to the semiconductor memory device 10 of embodiment 1 described above, the latency of the semiconductor memory device 10 can be improved. Hereinafter, the detailed effects of embodiment 1 will be described using comparative examples.

Fig. 34 shows an example of a command sequence and a timing chart in the pause reading in the erasing operation according to the comparative example of embodiment 1. As shown in fig. 34, in the comparative example of embodiment 1, first, the erase operation described with reference to fig. 11 is performed, and the semiconductor memory device 10 is turned into a busy state. Then, when receiving a command for a read operation from an external host device while the semiconductor memory device 10 is executing an erase operation, the memory controller transmits a command "FFh" to the semiconductor memory device 10. The command "FFh" is a command instructing the semiconductor memory device 10 to suspend an operation during processing.

The semiconductor memory device 10 suspends the erase operation when receiving the command "FFh" and transitions to the ready state when the suspension process is completed. In this way, the memory controller transmits, for example, the command "00 h", the address information "ADD", and the command "30 h" to the semiconductor memory device 10 based on the fact that the semiconductor memory device 10 is ready.

The semiconductor memory device 10 transitions to a busy state when receiving the command "30 h", and performs a read operation (suspend read) based on the received command or the like. The semiconductor memory device 10 transits to a ready state when the suspend readout ends, and outputs readout data "Dout" to the memory controller based on an instruction of the memory controller.

When the reception of the read data is completed, the memory controller continues to transmit, for example, the command "27 h" and the same command set as the interrupted erase operation to the semiconductor memory device 10. The command "27 h" is a command for instructing the semiconductor memory device 10 to resume the suspended operation. When receiving the command "D0 h", the semiconductor memory device 10 transitions to the busy state and resumes the erasing operation.

When the pause reading is executed as in the comparative example of embodiment 1 described above, the erasing operation is not performed during the execution of the pause reading. Therefore, in the comparative example of embodiment 1, the erasing operation is delayed. In addition, in the comparative example of embodiment 1, since the memory controller sends a command for a read operation after suspending the semiconductor memory device 10, these processing times affect the reduction of the waiting time.

In contrast, the semiconductor memory device 10 according to embodiment 1 uses a cache erase operation that performs an erase operation in a ready state using the command "D3 h" for execution of the erase operation. Further, in the semiconductor memory device 10 according to embodiment 1, when receiving an instruction of a read operation of an interrupt process in the middle of an erase operation, an execution method of the interrupt process is changed based on a relationship between a plane PL on which the erase operation is executed and a plane PL selected in the interrupt process.

For example, in each of the case where the plane PL of the same power supply group is selected and the case where the plane PL of a different power supply group is selected in the interrupt processing, the semiconductor memory device 10 executes the erase operation of the foreground and the read operation of the interrupt processing in parallel. When the same pair of planes is selected during the interrupt processing, the semiconductor memory device 10 suspends the erasing operation of the foreground and then executes the reading operation of the interrupt processing.

Further, in the semiconductor memory device 10 according to embodiment 1, the execution time of the interrupt process is appropriately adjusted based on the time when the read command is received and the progress state of the erase operation, and the interrupt process is executed.

For example, when the plane PL of the same power supply group is selected in the interrupt processing, the semiconductor memory device 10 executes the interrupt processing without being suspended when receiving the read command. In this case, the semiconductor memory apparatus 10 can transmit the read data of the interrupt process to the memory controller at the fastest speed.

When the plane PL of the same power supply group is selected during interrupt processing, the semiconductor memory device 10 suspends interrupt processing for a specific period and thereafter executes the interrupt processing when receiving a read command. In this case, the semiconductor memory device 10 can suppress the influence of power supply noise of the same power supply group caused by the erase operation performed in the foreground in the read operation in the interrupt process.

When the plane PL of a different power supply group is selected in the interrupt processing, it is considered that the influence of power supply noise generated by the erase operation is small. Therefore, the semiconductor memory device 10 can always maintain a good latency by executing the interrupt processing without suspension in response to the reception of the read instruction.

When the same pair of planes is selected in the interrupt processing, the semiconductor memory device 10 suspends the erasing operation at a specific time when receiving the read command, and executes the interrupt processing. For example, when priority is given to the waiting time, the semiconductor memory device 10 immediately suspends the erase operation and executes the interrupt processing upon receiving the read command. On the other hand, when it is desired to ensure that the erasing operation is performed together with the waiting time, the semiconductor memory device 10 can suppress the backward movement of the erasing operation by suspending the reading process for a specific period when receiving the reading command.

As described above, the semiconductor memory device 10 according to embodiment 1 can execute the interrupt processing without using the suspend command "FFh" by performing the erase operation in the ready state. Further, the semiconductor memory device 10 according to embodiment 1 can execute the read operation in the interrupt process without stopping the erase operation as much as possible, and can suppress the influence on the erase operation even when the erase operation is suspended.

As a result, the semiconductor memory device 10 according to embodiment 1 can output read data to the memory controller earlier than the read operation in the interrupt process of the comparative example. That is, the semiconductor memory device 10 according to embodiment 1 can improve the latency as compared with the read operation in the interrupt processing of the comparative example.

The interrupt processing described in embodiment 1 may be continuously executed. In this case, after receiving the read data for the interrupt processing, the memory controller continues to instruct the semiconductor memory device 10 to perform the read operation without issuing the command "48 h". When the series of interrupt processing is completed, the memory controller transmits a command "48 h" to the semiconductor memory device 10 to restart the erasing operation.

The plane PL selected in the successive interrupt processing is not restricted by a power supply group (for example, the same power supply group, different power supply groups, the same pair of planes). For example, if the same pair of planes is selected in the successive interrupt processing, the erasing operation of the semiconductor memory device 10 is suspended before the instruction "48 h" is issued after the interrupt processing is executed. When interrupt processing for selecting the same power supply group and interrupt processing for selecting the same pair of planes are executed successively, the former processing is executed without being suspended, but when an instruction for instructing the latter processing is received, the erasing operation is suspended at a specific time. In this case, the suspended erase operation may be resumed by transmitting a command "48 h" to the semiconductor memory device 10.

[2] Embodiment 2

The semiconductor memory device 10 according to embodiment 2 has the same configuration as the semiconductor memory device 10 according to embodiment 1. The semiconductor memory device 10 according to embodiment 2 differs from that according to embodiment 1 in the operation during the erase period of the erase operation. Hereinafter, differences from embodiment 1 will be described with respect to the semiconductor memory device 10 according to embodiment 2.

[2-1] Erasing action

Fig. 35 is a timing chart showing an example of an erasing operation in the semiconductor memory device 10 according to embodiment 2. As shown in fig. 35, the erase operation in embodiment 2 differs from the erase operation described with reference to fig. 12 in embodiment 1 in the erase period.

Specifically, during the erase period, the voltage generation circuit causes the voltage of the well line CPWELL to rise to Vera by rising a plurality of times. In fig. 35, the rise amount of the voltage of the well line CPWELL is represented by Vdelta, and the change in the voltage of the well line CPWELL during the erase period is represented by steps S0 to S3.

Further, the voltage of the well line CPWELL at the start time point (time t1) of the erase period may be set to an arbitrary voltage. In addition, the number of increases in the voltage of the well line CPWELL during erase can be set to any number of times, and the amount of increase can be set to any voltage. The voltage halfway through the rise during erase applied to the well line CPWELL may also be referred to as an erase voltage.

The semiconductor memory device 10 according to embodiment 2 can execute the same erase operation as that in fig. 35 as the cache erase operation when the command "D0 h" is replaced with the command "D3 h". The other operations of the erasing operation in embodiment 2 are the same as those in embodiment 1, and therefore, the description thereof is omitted.

[2-2] interrupt processing in Erase action

The erasing operation in embodiment 2 described above can also be applied to the erasing operation executed in the foreground in the interrupt processing described in embodiment 1. In this case, the execution time of the interrupt processing described in embodiment 1 may be applied to all the execution times of the interrupt processing. In the case of using the erasing operation in embodiment 2, the operation different from that in embodiment 1 can be executed in the background reading of the plane PL selecting the same power pack.

Fig. 36 shows an example of execution time of background reading for selecting the plane PL of the same power supply group in the semiconductor memory device 10 according to embodiment 2, and corresponds to an operation of the semiconductor memory device 10 when receiving a read command during an erase period of an erase operation.

In the example shown in fig. 36, the semiconductor memory device 10 starts background reading immediately when it receives a read command (for example, "30 h") during the erase period (fig. 20, (2)). Then, during the execution of the background readout, the semiconductor memory apparatus 10 stops the rise of the voltage of the well line CPWELL. That is, the voltage of the well line CPWELL is maintained during the execution of the background readout. When the background readout ends, the semiconductor memory device 10 restarts the process during the erase, and restarts the rising of the voltage of the well line CPWELL.

Specifically, upon receiving a read instruction in step S2 during erasing, the semiconductor memory device 10 immediately starts background reading. Then, during the execution of the background readout, the voltage of the well line CPWELL maintains the voltage in step S2. When the background readout ends, the rising of the voltage of the well line CPWELL is resumed. Since other operations are the same as those described with reference to fig. 20, for example, the description thereof will be omitted.

[2-3] Effect of embodiment 2

As described above, the semiconductor memory device 10 according to embodiment 2 can use the erase operation different from that of embodiment 1, and can execute the interrupt processing in the erase operation as in embodiment 1. Therefore, the semiconductor memory device 10 according to embodiment 2 can obtain the same effects as those of embodiment 1, and can improve the waiting time.

The erasing operation described in embodiment 1 and the erasing operation described in embodiment 2 can be used separately from the semiconductor memory device 10. These erase operations can be distinguished and used according to the block BLK selected in the erase operation, for example, and can be suitably distinguished and used. These erasing operations can be used in a different manner according to a command issued by a memory controller, and the semiconductor memory device 10 can also be used in a different manner according to a specific condition.

[3] Embodiment 3

The configuration of the semiconductor memory device 10 according to embodiment 3 is the same as that of the semiconductor memory device 10 according to embodiment 1. The semiconductor memory device 10 according to embodiment 3 uses a special command to distinguish between the times of executing the interrupt processing for selecting the same pair of planes in embodiment 1. Hereinafter, differences from embodiments 1 and 2 will be described with respect to the semiconductor memory device 10 according to embodiment 3.

[3-1] interruption processing in Erase action

Fig. 37 and 38 show an example of a command sequence and a timing chart of an interrupt process for performing a cache erase operation and selecting the same pair of planes in the semiconductor memory device 10 according to embodiment 3. As shown in fig. 37 and 38, the operation in embodiment 3 differs from the operation described with reference to fig. 27 in embodiment 1 in the timing of resuming the erase operation after the instruction sequence and the interrupt processing (suspend reading).

In the example shown in fig. 37, the memory controller sequentially transmits a command "xxh", a command "00 h", address information "ADD", and a command "30 h" to the semiconductor memory device 10 in response to a read operation in an interrupt process. The instruction "xxh" is an instruction instructing the semiconductor memory apparatus 10 to execute an interrupt process with the 1 st condition. When receiving the command "30 h", the semiconductor memory device 10 interrupts the erase operation for a certain period of time and starts the read operation for the interrupt process described in embodiment 1. The subsequent operation in fig. 37 is the same as the operation described with reference to fig. 27.

On the other hand, in the example shown in fig. 38, the memory controller sequentially transmits the command "yyh", the command "00 h", the address information "ADD", and the command "30 h" to the semiconductor memory device 10 in accordance with the read operation of the interrupt processing. The instruction "yyh" is an instruction that instructs the semiconductor memory apparatus 10 to execute interrupt processing under the 2 nd condition different from the 1 st condition. When receiving the command "30 h", the semiconductor memory device 10 completes the erase operation and then continues the interrupt processing (suspend reading). At this time, the semiconductor memory device 10 continues to maintain the busy state from the erase operation, and when the suspend reading is completed, the busy state is changed to the ready state.

[3-2] Effect of embodiment 3

As described above, the semiconductor memory device 10 according to embodiment 3 can change the time for outputting the read data in the interrupt process by the use-by-division command. For example, the memory controller uses the instruction sequence under the 1 st condition when data is urgently needed, and uses the instruction sequence under the 2 nd condition when the time for which data is needed is sufficient.

That is, the semiconductor memory device 10 according to embodiment 3 can execute interrupt processing with different latencies by using a different instruction. As a result, the semiconductor memory device 10 according to embodiment 3 can suppress a decrease in the efficiency of the erasing operation due to the interrupt processing as necessary.

[4] Examples of variations and the like

The semiconductor memory device of the embodiment < e.g., fig. 1, 10 > includes a plurality of planes < e.g., fig. 2, PL > and a sequencer < e.g., fig. 1, 14 >. The planes each have a plurality of blocks as a set of storage units. The sequencer performs action 1 and action 2, which is shorter than action 1. The sequencer performs the 1 st action when receiving the 1 st instruction set indicating execution of the 1 st action. When the sequencer receives a 2 nd instruction set that instructs execution of a 2 nd action while the 1 st action is being executed, the 1 st action is suspended and the 2 nd action is executed < for example, fig. 16, 26 >, or the 2 nd action < for example, fig. 27 >, in parallel with the 1 st action, based on the address of the block to which the 1 st action is to be executed and the address of the block to which the 2 nd action is to be executed. Thus, the latency of the semiconductor memory device can be improved.

The semiconductor memory device 10 described in the above embodiment mode can be used as a memory system combined with a memory controller, for example. Fig. 39 is a block diagram showing an example of a memory system 1 including the semiconductor memory device 10 according to embodiment 1. As shown in fig. 39, the Memory system 1 includes, for example, semiconductor Memory devices 10-1 to 10-4, a Memory controller 2, and a Dynamic Random Access Memory (DRAM) 3.

Each of the semiconductor memory devices 10-1 to 10-4 has the same structure as the semiconductor memory device 10. The memory controller 2 is connected to each of the semiconductor memory devices 10-1 to 10-4, and can operate in the same manner as the external memory controller used in the description of the operation of the above embodiment. In addition, the memory controller 2 operates based on a command of the external host device 4. The DRAM3 is connected to the memory controller 2, and serves as an external storage area of the memory controller 2, for example. The number of semiconductor memory devices 10 included in the memory system 1 may be set to any number. The DRAM3 may also be built in the memory controller 2. The actions described in the embodiments may be performed by the memory system 1.

In the above embodiment, the case where the semiconductor memory device 10 executes the read operation while executing the erase operation is exemplified as the interrupt processing, but the present invention is not limited to this. For example, the semiconductor memory device 10 may execute the interrupt processing as described in the above embodiment while executing the write operation or the read operation. The operation executed in the interrupt processing is not limited to the read operation, and may be an erase operation or a write operation. In this case, the address EPG and EPP input to the determination circuit DC correspond to the address information during the operation of the foreground, and the address RPG and RPP input to the determination circuit DC correspond to the address information during the operation of the interrupt processing.

In the above-described embodiment, the case where the semiconductor memory device 10 restarts the erase operation using the command "48 h" when the interrupt processing is executed in the erase operation has been described as an example, but the present invention is not limited to this. For example, the semiconductor memory device 10 may autonomously restart the erasing operation after outputting read data obtained by the reading operation in the interrupt process to the memory controller. In other words, the semiconductor memory device 10 may be configured to restart the erasing operation without an instruction from the memory controller.

In the above embodiment, the case where the plane group PG includes the pair plane PP is exemplified, but the plane group PG may not include the pair plane PP. In this case, the plane group PG includes a plurality of planes PL independently. In this case, the semiconductor memory device 10 can also execute the operation described in the above embodiment, and the same effect as that of the above embodiment can be obtained.

The operation time in the interrupt processing described in the embodiment can be selected by the user. The semiconductor memory device 10 may store the parameters related to the operation time and change the operation time based on the parameters. The operation time in the interrupt processing may be automatically switched in the semiconductor memory device 10 according to the relationship between the address corresponding to the previous operation and the address corresponding to the interrupt processing operation, or the combination of the previous operation and the interrupt processing operation.

In the above embodiment, the case where 1 memory cell transistor MT stores 2-bit data is exemplified, but 1 memory cell transistor MT may store 1-bit data, or 3 or more bits of data. In addition, the distribution of data to the distribution of the threshold voltages of the memory cell transistors MT can be set to any distribution. In this case, the semiconductor memory device 10 can also perform the operation of the above embodiment, and the same effect can be obtained.

In the above embodiment, the instructions "xxh" and "yyh" used in the description may be replaced with arbitrary instructions. In addition, other instructions may be replaced with other instructions as appropriate. Further, although the case where the command related to the read operation starts with the command "00 h" has been described, a command for specifying a bit of a page to be read may be added before the command "00 h".

The memory cell array 20 in the above embodiment may have another configuration. The other memory cell array 20 is described in, for example, U.S. patent application 12/407,403 entitled "three-dimensional stacked nonvolatile semiconductor memory" applied on 3/19 of 2009, U.S. patent application 12/406,524 entitled "three-dimensional stacked nonvolatile semiconductor memory" applied on 3/18 of 2009, U.S. patent application 12/679,991 entitled "nonvolatile semiconductor memory device and method for manufacturing the same" applied on 3/25 of 2010, and U.S. patent application 12/532,030 entitled "semiconductor memory and method for manufacturing the same" applied on 3/23 of 2009. The entire contents of these patent applications are incorporated by reference in the specification of the present application.

In the above embodiment, the case where the memory cell transistor MT provided in the memory cell array 20 has a three-dimensional multilayer structure has been described as an example, but the present invention is not limited thereto. For example, the memory cell array 20 may be a planar NAND flash memory in which the memory cell transistors MT are two-dimensionally arranged. In this case, the above-described embodiment can be realized, and the same effects can be obtained.

In the embodiment, the block BLK may not be an erase unit. Other erase operations are described in U.S. patent application 13/235,389 entitled "nonvolatile semiconductor memory device" and applied on 9/18/2011 and U.S. patent application 12/694,690 entitled "nonvolatile semiconductor memory device" and applied on 27/2010/1/27. The entire contents of these patent applications are incorporated by reference in the specification of the present application.

In this specification, an "instruction set" indicates a group of instructions and address information corresponding to an operation. When receiving a command set from the memory controller, the semiconductor memory device 10 starts operation based on the command set.

In the present specification, "connection" means electrical connection, and does not exclude other elements interposed therebetween, for example. In this specification, the term "off state" means that a voltage smaller than the threshold voltage of the corresponding transistor is applied to the gate of the transistor, and does not exclude a minute current such as a leakage current flowing through the transistor.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.