阅读说明：本技术 陶瓷电子器件及其制造方法 (Ceramic electronic device and method for manufacturing the same ) 是由 志村哲生 萩原智也 猪又康之 于 2020-10-16 设计创作，主要内容包括：本申请涉及一种陶瓷电子器件,其包括层叠结构,其中电介质层和内部电极层交替层叠,其中电介质层的主要组分是(Ba,Sr,Ca)(Zr,Ti)O-3,其中在电介质层中的至少一个晶粒中Ba浓度和Ca浓度有变化。(The present application relates to a ceramic electronic device comprising a laminated structure in which dielectric layers and internal electrode layers are alternately laminated, wherein the main component of the dielectric layers is (Ba, Sr, Ca) (Zr, Ti) O 3 Wherein the concentration of Ba and the concentration of Ca vary in at least one grain in the dielectric layer.)

1. A ceramic electronic device comprising:

a stacked structure in which dielectric layers and internal electrode layers are alternately stacked,

wherein the main component of the dielectric layer is (Ba, Sr, Ca) (Zr, Ti) O₃，

Wherein there is a variation in the concentration of Ba and Ca in at least one grain in the dielectric layer.

2. The ceramic electronic device according to claim 1, wherein a CV value of (the Ca concentration)/(the Ba concentration) at 20 points of one or more crystal grains in a cross section of the dielectric layer is 0.06 or more.

3. The ceramic electronic device of claim 2, wherein the 20 dots comprise 10 dots of one grain of the dielectric layer and 10 dots of another grain of the dielectric layer.

4. The ceramic electronic device according to any one of claims 1 to 3, wherein when the dielectric layer is (Ba, Sr, Ca) (Zr, Ti) O₃The reference composition of (B) is represented by (Ba)_xSr_yCa_z)(Zr_sTi_t)O₃When x is not less than 0<0.4、0<y<0.7、0<z<0.8、x+y+z＝1、0.9<s<1 and 0<t<A relationship of 0.1.

5. The ceramic electronic device according to any one of claims 1 to 4, wherein an average diameter of crystal grains of the dielectric layer is 0.1 μm or more and 1.0 μm or less.

6. The ceramic electronic device according to any one of claims 1 to 5, wherein a thickness of the dielectric layer is 1 μm or more and 10 μm or less.

7. A method of manufacturing a ceramic electronic device, comprising the steps of:

forming a laminated structure in which dielectric green sheets including (Ba, Sr, Ca) (Zr, Ti) O and metal conductive paste layers are alternately laminated₃The powder of (a) is,

forming a dielectric layer from the dielectric green sheet by firing the laminated structure; and

cooling the laminated structure after firing,

wherein the cooling conditions of the cooling are adjusted during the cooling such that there is a variation in the concentration of Ba and the concentration of Ca in at least one grain in the dielectric layer.

8. The method of claim 7, wherein cooling from 800 ℃ to 250 ℃ takes more than 15 minutes.

Technical Field

One aspect of the present invention relates to a ceramic electronic component and a method of manufacturing the ceramic electronic component.

Background

Paraelectric perovskite type oxide (Ba, Sr, Ca) (Zr, Ti) O₃Is used as a main component of a ceramic composition for a temperature compensation material. A laminated ceramic capacitor including such a paraelectric perovskite type oxide for a dielectric layer is disclosed (for example, see japanese patent application laid-open nos. 2015 and 195352 and 2017 and 28254).

Disclosure of Invention

The invention provides a ceramic electronic device capable of improving reliability of a dielectric layer and a method for manufacturing the ceramic electronic device.

According to an aspect of the present invention, there is provided a ceramic electronic device including: a laminated structure of whereinDielectric layers and internal electrode layers are alternately stacked, wherein the main component of the dielectric layers is (Ba, Sr, Ca) (Zr, Ti) O₃Wherein the concentration of Ba and the concentration of Ca vary in at least one grain in the dielectric layer.

According to another aspect of the present invention, there is provided a method of manufacturing a ceramic electronic device, comprising the steps of: forming a laminated structure in which dielectric green sheets comprising (Ba, Sr, Ca) (Zr, Ti) O and metal conductive paste layers are alternately laminated₃The powder of (4); forming a dielectric layer from the dielectric green sheet by firing the laminated structure; and cooling the stacked structure after firing, wherein a cooling condition of the cooling is adjusted during the cooling so that a Ba concentration and a Ca concentration in at least one crystal grain in the dielectric layer are changed.

Drawings

Fig. 1 shows a perspective view of a laminated ceramic capacitor, in which a cross section of a part of the laminated ceramic capacitor is shown;

FIG. 2 illustrates individual grains of a dielectric layer;

fig. 3 shows a method for manufacturing a laminated ceramic capacitor.

FIG. 4 shows selected points in the observed grains for samples 2-3; and

fig. 5 shows selected points in another observed grain for samples 2-3.

Detailed Description

(Ba,Sr,Ca)(Zr,Ti)O₃Is relatively small. Therefore, in order to reduce the size of the device, it is necessary to reduce the thickness of the dielectric layer and stack the dielectric layer. In order to reduce the thickness of the dielectric layer, it is necessary to improve the reliability of the dielectric layer.

When a metal such as Ni is used for the internal electrode layers, a firing process in a reducing atmosphere is performed. In this case, (Ba, Sr, Ca) (Zr, Ti) O is used₃Is subjected to a reducing atmosphere, and (Ba, Sr, Ca) (Zr, Ti) O₃May be electronically conductive. Therefore, when the thickness of the dielectric layer is reduced, reliability related to the insulation resistance of the dielectric layer may be degraded.

A description will be given of embodiments with reference to the accompanying drawings.

(embodiment) fig. 1 shows a perspective view of a laminated ceramic capacitor 100 according to an embodiment, in which a cross section of a part of the laminated ceramic capacitor 100 is shown. As shown in fig. 1, the laminated ceramic capacitor 100 includes a laminated chip 10 having a rectangular parallelepiped shape, and a pair of external electrodes 20a and 20b provided respectively on both end faces of the laminated chip 10 facing each other. Of the four surfaces other than the two end surfaces of the laminated chip 10, two surfaces other than the upper surface and the lower surface of the laminated chip 10 in the laminating direction are referred to as side surfaces. The external electrodes 20a and 20b extend to the upper surface, the lower surface, and both side surfaces of the laminated chip 10. However, the external electrodes 20a and 20b are spaced apart from each other.

The laminated chip 10 has a structure designed to have dielectric layers 11 and internal electrode layers 12 alternately laminated. The dielectric layer 11 includes a ceramic material serving as a dielectric material. The internal electrode layers 12 comprise a base metal material. The edges of the internal electrode layers 12 are alternately exposed at a first end face of the laminated chip 10 and a second end face of the laminated chip 10 different from the first end face. In this embodiment, the first end face faces the second end face. The external electrode 20a is provided on the first end face. The external electrode 20b is disposed on the second end face. Therefore, the internal electrode layers 12 are alternately guided to the external electrodes 20a and the external electrodes 20 b. Therefore, the laminated ceramic capacitor 100 has a structure in which a plurality of dielectric layers 11 are laminated and every two dielectric layers 11 sandwich the internal electrode layer 12. In the laminated chip 10, the internal electrode layers 12 are located at the outermost layers. The upper and lower surfaces of the laminated chip 10 are internal electrode layers 12, which are covered with a cover layer 13. The main component of the cover layer 13 is a ceramic material. For example, the main component of the cover layer 13 is the same as that of the dielectric layer 11.

For example, the laminated ceramic capacitor 100 may have a length of 0.25mm, a width of 0.125mm, and a height of 0.125 mm. The laminated ceramic capacitor 100 may have a length of 0.4mm, a width of 0.2mm, and a height of 0.2 mm. The laminated ceramic capacitor 100 may have a length of 0.6mm, a width of 0.3mm, and a height of 0.3 mm. The laminated ceramic capacitor 100 may have a length of 1.0mm, a width of 0.5mm, and a height of 0.5 mm. The laminated ceramic capacitor 100 may have a length of 3.2mm, a width of 1.6mm, and a height of 1.6 mm. The laminated ceramic capacitor 100 may have a length of 4.5mm, a width of 3.2mm, and a height of 2.5 mm. However, the size of the laminated ceramic capacitor 100 is not limited.

The main component of the internal electrode layers 12 is a base metal such as nickel (Ni), copper (Cu), tin (Sn), or the like. The internal electrode layers 12 may be made of a noble metal such as platinum (Pt), palladium (Pd), silver (Ag), gold (Au), or an alloy thereof. The average thickness of each internal electrode layer 12 is preferably 1 μm or less. More preferably, the average thickness is 0.5 μm or less.

The dielectric layer 11 is mainly composed of a material represented by the general formula ABO₃Represents and has a perovskite structure. The perovskite structure comprises an ABO having a non-stoichiometric composition_3-α. Specifically, the main component of the dielectric layer 11 is (Ba, Sr, Ca) (Zr, Ti) O₃。(Ba,Sr,Ca)(Zr,Ti)O₃The A site of (B) includes Ba (barium), Sr (strontium) and Ca (calcium). (Ba, Sr, Ca) (Zr, Ti) O₃The B site of (a) includes Zr (zirconium) and Ti (titanium). There are cases where the A site does not include Ba. (Ba, Sr, Ca) (Zr, Ti) O₃Is paraelectric and has a temperature compensation characteristic in which the dependence of the electrostatic capacitance on temperature is small. (Ba, Sr, Ca) (Zr, Ti) O₃The reference composition of (b) is an average composition ratio of Ba, Sr, Ca, Zr, and Ti of the entire dielectric layer 11. In order to suppress the influence of segregation, the reference composition can be confirmed by TEM (transmission electron microscope) by performing surface analysis of a plurality of regions. For example, when the reference composition of the dielectric layer 11 is expressed as (Ba)_xSr_yCa_z)(Zr_sTi_t)O₃When x is more than or equal to 0 and less than 0.4, y is more than 0 and less than 0.7, z is more than 0 and less than 0.8, x + y + z is 1, 0.9<s<1，0<t<0.1, s + t is a relationship of 1.

For example, the internal electrode layers 12 are formed by firing a metal conductive paste including metal powder. The dielectric layer 11 and the cover layer 13 are formed by firing a green sheet including ceramic powder. Base metal powder is used for the internal electrode layers 12. Therefore, a reducing atmosphere is preferably used as the firing atmosphere. In this case, the reducing atmosphere affects (Ba, Sr, Ca) (Zr, Ti) O₃And (Ba, Sr, Ca) (Zr,Ti)O₃may be electronically conductive. Therefore, when the thickness of the dielectric layer 11 is reduced, the reliability of the insulation resistance of the dielectric layer 11 may be reduced. Accordingly, the dielectric layer 11 of the embodiment has a structure for improving reliability.

Fig. 2 shows a cross section of a grain 14 in the dielectric layer 11. As shown in fig. 2, the dielectric layer 11 has crystal grains 14, which are demarcated as crystal grain boundaries 15. The crystal grain 14 is (Ba, Sr, Ca) (Zr, Ti) O₃The crystal grains of (1). Each crystal grain 14 has an element in which the amount of Ba is larger than (Ba, Sr, Ca) (Zr, Ti) O₃And wherein the amount of Ca is greater than (Ba, Sr, Ca) (Zr, Ti) O₃The average amount of Ca in the crystal grains. That is, the concentration of Ba and the concentration of Ca are not uniform in each crystal grain 14. For example, when spot quantification is performed, the Ba-rich spot P_BaAnd a Ca-rich point P_CaMixed together as shown in fig. 2. However, in each point, the a site includes Ba, Sr, and Ca, and the B site includes Zr and Ti. The dielectric layer 11 has a temperature compensation characteristic. The dot size (dot diameter) is, for example, about 1.0 nm.

When the crystal grains 14 of the dielectric layer 11 have such a structure, breakdown up to a high voltage can be suppressed as compared with the case where Ca and Ba are solid-dissolved in the crystal grains 14 and the ratio of Ca concentration/Ba concentration is uniform in the crystal grains 14. This is because the composition distribution (concentration of Ca and concentration of Ba are not uniform) formed in the crystal grains 14 functions as a barrier against ion diffusion, the insulating property is improved, and electric field breakdown hardly occurs. Thus, the reliability of the insulation resistance can be improved, while the dielectric layer 11 still has temperature compensation.

When point P_BaAnd point P_CaWhen mixed together in the crystal grains 14, the crystal grains are not divided into a Ba-rich region and a Ca-rich region, but a point P_BaAnd point P_CaAre randomly distributed. Therefore, when a point is randomly selected in a cross section of one crystal grain 14, there may be a midpoint P thereof_BaAnd point P_CaIn the case of alternating arrangement.

It is preferable that the variation in Ba concentration and the variation in Ca concentration be large in each point of the crystal grains 14. For example, when taken from a cross-section of one or more of the grains 14When a plurality of spots (for example, 20 spots) are selected and EDS elemental analysis is performed on the plurality of spots using a TEM (transmission electron microscope), the CV (coefficient of variation) of Ca concentration (atm%)/Ba concentration (atm%) at each spot is preferably 0.06 or more. More preferably, the CV value is 0.12 or more. More preferably, the CV value is 0.19 or more. 20 points, 10 points for one die 14 and 10 points for another die 14 may be selected. Half of the plurality of dots may be selected from the Ba-rich dots P_BaWhile the remaining half may be selected from the Ca-rich points P_Ca。

For example, the average particle size of the crystal grains 14 is 0.1 μm or more and 1.0 μm or less.

When the thickness of the dielectric layer 11 is reduced, the influence of deterioration in reliability of the dielectric layer 11 is large. Therefore, when the thickness of the dielectric layer 11 is reduced, the effect of improving the reliability of the dielectric layer 11 is remarkable. For example, when the thickness of the dielectric layer 11 is 1 μm or more and 10 μm or less, the effect of improving the reliability is remarkable. When the thickness of the dielectric layer 11 is 1 μm or more and 5 μm or less, the effect of improving the reliability is more remarkable.

Next, a description will be given of a manufacturing method of the laminated ceramic capacitor 100. Fig. 3 shows a method for manufacturing the laminated ceramic capacitor 100.

(process for producing raw material powder) a dielectric material for forming the dielectric layer 11 is prepared. Preparation of (Ba, Sr, Ca) (Zt, Ti) O₃The ceramic powder of (1). As (Ba, Sr, Ca) (Zt, Ti) O, various methods can be used₃The method for synthesizing a ceramic powder of (1). For example, a solid phase method, a sol-gel method, a hydrothermal method, or the like can be used. Embodiments may use any of these methods.

The additive compound may be added to the obtained ceramic powder according to the purpose. The additive compound may be an oxide or glass of Mo (molybdenum), Nb (niobium), Ta (tantalum), W (tungsten), Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium)), Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium) and Si.

The ceramic powder is mixed with a compound including an additive and calcined at a temperature ranging from 820 ℃ to 1150 ℃. Subsequently, the obtained ceramic powder is wet-mixed, dried and pulverized. For example, from the viewpoint of reducing the thickness of the dielectric layer 11, the average particle diameter of the obtained ceramic powder is preferably 50nm to 300 nm. The particle size can be adjusted by pulverizing the obtained ceramic powder as necessary. Alternatively, the particle size of the obtained ceramic powder may be adjusted by a combination of pulverization and classification.

(laminating process) next, a binder such as a polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the resulting dielectric material and wet-mixed. Using the resulting slurry, a strip-shaped dielectric green sheet is coated on a substrate by, for example, a die coater method or a doctor blade method, and then dried.

Then, a pattern of the internal electrode layers 12 is provided on the surface of the dielectric green sheet by printing a metal conductive paste for forming the internal electrodes using screen printing or gravure printing. The conductive paste includes an organic binder. The metal conductive paste may include ceramic particles as a common material. The metal conductive paste may not necessarily include ceramic particles. When the metal conductive paste includes ceramic particles, the main component of the ceramic particles is not limited. However, it is preferable that the main component of the ceramic particles is the same as that of the dielectric layer 11.

Then, the dielectric green sheets on which the internal electrode layer pattern is printed are punched out into a predetermined size, and a predetermined number (for example, 100 to 500) of the punched out dielectric green sheets are stacked while peeling off the base material so that the internal electrode layers 12 and the dielectric layers 11 alternate with each other and the end edges of the internal electrode layers 12 are alternately exposed to both end surfaces in the longitudinal direction of the dielectric layers 11, thereby being alternately led out to a pair of external electrodes 20a and 20b different in polarity. A cover sheet to be the cover layer 13 is pressure-bonded to the upper surface of the laminated dielectric green sheet, and another cover sheet to be the cover layer 13 is pressure-bonded to the lower surface of the laminated dielectric green sheet. The resulting laminated structure is blanked to a predetermined size (e.g., 1.0mm x 0.5 mm).

(firing step) in N₂The binder is removed in an atmosphere. Thereafter, the resulting shape is formedBody partial pressure of oxygen is 10^-5To 10^{- 8}Firing in a reducing atmosphere of atm at a temperature ranging from 1100 ℃ to 1300 ℃ for 10 minutes to 2 hours. Thus, each compound was sintered. In this way, a ceramic laminated structure is obtained.

(cooling process) at a high temperature such as a firing temperature, each element is uniformly present in each crystal grain 14. Therefore, the variation in Ba concentration and the variation in Ca concentration are small. When the dielectric layer 11 is cooled at a large cooling rate from this state, the movement of the element in the crystal grains 14 is suppressed. Therefore, variation in Ba concentration and variation in Ca concentration hardly occur in each crystal grain 14. On the other hand, when the dielectric layer 11 is cooled at a low cooling rate, the element moves in each crystal grain 14. Therefore, a change in Ba concentration and a change in Ca concentration easily occur. Therefore, in this embodiment, the cooling conditions are adjusted so that a variation in Ba concentration and a variation in Ca concentration occur in each crystal grain 14. For example, the dielectric layer 11 is cooled at a low rate from the firing temperature.

Specifically, it takes preferably 15 minutes or more to cool the dielectric layer 11 from 600 ℃ to 250 ℃. More preferably, it takes more than 20 minutes to cool the dielectric layer 11 from 600 c to 250 c. More preferably, it takes more than 30 minutes to cool the dielectric layer 11 from 600 c to 250 c. When the cooling time is long, internal cracking due to phase transformation may occur. Preferably, the cooling time from 800 ℃ to 250 ℃ has an upper limit. For example, it preferably takes 120 minutes or less to cool the dielectric layer 11 from 800 ℃ to 250 ℃. It preferably takes less than 90 minutes to cool the dielectric layer 11 from 800 c to 250 c. More preferably, it takes 60 minutes or less to cool the dielectric layer 11 from 800 c to 250 c.

After the (reoxidation step), in the presence of N₂The reoxidation step is carried out at a temperature in the range of 600 to 1000 ℃ in an atmosphere.

After (the plating process), the external electrodes 20a and 20b are coated with metals such as Cu, Ni, and Sn by electrolytic plating or the like.

In the method of manufacturing the laminated ceramic capacitor of the embodiment, the cooling conditions are adjusted in the cooling process after the firing process so that the Ba concentration occurs in the crystal grains 14Variation and variation in Ca concentration. Thus, for (Ba, Sr, Ca) (Zr, Ti) O₃A Ba-rich point P of the reference composition_BaAnd with respect to (Ba, Sr, Ca) (Zr, Ti) O₃A Ca-rich point P of the reference composition of (1)_CaMixed together in the grains 14 of the dielectric layer 11. Therefore, as compared with the case where Ca and Ba are uniformly solid-dissolved in the crystal grains 14, breakdown can be suppressed up to a higher voltage. Accordingly, the dielectric layer 11 may function as a temperature compensation member and improve the reliability of the insulation resistance. The cooling rate of the dielectric layer 11 is lower than that in the normal firing step. Therefore, the overall volume change is small, and the residual stress after firing is small. Thus, mechanical reliability is improved.

In the embodiment, a laminated ceramic capacitor is described as an example of a ceramic electronic device. However, the embodiment is not limited to the laminated ceramic capacitor. For example, the embodiments may be applied to another electronic device such as a varistor or a thermistor.

[ examples ]

The laminated ceramic capacitor according to the embodiment was manufactured, and the performance was measured.

(example 1) the main component of the dielectric green sheet was (Ba)_0.17Sr_0.56Ca_0.27)(Zr_0.95Ti_0.05)O₃. When the concentration of (Zr + Ti) was 100 atm%, the concentration of Si in the dielectric green sheet was 1 atm%. When the concentration of (Zr + Ti) is 100 atm%, the concentration of Mn of the dielectric sheet is 3 atm%. The thickness of the dielectric green sheet was 2.5 μm. Firing the laminated structure of the dielectric green sheet and the Ni conductive paste. It took 10 to 20 minutes to cool the laminated capacitor from 600 ℃ to 250 ℃. Thereby, the laminated ceramic capacitor 100 is manufactured. The number of samples was 5. Sample numbers 1-1 to 1-5.

(example 2) dielectric Green sheet the main component was (Ba)_0.15Sr_0.59Ca_0.26)(Zr_0.94Ti_0.06). Other conditions were the same as in example 1. The number of samples was 5. Sample numbers were 2-1 to 2-5.

(analysis) each sample was cut in a direction perpendicular to the inner electrode layers 12. The cross section is polished. And the composition image was observed in the cross section with a transmission electron microscope. A transmission Electron microscope JEM2100F manufactured by Japan Electron Optics corporation (Japan Electron Optics Laboratory) was used as the transmission Electron microscope. The acceleration voltage was 200 kV. The observation mode is STEM. Crystal grains 14 having a grain size of 500nm or more are observed in the dielectric layer 11. In the crystal grains 14, pattern traces were observed. This is part of the influence of changes in Ca concentration and changes in Ba concentration.

Two grains 14 were selected from a single dielectric layer 11 in each sample. EDS elemental analysis was performed on 10 points of each of the two dies 14. In the obtained image, 5 bright spots are selected, and 5 dark spots are selected. The dot size (dot diameter) was 1.0 nm.

Fig. 4 and 5 show selected points in two grains 14 observed for samples 2-3. In fig. 4 and 5, the dots 1 to 5 are bright dots. Points 6 to 10 are dark points. The bright spot is a Ba-rich spot. Dark spots are Ca-rich spots.

Table 1 shows the EDS elemental analysis results of the points in fig. 4. Table 2 shows the EDS elemental analysis results of the points in fig. 5. In tables 1 and 2, Ba/(Ca + Sr + Ba) of each bright point is larger than the reference composition ratios of 0.17 and 0.15 in tables 1 and 2. Therefore, the bright point was confirmed to be a Ba-rich point. On the other hand, Ca/(Ca + Sr + Ba) of each dark spot was larger than the reference composition ratios of 0.27 and 0.26 in tables 1 and 2. Therefore, it was confirmed that the dark spot was a Ca-rich spot.

[ Table 1]

[ Table 2]

For each sample, the standard deviation σ of (Ca concentration)/(Ba concentration) and the average value (ave) of (Ca concentration)/(Ba concentration) and the CV value (σ/ave) of (Ca concentration)/(Ba concentration) were calculated using the EDS elemental analysis results of 20 points. Table 3 shows the results. For sample 1-1, the standard deviation σ was 0.26, the average (ave) was 0.71, and the CV value was 0.37. With respect to samples 1-2, the standard deviation σ was 0.22, the average value (ave) was 0.73, and the CV value was 0.30. For samples 1-3, the standard deviation σ was 0.13, the average (ave) was 0.71, and the CV value was 0.19. For samples 1-4, the standard deviation σ was 0.08, the mean (ave) was 0.70, and the CV value was 0.12. For samples 1-5, the standard deviation σ was 0.04, the mean (ave) was 0.71, and the CV value was 0.06. For sample 2-1, the standard deviation σ was 0.72, the mean (ave) was 1.76, and the CV value was 0.41. For sample 2-2, the standard deviation σ was 0.58, the mean (ave) was 1.75, and the CV value was 0.33. For samples 2-3, the standard deviation σ was 0.35, the mean (ave) was 1.67, and the CV value was 0.21. For samples 2-4, the standard deviation σ was 0.23, the mean (ave) was 1.78, and the CV value was 0.13. For samples 2-5, the standard deviation σ was 0.12, the mean (ave) was 1.74, and the CV value was 0.07.

Next, the insulation resistance was measured for each sample. Specifically, the voltage-current characteristics between the external electrodes at 125 ℃ of each sample were measured. When the resistivity of the dielectric ceramic is 1 G.OMEGA.m or more, the insulation state is judged to be normal. When the resistivity is less than 1G Ω m, the insulation condition is judged as dielectric breakdown. When the electric field strength at which breakdown occurs is a value obtained by dividing the applied voltage by the average layer thickness of the dielectric is greater than 100V/μm, the situation is determined as good. When the value is less than 100V/μm, the condition is determined to be poor "x". Table 3 shows the results. All samples were judged good ". smallcircle". It is considered that this is because there are variations in Ba concentration and variations in Ca concentration in the respective crystal grains 14, and breakdown is suppressed up to a high voltage.

[ Table 3]

Although the embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention. The amounts of the respective elements of the dielectric layer 11 can be confirmed by performing ICP analysis or La-ICP-MS (laser ablation inductively coupled plasma mass spectrometry). And it has been confirmed that the amounts of the respective elements of the product measured by the analysis are consistent with the amounts of the respective elements added as the raw materials.