阅读说明：本技术 电压调节装置及采用其的存储器 (Voltage regulating device and memory using same ) 是由 蔡友刚 史维华 于 2020-12-15 设计创作，主要内容包括：本发明提供一种电压调节装置及采用其的存储器。所述电压调节装置能够根据预设采样点的反馈而调节预设采样点处的电压,使其保持稳定,提高预设采样点的电压稳定性及一致性。所述存储器能够通过所述电压调节装置钳位所述预设采样点的电压,使得其维持稳定,从而使得所述存储阵列的公共源极端电压维持稳定,提高公共源极端电压稳定性及一致性,进而提高存储器的读取精度。(The invention provides a voltage regulating device and a memory using the same. The voltage adjusting device can adjust the voltage at the preset sampling point according to the feedback of the preset sampling point, so that the voltage is kept stable, and the voltage stability and consistency of the preset sampling point are improved. The memory can clamp the voltage of the preset sampling point through the voltage regulating device to keep the voltage stable, so that the voltage of the common source terminal of the memory array is kept stable, the voltage stability and consistency of the common source terminal are improved, and the reading precision of the memory is further improved.)

1. A voltage adjustment device for adjusting a voltage at a predetermined sampling point, comprising:

the operational amplifier comprises an inverting input end, a non-inverting input end and an output end, wherein the inverting input end inputs a reference voltage, and the non-inverting input end is electrically connected with the preset sampling point and used for inputting the voltage of the preset sampling point to form a feedback loop;

the pull-up transistor comprises a control end, a first end and a second end, wherein the control end is electrically connected with the output end of the operational amplifier, the first end is electrically connected with a power supply, and the second end is electrically connected with the preset sampling point;

the pull-down transistor comprises a control end, a first end and a second end, wherein the control end is electrically connected with the output end of the operational amplifier, the first end is electrically connected with the grounding end, and the second end is electrically connected with the preset sampling point.

2. The voltage regulation device of claim 1, wherein the pull-up transistor is a PMOS transistor and the pull-down transistor is an NMOS transistor.

3. The voltage regulation device of claim 2, wherein a pull-down capability of the pull-down transistor is greater than a pull-up capability of the pull-up transistor.

4. The voltage regulation device of claim 1, wherein the voltage regulation device operates in class a/b mode when pulled up or lightly loaded, and operates in class a mode when heavily loaded.

5. The voltage regulation device of claim 1, wherein the pull-up transistor and the pull-down transistor are low voltage transistors.

6. The voltage regulator of claim 1, further comprising a switch transistor, wherein the second terminal of the pull-up transistor and the second terminal of the pull-down transistor are electrically connected to the switch transistor.

7. The voltage regulator according to claim 6, wherein the predetermined sampling point is provided on a path where the second terminal of the pull-up transistor and the second terminal of the pull-down transistor are connected to the switching transistor, or the second terminal of the pull-up transistor and the second terminal of the pull-down transistor are electrically connected to the predetermined sampling point through the switching transistor.

8. The voltage regulation device of claim 6, wherein the switching tube is a high voltage transistor.

9. The voltage regulator of claim 6, further comprising a level shifter electrically connected to the switching tube for level-shifting the voltage signal as a control signal of the switching tube.

10. A memory, comprising:

a memory array including a common source terminal;

a voltage regulation device as claimed in any one of claims 1 to 9 electrically connected to the common source terminal for connecting the common source terminal to ground, the predetermined sampling point being provided on a connection path of the common source terminal to the voltage regulation device.

Technical Field

The present invention relates to the field, and in particular, to a voltage regulator and a memory using the same.

Background

In the 3D NAND memory, information of a memory cell (cell) is stored in the memory cell in the form of a threshold voltage (Vth). The process of reading the stored information is a process of determining the threshold voltage (Vth). In this process, a Bit line (BL, Bit line) is first pulled up, then word lines (WL, word line) are turned on, a read voltage (Vrd) is applied to a selected word line (select WL), a turn-on voltage (Vpass) is applied to an unselected word line (unselect WL), and a Common Source terminal (ACS, Common Source/100Common Source) is pulled to Ground (GND), thereby forming a current path to discharge the Bit line.

At this time, the threshold voltage of the programmed memory cell is higher, the difference between the corresponding gate-source voltage (Vgs) and the threshold voltage (Vth) is lower, and the discharge speed is slow; the threshold voltage of the memory cell which is not programmed is low, the difference between the corresponding gate-source voltage (Vgs) and the threshold voltage (Vth) is high, and the discharging speed is high. After a discharge time has elapsed, the bit line voltage is determined, and whether the information stored in the memory cell is "0" or "1" is determined based on whether the bit line voltage is lower than a reference voltage. In this process, the magnitude of the discharge current depends on the difference between the gate-source voltage (Vgs) and the threshold voltage (Vth). Thus, the discharge current is related to both the gate voltage and the threshold voltage, as well as the source voltage (i.e., ACS).

In the prior art, the common source terminal is connected to the ground terminal through a switch tube during reading. With the increase of the storage capacity and area of the chip, due to the limitation of the strength of the ground terminal network of the chip, when the read current flows, the ground terminal voltages at different positions of the chip may be different, and the ground terminal voltages at the same position and at different times may also be different. The ground voltage is directly reflected in the gate-source voltage (Vgs), and therefore, the ground voltage has an influence on the reading accuracy.

In the 3D NAND of TLC (Trinary-Level Cell)/QLC (Quad-Level Cell), the threshold voltage of one memory Cell is divided into several regions, so as to store as much information as possible. For example, in the 3D NAND by TLC, the threshold voltage of one memory cell is divided into 8 sections, and each section stores 3bit information, and in the 3D NAND by QLC, the threshold voltage of one memory cell is divided into 16 sections, and each section stores 4bit information, so that the accuracy requirement for the threshold voltage (Vth) determination is higher and higher, and higher requirements for the stability and consistency of the ground voltage are also provided.

Disclosure of Invention

The invention aims to provide a voltage regulating device and a memory adopting the same.

In order to solve the above problem, the present invention provides a voltage adjusting apparatus for adjusting a voltage at a preset sampling point, comprising: the operational amplifier comprises an inverting input end, a non-inverting input end and an output end, wherein the inverting input end inputs a reference voltage, and the non-inverting input end is electrically connected with the preset sampling point and used for inputting the voltage of the preset sampling point to form a feedback loop; the pull-up transistor comprises a control end, a first end and a second end, wherein the control end is electrically connected with the output end of the operational amplifier, the first end is electrically connected with a power supply, and the second end is electrically connected with the preset sampling point; the pull-down transistor comprises a control end, a first end and a second end, wherein the control end is electrically connected with the output end of the operational amplifier, the first end is electrically connected with the grounding end, and the second end is electrically connected with the preset sampling point.

Further, the pull-up transistor is a PMOS transistor, and the pull-down transistor is an NMOS transistor.

Further, the pull-down capability of the pull-down transistor is greater than the pull-up capability of the pull-up transistor.

Further, when the vehicle is pulled up or under light load, the voltage regulating device works in a class A mode and a class B mode, and when the vehicle is under heavy load, the voltage regulating device works in the class A mode.

Further, the pull-up transistor and the pull-down transistor are low-voltage transistors.

Further, the voltage regulating device further comprises a switch tube, and the second end of the pull-up transistor and the second end of the pull-down transistor are connected with the switch tube.

Further, the preset sampling point is arranged on a path where the second end of the pull-up transistor and the second end of the pull-down transistor are connected with the switch tube, or the second end of the pull-up transistor and the second end of the pull-down transistor are electrically connected with the preset sampling point through the switch tube.

Further, the switch tube is a high-voltage transistor.

Furthermore, the voltage regulating device further comprises a level shifter, wherein the level shifter is electrically connected with the switching tube and is used for performing level shifting on the voltage signal to be used as a control signal of the switching tube.

The present invention also provides a memory, comprising: a memory array having a common source terminal; the voltage regulating device as described above is electrically connected to the common source terminal for connecting the common source terminal to a ground terminal, and the preset sampling point is disposed on a connection path of the common source terminal and the voltage regulating device or on a connection path of the common source terminal and the memory array.

One advantage of the present invention is that the voltage adjusting device can adjust the voltage at the preset sampling point according to the feedback of the preset sampling point, so that the voltage is kept stable, and the voltage stability and consistency of the preset sampling point are improved.

The memory has the advantages that the voltage of the preset sampling point can be clamped by the voltage regulating device to be kept stable, so that the voltage of the common source terminal of the memory array is kept stable, the stability and the consistency of the voltage of the common source terminal are improved, and the reading precision of the memory is further improved.

Drawings

FIG. 1 is a circuit schematic of a common source terminal of a prior art memory;

FIG. 2 is a circuit schematic of a voltage regulating device according to a first embodiment of the present invention;

FIG. 3 is another circuit schematic of the voltage regulating device of the first embodiment of the present invention;

FIG. 4 is a circuit schematic of a voltage regulating device according to a second embodiment of the present invention;

FIG. 5 is a circuit schematic of the memory of the present invention;

FIG. 6 is a circuit schematic of a memory array of the memory of the present invention.

Detailed Description

Embodiments of a voltage regulator and a memory using the same according to the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a circuit diagram of a common source terminal of a memory device connected to ground in the prior art. Referring to fig. 1, in the prior art, a common source terminal ACS of a memory array 100 is connected to a ground terminal VSS _ PAD through a switch S. The inventors have found that the voltage at the common source terminal ACS is unstable because there are several resistors on the path from the common source terminal ACS to the ground terminal VSS _ PAD. Specifically, the resistors present on the path from the common source terminal ACS to the ground terminal VSS _ PAD include: a wiring resistance R1 from VSS _ PAD to the switching tube S, an on-resistance of the switching tube S, a wiring resistance R2 from the common source terminal ACS to the switching tube S. When the operating current of the memory chip flows through these resistors, a corresponding voltage drop is generated. For example, the memory array 100 of the memory chip sinks the current I1 to the common source terminal ACS, the operating current I2 of the other operating modules of the memory chip, and so on. The voltage drop across these resistors makes the voltage at the common source terminal ACS unstable, not ideally "ground", but varies from location to location and from time to time of the memory chip. This has an effect on the discharge current of the memory array and ultimately on the accuracy of the read.

Therefore, the present invention provides a voltage regulator capable of regulating the voltage at the common source terminal ACS to be clamped at a set value, thereby improving the stability and uniformity of the voltage at the common source terminal ACS.

The voltage regulating device is used for regulating the voltage at the preset sampling point. Fig. 2 is a circuit diagram of a voltage regulating device according to a first embodiment of the present invention. Referring to fig. 2, the voltage regulator includes an operational amplifier OPAMP, a pull-up transistor MP1, and a pull-down transistor MN 1.

The operational amplifier OPAMP includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input end inputs a reference voltage Vref, and the non-inverting input end is electrically connected with a preset sampling point A and used for inputting the voltage Va of the preset sampling point A to form a feedback loop.

The reference voltage Vref may be set according to a required voltage of the preset sampling point a, and the reference voltage Vref may be equal to the required voltage of the preset sampling point a.

In this embodiment, the pull-up transistor MP1 is a PMOS transistor. The pull-up transistor MP1 includes a control terminal, a first terminal, and a second terminal. The control end with operational amplifier OPAMP the output electricity is connected, first end is connected with power VCC electricity, the second end with preset sampling point A electricity is connected. That is, the output signal Vout of the operational amplifier OPAMP serves as the input signal of the control terminal of the pull-up transistor MP1, and the output signal of the second terminal of the pull-up transistor MP1 serves as the voltage signal of the preset sampling point a.

In this embodiment, the pull-down transistor MN1 is an NMOS transistor. The pull-down transistor MN1 includes a control terminal, a first terminal, and a second terminal. The control terminal is electrically connected with the output terminal of the operational amplifier OPAMP, the first terminal is electrically connected with a ground terminal VSS, and the second terminal is electrically connected with the preset sampling point a. That is, the output signal Vout of the operational amplifier OPAMP serves as the input signal of the control terminal of the pull-down transistor MN1, and the output signal of the second terminal of the pull-down transistor MN1 serves as the voltage signal of the preset sampling point a.

In the voltage regulator of the present invention, the control terminal of the pull-up transistor MP1 and the control terminal of the pull-down transistor MN1 are both connected to the output terminal of the operational amplifier OPAMP, and the output signal of the output terminal of the operational amplifier OPAMP is used as the control signal of the pull-up transistor MP1 and the pull-down transistor MN 1. A second terminal (i.e., an output terminal) of the pull-up transistor MP1 and a second terminal (i.e., an output terminal) of the pull-down transistor MN1 are both connected to the predetermined sampling point a, and then the output signal of the pull-up transistor MP1 and the output signal of the pull-down transistor MN1 are used together as the voltage signal of the predetermined sampling point a.

The working process of the voltage regulating device of the invention is described as follows:

when the voltage at the preset sampling point a decreases, the voltage Va at the non-inverting input terminal of the operational amplifier OPAMP is lower than the voltage Vref at the inverting input terminal, and the output voltage Vout at the output terminal of the operational amplifier OPAMP decreases, which changes the turn-on capabilities of the pull-up transistor MP1 and the pull-down transistor MN 1. Specifically, the voltage at the control terminal of the pull-up transistor MP1 decreases, and the pull-up capability of the pull-up transistor MP1 becomes stronger; the voltage of the control end of the pull-down transistor MN1 is lowered, the pull-down capability of the pull-down transistor MN1 is weakened, the pull-up transistor MP1 and the pull-down transistor MN1 cooperate to raise the voltage of the output end, i.e., the voltage of the preset sampling point a is raised, so that the voltage of the preset sampling point a can be adjusted, the lowering of the voltage is avoided, and the stability is maintained.

When the voltage at the preset sampling point a increases, the voltage Va at the non-inverting input terminal of the operational amplifier OPAMP is greater than the voltage Vref at the inverting input terminal, and the output voltage Vout at the output terminal of the operational amplifier OPAMP increases, which causes the turn-on capabilities of the pull-up transistor MP1 and the pull-down transistor MN1 to change. Specifically, the voltage of the control terminal of the pull-up transistor MP1 rises, and the pull-up capability of the pull-up transistor MP1 becomes weak; the voltage of the control terminal of the pull-down transistor MN1 rises, the pull-down capability of the pull-down transistor MN1 becomes stronger, and the voltage of the output terminal drops by the cooperation of the pull-up transistor MP1 and the pull-down transistor MN1, i.e., the voltage of the preset sampling point a drops, so that the voltage of the preset sampling point a can be adjusted, prevented from rising and kept stable.

The voltage adjusting device can adjust the voltage at the preset sampling point A according to the feedback of the preset sampling point A, so that the voltage is kept stable, and the voltage stability and consistency of the preset sampling point are improved.

Further, when the voltage regulator is used as a connection device between the common source terminal and the ground terminal of the memory array of the memory, the voltage regulator mainly absorbs current rather than providing current during operation, and the operation mode of absorbing current corresponds to the reading of the memory array, at this time, the requirement on speed is higher, i.e., the requirement on the pull-down capability of the output is higher, and the requirement on the pull-up capability of the output is lower, so in this embodiment, the pull-down capability of the pull-down transistor MN1 is greater than the pull-up capability of the pull-up transistor MP1, so as to be suitable for the operation mode thereof. That is, in the present embodiment, the pull-down transistor MN1 and the pull-up transistor MP1 are in an asymmetric relationship. Wherein the asymmetry of the pull-down transistor MN1 and the pull-up transistor MP1 can be achieved by changing the aspect ratio of the two.

Further, the voltage regulating device operates in a pseudo class AB mode. Specifically, when the voltage regulating device is pulled up or under light load, the voltage regulating device works in a class A mode, and when the voltage regulating device is under heavy load, the voltage regulating device works in a class A mode. Specifically, referring to fig. 3, which is another circuit diagram of the first embodiment of the present invention, the operational amplifier OPAMP includes a transconductance stage (Gm stage), a Class AB Bias circuit (Class AB Bias), and current mirrors Ia and Ib. These structures are conventional structures of the operational amplifier OPAMP and are not described in detail. When the voltage regulating device is used as a connecting device between a common source terminal and a ground terminal of a memory array of a memory, because the pull-down current needs to be large, the gate voltage (vg _ MN1) of a pull-down transistor MN1 is pulled to be high during reading, and Vbn and Vbp in a class ab Bias circuit (classa Bias) are both preset fixed voltages. When the gate voltage (vg _ MN1) of the pull-down transistor MN1 is high, the NMOS transistor (MNb) in the class ab Bias circuit (ClassA Bias) is turned off, so that the circuit actually operates in class a amplifier mode (ClassA); when the pull-down current is small, the gate voltage (vg _ MN1) of the pull-down transistor MN1 is not very high, and the NMOS transistor (MNb) in the class ab Bias circuit (classa Bias) is not turned off, so that the circuit operates in the class ab amplifier mode (classa). Therefore, in the pull-up or light load mode, the voltage regulating device works in the class A mode; and under the heavy-load mode, the system works in the class A and B mode.

Further, the operational amplifier OPAMP, the pull-up transistor MP1 and the pull-down transistor MN1 are all fabricated in a low voltage power domain (Vcc domain), and therefore, the pull-up transistor MP1 and the pull-down transistor MN1 both use low voltage transistors, so as to simplify layout design and save layout area while achieving functions.

In some cases, for example, when the memory is erased, the voltage regulator is not required to be connected to the ground, i.e., the voltage regulator is not required to be connected to the circuit of the memory. The second embodiment is different from the first embodiment in that the voltage regulator further includes a switching tube. The differences of the second embodiment from the first embodiment will be described below with emphasis.

Referring to fig. 4, which is a circuit diagram of a voltage regulating device according to a second embodiment of the present invention, the voltage regulating device further includes a switch transistor S, and the second terminal of the pull-up transistor MP1 and the second terminal of the pull-down transistor MN1 are electrically connected to the switch transistor S. The switch tube S is used as a switch of the voltage regulating device, when the switch tube S is switched on, the voltage regulating device works, and when the switch tube S is switched off, the voltage regulating device does not work.

Further, since the switch tube S also has a voltage drop, which also affects the voltage at the output terminal (common source terminal) of the memory, in the present embodiment, the second terminal of the pull-up transistor MP1 and the second terminal of the pull-down transistor MN1 are electrically connected to the predetermined sampling point a through the switch tube S. That is, in the second embodiment, the switching tube S is also covered by the feedback loop, so that the voltage drop of the switching tube S has no influence on the voltage of the preset sampling point a, and the voltage stability and consistency at the preset sampling point a are further improved. In this embodiment, when the voltage adjustment device is required to adjust the voltage of the preset sampling point a, the switch tube S is turned on, and when the voltage adjustment device is not required to adjust the voltage of the preset sampling point a, the switch tube S is turned off, so that the voltage adjustment device can selectively adjust the voltage of the preset sampling point a.

Further, in other embodiments of the present invention, if the on-resistance of the switch tube S is small and the voltage drop thereof is negligible, or the voltage drop of the switch tube S has little influence on the voltage of the output terminal (the common source terminal) of the memory, the preset sampling point a may also be disposed on the path connecting the second terminal of the pull-up transistor MP1 and the second terminal of the pull-down transistor MN1 with the switch tube S.

Further, in the second embodiment, the switch tube S is fabricated in the high voltage domain, so it is a high voltage transistor. In this embodiment, the switch tube S is a high voltage NMOS transistor. When the voltage regulation device is not required to regulate the voltage of the preset sampling point A, a low level signal is input to the control end of the switching tube S, so that the switching tube S is cut off, and the voltage regulation device is disconnected with the preset sampling point A; when the voltage adjusting device is required to adjust the voltage of the preset sampling point A, a high-level enabling signal is input to the control end of the switching tube S, so that the switching tube S is conducted, and the voltage adjusting device is connected with the preset sampling point A.

Further, when the voltage regulating device is used as a connection device between the common source terminal and the ground terminal of the memory array of the memory, a high voltage is generated in some operation states of the common source terminal, for example, when an erase (erase) operation is performed, and the voltage regulating device is not required to be connected to the common source terminal, and thus, the switching tube S is required to be turned off in order to protect the internal circuit of the voltage regulating device. At this time, the switching tube S receives a high level signal, and if the level signal is directly adopted as the control signal of the switching tube S, the switching tube S is turned on. Therefore, the voltage regulating device further comprises a level shifter LS (level shifter), electrically connected to the switching tube S, and configured to perform level shifting on a voltage signal to be used as a control signal of the switching tube S, so as to achieve on and off of the switching tube S.

The invention also provides a memory adopting the voltage regulating device. Please refer to fig. 5, which is a circuit diagram of a memory according to the present invention, the memory includes the memory array 100 and the voltage regulating device 500.

Please refer to fig. 6, which is a schematic diagram of the memory array 100, wherein the memory array includes a plurality of memory cells arranged in a three-dimensional space in an array, and a plurality of memory strings are formed, and channels of the memory cells in the same memory string are physically connected. The transistor at the top of each memory string is an upper selection tube TSG, the upper selection tube TSG is connected to a bit line BL, the transistor at the bottom of the memory string is a lower selection tube BSG, and different memory strings are distinguished by the upper selection tube TSG and the lower selection tube BSG. A plurality of memory units in the same layer form a memory row, and the gates of the memory units in different memory strings but in the same memory row are physically connected and are all connected to the same word line WL.

The memory array 100 also includes a common source terminal ACS. The common source terminal ACS is used to electrically connect the memory array 100 to ground.

The process of reading the stored information is a process of determining the threshold voltage (Vth). In this process, the bit line is discharged by first pulling up the bit line BL, then turning on the word line WL, applying a read voltage to the selected word line (select WL), applying a pass voltage (Vpass) to the unselected word lines (unselect WL), and pulling the common source terminal ACS to Ground (GND). As the storage capacity and area of the chip increase, due to the limitation of the strength of the ground terminal network of the chip, when the read current flows, the ground terminal voltages at different positions of the chip may be different, and the ground terminal voltages at the same position and at different times may also be different, so that the voltage of the common source terminal ACS is unstable, and the performance and reliability of the memory array are affected.

With continued reference to fig. 5, to solve the above problem, the voltage regulator 500 is electrically connected to the common source terminal ACS for connecting the common source terminal ACS to ground. Wherein the predetermined sampling point a is disposed on a connection path between the common source terminal ACS and the voltage regulator 500.

The memory of the invention can clamp the voltage of the preset sampling point A through the voltage adjusting device 500 to keep the voltage stable, thereby keeping the voltage of the public source terminal ACS of the memory array 100 stable, improving the voltage stability and consistency of the public source terminal ACS and further improving the reading precision of the memory.

Further, the closer the preset sampling point a is to the memory array 100, the better, so that the voltage drop on the current path between the output terminal of the memory array and the ground terminal is included in the feedback loop as much as possible, thereby improving the stability of the voltage at the output terminal of the memory array.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.