阅读说明：本技术 半导体存储器件 (Semiconductor memory device with a plurality of memory cells ) 是由 孙龙勋 金哉勋 朴光浩 宋炫知 李耕希 郑承宰 于 2020-09-01 设计创作，主要内容包括：公开了一种半导体存储器件。该器件包括：在衬底上的外围电路结构；在外围电路结构上的半导体层；在半导体层上的电极结构,该电极结构包括堆叠在半导体层上的电极；垂直沟道结构,其穿透电极结构并且连接到半导体层；分离结构,其穿透电极结构,在第一方向上延伸并且将电极结构的电极水平地分成一对电极；覆盖电极结构的层间绝缘层；以及穿透层间绝缘层并且电连接到外围电路结构的贯穿接触。(A semiconductor memory device is disclosed. The device includes: a peripheral circuit structure on the substrate; a semiconductor layer on the peripheral circuit structure; an electrode structure on the semiconductor layer, the electrode structure including an electrode stacked on the semiconductor layer; a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer; a separation structure penetrating the electrode structure, extending in a first direction and horizontally separating an electrode of the electrode structure into a pair of electrodes; an interlayer insulating layer covering the electrode structure; and a through contact penetrating the interlayer insulating layer and electrically connected to the peripheral circuit structure.)

1. A semiconductor memory device comprising:

a peripheral circuit structure on the substrate;

a semiconductor layer on the peripheral circuit structure;

an electrode structure on the semiconductor layer, the electrode structure including an electrode stacked on the semiconductor layer;

a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer;

a separation structure penetrating the electrode structure, the separation structure extending in a first direction and horizontally dividing at least one of the electrodes of the electrode structure into a pair of electrodes;

an interlayer insulating layer covering the electrode structure; and

a through contact penetrating the interlayer insulating layer and electrically connected to the peripheral circuit structure,

wherein a top surface of the separation structure, a top surface of the vertical channel structure, a top surface of the through contact, and a top surface of the interlayer insulating layer are coplanar with each other.

2. The semiconductor memory device according to claim 1,

when viewed in plan, the side walls of the separation structure include protruding portions and recessed portions,

the protruding portion protrudes in a direction away from a centerline of the separating structure,

the recessed portion is recessed toward the centerline, an

The side wall of the separation structure has at least one of a wavy and a concavo-convex shape.

3. The semiconductor memory device according to claim 2, wherein, in the second direction, the protruding portion defines a maximum width of the separation structure,

in the second direction, the recessed portion defines a minimum width of the separation structure, an

The second direction intersects the first direction.

4. The semiconductor memory device of claim 3, wherein the maximum width of the separation structure is greater than a diameter of an upper portion of the vertical channel structure.

5. The semiconductor memory device of claim 1, wherein the vertical channel structure comprises:

a vertical semiconductor pattern having a tubular shape with an open top end; and

vertical insulating patterns including a data storage layer interposed between the vertical semiconductor patterns and at least one of the electrodes.

6. The semiconductor memory device according to claim 1, wherein the electrode of the electrode structure and the vertical channel structure penetrating the electrode of the electrode structure correspond to memory cells arranged three-dimensionally.

7. The semiconductor memory device according to claim 1, wherein the semiconductor layer includes a lower semiconductor layer, an upper semiconductor layer, and a source semiconductor layer interposed between the lower semiconductor layer and the upper semiconductor layer, and

the vertical channel structure is connected to the source semiconductor layer.

8. The semiconductor memory device according to claim 1, further comprising:

a cell contact plug penetrating the stepped structure of the electrode structure,

wherein the cell contact plug is electrically connected to one of the electrodes of the electrode structure.

9. The semiconductor memory device according to claim 8, wherein the cell contact plug is coupled to a peripheral interconnect line of the peripheral circuit structure.

10. The semiconductor memory device according to claim 8, wherein the cell contact plug extends toward the semiconductor layer, and

the device further includes an insulation pattern interposed between the cell contact plug and the semiconductor layer.

11. A semiconductor memory device comprising:

a peripheral circuit structure on the substrate;

a semiconductor layer on the peripheral circuit structure;

an electrode structure on the semiconductor layer, the electrode structure including an electrode stacked on the semiconductor layer;

a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer;

a separation structure penetrating the electrode structure and horizontally dividing at least one of the electrodes of the electrode structure into a pair of electrodes;

a cell contact plug penetrating the stepped structure of the electrode structure;

an interlayer insulating layer covering the electrode structure; and

a through contact penetrating the interlayer insulating layer and electrically connected to the peripheral circuit structure,

wherein the separation structure comprises a lower separation structure and an upper separation structure on the lower separation structure, an

The width of the upper portion of the lower separation structure is greater than the width of the lower portion of the upper separation structure.

12. The semiconductor memory device of claim 11, wherein the vertical channel structure comprises a lower channel structure and an upper channel structure on the lower channel structure,

the width of the upper portion of the lower channel structure is greater than the width of the lower portion of the upper channel structure, an

The top surface of the lower separation structure and the top surface of the lower channel structure are at the same level.

13. The semiconductor memory device of claim 12, wherein the cell contact plug includes a lower contact plug and an upper contact plug on the lower contact plug,

a width of an upper portion of the lower contact plug is greater than a width of a lower portion of the upper contact plug, an

A top surface of the lower contact plug is at the same level as the top surface of the lower channel structure.

14. The semiconductor memory device of claim 11, wherein the through contact comprises a lower through contact and an upper through contact on the lower through contact, and

the width of the upper portion of the lower through contact is greater than the width of the lower portion of the lower through contact.

15. The semiconductor memory device according to claim 11, wherein the separation structure extends in a first direction,

the side wall of the separation structure includes a plurality of protruding portions when viewed in a plan view, an

Each of the protruding portions protrudes in a second direction crossing the first direction.

16. A semiconductor memory device comprising:

a peripheral circuit structure on a substrate, the peripheral circuit structure including a peripheral transistor on the substrate, a peripheral interconnect line on the peripheral transistor, and a peripheral contact electrically connecting the peripheral transistor to the peripheral interconnect line;

a semiconductor layer on the peripheral circuit structure;

an electrode structure on the semiconductor layer, the electrode structure including an electrode stacked on the semiconductor layer;

a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer;

a separation structure penetrating the electrode structure extending in a first direction and horizontally dividing a first electrode of the electrodes into a pair of electrodes;

a cell contact plug penetrating the stepped structure of the electrode structure and electrically connected to a second electrode of the electrodes;

an interlayer insulating layer covering the electrode structure;

a through contact penetrating the interlayer insulating layer and electrically connected to the peripheral interconnect line of the peripheral circuit structure; and

bit lines and connection lines on the interlayer insulating layer,

wherein the vertical channel structure comprises a first vertical channel structure,

a vertical semiconductor pattern having a tubular shape with an open top end, an

A vertical insulating pattern including a data storage layer interposed between the vertical semiconductor pattern and a third one of the electrodes, wherein

The bit lines are electrically connected to the vertical semiconductor patterns,

the connecting wire is electrically connected to the through contact, an

A top surface of the separation structure, a top surface of the vertical channel structure, a top surface of the cell contact plug, and a top surface of the through contact are coplanar with each other.

17. The semiconductor memory device according to claim 16, wherein the semiconductor layer includes a lower semiconductor layer, an upper semiconductor layer, and a source semiconductor layer interposed between the lower semiconductor layer and the upper semiconductor layer, and

the vertical semiconductor pattern is connected to the source semiconductor layer.

18. The semiconductor memory device according to claim 16, wherein the stair-step structure of the electrode structure comprises a molded structure under the second electrode,

the molded structure includes an insulator, an

The cell contact plug penetrates the second electrode and the mold structure.

19. The semiconductor memory device of claim 16, wherein a maximum diameter of the cell contact plug is greater than a maximum diameter of the vertical channel structure.

20. The semiconductor memory device of claim 16, wherein a maximum diameter of the through contact is greater than a maximum diameter of the vertical channel structure.

Technical Field

Example embodiments relate to a semiconductor device, and more particularly, to a three-dimensional semiconductor memory device having improved reliability.

Background

Higher integration of semiconductor devices is pursued/required to meet consumer demand for superior performance and/or low price. Since the degree of integration of semiconductor devices is an important factor in determining the price of products, increased degree of integration is particularly sought/required. Since the degree of integration of a two-dimensional (e.g., planar) semiconductor device is mainly determined by the area occupied by a unit memory cell, the degree of integration is greatly influenced by the level of fine patterning technology. However, the very expensive cost of processing equipment required or used to increase the fineness of the pattern places practical limits on increasing the integration of two-dimensional or planar semiconductor devices. To overcome such a limitation, a three-dimensional semiconductor memory device including memory cells arranged three-dimensionally has been recently proposed.

Disclosure of Invention

Some example embodiments of the inventive concepts provide a three-dimensional semiconductor memory device having improved reliability.

According to some example embodiments of the inventive concepts, a semiconductor memory device includes: a peripheral circuit structure on the substrate; a semiconductor layer on the peripheral circuit structure; an electrode structure on the semiconductor layer, the electrode structure including an electrode stacked on the semiconductor layer; a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer; a separation structure penetrating the electrode structure, the separation structure extending in a first direction and horizontally dividing at least one of the electrodes of the electrode structure into a pair of electrodes; an interlayer insulating layer covering the electrode structure; and a through contact penetrating the interlayer insulating layer and electrically connected to the peripheral circuit structure. The side wall of the separation structure includes a protruding portion protruding in a direction away from a center line of the separation structure and a recessed portion recessed toward the center line when viewed in a plan view.

According to some example embodiments of the inventive concepts, a semiconductor memory device may include: a peripheral circuit structure on the substrate; a semiconductor layer on the peripheral circuit structure; an electrode structure on the semiconductor layer, the electrode structure including an electrode stacked on the semiconductor layer; a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer; a separation structure penetrating the electrode structure and horizontally dividing at least one of the electrodes of the electrode structure into a pair of electrodes; a cell contact plug penetrating the stepped structure of the electrode structure; an interlayer insulating layer covering the electrode structure; and a through contact penetrating the interlayer insulating layer and electrically connected to the peripheral circuit structure. The separation structure includes a lower separation structure and an upper separation structure on the lower separation structure, and a width of an upper portion of the lower separation structure is greater than a width of a lower portion of the upper separation structure.

According to some example embodiments of the inventive concepts, a semiconductor memory device may include: a peripheral circuit structure on the substrate, the peripheral circuit structure including a peripheral transistor on the substrate, a peripheral interconnect line on the peripheral transistor, and a peripheral contact electrically connecting the peripheral transistor to the peripheral interconnect line; a semiconductor layer on the peripheral circuit structure; an electrode structure on the semiconductor layer, the electrode structure including an electrode stacked on the semiconductor layer; a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer; a separation structure penetrating the electrode structure extending in the first direction and horizontally dividing a first electrode of the electrodes into a pair of electrodes; a cell contact plug penetrating the stepped structure of the electrode structure and electrically connected to a second one of the electrodes; an interlayer insulating layer covering the electrode structure; a through contact penetrating the interlayer insulating layer and electrically connected to a peripheral interconnection line of the peripheral circuit structure; and bit lines and connection lines on the interlayer insulating layer. The vertical channel structure includes: a vertical semiconductor pattern having a tubular shape with an open top end; and vertical insulating patterns including data storage layers interposed between the vertical semiconductor patterns and third ones of the electrodes. The bit line is electrically connected to the vertical semiconductor pattern, the connection line is electrically connected to the through contact, and a top surface of the separation structure, a top surface of the vertical channel structure, a top surface of the cell contact plug, and a top surface of the through contact are coplanar with each other.

Drawings

Example embodiments will be more clearly understood from the following brief description in conjunction with the accompanying drawings. The drawings represent non-limiting example embodiments as described herein.

Fig. 1 is a schematic perspective view illustrating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.

Fig. 2 is a plan view illustrating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.

Fig. 3 is a sectional view taken along line I-I' of fig. 2.

Fig. 4 to 13 are cross-sectional views taken along line I-I' of fig. 2 for illustrating a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.

Fig. 14A, 14B, and 14C are plan views illustrating a method of forming the trench of fig. 8.

Fig. 15 is a cross-sectional view taken along line I-I' of fig. 2 for illustrating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.

Fig. 16A and 16B are enlarged sectional views respectively showing portions "M" and "N" of fig. 15.

Fig. 17 and 18 are cross-sectional views taken along line I-I' of fig. 2 for illustrating a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.

It should be noted that these drawings are intended to illustrate the general characteristics of methods, structures, and/or materials used in certain example embodiments, and to supplement the written description provided below. However, these drawings are not necessarily to scale, and may not accurately reflect the precise structural and/or performance characteristics of any given implementation, and should not be construed as limiting or restricting the scope of values or attributes encompassed by example implementations. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of like or identical reference numbers in the various figures is intended to indicate the presence of like or identical elements or features.

Detailed Description

Fig. 1 is a schematic perspective view illustrating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.

Referring to fig. 1, a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts may include a peripheral circuit structure PS, a cell array structure CS on the peripheral circuit structure PS, and through contacts (not shown) vertically connecting the cell array structure CS to the peripheral circuit structure PS. The cell array structure CS may overlap the peripheral circuit structure PS when viewed in a plan view.

In some example embodiments of the inventive concepts, the peripheral circuit structure PS may include row and/or column decoders, page buffers, control circuits, and/or peripheral logic circuits. The peripheral logic circuit included in the peripheral circuit structure PS may be integrated on a semiconductor substrate.

The cell array structure CS may include a cell array including a plurality of memory cells arranged three-dimensionally. For example, the cell array structure CS may include a plurality of memory blocks BLK 0-BLKn. Each of the memory blocks BLK0-BLKn may include a plurality of memory cells arranged three-dimensionally.

Fig. 2 is a plan view illustrating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts. Fig. 3 is a sectional view taken along line I-I' of fig. 2.

Referring to fig. 2 and 3, a peripheral circuit structure PS including a peripheral transistor PTR may be disposed on the substrate SUB. The cell array structure CS including the electrode structure ST may be disposed on the peripheral circuit structure PS. The substrate SUB may be or may comprise a silicon substrate, a silicon germanium substrate, a germanium substrate and/or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The substrate SUB may include an active region defined by a device isolation layer DIL.

The peripheral circuit structure PS may include a plurality of peripheral transistors PTR disposed on the active region of the substrate SUB. The peripheral transistor PTR may constitute the row and column decoders, the page buffer, the control circuit, and the peripheral logic circuit as described above or may be included in the row and column decoders, the page buffer, the control circuit, and the peripheral logic circuit as described above. The peripheral transistor PTR may include NMOS and/or PMOS transistors having various oxide thicknesses and/or threshold voltages. The peripheral transistor PTR may include a planar transistor; however, example embodiments are not limited thereto. The peripheral interconnection line PIL may be electrically connected to the peripheral transistor PTR through a peripheral contact PCNT.

A first interlayer insulating layer ILD1 may be provided on the substrate SUB to cover the peripheral transistor PTR, the peripheral contact PCNT, and the peripheral interconnection line PIL. The first interlayer insulating layer ILD1 may include a plurality of stacked insulating layers. For example, the first interlayer insulating layer ILD1 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a low-k dielectric layer.

The cell array structure CS may be provided on the peripheral circuit structure PS. Hereinafter, the cell array structure CS will be described in more detail below.

The etch stop layer ESL may be provided on the first interlayer insulating layer ILD 1. A second interlayer insulating layer ILD2 may be provided on the etch stop layer ESL. The semiconductor layer SL may be provided in the second interlayer insulating layer ILD 2. The semiconductor layer SL may be provided in the cell array region CAR of the cell array structure CS. A portion of the semiconductor layer SL may be provided in the connection region CNR of the cell array structure CS.

The semiconductor layer SL may include a lower semiconductor layer LSL, a source semiconductor layer SSL on the lower semiconductor layer LSL, and an upper semiconductor layer USL on the source semiconductor layer SSL. The lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may vertically overlap each other. The source semiconductor layer SSL may be interposed between the lower semiconductor layer LSL and the upper semiconductor layer USL. The lower semiconductor layer LSL and the upper semiconductor layer USL may be electrically connected to each other through the source semiconductor layer SSL.

In detail, the lower semiconductor layer LSL may be formed of and/or include at least one of a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs), or a mixture thereof. The lower semiconductor layer LSL may have at least one of a single crystal structure, an amorphous structure, and a polycrystalline structure. As an example, the lower semiconductor layer LSL may comprise an n-type doped polysilicon layer, for example a polysilicon layer comprising dopants such as arsenic and/or phosphorous.

Although not shown, in some example embodiments, a metal-containing conductive layer may be provided under the lower semiconductor layer LSL. Due to the conductive layer, the resistance of the semiconductor layer SL can be reduced.

In some example embodiments, each of the source semiconductor layer SSL and the upper semiconductor layer USL may include the same semiconductor material as the lower semiconductor layer LSL. As an example, the source semiconductor layer SSL may include an n-type doped polysilicon layer. The upper semiconductor layer USL may include an n-type doped polysilicon layer. The concentration of the impurity in the source semiconductor layer SSL may be different from (e.g., may be greater than or less than) the concentration of the impurity in the lower semiconductor layer LSL. The concentration of the impurity in the upper semiconductor layer USL may be different from (e.g., may be greater than or less than) the concentration of the impurity in the lower semiconductor layer LSL.

The electrode structure ST may be provided on the semiconductor layer SL. The electrode structure ST may include a plurality of electrodes EL stacked on the upper semiconductor layer USL in a vertical direction (e.g., the third direction D3). The electrode structure ST may further include a first insulating layer IL1 separating the stacked electrodes EL from each other. The first insulating layers IL1 and the electrodes EL of the electrode structure ST may be alternately stacked in the third direction D3.

The electrode structure ST may extend from the cell array region CAR of the cell array structure CS to the connection region CNR of the cell array structure CS. The electrode structure ST may have a step structure STs on or within the connection region CNR. For example, as the distance from the cell array region CAR increases, the height of the electrode structure ST on the connection region CNR may decrease in a stepwise manner.

The electrode structure ST may further include a molded structure MO provided therein. The mold structure MO may be provided in the step structure STS, and may not be provided within the cell array region CAR. The molding structure MO may include a sacrificial layer HL stacked on the second interlayer insulating layer ILD2 in the third direction D3. The molding structure MO may further include a first insulating layer IL1, the first insulating layer IL1 separating the stacked sacrificial layers HL from each other. The first insulating layers IL1 and the sacrificial layers HL of the molding structure MO may be alternately stacked in the third direction D3.

The sacrificial layer HL of the molding structure MO may be provided to have a stepped structure. For example, as the distance from the cell array region CAR increases, the height of the molding structure MO on the connection region CNR may decrease in a stepwise manner.

The sacrificial layer HL of the molding structure MO may physically connect the electrode EL on the cell array region CAR and the electrode EL on the connection region CNR to each other, wherein the electrode EL on the cell array region CAR and the electrode EL on the connection region are located at the same level. For example, the sacrificial layer HL may be interposed between the electrodes EL disposed on the cell array region CAR and the connection region CNR, respectively, and at the same level.

The sacrificial layer HL can be formed of and/or include an insulating material (such as silicon nitride and/or silicon oxynitride). Since the sacrificial layer HL and the first insulating layer IL1 of the molded structure MO each include an insulating material, the molded structure MO may be an insulator.

The lowermost electrode of the electrodes EL of the electrode structure ST may serve as a lower selection line. The uppermost electrode of the electrodes EL of the electrode structure ST may serve as an upper selection line. All the electrodes EL except the lower selection line and the upper selection line may be used as word lines.

The electrode EL may include at least one conductive material selected from the group consisting of or including: doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum). The first insulating layer IL1 may be formed of and/or include silicon oxide.

The electrode structure ST on the cell array region CAR may further include a second insulating layer IL 2. The second insulating layer IL2 may be provided only locally on the cell array region CAR, and may not be provided on the connection region CNR. The thickness of the second insulating layer IL2 may be greater than that of the first insulating layer IL 1. The second insulating layer IL2 may be formed of the same insulating material as the first insulating layer IL1 and/or include the same insulating material as the first insulating layer IL 1. As an example, the second insulation layer IL2 may be formed of and/or include silicon oxide.

A plurality of vertical channel structures VS penetrating the electrode structure ST may be provided on the cell array region CAR. The vertical channel structures VS may be arranged in a particular (e.g., periodic) direction and/or in a zigzag and/or honeycomb shape when viewed in plan view. Each vertical channel structure VS may include a vertical insulation pattern VP, a vertical semiconductor pattern SP, and a gap-fill insulation pattern VI.

The vertical insulating pattern VP may be interposed between the electrode structure ST and the vertical semiconductor pattern SP. The vertical insulation pattern VP may vertically extend from the top surface of the electrode structure ST toward the lower semiconductor layer LSL. The vertical insulation pattern VP may be shaped like an open-topped tube (e.g., like a PVC tube). The vertical semiconductor pattern SP may cover an inner surface of the vertical insulation pattern VP. The vertical semiconductor patterns SP may extend toward the lower semiconductor layer LSL together with the vertical insulation patterns VP. The vertical semiconductor pattern SP may also be shaped like an open-topped tube (e.g., like a PVC tube). The inner space of the vertical semiconductor pattern SP may be filled with the gap-filling insulation pattern VI.

The vertical insulation pattern VP may include one or more layers. In some example embodiments of the inventive concepts, the vertical insulation patterns VP may include a data storage layer. For example, the vertical insulation patterns VP may be used as and/or as a portion of a data storage layer of the NAND FLASH memory device, and may include a tunnel insulation layer, a charge storage layer, and a blocking insulation layer. In the NAND FLASH memory device, a charge storage layer between the electrode EL and the vertical semiconductor pattern SP may be used to store data. The data stored in the charge storage layer may be changed due to Fowler-Nordheim (FN) tunneling phenomenon, which may occur when a voltage difference (e.g., at least a certain voltage difference) exists between the electrode EL and the vertical semiconductor pattern SP.

For example, the charge storage layer may be and/or may include a trap insulating layer, a floating gate electrode, or an insulating layer having conductive nanodots. In some example embodiments, the charge storage layer may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nano-crystal silicon layer, and a stacked trap layer. The tunnel insulating layer may be formed of and/or include at least one of a material having a band gap greater than that of the charge storage layer. The tunnel insulating layer may be formed of and/or include at least one of a high-k dielectric material (e.g., aluminum oxide and/or hafnium oxide) or silicon oxide. The blocking insulating layer may be formed of and/or include silicon oxide.

The vertical semiconductor pattern SP may be formed of and/or include at least one of semiconductor materials, such as silicon (Si), germanium (Ge), or a mixture thereof. Furthermore, the vertical channel structure VS may be formed of and/or comprise a doped semiconductor material or an intrinsic semiconductor material. The vertical semiconductor pattern SP containing a semiconductor material may be used as a channel region of a transistor constituting or corresponding to a cell string of the NAND FLASH memory device.

The conductive PAD may be provided in or on an upper portion of each vertical channel structure VS. The conductive PAD may cover the top surface of the vertical semiconductor pattern SP and the top surface of the gap-filling insulating pattern VI. The side surface of the conductive PAD may be in contact with the inner surface of the vertical insulating pattern VP. The conductive PAD may be formed of and/or include at least one of a doped semiconductor material and a conductive material. The bit line contact plug BPLG may be electrically connected to the vertical semiconductor pattern SP through the conductive PAD.

Each vertical channel structure VS may have a first diameter DI 1. The first diameter DI1 of the vertical channel structure VS may taper in a downward direction. The first diameter DI1 may have a maximum at the top level of the vertical channel structure VS. The cross-section of the vertical channel structure VS may have a tapered shape.

The source semiconductor layer SSL may be in contact, e.g., in direct contact, with the lower sidewall of each of the vertical semiconductor patterns SP. The source semiconductor layer SSL may electrically connect the vertical semiconductor patterns SP to each other. Accordingly, the vertical semiconductor pattern SP, the source semiconductor layer SSL, the lower semiconductor layer LSL, and the upper semiconductor layer USL may be electrically connected to each other.

The three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts may be or may include a three-dimensional NAND FLASH memory device. NAND FLASH cell strings of memory devices may be integrated in the electrode structure ST on the semiconductor layer SL. The electrode structure ST and the vertical channel structure VS penetrating the electrode structure ST may constitute or correspond to a memory cell three-dimensionally arranged on the semiconductor layer SL. The electrode EL of the electrode structure ST may serve as a gate electrode of the transistor.

A plurality of separate structures SPS may be provided as the penetrating electrode structure ST. The separation structures SPS may extend in the second direction D2 and be parallel to each other. For example, the separation structure SPS may horizontally divide one electrode EL in the electrode structure ST into a plurality of electrodes EL. The plurality of electrodes EL divided by the separation structure SPS may be arranged in the first direction D1. The first direction D1 may be horizontal with respect to the surface of the substrate SUB. The plurality of electrodes EL divided by the separation structure SPS may extend in the second direction D2 and may be parallel to each other. The second direction D2 may be horizontal with respect to the surface of the substrate SUB. The separation structure SPS may be formed of and/or include an insulating material (e.g., silicon oxide).

Referring back to fig. 2, the sidewall SW of the separation structure SPS may have a wavy and/or concavo-convex shape when viewed in a plan view. In detail, the sidewall SW of the separation structure SPS may include a protruding portion PP and a recessed portion SS. The protruding portion PP may protrude in a direction away from the centerline CLE of the separation structure SPS. For example, the protruding portion PP may protrude in the first direction D1 from the centerline CLE of the separation structure SPS. The recessed portion SS may be recessed from the protruding portion PP toward the centerline CLE of the separation structure SPS.

The maximum width W1 of the separation structure SPS in the first direction D1 may be defined by a pair of opposing protruding portions PP of the side walls SW opposite to each other. The minimum width W2 of the separation structure SPS in the first direction D1 may be defined by a pair of opposing recessed portions SS of the sidewalls SW opposite to each other. The maximum width W1 of the separation structure SPS may be greater than the first diameter DI1 of the upper portion of the vertical channel structure VS. The minimum width W2 of the separation structure SPS may be less than, equal to, or greater than the first diameter DI1 of the upper portion of the vertical channel structure VS.

Referring back to fig. 2 and 3, a third interlayer insulating layer ILD3 may be provided on the semiconductor layer SL and the second interlayer insulating layer ILD 2. The third interlayer insulating layer ILD3 may cover the step structure STs of the electrode structure ST. A fourth interlayer insulating layer ILD4 may be provided on the third interlayer insulating layer ILD 3.

The cell contact plug PLG may be provided on the connection region CNR. The cell contact plug PLG may be provided to penetrate the electrode EL of the step structure STS and the molding structure MO under the electrode EL. As described above, since the molding structure MO is an insulator or includes an insulator, one cell contact plug PLG may be connected to one electrode EL.

Each of the cell contact plugs PLG may have a second diameter DI 2. The second diameter DI2 of the cell contact plug PLG may be gradually decreased in a downward direction. The second diameter DI2 may have a maximum value at the top level of the cell contact plug PLG. The second diameter DI2 of the upper portion of the cell contact plug PLG may be greater than the first diameter DI1 of the upper portion of the vertical channel structure VS. The contact plug PLG may have a tapered shape.

The cell contact plugs PLG may include first and second cell contact plugs PLG1 and PLG 2. The first cell contact plug PLG1 may be provided as a stepped structure STs penetrating the electrode structure ST, and may extend toward the semiconductor layer SL. The insulating pattern IP may be interposed between the first cell contact plug PLG1 and the upper semiconductor layer USL. The first cell contact plug PLG1 may be separated, e.g., electrically separated, from the semiconductor layer SL by the insulation pattern IP.

The second cell contact plug PLG2 may penetrate the step structure STs of the electrode structure ST and may extend toward the peripheral circuit structure PS. The second cell contact plug PLG2 may also penetrate the second interlayer insulating layer ILD2 and the etch stop layer ESL, and may be coupled to an uppermost peripheral interconnection line of the peripheral interconnection lines PIL. As a result, the uppermost one of the electrode EL and the peripheral interconnection line PIL may be electrically connected to each other through the second cell contact plug PLG 2.

At least one through-contact TVS may be provided on the through-contact region TVR of the substrate SUB. The through contact TVS may be provided to penetrate the third interlayer insulating layer ILD3, the second interlayer insulating layer ILD2, and the etch stop layer ESL, and may be coupled to an uppermost peripheral interconnection line of the peripheral interconnection lines PIL. The through-contact TVS may be provided in the through-contact region TVR when viewed in a plan view. The through contact region TVR may be adjacent to the stepped structure STs of the electrode structure ST in the second direction D2.

The through contact TVS may have a third diameter DI 3. The third diameter DI3 of the through contact TVS may gradually decrease in a downward direction. The third diameter DI3 may have a maximum at the highest level of the through contact TVS. The third diameter DI3 of the upper portion of the through contact TVS may be greater than the first diameter DI1 of the upper portion of the vertical channel structure VS. The through contact TVS may have a tapered shape.

A plurality of bit lines BL and a plurality of connection lines CL may be provided on the fourth interlayer insulating layer ILD 4. The bit lines BL may extend in the first direction D1 and be parallel to each other.

The bit line contact plug BPLG may be provided in the fourth interlayer insulating layer ILD4, for example, within the fourth interlayer insulating layer ILD 4. The bit line contact plugs BPLG may be respectively coupled to the conductive PADs PAD on the vertical channel structure VS. Each bit line BL may be electrically connected to the vertical semiconductor pattern SP through a bit line contact plug BPLG and a conductive PAD.

The VIA may be provided in the fourth interlayer insulating layer ILD 4. At least one of the connection lines CL may be electrically connected to the first cell contact plug PLG1 through a VIA. At least one of the connection lines CL may be electrically connected to the through contact TVS through the VIA.

According to some example embodiments of the inventive concepts, each or at least some of the vertical channel structure VS, the separation structure SPS, the cell contact plug PLG, and the through contact TVS may have top surfaces coplanar with each other. For example, a top surface of each or at least some of the vertical channel structure VS, the separation structure SPS, the cell contact plug PLG, and the through contact TVS may be coplanar with a top surface of the third interlayer insulating layer ILD 3.

Fig. 4 to 13 are sectional views taken along line I-I' of fig. 2 to illustrate methods of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts. Fig. 14A, 14B, and 14C are plan views illustrating a method of forming the trench of fig. 8.

Referring to fig. 2 and 4, a peripheral circuit structure PS may be formed on the substrate SUB. The forming of the peripheral circuit structure PS may include: forming a peripheral transistor PTR on the substrate SUB; forming a peripheral interconnection line PIL on the peripheral transistor PTR; forming a peripheral contact PCNT connecting the peripheral transistor PTR to the peripheral interconnection line PIL; and forming a first interlayer insulating layer ILD 1.

For example, the formation of the peripheral transistor PTR may include: forming a device isolation layer DIL on the substrate SUB to define an active region; doping a portion of the active region to form a well region; forming a gate insulating layer and a gate electrode on the active region; and/or doping an upper portion of the active region to form source/drain regions.

An etch stop layer ESL may be formed on the first interlayer insulating layer ILD 1. A second interlayer insulating layer ILD2 may be formed on the etch stop layer ESL. The lower semiconductor layer LSL may be formed in the second interlayer insulating layer ILD 2. The lower semiconductor layer LSL may be formed of and/or include at least one of a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

A third insulating layer IL3, a lower sacrificial layer LHL, and a fourth insulating layer IL4 may be formed on the lower semiconductor layer LSL. The lower sacrificial layer LHL may overlap the lower semiconductor layer LSL when viewed in a plan view. For example, the third and fourth insulating layers IL3 and IL4 may be formed of and/or include silicon oxide, and the lower sacrificial layer LHL may be formed of and/or include silicon nitride or silicon oxynitride.

An upper semiconductor layer USL may be formed on the fourth insulating layer IL 4. The upper semiconductor layer USL may overlap with the lower semiconductor layer LSL when viewed in a plan view. The top surface of the upper semiconductor layer USL may be coplanar with the top surface of the second interlayer insulating layer ILD 2. The upper semiconductor layer USL may be formed of and/or include a semiconductor material.

The molding structure MO may be formed on the upper semiconductor layer USL. For example, the molding structure MO may be formed by repeatedly and alternately stacking the first insulating layer IL1 and the sacrificial layer HL on the upper semiconductor layer USL. The second insulation layer IL2 may be formed as the uppermost layer of the molding structure MO.

The first insulating layer IL1, the sacrificial layer HL, and the second insulating layer IL2 may be deposited using at least one of thermal or low pressure Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), physical chemical vapor deposition, and Atomic Layer Deposition (ALD) processes. The first insulating layer IL1 may be formed of and/or include silicon oxide, and the sacrificial layer HL may be formed of and/or include silicon nitride or silicon oxynitride.

The stair-step structure STS may be formed in the molded structure MO. For example, the cell array structure CS on the peripheral circuit structure PS may include a cell array region CAR and a connection region CNR. A cyclic patterning process may be performed on the molding structure MO to form a staircase structure STS on the connection region CNR.

The formation of the stair-step structure STS may include forming a mask pattern (not shown) on the molding structure MO and performing a cyclic patterning process several times using the mask pattern. Each cycle of the patterning process may include etching a portion of the molding structure MO using the mask pattern as an etching mask and performing a trimming process of reducing a size of the mask pattern.

The third interlayer insulating layer ILD3 may be formed on the molding structure MO. The formation of the third interlayer insulating layer ILD3 may include thickly forming an insulating layer to cover the molding structure MO and performing a planarization process, such as a Chemical Mechanical Planarization (CMP) and/or an etch-back process, on the insulating layer to expose the second insulating layer IL 2.

Referring to fig. 2 and 5, a patterning process may be performed on the structure having the third interlayer insulating layer ILD3 to form first to fifth holes HO1-HO5 having a high aspect ratio. The patterning process may include forming a hard mask having a plurality of openings on the molding structure MO and the third interlayer insulating layer ILD3 and performing an anisotropic etching process using the hard mask as an etching mask. The anisotropic etching process may be or include a plasma etching process, a Reactive Ion Etching (RIE) process, an inductively coupled plasma reactive ion etching (ICP-RIE) process, and/or an Ion Beam Etching (IBE) process.

The first to fifth holes HO1-HO5 may be formed to have the same or similar diameters. Each of the first through fifth holes HO1-HO5 may have a first diameter DI1 at a top level thereof.

The first to third holes HO1, HO2, and HO3 may be formed on the upper semiconductor layer USL. The first to third holes HO1, HO2, and HO3 may penetrate the molding structure MO and may expose the upper semiconductor layer USL. The first to third holes HO1, HO2 and HO3 may have bottoms located at the same level (e.g., first height LV 1).

The fourth hole HO4 and the fifth hole HO5 may be formed on the first interlayer insulating layer ILD 1. The fifth hole HO5 may be formed in the through contact region TVR. The fourth hole HO4 and the fifth hole HO5 may penetrate the molding structure MO, the second interlayer insulating layer ILD2, and the etch stop layer ESL, and may expose an uppermost peripheral interconnection line of the peripheral interconnection lines PIL. Fourth hole HO4 and fifth hole HO5 may have bottoms located at the same level (e.g., second height LV 2). The second level LV2 may be lower than the first level LV 1.

By adjusting the etching recipe in the anisotropic etching process for forming the first to fifth holes HO1-HO5, it is possible to terminate the etching of the first to third holes HO1, HO2, and HO3 when the upper semiconductor layer USL is exposed. The etching of the fourth hole HO4 and the fifth hole HO5 may be adjusted to terminate when an uppermost peripheral interconnect line of the peripheral interconnect lines PIL is exposed. In other words, it is possible to form the holes HO1-HO5 whose bottoms are located at different levels by performing the anisotropic etching process once. The anisotropic etching process may be performed using (e.g., based on) an etching selectivity (i.e., a difference in etching rate) between the upper semiconductor layer USL and the second interlayer insulating layer ILD 2. For example, the endpoint of the anisotropic etch process can be determined based on the optical emission signal associated with the upper semiconductor layer USL.

Referring to fig. 2 and 6, a sacrificial material SAC may be formed to fill the first to fifth holes HO1-HO 5. Thereafter, the first hole HO1 may be vacated by selectively removing the sacrificial material SAC from the first hole HO 1. An anisotropic etching process may be additionally performed on the first hole HO1 from which the sacrificial material SAC has been removed, such that the first hole HO1 has a bottom HO1b located at the third level LV 3. The third level LV3 may be lower than the first level LV 1. The third level LV3 may be located between the bottom level and the top level of the lower semiconductor layer LSL. For example, the first hole HO1 may be formed to expose the lower semiconductor layer LSL due to an additional anisotropic etching process.

Referring to fig. 2 and 7, a vertical channel structure VS may be formed in the first hole HO1, respectively. In detail, the formation of the vertical channel structure VS may include sequentially forming a vertical insulating layer, a vertical semiconductor layer, and an insulating gap filling layer on the inner surface of the first hole HO1, and then performing a planarization process to expose the top surface of the second insulating layer IL 2. The planarization process may include at least one of a CMP process and an etch-back process. The vertical insulating layer and the vertical semiconductor layer may be formed to conformally cover the inner surfaces of the first hole HO 1.

As a result of the planarization process, the vertical insulation pattern VP may be formed to cover the inner surface of the first hole HO 1. The vertical insulation pattern VP may be shaped like a tube having an open top end (e.g., a PVC tube). The vertical insulation pattern VP may include a data storage layer.

Similarly, the vertical semiconductor pattern SP may be formed to cover an inner surface of the vertical insulation pattern VP. The vertical semiconductor pattern SP may be shaped like a tube having an open top end (e.g., a PVC tube). The vertical semiconductor pattern SP may be spaced apart from the upper semiconductor layer USL and the lower semiconductor layer LSL due to the vertical insulation pattern VP.

The gap-filling insulating pattern VI may be formed to fill an inner space of the vertical semiconductor pattern SP. The vertical insulating pattern VP, the vertical semiconductor pattern SP, and the gap-filling insulating pattern VI may constitute or be included in the vertical channel structure VS. The conductive PAD may be formed in or on an upper portion of each vertical channel structure VS.

Referring to fig. 2, 8 and 14A, the second hole HO2 may be vacated by selectively removing the sacrificial material SAC from the second hole HO 2. The second holes HO2 may be arranged in the second direction D2.

Referring to fig. 2, 8 and 14B, an isotropic etching process may be performed on the second hole HO2 to expand the second hole HO 2. The second hole HO2 may correspond to a hole from which the sacrificial material SAC is removed. As a result of the isotropic etching process, the second holes HO2 arranged in the second direction D2 may be connected to each other to form a trench TR elongated in the second direction D2.

The trench TR may be formed to penetrate the molding structure MO. The grooves TR may extend in the second direction D2 and may be parallel to each other. Due to the trenches TR, each sacrificial layer HL of the molding structure MO may be horizontally divided into a plurality of sacrificial layers HL. The side walls SW of the grooves TR may have a wavy or concave-convex shape when viewed in a plan view. The sidewalls SW of the trench TR may include a protruding portion PP and a recessed portion SS.

In some example embodiments, in the case where the isotropic etching process is performed on the second hole HO2 in an enhanced manner compared to the method shown in fig. 14B, the trench TR may be formed to have a line shape in a plan view, as shown in fig. 14C. For example, the sidewalls SW of the trenches TR may have a linear shape. Therefore, the separation structure SPS to be formed in the trench TR may also have a line shape when viewed in a plan view.

Referring to fig. 2 and 9, a sidewall spacer SSP may be formed on an inner sidewall of the trench TR. The formation of the sidewall spacer SSP may include forming an insulating layer on inner sidewalls of the trench TR and anisotropically etching the insulating layer to expose a bottom of the trench TR.

An anisotropic etching process may be performed on the trench TR to form a recess RES extending from the trench TR to the lower semiconductor layer LSL. For example, the trench TR may be formed to expose the lower semiconductor layer LSL. The trench TR may expose inner sidewalls of the third insulation layer IL3, inner sidewalls of the lower sacrificial layer LHL, and inner sidewalls of the fourth insulation layer IL 4.

Referring to fig. 2 and 10, the lower sacrificial layer LHL exposed through the trench TR may be replaced with a source semiconductor layer SSL. In detail, the lower sacrificial layer LHL exposed through the trench TR may be selectively removed. The lower sacrificial layer LHL can be removed by a wet etching process; however, example embodiments are not limited thereto. Due to the removal of the lower sacrificial layer LHL, a lower portion of the vertical insulation pattern VP of each vertical channel structure VS may be exposed.

The exposed lower portion of the vertical insulation pattern VP may be selectively removed, for example, using a wet etching process. Accordingly, the lower portion of the vertical semiconductor pattern SP may be exposed. During the removal of the lower portion of the vertical insulation pattern VP, the third insulation layer IL3 and the fourth insulation layer IL4 may be simultaneously removed.

The source semiconductor layer SSL may be formed in a space formed by removing the third insulating layer IL3, the lower sacrificial layer LHL, and the fourth insulating layer IL 4. The source semiconductor layer SSL may be in contact (e.g., direct contact) with the exposed lower portion of the vertical semiconductor pattern SP. The source semiconductor layer SSL may also be in direct contact with the lower semiconductor layer LSL thereunder. The source semiconductor layer SSL may also be in contact (e.g., in direct contact) with the upper semiconductor layer USL thereon. The upper semiconductor layer USL, the source semiconductor layer SSL, and the lower semiconductor layer LSL may be configured or included in the semiconductor layer SL.

Thereafter, the sidewall spacers SSP may be selectively removed from the trenches TR. Accordingly, the inner sidewalls of the sacrificial layer HL may be exposed through the trench TR.

Referring to fig. 2 and 11, the sacrificial layer HL exposed through the trench TR may be replaced with an electrode EL, respectively. In detail, the sacrificial layer HL exposed through the trench TR may be selectively removed (e.g., may be selectively removed with a wet etching process). The electrodes EL may be respectively formed in empty spaces from which the sacrificial layer HL is removed. The alternative electrode EL may constitute (e.g. may correspond to) the electrode structure ST. The unremoved portions of the sacrificial layer HL remaining on the connection region CNR may constitute or correspond to the molding structure MO.

Referring to fig. 2 and 12, the third hole HO3 and the fourth hole HO4 may be left free by selectively removing the sacrificial material SAC from the third hole HO3 and the fourth hole HO 4. An isotropic etching process may be performed on the third and fourth holes HO3 and HO4 from which the sacrificial material SAC is removed to expand each of the third and fourth holes HO3 and HO4 (e.g., to expand a diameter of each of the third and fourth holes HO3 and HO 4). Thus, each of the third hole HO3 and the fourth hole HO4 may have the second diameter DI2 at a top level thereof. The second diameter DI2 may be larger than the first diameter DI1 previously described with reference to FIG. 5. The isotropic etching process may be or may include a wet etching process; however, example embodiments are not limited thereto.

An oxidation process such as a thermal oxidation process may be performed on the upper semiconductor layer USL exposed through the third hole HO3 to form an insulation pattern IP filling a lower portion of the third hole HO 3. The first and second cell contact plugs PLG1 and PLG2 may be formed by filling the third and fourth holes HO3 and HO4 with a conductive material, respectively.

Referring to fig. 2 and 13, the fifth hole HO5 may be vacated by selectively removing the sacrificial material SAC from the fifth hole HO 5. An isotropic etching process, such as a wet etching process, may be performed on the fifth hole HO5 from which the sacrificial material SAC is removed to expand the fifth hole HO 5. Thus, the fifth hole HO5 may have a third diameter DI3 at its top level. The third diameter DI3 may be larger than the first diameter DI1 previously described with reference to FIG. 5. The through contact TVS may be formed by filling the fifth hole HO5 with a conductive material.

Referring back to fig. 2 and 3, a fourth interlayer insulating layer ILD4 may be formed on the molding structure MO and the third interlayer insulating layer ILD 3. The bit line contact plug BPLG and the VIA may be formed in the fourth interlayer insulating layer ILD 4. A bit line BL electrically connected to the bit line contact plug BPLG and a connection line CL electrically connected to the VIA may be formed on the fourth interlayer insulating layer ILD 4.

According to some example embodiments of the inventive concepts, it is possible to simultaneously form the first to fifth holes HO1-HO5 and define the vertical channel structure VS, the separation structure SPS, the cell contact plugs PLG, and the through contact TVS. The first to fifth holes HO1-HO5 may have a high aspect ratio. Since a plurality of structures are formed by a single process, the process of manufacturing a semiconductor memory device may be simplified, and/or a reduction in manufacturing cost may be achieved. Since the first to fifth holes HO1-HO5 are simultaneously formed, the vertical channel structure VS, the separation structure SPS, the cell contact plug PLG, and the through contact TVS may have top surfaces coplanar with each other.

Fig. 15 is a cross-sectional view taken along line I-I' of fig. 2 to illustrate a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts. Fig. 16A and 16B are enlarged sectional views respectively showing portions "M" and "N" of fig. 15. For brevity of description, elements previously described with reference to fig. 2 and 3 may be identified by the same reference numerals without repeating repeated descriptions thereof.

Referring to fig. 2, 15, 16A and 16B, each vertical channel structure VS may include a lower channel structure VSa and an upper channel structure VSb on the lower channel structure VSa. Each separation structure SPS may include a lower separation structure SPSa and an upper separation structure SPSb on the lower separation structure SPSa. Each of the cell contact plugs PLG may include a lower contact plug PLGa and an upper contact plug PLGb on the lower contact plug PLGa. The through-contact TVS may include a lower through-contact TVSa and an upper through-contact TVSb on the lower through-contact TVSa.

The top surface of the lower channel structure VSa, the top surface of the lower separation structure SPSa, the top surface of the lower contact plug PLGa, and the top surface of the lower through contact TVSa may be coplanar with each other. For example, the top surface of the lower channel structure VSa, the top surface of the lower separation structure SPSa, the top surface of the lower contact plug PLGa, and the top surface of the lower through contact TVSa may be located at the same level (e.g., the fourth level LV 4).

The top surface of the upper channel structure VSb, the top surface of the upper separation structure SPSb, the top surface of the upper contact plug PLGb, and the top surface of the upper through contact TVSb may be coplanar with each other.

A diameter DI1a of an upper portion of the lower channel structure VSa may be greater than a diameter DI1b of a lower portion of the upper channel structure VSb. The diameter of the vertical channel structure VS may be drastically changed near the boundary between the lower channel structure VSa and the upper channel structure VSb.

The width Wla of the upper portion of the lower separation structure SPSa may be greater than the width Wlb of the lower portion of the upper separation structure SPSb. The width of the separation structure SPS may be drastically changed near the boundary between the lower separation structure SPSa and the upper separation structure SPSb.

A diameter DI2a of an upper portion of the lower contact plug PLGa may be greater than a diameter DI2b of a lower portion of the upper contact plug PLGb. The diameter of the cell contact plug PLG may sharply change near the boundary between the lower contact plug PLGa and the upper contact plug PLGb.

Fig. 17 and 18 are sectional views taken along line I-I' of fig. 2 to illustrate methods of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts. For the sake of brevity, elements previously described with reference to fig. 2 and 4 to 14B may be identified by the same reference numerals without repeating repeated descriptions thereof.

Referring to fig. 2 and 17, a first molding structure MO1 may be formed on the upper semiconductor layer USL. In detail, the first molding structure MO1 may be formed by vertically and alternately stacking a first insulating layer IL1 and a sacrificial layer HL on the upper semiconductor layer USL. A stair-step structure STS may be formed in the first molding structure MO 1. The third interlayer insulating layer ILD3 may be formed to cover the stepped structure STS of the first molding structure MO 1.

A patterning process may be performed on the structure having the third interlayer insulating layer ILD3 to form first to fifth holes HO1-HO5 having a high aspect ratio. The first to fourth holes HO1-HO4 may be formed to penetrate the first molding structure MO 1.

Referring to fig. 2 and 18, a sacrificial material SAC may be formed to fill the first to fifth holes HO1-HO 5. A second molded structure MO2 may be formed on the first molded structure MO1 and the third interlayer insulating layer ILD 3. In detail, the second molding structure MO2 may be formed by vertically and alternately stacking a first insulation layer IL1 and a sacrificial layer HL on the first molding structure MO 1. The second insulating layer IL2 may be formed as an uppermost layer of the second molding structure MO 2. The stair-step structure STS may be formed in the second molding structure MO 2. An additional interlayer insulating layer ILD3a may be formed to cover the stepped structure STS of the second molding structure MO 2.

A patterning process may be performed on the structure having the additional interlayer insulating layer ILD3a to additionally form first to fifth holes HO1-HO5 having a high aspect ratio. The first to fifth holes HO1-HO5 may be formed to expose the sacrificial material SAC filling the first to fifth holes HO1-HO5 of the first molding structure MO 1. The subsequent processes may be performed in substantially the same manner as described with reference to fig. 6 to 13.

In the method of manufacturing a semiconductor memory device according to some example embodiments of the inventive concepts, holes defining high aspect ratios of the vertical channel structure, the separation structure, the cell contact plug, and the through contact may be simultaneously formed. Since a plurality of structures are formed by a single process, the process of manufacturing the semiconductor memory device can be simplified, and reduction in manufacturing cost can be achieved.

According to example embodiments described with reference to fig. 1 to 18, the semiconductor device may correspond to a three-dimensional memory device in which memory cells are above peripheral circuits. However, example embodiments are not limited thereto, and a semiconductor device according to some example embodiments may include a semiconductor layer, an electrode structure on the semiconductor layer, an electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer, a separation structure penetrating the electrode structure, the separation structure extending in a first direction and horizontally separating at least one of the electrodes of the electrode structure into a pair of electrodes, and an interlayer insulating layer covering the electrode structure. The side wall of the separation structure includes a protruding portion and a recessed portion when viewed in a plan view, the protruding portion protruding in a direction away from a centerline of the separation structure, and the recessed portion being recessed toward the centerline. The peripheral circuit structure may be on the substrate, but the memory cell may not be above the peripheral circuits.

Although example embodiments of the inventive concept have been particularly shown and described, it will be understood by those of ordinary skill in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

This application claims priority from korean patent application No. 10-2019-0113457, filed on 16.9.2019 with the korean intellectual property office, the entire contents of which are incorporated herein by reference.