阅读说明：本技术 一种电容器 (Capacitor ) 是由 程伟 左成杰 王政 何军 于 2021-06-18 设计创作，主要内容包括：本申请实施例提供一种电容器,涉及电容技术领域,该电容器包括：多个金属层,相邻金属层之间设置有介电层；每个金属层上包括至少一个金属块,相邻金属层上的金属块之间通过过孔连接形成一个金属极板,各金属层上的相邻金属块之间相隔预设距离；其中,该电容器等效的多个参考电容中的两个相邻的参考电容共用该电容器中的一个金属极板。应用本申请实施例,可以从整体上减小电容器的尺寸,进而使集成电路更加小型化。(The embodiment of the application provides a capacitor, relates to electric capacity technical field, and this capacitor includes: a plurality of metal layers, a dielectric layer being disposed between adjacent metal layers; each metal layer comprises at least one metal block, the metal blocks on the adjacent metal layers are connected through via holes to form a metal polar plate, and the adjacent metal blocks on each metal layer are separated by a preset distance; wherein, two adjacent reference capacitances in a plurality of equivalent reference capacitances of the capacitor share one metal plate in the capacitor. By applying the embodiment of the application, the size of the capacitor can be reduced on the whole, and further the integrated circuit is more miniaturized.)

1. A capacitor, characterized in that the capacitor comprises: a plurality of metal layers, a dielectric layer being disposed between adjacent metal layers;

each metal layer comprises at least one metal block, the metal blocks on the adjacent metal layers are connected through via holes to form a metal polar plate, and the adjacent metal blocks on each metal layer are separated by a preset distance;

wherein two adjacent reference capacitances of the plurality of reference capacitances equivalent to the capacitor share one metal plate of the capacitor.

2. The capacitor of claim 1, wherein the capacitor has a predetermined overlap area between the metal plates, the predetermined overlap area being related to a capacitance of a plurality of reference capacitances equivalent to the capacitor.

3. The capacitor of claim 2, wherein the number of metal plates included in the capacitor is related to the number of reference capacitances and the number of common metal plates between each reference capacitance.

4. The capacitor of claim 3 wherein said number of metal plates is 3.

5. The capacitor of claim 2, comprising a number of ports equal to the number of metal plates in the capacitor.

6. The capacitor of claim 5, wherein if a target port of the plurality of ports is to be grounded, a metal plate corresponding to the target port comprises a grounded metal layer.

7. The capacitor of claim 5, wherein if the port is connected to an external device, the external device is connected to any one of the metal blocks on the metal plate corresponding to the port.

8. The capacitor of claim 1 wherein each metal plate is comprised of at least 2 metal blocks.

9. The capacitor according to any one of claims 1-8, wherein the material of the via is the same as the material of the metal block.

10. The capacitor of claim 9, wherein the material of the metal block is a conductive material.

Technical Field

The application relates to the technical field of capacitors, in particular to a capacitor.

Background

With the development of electronic information technology, increasingly higher requirements are put forward on miniaturization, light weight and the like of electronic equipment (such as wearable equipment and ultrathin computers). Capacitors are often used in electronic systems because of their ability to store electrical energy.

In order to miniaturize an integrated circuit, how to reduce the size of a capacitor is a problem to be solved.

Disclosure of Invention

It is an object of the present application to provide a multilayer capacitor structure that can reduce the size of the capacitor in view of the above-mentioned deficiencies in the prior art.

In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

an embodiment of the present application provides a capacitor, the capacitor includes: a plurality of metal layers, a dielectric layer being disposed between adjacent metal layers;

each metal layer comprises at least one metal block, the metal blocks on the adjacent metal layers are connected through via holes to form a metal polar plate, and the adjacent metal blocks on each metal layer are separated by a preset distance;

wherein two adjacent reference capacitances of the plurality of reference capacitances equivalent to the capacitor share one metal plate of the capacitor.

Optionally, the capacitor has a preset overlap area between the metal plates, and the preset overlap area is related to capacitances of a plurality of equivalent reference capacitances of the capacitor.

Optionally, the number of metal plates included in the capacitor is related to the number of reference capacitances and the number of shared metal plates between the reference capacitances.

Optionally, the number of the metal plates is 3.

Optionally, the capacitor comprises a plurality of ports, the number of ports being the same as the number of metal plates in the capacitor.

Optionally, if a target port of the plurality of ports needs to be grounded, the metal plate corresponding to the target port includes a grounded metal layer.

Optionally, if the port is connected with an external device, the external device is connected to any one of the metal blocks on the metal plate corresponding to the port.

Optionally, each metal plate is composed of at least 2 metal blocks.

Optionally, the material of the via is the same as the material of the metal block.

Optionally, the material of the metal block is a conductor material.

The beneficial effect of this application is:

the embodiment of this application provides a capacitor, this capacitor includes: a plurality of metal layers, a dielectric layer being disposed between adjacent metal layers; each metal layer comprises at least one metal block, the metal blocks on the adjacent metal layers are connected through via holes to form a metal polar plate, and the adjacent metal blocks on each metal layer are separated by a preset distance; wherein, two adjacent reference capacitances in a plurality of equivalent reference capacitances of the capacitor share one metal plate in the capacitor. By adopting the capacitor provided by the embodiment of the application, when the effect of connecting a plurality of reference capacitors is equivalent, the same metal plate in the capacitor can be used as a respective metal plate in two reference capacitors, so that the size of the capacitor can be reduced on the whole, and further an integrated circuit is miniaturized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic structural diagram of a capacitor according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a metal plate in a capacitor provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of a reference capacitor according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a connection relationship of a plurality of reference capacitors provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of another capacitor provided in an embodiment of the present application;

fig. 6 is a schematic structural diagram of another capacitor provided in the embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present application, it is further noted that, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a capacitor according to an embodiment of the present disclosure. As shown in fig. 1, the capacitor 100 may include: a plurality of metal layers 101 with a dielectric layer 102 disposed between adjacent metal layers.

Each metal layer 101 comprises at least one metal block 1011, the metal blocks 1011 on adjacent metal layers 101 are connected through a via 103 to form a metal plate 104, and the adjacent metal blocks 1011 on each metal layer 101 are separated by a preset distance; wherein two adjacent reference capacitances of the equivalent plurality of reference capacitances of capacitor 100 share one metal plate 104 of capacitor 100.

First, it should be noted that, based on the connection relationship of the reference capacitors and the capacitance corresponding to the reference capacitors in the schematic diagram of fig. 4, the internal structure of the capacitor 100 is designed, and the capacitor 100 can be equivalent to the effect of connecting a plurality of reference capacitors to each other.

Specifically, the number of the metal layers 101 in the capacitor 100 may be set according to design requirements, and if the capacitor 100 needs a capacitance equivalent to three reference capacitors connected to each other, the number of the metal layers 100 in the capacitor 100 may be 5 or 6, which is not limited in this application. A dielectric layer 102 may be disposed between every two adjacent metal layers 101, wherein the dielectric layer 102 is an insulating dielectric material, and may include a solid insulating dielectric material and a liquid insulating dielectric material, the solid insulating dielectric material may include, for example, ceramic, mica, and the like, the liquid insulating dielectric material may include an electrolyte, and of course, air may also be used as the dielectric layer 102, and the material property of the dielectric layer 102 is not limited in this application.

Each metal layer 101 may include one metal block 1011, or may include a plurality of metal blocks 1011, for example, 2 or 3 metal blocks 1011, and two adjacent metal blocks 1011 included on each metal layer 101 may be separated by a predetermined distance, where the predetermined distance is related to an overlapping area between metal blocks 1011 on different metal layers 101, and may be set according to design requirements, which is not limited in this application.

It should be noted that the size of each via 103 in the capacitor 100 may be set according to the process requirements, and the size of each via 103 may be the same. The distance between adjacent metal layers 101 may also be set according to the process requirements, and the distance between every two adjacent metal layers 101 may be the same, which is not limited in this application.

Each metal plate 104 in the capacitor 100 is composed of a plurality of metal blocks 1011 and vias 103, fig. 2 is a schematic structural diagram of one metal plate in the capacitor provided in the embodiment of the present application, and as can be seen from fig. 2, the vias 103 connect the metal blocks 1011 on the 3 metal layers 101 to be equivalent to one metal plate 104, it should be noted that fig. 2 is only an example, the number of the metal layers 101 corresponding to the metal plate 104 may also be 2 or other multiple, and the present application does not limit the same.

Fig. 3 is a schematic structural diagram of a reference capacitor provided in an embodiment of the present application, where the structure of the reference capacitor is a basic structure of a capacitor, and the reference capacitor is composed of two metal plates (e.g., a metal plate a and a metal plate B) and an intermediate insulating dielectric layer, and as long as there is an overlapping region between the metal plates a and B, the reference capacitor can be used as a capacitor. Based on this, as long as there is an overlapping area between the metal blocks 1011 on the two metal plates 104 in the capacitor 100, the two metal plates 104 can be equivalent to the reference capacitance shown in fig. 3.

According to the structure of the capacitor 100, the two metal plates 104 in the capacitor 100 can be equivalent to the reference capacitance shown in fig. 3 as long as there is an overlapping region, and two equivalent reference capacitances can share the same metal plate 104, that is, if the capacitor 100 needs the effect of connecting a plurality of equivalent reference capacitances to each other, one metal plate 104 can be shared by the adjacent reference capacitances in the capacitor 100.

With the capacitor shown in fig. 1, the capacitor may include a plurality of metal layers, and a dielectric layer is disposed between adjacent metal layers; each metal layer comprises at least one metal block, the metal blocks on the adjacent metal layers are connected through via holes to form a metal pole plate, and the adjacent metal blocks on each metal layer are separated by a preset distance. By adopting the capacitor provided by the embodiment of the application, when the effect of connecting a plurality of reference capacitors is equivalent, the same metal plate in the capacitor can be used as a respective metal plate in two reference capacitors, so that the size of the capacitor can be reduced on the whole, and an integrated circuit is more miniaturized.

Optionally, the metal plates 104 of the capacitor 100 have a predetermined overlap area therebetween, and the predetermined overlap area is related to the capacitance of a plurality of reference capacitors equivalent to the capacitor 100.

First, the connection relationship among the reference capacitors and the capacitance corresponding to each reference capacitor are known. Fig. 4 is a schematic diagram of a connection relationship of multiple reference capacitors according to an embodiment of the present disclosure. As shown in fig. 4, the reference capacitor 1, the reference capacitor 2, and the reference capacitor 3 are sequentially connected, capacitances of the reference capacitor 1, the reference capacitor 2, and the reference capacitor 3 are C1, C2, and C3, respectively, E in fig. 4 represents a port between the reference capacitor 1 and the reference capacitor 2, F represents a port between the reference capacitor 2 and the reference capacitor 3, and G represents a port between the reference capacitor 1 and the reference capacitor 3.

The capacitance of the reference capacitor mentioned above can be calculated by using the following flat capacitance calculation formula:

C＝ε×ε₀×S/d

wherein C is capacitance, ε is relative dielectric constant, ε₀The dielectric constant is vacuum, the overlapping area is S, and the distance between the metal plates is d.

When other parameters are fixed, the capacitance C of the reference capacitor is in direct proportion to the overlapping area S between the two metal plates, that is, the more the overlapping area between the two metal plates is, the larger the capacitance C of the reference capacitor is.

Based on this, the overlapping area between the metal plates 104 in the capacitor 100 can be determined according to the capacitance corresponding to each reference capacitor in fig. 4, and the determined overlapping area is used as the design parameter of the capacitor 100, so as to design the corresponding relationship between the metal blocks 1011 in the metal plates 104 of the capacitor 100.

Optionally, the number of metal plates 104 included in the capacitor 100 is related to the number of reference capacitances and the number of shared metal plates between the reference capacitances.

For example, assuming that the number of reference capacitors is 3, and the connection relationship is as shown in fig. 4, it can be seen that a common metal plate exists between the reference capacitor 1 and the reference capacitor 2, a common metal plate exists between the reference capacitor 1 and the reference capacitor 3, a common plate exists between the reference capacitor 2 and the reference capacitor 3, that is, there are 3 common metal plates in the 3 interconnected reference capacitors of fig. 4, typically two metal plates for each reference capacitor, 6 for 3 reference capacitors, based on the number of common metal plates and the total number of metal plates, it can be seen that when the number of metal plates 104 included in the capacitor 100 is 3, and in particular, the capacitor 100 has the effect of being equivalent to 3 reference capacitors connected to each other, the number of metal plates 104 included in capacitor 100 is the number of total metal plates minus the number of common metal plates.

In another example, assuming that 2 reference capacitors are connected to each other and there are common metal plates between reference capacitor 1 and reference capacitor 2, and typically, 4 metal plates are needed for 2 reference capacitors, then when capacitor 100 is equivalent to the effect of 2 reference capacitors connected to each other, the number of metal plates 104 included in capacitor 100 is the number of total metal plates minus the number of common metal plates, i.e. 3 metal plates 104 are included in capacitor 100.

In summary, assuming that the number of reference capacitances is N and the number of common metal plates between the reference capacitances is M, the number of metal plates in the capacitor 100 is 2 × N-M.

With 3 reference capacitors connected to each other, the capacitor 100 achieves the effect of connecting 3 reference capacitors to each other by using only 3 metal plates 104, which can improve the space utilization, and the parasitic parameters are increased as the number of metal plates is increased, and the parasitic parameters of the capacitor 100 can be reduced.

The following description will be given mainly taking as an example the effect of the capacitor 100 equivalent to 3 reference capacitances connected to each other.

Fig. 5 is a schematic structural diagram of another capacitor provided in an embodiment of the present application. As shown in fig. 5, metal block M1, metal block M2, metal block M3, metal block M4, metal block M5, and metal block M6 correspond to metal block 1011 mentioned above, via V1, via V2, and via V3 correspond to via 103 mentioned above, and metal plate P1, metal plate P2, and metal plate P3 correspond to metal plate 104 mentioned above.

As can be seen from the above description, the overlapping area between the metal plate P1 and the metal plate P2 is related to the capacitance C1 of the reference capacitor 1, the overlapping area between the metal plate P1 and the metal plate P3 is related to the capacitance C2 of the reference capacitor 2, and the overlapping area between the metal plate P2 and the metal plate P3 is related to the capacitance C3 of the reference capacitor 3. As can be seen from fig. 5, the metal plate P1 is composed of a metal block M1, a metal block M3, and another metal block belonging to the same metal layer as the metal block M2, the metal plate P2 is composed of a metal block M2, a metal block M5, and another metal block belonging to the same metal layer as the metal block M3, and the metal plate P3 is composed of a metal block M4 and a metal block M6.

Specifically, the metal plate P1 and the metal plate P2 are crossed, wherein an overlapping area exists between the metal block M1 and the metal block M2 to generate a capacitance 1, an overlapping area exists between the metal block M2 and the metal block M3 to generate a capacitance 2, and an overlapping area exists between the metal block M3 and the metal block M5 to generate a capacitance 3, that is, the total capacitance between the metal plate P1 and the metal plate P2 can be the sum of the capacitances 1, 2 and 3, that is, the sum of the capacitances 1, 2 and 3 can be equal to the capacitance C1 of the reference capacitor 1.

The metal plate P1 and the metal plate P3 do not intersect with each other, wherein there is an overlapping area between the metal mass M3 and the metal mass M4, which generates a capacitance corresponding to the capacitance C2 of the reference capacitor 2, and it can be seen that the overlapping area between the metal mass M3 and the metal mass M4 is smaller, which represents that the capacitance C2 of the reference capacitor 2 is smaller.

The metal plate P2 and the metal plate P3 do not intersect with each other, and an overlapping area is formed between the metal block M5 and the metal block M6, so that a capacitance corresponding to the capacitance C3 of the reference capacitor 3 can be generated.

From the perspective of the size of the overlapping area, the magnitude relationship of the capacitance corresponding to each reference capacitor can be as follows: the capacitance C3 of the reference capacitor 3 is larger than the capacitance C2 of the reference capacitor 2 and smaller than the capacitance C1 of the reference capacitor 1, i.e. the capacitance C1 of the reference capacitor 1 is the largest and the capacitance C2 of the reference capacitor 2 is the smallest. That is, if the capacitance of a reference capacitor is large, the design concept of crossing metal plates can be used to design the positional relationship between the metal plates 104 in the capacitor 100.

For example, if the capacitance C2 of the reference capacitor 2 and the capacitance C3 of the reference capacitor 3 are increased, the metal plate P1 and the metal plate P3 are crossed, and the metal plate P2 and the metal plate P3 are crossed. Specifically, fig. 6 is a schematic structural diagram of another capacitor provided in the embodiment of the present application. As shown in fig. 6, the metal blocks included in the metal plate P1 and the metal plate P2 are the same as those in fig. 5, and the metal plate P3 is composed of a metal block M0, another metal block belonging to the same metal layer as the metal block M1, another metal block belonging to the same metal layer as the metal block M2, another metal block belonging to the same metal layer as the metal block M3, another metal block belonging to the same metal layer as the metal block M5, and a metal block M6, which will not be described again here.

Specifically, the metal plate P1 and the metal plate P2 intersect with each other, and the details can be referred to the description of fig. 5, and will not be further described here.

The metal plate P1 and the metal plate P3 are crossed, wherein an overlapping area exists between the metal block M0 and the metal block M1 to generate a capacitance of 4, and an overlapping area exists between the metal block M3 and the metal block M6 to generate a capacitance of 5, that is, the total capacitance between the metal plate P1 and the metal plate P3 can be the sum of the capacitance of 4 and the capacitance of 5, that is, the sum of the capacitance of 4 and the capacitance of 5 can be equal to the capacitance of C2 of the increased reference capacitor 2.

The metal plate P2 and the metal plate P3 are crossed, wherein an overlapping area exists between the metal block M0 and the metal block M2 to generate a capacitance of 6, and an overlapping area exists between the metal block M5 and the metal block M6 to generate a capacitance of 7, that is, the total capacitance between the metal plate P2 and the metal plate P3 can be the sum of the capacitance of 6 and the capacitance of 7, that is, the sum of the capacitance of 6 and the capacitance of 7 can be equal to the capacitance of C3 of the increased reference capacitor 3.

It can be seen that the capacitor 100 uses a small number of metal plates to achieve the same effect as the interconnection of multiple reference capacitors regardless of the change in capacitance of each reference capacitor.

Optionally, the capacitor 100 may include a number of ports that is the same as the number of metal plates 104 in the capacitor 100.

Capacitor 100 is a unitary structure that often requires connections to other devices in the circuit, and ports are provided on capacitor 100 for connection to other devices. As can be seen from the schematic diagram of the multiple reference capacitive connections shown in fig. 4, the nodes E, F, G correspond to the ports where connections exist with other devices, the number of the ports is the same as the number of the metal plates 104 in the capacitor 100, and the positions correspond to the positions of the metal plates 104 in the capacitor. Specifically, as shown in fig. 5, node E corresponds to metal plate P1, node G corresponds to metal plate P2, and node F corresponds to metal plate P3. It can be seen that the positions of the metal plate P1, the metal plate P2 and the metal plate P3 in fig. 5 can be provided with ports respectively.

Optionally, if a target port of the plurality of ports needs to be grounded, the metal plate corresponding to the target port includes a grounded metal layer.

For example, if the node E in fig. 4 needs to be grounded, i.e. the port corresponding to the metal plate P1 in fig. 5 needs to be grounded, the metal plate P1 needs to include a grounded metal block, i.e. the grounded metal block is located on a grounded metal layer, such as the metal block M1 in the metal plate P1 belongs to the metal block on the grounded metal layer, or the metal layer including the metal block M1 is connected to the metal layer as ground.

If the node F in fig. 4 needs to be grounded, that is, the port corresponding to the metal plate P3 in fig. 5 needs to be grounded, the metal plate P3 needs to include a grounded metal block, that is, the grounded metal block is located on a grounded metal layer, for example, the metal block M6 in the metal plate P3 belongs to a metal block on a grounded metal layer. Referring to fig. 6, if the metal plate P3 needs to include a grounded metal block, the metal block M0 in the metal plate P3 belongs to a metal block on a grounded metal layer, or the metal block M6 in the metal plate P3 belongs to a metal block on a grounded metal layer, a metal layer including the metal block M0 and a metal layer as ground may be connected, or a metal layer including the metal block M6 and a metal layer as ground may be connected.

Optionally, if the port is connected with an external device, the external device is connected to any one of the metal blocks on the metal plate corresponding to the port.

For example, as shown in fig. 5, if the port corresponding to the metal plate P1 needs to be connected to an external device, that is, the node E in fig. 4 needs to be connected to an external device, the external device may be connected to the metal block M1 included in the metal plate P1, another metal block or metal block M3 belonging to the same metal layer as the metal block M2, or may be connected to any position of the via V1; if the port corresponding to the metal plate P2 needs to be connected with an external device, that is, the node G in fig. 4 needs to be connected with an external device, the external device may be connected to the metal block M2, the metal block M5, or another metal block belonging to the same metal layer as the metal block M3 included in the metal plate P2, or may be connected to any position of the via hole V2; if the port corresponding to the metal plate P3 needs to be connected with an external device, that is, the node F in fig. 4 needs to be connected with an external device, the external device may be connected to the metal block M4 or the metal block M6 included in the metal plate P3. Of course, the connection may be made at any position of the via V3.

Alternatively, each metal plate 104 in the capacitor 100 may be comprised of at least 2 metal blocks, with each metal block being located on a different metal layer. As shown in fig. 5, the metal plate P1 is composed of 3 metal blocks, the metal plate P2 is composed of 3 metal blocks, and the metal plate P3 is composed of 2 metal blocks. The metal plate P3 shown in fig. 6 is composed of 6 metal blocks, and it should be noted that the present application does not limit the number of metal blocks included in the metal plate.

Optionally, the material of the via 103 in the capacitor 100 is the same as the material of the metal block 1011. The material of the metal block 1011 is a conductor material, and specifically, the conductor material includes one or more of copper, gold, silver, aluminum, a conductive alloy, a carbon material, and the like, which is not limited in this application.

The following process flow of the capacitor 100 will be briefly described, and the capacitor 100 including 4 metal layers will be described as an example. Firstly, establishing two middle metal layers, etching the two metal layers to obtain metal blocks on the two metal layers, then carrying out processes of drilling, electroplating, etching patterns and the like, obtaining the two middle metal layers, then carrying out hot pressing process, namely adding dielectric layers, drilling, electroplating, etching patterns and the like in the area adjacent to the metal layers, and forming 4 metal layers. By analogy, the capacitor 100 with multiple metal layers can be obtained.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.