阅读说明：本技术 非易失性存储器装置 (Non-volatile memory device ) 是由 南尚完 千毅贤 闵丙俊 于 2020-01-09 设计创作，主要内容包括：提供了一种非易失性存储器装置。该非易失性存储器装置包括：第一存储器块,包括沿与基底垂直的方向堆叠的多个单元晶体管,所述多个单元晶体管与多条地选择线、多条字线和多条串选择线互连；块选择电路,与所述多条地选择线、所述多条字线和所述多条串选择线连接,并响应于块选择信号而将相应的驱动电压分别提供给所述多条地选择线、所述多条字线和所述多条串选择线；以及块未选择电路,仅与所述多条串选择线中的特定串选择线连接,并响应于块未选择信号而将截止电压仅提供给特定串选择线。(A non-volatile memory device is provided. The nonvolatile memory device includes: a first memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate, the plurality of cell transistors interconnected with a plurality of ground select lines, a plurality of word lines, and a plurality of string select lines; a block selection circuit connected to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and supplying corresponding driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, respectively, in response to a block selection signal; and a block non-selection circuit connected only to a specific string selection line among the plurality of string selection lines and supplying an off-voltage only to the specific string selection line in response to a block non-selection signal.)

1. A non-volatile memory device, comprising:

a first memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate, the plurality of cell transistors interconnected with a plurality of ground select lines, a plurality of word lines, and a plurality of string select lines;

a block selection circuit connected to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines and configured to supply corresponding driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, respectively, in response to a block selection signal; and

a block non-selection circuit connected only with a specific string selection line of the plurality of string selection lines and configured to supply an off-voltage only to the specific string selection line in response to a block non-selection signal,

wherein the number of the specific string selection lines is smaller than the number of the plurality of string selection lines.

2. The non-volatile memory device of claim 1, further comprising:

a block decoder configured to receive an address from an external device and output a block selection signal and a block non-selection signal based on the received address.

3. The non-volatile memory device of claim 2, wherein in response to activation of the block non-select signal, the non-volatile memory device is configured such that the block non-select circuit provides a cutoff voltage to a particular string select line, and

wherein the block selection circuit floats remaining ones of the plurality of string selection lines except for a specific string selection line in response to deactivation of the block selection signal.

4. The nonvolatile memory device according to claim 1, wherein the off voltage is any one of a ground voltage and a negative voltage.

5. The non-volatile memory device of claim 1, wherein the first memory block includes a first cell string and a second cell string both interposed between the substrate and the first bit line,

wherein the first unit string includes:

a first ground selection transistor among the plurality of cell transistors, the first ground selection transistor being stacked in a direction perpendicular to the substrate and connected to a first ground selection line among the plurality of ground selection lines;

a first memory cell of the plurality of cell transistors, the first memory cell being located above the first ground selection transistor, stacked in a direction perpendicular to the substrate, and connected to the plurality of word lines, respectively; and

a first string selection transistor of the plurality of cell transistors, the first string selection transistor being positioned above the first memory cell, stacked in a direction perpendicular to the substrate, and respectively connected to a first string selection line of the plurality of string selection lines, and

wherein the second unit string includes:

a second ground selection transistor of the plurality of cell transistors, stacked in a direction perpendicular to a substrate and connected to a second ground selection line of the plurality of ground selection lines;

a second memory cell of the plurality of cell transistors, the second memory cell being located above the second ground selection transistor, stacked in a direction perpendicular to the substrate, and connected to the plurality of word lines, respectively; and

and a second string selection transistor of the plurality of cell transistors, the second string selection transistor being positioned above the second memory cell, stacked in a direction perpendicular to the substrate, and connected to a second string selection line of the plurality of string selection lines, respectively.

6. The non-volatile memory device of claim 5, wherein a particular string select line includes a first portion in a first string select line and a second portion in a second string select line.

7. The non-volatile memory device of claim 6, wherein a first portion of the first string selection line is connected to a first portion of the first string selection transistors, the first portion of the first string selection transistors is arranged closer to the first bit line than remaining first string selection transistors of the first string selection transistors other than the first portion of the first string selection transistors, and

wherein a second portion of the second string selection lines is connected to a second portion of the second string selection transistors, the second portion of the second string selection transistors being arranged closer to the first bit lines than remaining second string selection transistors of the second string selection transistors except for the second portion of the second string selection transistors.

8. The non-volatile memory device of claim 6, wherein the number of first string select lines is M,

wherein the number of string selection transistors connected to the first portion in the first string selection line among the first string selection transistors is N,

wherein each of M and N is a positive integer, and N is less than M,

wherein the number of the second string selection lines is M, and

wherein the number of string selection transistors connected to the second portion of the second string selection line among the second string selection transistors is N.

9. The nonvolatile memory device according to claim 6, wherein a threshold voltage of a string selection transistor connected to a first portion in the first string selection line among the first string selection transistors is larger than a threshold voltage of a string selection transistor connected to the remaining string selection lines except the first portion in the first string selection line among the first string selection transistors, and

wherein a threshold voltage of a string selection transistor among the second string selection transistors connected to the second portion of the second string selection lines is greater than a threshold voltage of a string selection transistor among the second string selection transistors connected to the remaining string selection lines of the second string selection lines other than the second portion of the second string selection lines.

10. The non-volatile memory device of claim 1, wherein block non-selection circuitry comprises: a plurality of unselected path transistors configured to supply a cut-off voltage to a specific string selection line in response to a block unselected signal; and is

Wherein a number of the plurality of unselected path transistors is less than a number of the plurality of string select lines.

11. A non-volatile memory device, comprising:

a first cell string including a plurality of first cell transistors connected in series between a common source line and a first bit line and stacked one on another in a direction perpendicular to a substrate;

a second cell string including a plurality of second cell transistors connected in series between the common source line and the first bit line and stacked on each other in a direction perpendicular to the substrate;

a block selection circuit connected with the first cell string and the second cell string through a plurality of signal lines and configured to supply respective driving voltages to the plurality of signal lines in response to a block selection signal; and

a block non-selection circuit connected only with a specific signal line of the plurality of signal lines and configured to supply an off-voltage to the specific signal line in response to a block non-selection signal,

wherein remaining signal lines except for the specific signal line among the plurality of signal lines include at least one first string selection line connected to the first cell string and at least one second string selection line connected to the second cell string.

12. The nonvolatile memory device according to claim 11, wherein the specific signal line includes:

a first signal line connected to a first cell transistor adjacent to a first bit line among the plurality of first cell transistors; and

and a second signal line connected to a second unit transistor adjacent to the first bit line among the plurality of second unit transistors.

13. The non-volatile memory device of claim 12, wherein the plurality of first cell transistors comprises a plurality of first string select transistors,

wherein the plurality of second cell transistors includes a plurality of second string selection transistors,

wherein the first cell transistor is one of the plurality of first string selection transistors, and

wherein the second cell transistor is one of the plurality of second string selection transistors.

14. The non-volatile memory device of claim 12, wherein the plurality of first cell transistors includes a first erase control transistor,

wherein the plurality of second cell transistors includes a second erase control transistor,

wherein the first cell transistor is a first erase control transistor, and

wherein the second cell transistor is a second erase control transistor.

15. The nonvolatile memory device according to claim 14, wherein the first signal line and the second signal line are erase control lines commonly connected to the first erase control transistor and the second erase control transistor.

16. The non-volatile memory device of claim 11, wherein the first cell string and the second cell string are included in a first memory block,

wherein when the first memory block is a selected block, the non-volatile memory device is configured such that: the block selection circuit supplies the respective drive voltages to the plurality of signal lines, and the block non-selection circuit is turned off, and

wherein, when the first memory block is an unselected block, the non-volatile memory device is configured such that: the block selection circuit makes the plurality of signal lines float, and the block non-selection circuit supplies an off-voltage to a specific signal line.

17. The non-volatile memory device of claim 11, wherein the cutoff voltage is a ground voltage or a negative voltage.

18. A non-volatile memory device, comprising:

a first memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate, the plurality of cell transistors being interconnected with a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines;

a block decoder configured to activate a block selection signal and a block non-selection signal based on a first address corresponding to a first memory block and a second address not corresponding to the first memory block, respectively, the first address and the second address being received from an external device;

a plurality of path transistors configured to supply respective driving voltages to the plurality of string selection lines, the plurality of word lines, and the plurality of ground selection lines, respectively, in response to activation of a block selection signal; and

a plurality of unselected path transistors configured to provide an off-voltage to a particular string selection line of the plurality of string selection lines in response to activation of a block unselected signal,

wherein a number of the plurality of unselected path transistors is less than a number of the plurality of string select lines.

19. The non-volatile memory device of claim 18, wherein the first memory block comprises:

a first cell string connected to the first bit line and including a plurality of first cell transistors connected in series;

a second cell string connected to the first bit line and including a plurality of second cell transistors connected in series;

a third cell string connected to the second bit line and including a plurality of third cell transistors connected in series; and

a fourth cell string connected with the second bit line and including a plurality of fourth cell transistors connected in series,

wherein a first string selection line of the plurality of string selection lines is connected with the first cell string and the third cell string;

wherein a second string selection line of the plurality of string selection lines is connected with the second cell string and the fourth cell string, and

wherein the particular string selection line includes a first portion in the first string selection line and a second portion in the second string selection line.

20. The non-volatile memory device of claim 19, wherein a first portion of the first string selection line is connected to a cell transistor physically closest to the first bit line among the plurality of first cell transistors and a cell transistor physically closest to the second bit line among the plurality of third cell transistors, and

wherein the second portion of the second string selection line is connected to a cell transistor physically closest to the first bit line among the plurality of second cell transistors and a cell transistor physically closest to the second bit line among the plurality of fourth cell transistors.

Technical Field

Embodiments of the inventive concepts described herein relate to a semiconductor memory, and more particularly, to a non-volatile memory device.

Background

Semiconductor memory devices are classified into volatile memory devices, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), in which stored data disappears when power is turned off, and non-volatile memory devices, such as flash memory devices, phase change ram (pram), magnetic ram (mram), resistive ram (rram), or ferroelectric ram (fram), in which stored data is retained even when power is turned off.

Flash memory devices are being widely used as high-capacity storage media. Now, with the development of three-dimensional flash memory devices, the integration degree of the flash memory devices is being improved, and various technologies for controlling the flash memory devices having the improved integration degree are being developed.

Disclosure of Invention

Embodiments of the inventive concept provide a nonvolatile memory device capable of reducing costs by reducing an area of a peripheral circuit (particularly, a row decoder) of the nonvolatile memory device.

According to an exemplary embodiment, a non-volatile memory device includes: a first memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate, the plurality of cell transistors interconnected with a plurality of ground select lines, a plurality of word lines, and a plurality of string select lines; a block selection circuit connected to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and supplying corresponding driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, respectively, in response to a block selection signal corresponding to a first memory block; and a block non-selection circuit connected only to a specific string selection line among the plurality of string selection lines and supplying an off-voltage only to the specific string selection line in response to a block non-selection signal that does not correspond to the first memory block. The number of the specific string selection lines may be less than the number of the plurality of string selection lines.

According to an exemplary embodiment, a non-volatile memory device includes: a first cell string including a plurality of first cell transistors connected in series between a common source line and a first bit line and stacked one on another in a direction perpendicular to a substrate; a second cell string including a plurality of second cell transistors connected in series between the common source line and the first bit line and stacked on each other in a direction perpendicular to the substrate; a block selection circuit connected to the first cell string and the second cell string through a plurality of signal lines and supplying corresponding driving voltages to the plurality of signal lines in response to a block selection signal; and a block non-selection circuit connected only to a specific signal line among the plurality of signal lines and supplying an off-voltage to the specific signal line in response to a block non-selection signal. The remaining signal lines except for the specific signal line among the plurality of signal lines include at least one first string selection line connected to the first cell string and at least one second string selection line connected to the second cell string.

According to an exemplary embodiment, a non-volatile memory device includes: a first memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate, the plurality of cell transistors being interconnected with a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines; a block decoder that activates a block selection signal and a block non-selection signal based on a first address corresponding to a first memory block and a second address not corresponding to the first memory block, respectively, the first address and the second address being received from an external device; a plurality of path transistors which supply respective driving voltages to the plurality of string selection lines, the plurality of word lines, and the plurality of ground selection lines, respectively, in response to activation of a block selection signal; and a plurality of unselected path transistors that supply an off-voltage to a particular string selection line of the plurality of string selection lines in response to activation of a block unselected signal. The number of the plurality of unselected path transistors is less than the number of the plurality of string select lines.

Drawings

The above and other objects and features of the inventive concept will become apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the inventive concept.

Fig. 2 is a circuit diagram illustrating a first memory block among a plurality of memory blocks included in a memory cell array of the nonvolatile memory device of fig. 1.

Fig. 3 is a diagram illustrating a row decoder of the non-volatile memory device of fig. 1 according to an example embodiment.

FIG. 4 is a flowchart illustrating operation of the non-volatile memory device of FIG. 1 according to an example embodiment.

Fig. 5 is a diagram illustrating in detail a configuration of a row decoder of fig. 3 according to an example embodiment.

Fig. 6 is a diagram illustrating program biasing of the row decoder of fig. 5 according to an example embodiment.

Fig. 7 is a diagram for describing an operation of the nonvolatile memory device of fig. 1 according to an example embodiment.

Fig. 8 is a diagram illustrating a row decoder of the nonvolatile memory device of fig. 1 according to an example embodiment.

Fig. 9A is a diagram illustrating a row decoder of the nonvolatile memory device of fig. 1 according to an example embodiment.

Fig. 9B is a diagram for describing a configuration of the row decoder of fig. 9A according to an example embodiment.

Fig. 10 is a circuit diagram illustrating a third memory block according to an embodiment of the inventive concept.

Fig. 11A to 11D are diagrams illustrating a row decoder according to an embodiment of the inventive concept.

Fig. 12 is a block diagram illustrating a memory system including a nonvolatile memory device according to an embodiment of the inventive concepts.

Detailed Description

Hereinafter, embodiments of the inventive concept may be described in detail and clearly to the extent that the inventive concept is easily implemented by those skilled in the art.

Fig. 1 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the inventive concept.

Referring to fig. 1, a nonvolatile memory device 100 may include a memory cell array 110 and peripheral circuits 120. For convenience of description, hereinafter, a description will be given as if the nonvolatile memory device 100 is a NAND flash memory device, but the inventive concept is not limited thereto.

The memory cell array 110 may include a plurality of memory Blocks (BLKs). Each memory block may include a plurality of cell strings. Each of the plurality of cell strings may include a plurality of series-connected cell transistors connected with a string selection line SSL, a word line WL, and a ground selection line GSL.

In one exemplary embodiment, the cell transistors of the memory cell array 110 may be stacked in a direction perpendicular to the semiconductor substrate. For example, the memory cell array 110 may include a three-dimensional memory block.

The peripheral circuit 120 may include a row decoder 121, a voltage generator 122, a control logic circuit 123, and an input/output circuit (I/O circuit) 124. In one exemplary embodiment, the memory cell array 110 may be formed in a cell region of a semiconductor substrate, and the peripheral circuit 120 may be formed in a peripheral region of the semiconductor substrate physically separated from the cell region. Alternatively, the peripheral circuit 120 may be formed on a semiconductor substrate, and the memory cell array 110 may be stacked on the peripheral circuit 120. For example, the non-volatile memory device 100 may be formed with a Cell On Periphery (COP) structure. However, the inventive concept is not limited thereto. For example, the non-volatile memory device 100 may be implemented in various shapes.

The row decoder 121 may be connected with the memory cell array 110 through string selection lines SSL, word lines WL, and ground selection lines GSL. The row decoder 121 may receive an address ADDR from an external device (e.g., a memory controller or a host device). In an exemplary embodiment, the address ADDR may include various address information, such as a block address, a row address, a column address, and the like. The row decoder 121 may decode the received address ADDR to control voltages of the string selection line SSL, the word line WL, and the ground selection line GSL.

The voltage generator 122 may generate various voltages (e.g., a plurality of program voltages, a plurality of verify voltages, a plurality of pass voltages, a plurality of select read voltages, a plurality of non-select read voltages, and a plurality of block select voltages) required for the operation of the nonvolatile memory device 100. The voltage generated from the voltage generator 122 may be provided to the row decoder 121.

The control logic circuit 123 may receive a command CMD or a control signal CTRL from an external device (e.g., a memory controller or a host device), and may control the row decoder 121, the voltage generator 122, and the input/output circuit 124 based on the received command CMD or the received control signal CTRL.

The input/output circuit 124 may be connected to the memory cell array 110 through a plurality of bit lines BL. The input/output circuit 124 may read DATA stored in the memory cell array 110 through the plurality of bit lines BL and may output the read DATA DADA to an external device. Alternatively, the input/output circuit 124 may receive DATA from an external device, and the received DATA may be stored in the memory cell array 110 through the plurality of bit lines BL.

Although not shown in fig. 1, the input/output circuit 124 may include a column decoder connected to the memory cell array 110 through a plurality of bit lines BL. The column decoder may receive a column address from an external device, and may decode the received column address to control the plurality of bit lines BL. The input/output circuit 124 may further include a page buffer connected to the plurality of bit lines BL to temporarily store data received from an external device or data read from the memory cell array 110 through the plurality of bit lines BL.

In one exemplary embodiment, the nonvolatile memory device 100 may operate in a specific cell (e.g., a block cell, a sub-block cell, a word line cell, or a page cell). For example, when a page-based program operation is performed on a first word line of the nonvolatile memory device 100, the row decoder 121 may select at least one memory block among a plurality of memory blocks included in the memory cell array 110 based on an address ADDR (specifically, a block address) received from an external device. The row decoder 121 may control the string selection line SSL, the word line WL, and the ground selection line GSL based on an address ADDR (specifically, a row address) received from an external device such that a program operation is performed on a first word line of a selected memory block.

In one exemplary embodiment, a plurality of memory blocks may share the bit line BL. For example, during a program operation, the bit line voltage may be provided to remaining memory blocks (i.e., unselected memory blocks) other than the selected memory block among the plurality of memory blocks. A particular cell transistor (e.g., a string selection transistor) of the unselected memory block may be turned off so that the bit line voltage is not applied to the unselected memory block. The row decoder 121 may provide a particular voltage to a control line (e.g., a portion of the string selection lines SSL) connected with a particular string selection transistor, so that the particular cell transistor is turned off. For example, when the number of string selection lines SSL is Y, the number of portions (e.g., X) in the string selection lines SSL is equal to or greater than 1 and less than Y. Here, X may be a positive integer equal to or greater than 1, and Y may be a positive integer greater than X and equal to or greater than 2.

In one exemplary embodiment, the row decoder 121 according to an embodiment of the inventive concept may supply a specific voltage to only a specific string selection line among string selection lines of unselected memory blocks. In this case, since it is not necessary to apply a specific voltage to all string selection lines of unselected memory blocks, the size of the row decoder 121 can be reduced. The configuration of the row decoder 121 according to an embodiment of the inventive concept will be described more precisely with reference to the accompanying drawings.

Fig. 2 is a circuit diagram illustrating a first memory block among a plurality of memory blocks included in the memory cell array 110 in fig. 1. In one exemplary embodiment, the three-dimensional structure of the first memory block BLK1 will be described with reference to fig. 2, but the inventive concept is not limited thereto. For example, the memory cell array 110 includes a plurality of memory blocks, each of which has a structure similar to that of the first memory block BLK1 of fig. 2. In one exemplary embodiment, the first memory block BLK1 illustrated in fig. 2 may correspond to a physical erase unit of the nonvolatile memory device 100, but the inventive concept is not limited thereto. For example, the physical erase units may be changed to page units, word line units, sub-block units, etc.

Referring to fig. 1 and 2, the first memory block BLK1 may include a plurality of cell strings CS11, CS12, CS21, and CS 22. The cell strings CS11, CS12, CS21, and CS22 may be arranged in a row direction and a column direction. For simplicity of explanation, four cell strings CS11, CS12, CS21, and CS22 are shown in fig. 2, but the inventive concept is not limited thereto. For example, the number of cell strings may increase or decrease in the row direction or the column direction.

Cell strings located at the same column among the plurality of cell strings CS11, CS12, CS21, and CS22 may be connected to the same bit line. For example, the cell strings CS11 and CS21 may be connected with the first bit line BL1, and the cell strings CS12 and CS22 may be connected with the second bit line BL 2.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22 may include a plurality of cell transistors. Each of the plurality of cell transistors may include a Charge Trap Flash (CTF) memory cell. The plurality of cell transistors may be stacked in a height direction, which is a direction perpendicular to a plane (e.g., a semiconductor substrate (not shown)) defined by a row direction and a column direction.

In each cell string, a plurality of cell transistors may be connected in series between a corresponding bit line (e.g., BL1 or BL2) and the common source line CSL. For example, the plurality of cell transistors may include string selection transistors SSTb and SSTa, dummy memory cells DMC1 and DMC2, memory cells MC1 to MC4, and ground selection transistors GSTa and GSTb. The series-connected string selection transistors SSTb and SSTa may be disposed between the series-connected memory cells MC1 through MC4 and a corresponding bit line (e.g., BL1 or BL 2). The series-connected ground selection transistors GSTa and GSTb may be disposed between the series-connected memory cells MC1 through MC4 and the common source line CSL.

In one exemplary embodiment, a second dummy memory cell DMC2 may be further disposed between the series-connected string selection transistors SSTb and SSTa and the series-connected memory cells MC1 through MC4, and a first dummy memory cell DMC1 may be further disposed between the series-connected memory cells MC1 through MC4 and the series-connected ground selection transistors GSTb and GSTa.

Here, the second dummy memory cell DMC2 is connected between the string selection transistor SSTa and the memory cell MC4, and the first dummy memory cell DMC1 is connected between the ground selection transistor GSTb and the memory cell MC 1. For example, the first dummy memory cell DMC1 and the second dummy memory cell DMC2 may have a similar or identical structure to the memory cells MC1 to MC4 and may be formed in the same process. The first dummy memory cell DMC1 and the second dummy memory cell DMC2 may be activated by the first dummy word line DWL1 and the second dummy word line DWL2, respectively, but may not have any "data" stored or read from an external device. For example, unlike the case of normal memory cells (e.g., memory cells MC 1-MC 4), data stored in dummy memory cells electrically connected to a dummy word line may not be sent outside the memory cell array by any select signals provided by the column decoder.

In one exemplary embodiment, each of the plurality of cell strings CS11, CS12, CS21, and CS22 may not include one or both of the first dummy memory cell DMC1 and the second dummy memory cell DMC 2. For example, without the first dummy memory cell DMC1 and the second dummy memory cell DMC2, the memory cells MC1 to MC4 connected in series may be directly connected to the string selection transistors SSTb and SSTa connected in series and the ground selection transistors GSTb and GSTa connected in series.

In the plurality of cell strings CS11, CS12, CS21, and CS22, memory cells located at the same height among the memory cells MC1 to MC4 may share the same word line. For example, the first memory cell MC1 of the plurality of cell strings CS11, CS12, CS21, and CS22 may be located at the same height from the substrate (not shown), and may share the first word line WL 1. The second memory cell MC2 of the plurality of cell strings CS11, CS12, CS21, and CS22 may be located at the same height from the substrate (not shown), and may share the second word line WL 2. Likewise, the third memory cell MC3 of the plurality of cell strings CS11, CS12, CS21, and CS22 may be located at the same height from the substrate (not shown) and may share the third word line WL3, and the fourth memory cell MC4 of the plurality of cell strings CS11, CS12, CS21, and CS22 may be located at the same height from the substrate (not shown) and may share the fourth word line WL 4.

In the plurality of cell strings CS11, CS12, CS21, and CS22, dummy memory cells located at the same height among the dummy memory cells DMC1 and DMC2 may share the same dummy word line. For example, a first dummy memory cell DMC1 in the plurality of cell strings CS11, CS12, CS21, and CS22 may share the first dummy word line DWL1, and a second dummy memory cell DMC2 in the plurality of cell strings CS11, CS12, CS21, and CS22 may share the second dummy word line DWL 2.

In the plurality of cell strings CS11, CS12, CS21, and CS22, string selection transistors located at the same height and at the same row among the string selection transistors SSTb and SSTa may be connected to the same string selection line. For example, the string selection transistors SSTb of the cell strings CS11 and CS12 may be connected with the string selection line SSL1b, and the string selection transistors SSTa of the cell strings CS11 and CS12 may be connected with the string selection line SSL1 a. The string selection transistors SSTb of the cell strings CS21 and CS22 may be connected with a string selection line SSL2b, and the string selection transistors SSTa of the cell strings CS21 and CS22 may be connected with a string selection line SSL2 a.

Although not shown in the drawings, in the plurality of cell strings CS11, CS12, CS21, and CS22, string selection transistors located at the same row among the string selection transistors SSTb and SSTa may share the same string selection line. For example, the string selection transistors SSTb and SSTa of the cell strings CS11 and CS12 may share a first string selection line, and the string selection transistors SSTb and SSTa of the cell strings CS21 and CS22 may share a second string selection line different from the first string selection line.

In the plurality of cell strings CS11, CS12, CS21, and CS22, ground selection transistors located at the same height and at the same row among the ground selection transistors GSTb and GSTa may be connected to the same ground selection line. For example, the ground selection transistors GSTb of the cell strings CS11 and CS12 may be connected to the ground selection line GSL1b, and the ground selection transistors GSTa of the cell strings CS11 and CS12 may be connected to the ground selection line GSL1 a. The ground selection transistors GSTb of the cell strings CS21 and CS22 may be connected to the ground selection line GSL2b, and the ground selection transistors GSTa of the cell strings CS21 and CS22 may be connected to the ground selection line GSL2 a.

Although not shown in the drawings, the ground selection transistors GSTa and GSTb may share the same ground selection line in each of the plurality of cell strings CS11, CS12, CS21, and CS 22. In the plurality of cell strings CS11, CS12, CS21, and CS22, ground selection transistors located at the same height among the ground selection transistors GSTa and GSTb may share the same ground selection line. Alternatively, in the plurality of cell strings CS11, CS12, CS21, and CS22, ground selection transistors located at the same row among the ground selection transistors GSTa and GSTb may share the same ground selection line.

In one exemplary embodiment, the first memory block BLK1 shown in fig. 2 is exemplary. For example, the number of cell strings may be increased or decreased, and the number of rows of cell strings and the number of columns of cell strings may be increased or decreased according to the number of cell strings. Also, in the first memory block BLK1, the number of cell transistors (GST, MC, DMC, SST, etc.) may increase or decrease, and the height of the first memory block BLK1 may increase or decrease according to the number of cell transistors. Further, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may be increased or decreased according to the number of cell transistors.

Fig. 3 is a diagram illustrating the row decoder 121 of fig. 1 according to an example embodiment. For brief explanation, the configuration of the row decoder 121 will be described with reference to one cell string CS11 among the plurality of cell strings CS11, CS12, CS21, and CS22 of the first memory block BLK 1. Further, components unnecessary for describing the row decoder 121 are omitted.

Hereinafter, in order to clearly describe various embodiments of the inventive concept, an example of performing an operation of the nonvolatile memory device 100 based on memory block units will be described. That is, in the following embodiments, the operation of the nonvolatile memory device 100 will be described with respect to selected memory blocks and unselected memory blocks, but the inventive concept is not limited thereto. For example, an operation of controlling various lines (e.g., GSL, WL, DWL, SSL, etc.) connected with a selected memory block based on the kind of operation (e.g., a program operation, a read operation, or an erase operation) of the nonvolatile memory device 100 may be performed.

Referring to fig. 1 to 3, the row decoder 121 may include a block decoder 121a, a block selection circuit 121b, a block non-selection circuit 121c, and a line driver 121 d.

The block decoder 121a may decode the block address ADDR _ BLK (e.g., included in the address ADDR) to output a block selection signal SEL _ BLK. For example, the block decoder 121a may determine whether the block address ADDR _ BLK corresponds to the first memory block BLK1 including the cell string CS 11. When the block address ADDR _ BLK corresponds to the first memory block BLK1, the first memory block BLK1 may be a selected block; when the block address ADDR _ BLK does not correspond to the first memory block BLK1, the first memory block BLK1 may be an unselected block. That is, the block decoder 121a may determine whether the first memory block BLK1 is a selected block or an unselected block based on the block address ADDR _ BLK.

When first memory block BLK1 is a selected block, block decoder 121a may output a "logic high" block select signal SEL _ BLK (e.g., cause block select signal SEL _ BLK to be activated) and a "logic low" block non-select signal/SEL _ BLK (e.g., cause block non-select signal/SEL _ BLK to be deactivated). When first memory block BLK1 is an unselected block, block decoder 121a may output a "logic low" block select signal SEL _ BLK (e.g., deactivate block select signal SEL _ BLK) and a "logic high" block unselected signal/SEL _ BLK (e.g., activate block unselected signal/SEL _ BLK). In an example embodiment, the block non-selection signal/SEL _ BLK may be generated by inverting the block selection signal SEL _ BLK. However, the inventive concept is not limited thereto. For example, the level of the block selection signal SEL _ BLK may be changed or modified differently.

The block selection circuit 121b may be connected between signal lines SSL1a, SSL1b, DWL1, DWL2, WL1 to WL4, GSL1a, and GSL1b (i.e., including string selection lines SSL1a and SSL1b, dummy word lines DWL1 and DWL2, word lines WL1 to WL4, and ground selection lines GSL1a and GSL1b) connected to the cell strings CS11 of the first memory block BLK1 and the line driver 121 d.

The block selection circuit 121b may operate in response to a block selection signal SEL _ BLK. For example, the block selection circuit 121b may include a plurality of path transistors respectively connected between a plurality of signal lines (e.g., SSL1a, SSL1b, DWL2, WL4 … WL1, DWL1, GSL1b, and GSL1a) and the line driver 121 d. The plurality of path transistors of the block selection circuit 121b may be turned on in response to a block selection signal SEL _ BLK of "logic high". In this case, driving voltages (e.g., VSSL1a, VSSL1b, VDWL2, VWL4 … VWL1, VDWL1, VGSL1b, and VGSL1a) from the line driver 121d may be supplied to the respective signal lines (e.g., SSL1a, SSL1b, DWL2, WL4 … WL1, DWL1, GSL1b, GSL1a), respectively.

The plurality of path transistors of the block selection circuit 121b may be turned off in response to the block selection signal SEL _ BLK of "logic low". In this case, the respective lines (e.g., SSL1a, SSL1b, DWL2, WL4 … WL1, DWL1, GSL1b, GSL1a) may be floated.

For example, when the first memory block BLK1 is a selected block, the block selection circuit 121b may supply corresponding driving voltages to various lines connected to the first memory block BLK 1; when the first memory block BLK1 is an unselected block, the block selection circuit 121b may float various lines connected to the first memory block BLK1, or may prevent a corresponding driving voltage from being supplied to the various lines.

In one exemplary embodiment, the driving voltage (e.g., VSSL1a, VSSL1b, VDWL2, VWL4 … VWL1, VDWL1, VGSL1b, VGSL1a) from the line driver 121d may be changed or modified differently according to the kind of operation (e.g., a program operation, a verify operation, a read operation, or an erase operation) of the nonvolatile memory device 100, whether a cell string is selected or unselected, or whether a word line is selected or unselected.

In one exemplary embodiment, when the first memory block BLK1 is an unselected block, a portion of the string selection transistors SSTb and SSTa may be turned off so that a voltage supplied to a bit line (e.g., BL1) is not applied to the first memory block BLK 1.

For example, the block non-selection circuit 121c may include a non-selection path transistor connected between the off-voltage VOFF and a first string selection line SSL1b among string selection lines SSL1a and SSL1b connected to the first memory block BLK1, and the non-selection path transistor may operate in response to a block non-selection signal/SEL _ BLK. In one exemplary embodiment, the off-voltage VOFF may be the ground voltage GND or a negative voltage.

For example, when the first memory block BLK1 is a selected block, the block unselection circuit 121c may be turned off, and when the first memory block BLK1 is an unselected block, the block unselection circuit 121c may be turned on. When the block non-selection circuit 121c is turned on, the off-voltage VOFF may be applied to the first string selection line SSL1b, and thus, the string selection transistor SSTb connected to the first string selection line SSL1b may be turned off. In this case, the voltage of the first bit line BL1 may not be applied to the first memory block BLK 1.

In one exemplary embodiment, when a specific memory block is an unselected block, the conventional nonvolatile memory device is configured to supply the off-voltage VOFF to all string selection lines associated with the specific memory block. In this case, the block non-selection circuit may include non-selection path transistors respectively connected to all the string selection lines. This means an increase in the size of the row decoder.

In contrast, according to an embodiment of the inventive concept, the block non-selection circuit 121c may be connected with only some of a plurality of string selection lines connected with one memory block (i.e., the first memory block BLK1), and the size of the row decoder 121 may be reduced.

FIG. 4 is a flowchart illustrating operation of the non-volatile memory device 100 of FIG. 1 according to an example embodiment. Hereinafter, the operation of the nonvolatile memory device 100 according to an embodiment of the inventive concept will be described with reference to the first memory block BLK 1. However, the inventive concept is not limited thereto. For example, the non-volatile memory device 100 may perform operations with respect to multiple memory blocks according to the flowchart of FIG. 4.

Referring to fig. 1 through 4, in operation S110, the nonvolatile memory device 100 may determine whether the first memory block BLK1 is a selected block. For example, the nonvolatile memory device 100 may receive an address ADDR from an external device (e.g., a memory controller or a host device), and may select at least one memory block of the plurality of memory blocks based on the received address ADDR. For example, the non-volatile memory device 100 may determine whether the first memory block BLK1 is a selected block based on an address ADDR received from an external device.

When the first memory block BLK1 is not a selected block (i.e., the first memory block BLK1 is an unselected block), the nonvolatile memory device 100 may disconnect the block selection circuit 121b such that the signal line connected to the first memory block BLK1 is floated in operation S120. For example, as described with reference to fig. 3, when the first memory block BLK1 is an unselected block, the block decoder 121a may output a block selection signal SEL _ BLK of "logic low". The block selection circuit 121b may float a signal line connected to the first memory block BLK1 in response to a block selection signal SEL _ BLK of "logic low". For example, the block selection circuit 121b may disconnect a signal line connected to the first memory block BLK1 from the line driver 121 d.

In operation S130, the non-volatile memory device 100 may provide the off-voltage VOFF to only some of the string selection lines SSL. For example, as described with reference to fig. 3, when the first memory block BLK1 is an unselected block, the block non-selection circuit 121c may be turned on in response to (e.g., activate) the block non-selection signal/SEL _ BLK, and thus, the off-voltage VOFF may be provided to only a portion of the string selection lines (e.g., SSL1 b). In this case, since the block unselect circuit 121c is connected only to the string selection line SSL1b of the string selection lines SSL1b and SSL1a, the off-voltage VOFF may be supplied only to the string selection line SSL1 b. In this case, the remaining string select lines (e.g., SSL1a) may be in a floating state.

When the first memory block BLK1 is a selected block, the nonvolatile memory device 100 may turn on the block selection circuit 121b such that the driving voltage is supplied to the signal line connected to the first memory block BLK1 in operation S140. In operation S150, the nonvolatile memory device 100 may control driving voltages supplied to a plurality of lines connected to the first memory block BLK 1.

For example, as described with reference to fig. 3, when the first memory block BLK1 is a selected block, the block decoder 121a may output a block selection signal SEL _ BLK of "logic high". The block selection circuit 121b may be turned on in response to a block selection signal SEL _ BLK of "logic high". Various driving voltages from the line driver 121d can be supplied to the corresponding signal line through the turned-on block selection circuit 121 b.

In one exemplary embodiment, the driving voltage may be variously changed according to the kind of operation of the nonvolatile memory device 100, whether a cell string is selected, whether a word line is selected, or an operating condition. In one exemplary embodiment, when the first memory block BLK1 is a selected block, the block non-selection circuit 121c may be turned off.

Fig. 5 is a block diagram illustrating in detail a configuration of a row decoder of fig. 3 according to an example embodiment. The schematic configuration of the row decoder 121 is described with reference to fig. 3 in which only one cell string CS11 is shown, but the configuration of the row decoder 121 will be described more fully with reference to fig. 5 in which a first memory block BLK1 is shown. For the sake of brief explanation and ease of description, the description of components unnecessary for the row decoder 121 is omitted, and thus additional description will be omitted to avoid redundancy.

Referring to fig. 1 to 5, the first memory block BLK1 may include a plurality of cell strings CS11, CS12, CS21, and CS 22. Each of the plurality of cell strings CS11, CS12, CS21, and CS22 may include string selection transistors SSTb and SSTa. The remaining components of the first memory block BLK1 are described with reference to fig. 2, and thus additional description will be omitted to avoid redundancy.

The row decoder 121 may include a block decoder 121a, a block selection circuit 121b, a block non-selection circuit 121c, and a line driver 121 d. The block decoder 121a and the line driver 121d are described above, and thus additional description will be omitted to avoid redundancy.

The block selection circuit 121b may be connected with various lines (e.g., SSL1a, SSL1b, SSL2a, and SSL2b) connected with the first memory block BLK 1; in response to the block selection signal SEL _ BLK, the block selection circuit 121b may supply the driving voltage from the line driver 121d to the corresponding signal line, or may block the driving voltage (or may float the corresponding signal line).

In response to the block unselect signal/SEL _ BLK, the block unselect circuit 121c may supply the off voltage VOFF to some of string select lines SSL1a, SSL1b, SSL2a, and SSL2b (e.g., SSL1b and SSL2b) connected to the first memory block BLK 1. For example, as shown in fig. 5, in response to the block unselect signal/SEL _ BLK, the block unselect circuit 121c may supply the off voltage VOFF to only some of the string selection lines SSL1b and SSL2b among the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b connected to the first memory block BLK 1.

In one exemplary embodiment, some of the string selection lines SSL1b and SSL2b connected with the block unselect circuit 121c may be string selection lines connected with string selection transistors that are located immediately adjacent to (e.g., without other intermediate cell transistors located therebetween) and at the same row among the string selection transistors. For example, as shown in fig. 5, the string selection transistors SSTa of the cell strings CS11 and CS12 are in the same row and are respectively connected to the string selection line SSL1a, and the string selection transistors SSTb of the cell strings CS11 and CS12 are in the same row and are respectively connected to the string selection line SSL1 b. In this case, the string selection transistor SSTb may be physically closer to the bit lines BL1 and BL2 than the string selection transistor SSTa. When the first memory block BLK1 is an unselected block, the off-voltage VOFF may be applied only to string select lines (e.g., SSL1b and SSL2b) connected to string select transistors (e.g., SSTb) immediately adjacent to the bit lines BL1 and BL 2.

In one exemplary embodiment, the block non-selection circuit 121c may not be connected with the remaining string selection lines (e.g., SSL1a and SSL2 a). For example, when the first memory block BLK1 is an unselected block, the off voltage VOFF may not be applied to the remaining string selection lines SSL1a and SSL2 a. This may mean that the remaining string select lines SSL1a and SSL2a are floated.

In one exemplary embodiment, as in the above description, the block non-selection circuit 121c may include a non-selection path transistor configured to provide the off-voltage VOFF to a specific string selection line (e.g., SSL1b and SSL2b) in response to the block non-selection signal/SEL _ BLK. In this case, the number of unselected path transistors ("2" in the embodiment of fig. 5) may be less than the number of the plurality of string selection lines SSL1a, SSL1b, SSL2a, and SSL2b ("4" in the embodiment of fig. 5) connected to the first memory block BLK 1.

As described above, according to an embodiment of the inventive concept, the block non-selection circuit 121c configured to provide the off-voltage VOFF for turning off the string selection transistors of the non-selected blocks may be connected only with some of the plurality of string selection lines connected to the non-selected blocks, and the block non-selection circuit 121c may be omitted with respect to the remaining string selection lines (i.e., the block non-selection circuit 121c may not be connected with the remaining string selection lines). Therefore, even if the number of string selection transistors included in the memory block or the number of string selection lines connected to the memory block increases, the number of unselected path transistors included in the block unselection circuit 121c does not increase, and thus, the overall size of the row decoder 121 can be reduced.

Fig. 6 is a diagram illustrating a Programming (PGM) bias of the row decoder of fig. 5 according to an example embodiment. In order to clearly describe embodiments of the inventive concept, a program operation will be described with reference to selected blocks and unselected blocks. Further, in order to prevent the inventive concept from becoming ambiguous, a description will be given only with respect to the offset string selection lines of the selected block and the unselected blocks, and a detailed description will be omitted with respect to the remaining signal lines (e.g., WL, DWL, GSL, and CSL).

Referring to fig. 5 and 6, a power supply voltage VCC or a ground voltage VSS may be applied to the first bit line BL1 and the second bit line BL 2. As described above, when the first memory block BLK1 is a selected block, the block selection circuit 121b may be turned on and the block non-selection circuit 121c may be turned off; accordingly, the driving voltages VSSL1a, VSSL1b, VSSL2a, and VSSL2b may be provided to the respective string selection lines SSL1a, SSL1b, SSL2a, and SSL2 b. In one exemplary embodiment, the driving voltages VSSL1a, VSSL1b, VSSL2a, and VSSL2b may be variously changed according to whether the cell strings CS11, CS12, CS21, and CS22 are selected. For example, when the cell strings CS11 and CS12 are selected strings and the cell strings CS21 and CS22 are unselected strings, each of the driving voltages VSSL1a and VSSL1b may be a high voltage (e.g., VCC) for turning on the string selection transistors SSTa and SSTb of the cell strings CS11 and CS12, and each of the driving voltages VSSL2a and VSSL2b may be a low voltage for turning off the string selection transistors SSTa and SSTb of the cell strings CS21 and CS 22. In one exemplary embodiment, the driving voltages VSSL2a and VSSL2b may have different levels from each other.

When the first memory block BLK1 is an unselected block, as described above, the block selection circuit 121b may be turned off, and the block unselected circuit 121c may be turned on; the off voltage VOFF may be applied to only some of the string selection lines SSL1b and SSL2b, and the remaining string selection lines SSL1a and SSL2a may be floated.

Fig. 7 is a diagram for describing an operation of the nonvolatile memory device of fig. 1 according to an example embodiment. The operation of the row decoder 121 associated with the selected block and the unselected block will be described with reference to fig. 7. For convenience of description, additional description associated with the above components will be omitted to avoid redundancy.

In one exemplary embodiment, each of the first and second memory blocks BLK1 and BLK2 shown in fig. 7 may include a plurality of cell strings arranged along three rows, and the cell strings in the same row may be connected to the same string selection line. However, the inventive concept is not limited thereto.

Referring to fig. 7, the row decoder 121 may include a first block selection circuit 121b-1, a second block selection circuit 121b-2, a first block non-selection circuit 121c-1, and a second block non-selection circuit 121 c-2. The first block select circuit 121b-1 may be connected with a plurality of string select lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, and SSL3b of the first memory block BLK 1. The first block unselected circuit 121c-1 may be connected with only some of the plurality of string select lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, and SSL3b (e.g., SSL1b, SSL2b, and SSL3b) of the first memory block BLK 1.

The second block selection circuit 121b-2 may be connected with a plurality of string selection lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, and SSL3b of the second memory block BLK 2. The second block non-selection circuit 121c-2 may be connected with only some of the plurality of string selection lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, and SSL3b (e.g., SSL1b, SSL2b, and SSL3b) of the second memory block BLK 2.

For the sake of brief explanation and convenient description, string selection lines connected to the first and second memory blocks BLK1 and BLK2 are denoted by the same reference numerals, but the inventive concept is not limited thereto. The string select line of the first memory block BLK1 may be physically separated from the string select line of the second memory block BLK 2.

For brief explanation, only string selection lines connected to the first and second memory blocks BLK1 and BLK2 are shown, but the inventive concept is not limited thereto. For example, the first memory block BLK1 and the first block selection circuit 121b-1, or the second memory block BLK2 and the second block selection circuit 121b-2 may also be connected to the above-described various lines (e.g., DWL, WL, and GSL).

For convenience of description, it is assumed that the first memory block BLK1 is a selected block and the second memory block BLK2 is an unselected block. In this case, as described above, the first block selection circuit 121b-1 connected to the first memory block BLK1 as the selected block is turned on. In this case, as shown in fig. 7, the respective voltages VSSL1b, VSSL1a, VSSL2b, VSSL2a, VSSL3b, and VSSL3a may be respectively supplied to string select lines (e.g., SSL1b, SSL1a, SSL2b, SSL2a, SSL3b, and SSL3a) of the first memory block BLK1 through the first block select circuit 121 b-1.

The second block selection circuit 121b-2 connected to the second memory block BLK2 as an unselected block is disconnected. In this case, as shown in fig. 7, the string selection lines SSL1b, SSL1a, SSL2b, SSL2a, SSL3b, and SSL3a of the second memory block BLK2 may be floated by the second block selection circuit 121b-2, or the respective voltages (e.g., VSSL1b, VSSL1a, VSSL2b, VSSL2a, VSSL3b, and VSSL3a) may not be provided or may be blocked by the second block selection circuit 121 b-2.

In this case, when the second block non-selection circuit 121c-2 connected to some of the string selection lines SSL1b, SSL2b, and SSL3b of the second memory block BLK2 as a non-selected block is turned on, the off voltage VOFF may be supplied to some of the string selection lines SSL1b, SSL2b, and SSL3b of the second memory block BLK 2. In this way, even if the second memory block BLK2, which is an unselected block, shares a bit line with the first memory block BLK1, the voltage of the shared bit line is not applied to the second memory block BLK 2.

Further, even though various voltages supplied to the first and second block selection circuits 121b-1 and 121b-2 are shared, no operation is performed in the second memory block BLK2 because the various voltages are blocked by the second block selection circuit 121 b-2.

As described above, according to an embodiment of the inventive concept, the nonvolatile memory device may apply the off-voltage VOFF to only some of the plurality of string selection lines connected to the unselected memory blocks, thereby preventing abnormal operation of the unselected memory blocks. Since the block non-selection circuit is connected to only some of the plurality of string selection lines, the size of the row decoder is reduced even if the number of string selection transistors or the number of string selection lines is increased.

In one exemplary embodiment, a string selection line to which an off-voltage is applied among a plurality of string selection lines connected to one memory block may be a string selection line connected to a string selection transistor next to a bit line among string selection transistors connected to the plurality of string selection lines. Alternatively, a string selection line to which an off-voltage is applied among a plurality of string selection lines connected to one memory block may be a string selection line connected to a string selection transistor located on an uppermost level from the substrate among string selection transistors connected to the plurality of string selection lines.

Fig. 8 is a diagram illustrating an example of the row decoder of fig. 1 according to an example embodiment. For the sake of brief explanation and for convenience of description, additional description will be omitted with respect to the same components to avoid redundancy.

Referring to fig. 1 and 8, the row decoder 121-3 may include a block decoder 121a-3, a block selection circuit 121b-3, a block non-selection circuit 121c-3, and a line driver 121 d-3. The block decoder 121a-3, the block selection circuit 121b-3, and the line driver 121d-3 are described above, and thus additional description will be omitted to avoid redundancy.

Unlike the above embodiments, in the embodiment of fig. 8, the cell string CS11-1 may include a plurality of string selection transistors SST. The plurality of string selection transistors SST may be connected with string selection lines SSL1a through SSL1k, respectively.

The block unselect circuit 121c-3 may be connected with some string select lines SSL1a to SSL1i among a plurality of string select lines SSL1a to SSL1k, where a is a positive integer and i is an integer greater than a and less than k. For example, when a memory block including the cell string CS11-1 is an unselected block, the block unselect circuit 121c-3 may be configured to provide the off voltage VOFF to some of the plurality of string selection lines SSL1a to SSL1k, SSL1a to SSL1 i.

In one exemplary embodiment, some of the string selection lines SSL1a through SSL1i connected with the block unselect circuit 121c may have a greater number than the remaining string selection lines SSL1i +1 through SSL1 k.

In fig. 8, a plurality of string selection transistors SST and a plurality of string selection lines SSL1a to SSL1k are shown as 1: 1 are correspondingly connected, but the inventive concept is not limited thereto. For example, the number of the plurality of string selection transistors SST may be "m" (here, m is a positive integer), and the number of the plurality of string selection lines SSL1a through SSL1k may be "k" (here, "k" is an integer less than "m"). For example, one string selection line may be shared by at least two or more string selection transistors.

Fig. 9A is a diagram illustrating an example of the row decoder of fig. 1 according to an example embodiment. Fig. 9B is a diagram for describing a configuration of the row decoder of fig. 9A according to an example embodiment. For the sake of brief explanation and ease of description, components unnecessary for describing the row decoder 121-4 are omitted, and thus additional description will be omitted to avoid redundancy.

Referring to fig. 1, 2, 9A and 9B, the row decoder 121-4 may include block decoders 121a-4, block selection circuits 121B-4, block non-selection circuits 121c-4, and line drivers 121 d-4. The block decoders 121a-4, the block selection circuits 121b-4, and the line drivers 121d-4 are described above, and thus additional description will be omitted to avoid redundancy.

The block non-selection circuit 121c-4 may be connected with a specific string selection line among the plurality of string selection lines SSL1a, SSL1b, SSL2a, and SSL2 b. For example, the block non-selection circuit 121c-4 may be connected with specific string selection lines SSL1a and SSL2b among the plurality of string selection lines SSL1a, SSL1b, SSL2a, and SSL2 b. In one exemplary embodiment, the specific string selection lines SSL1a and SSL2b connected with the block non-selection circuits 121c-4 may be determined based on the threshold voltages of the string selection transistors SSTa and SSTb.

In detail, as shown in fig. 9B, the string selection transistors connected with the string selection line SSL1B may form a first threshold voltage distribution Vth1, and the string selection transistors connected with the string selection line SSL1a may form a second threshold voltage distribution Vth 2. In this case, the second threshold voltage distribution Vth2 may be higher in level than the first threshold voltage distribution Vth 1. For example, the lower or upper limit value of the second threshold voltage distribution Vth2 may be higher than the lower or upper limit value of the first threshold voltage distribution Vth 1.

Likewise, as shown in fig. 9B, the string selection transistors connected with the string selection line SSL2B may form a third threshold voltage distribution Vth3, and the string selection transistors connected with the string selection line SSL2a may form a fourth threshold voltage distribution Vth 4. In this case, the third threshold voltage distribution Vth3 may be higher in level than the fourth threshold voltage distribution Vth 4. For example, the lower or upper limit value of the third threshold voltage distribution Vth3 may be higher than the lower or upper limit value of the fourth threshold voltage distribution Vth 4.

A string select line (e.g., SSL1a or SSL2B in the embodiment of fig. 9B) connected to the string select transistor having the highest threshold voltage distribution among string select lines (e.g., SSL1B and SSL1a, or SSL2B and SSL2a) located at the same row may be connected to the block non-select circuit 121 c-4.

In some examples, the threshold voltage of the string selection transistors connected to the string selection line connected to the block non-selection circuit 121c-4 may be greater than the threshold voltage of the string selection transistors connected to the remaining string selection lines connected to the block non-selection circuit 121 c-4.

In one exemplary embodiment, the string selection transistor connected to the string selection line connected to the block unselect circuit 121c-4 may be programmed to have a threshold voltage of a reference value or higher.

Fig. 10 is a circuit diagram illustrating a third memory block according to an embodiment of the inventive concept. For convenience of description, additional description associated with the above components will be omitted to avoid redundancy. In one exemplary embodiment, the third memory block BLK3 of fig. 10 is an exemplary structure of a three-dimensional memory block, and embodiments of the inventive concept are not limited thereto. In one exemplary embodiment, each memory block included in the memory cell array may have the structure of the first memory block BLK1 of fig. 2 or may have the structure of the third memory block BLK3 of fig. 10.

Referring to fig. 10, the third memory block BLK3 may include a plurality of cell strings CS11, CS12, CS21, and CS 22. The plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged in a row direction and a column direction. Cell strings belonging to the same column may be connected to the same bit line. For example, the cell strings CS11 and CS21 may be connected with the first bit line BL1, and the cell strings CS12 and CS22 may be connected with the second bit line BL 2.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22 may include a plurality of cell transistors. In each cell string, a plurality of cell transistors may be connected in series between a corresponding bit line and the common source line CSL. In one exemplary embodiment, in each cell string, the plurality of cell transistors may include string selection transistors SSTa and SSTb, memory cells MC1 through MC4, dummy memory cells DMC1 through DMC3, ground selection transistors GSTa and GSTb, and erase control transistors ECT1 and ECT 2. The cell transistors in each cell string may be respectively connected with corresponding lines (e.g., SSL1a, SSL1b, SSL2a, SSL2b, DWL1 to DWL3, WL1 to WL4, GSL1a, GSL1b, GSL2a, GSL2b, ECL1, and ECL 2). The string selection transistors SSTa and SSTb, the memory cells MC1 to MC4, the dummy memory cells DMC1 and DMC2, and the ground selection transistors GSTa and GSTb are described with reference to fig. 2, and thus additional description will be omitted to avoid redundancy.

Unlike the first memory block BLK1 of fig. 2, the third memory block BLK3 of fig. 10 may further include erase control transistors ECT1 and ECT2 and a third dummy memory cell DMC 3.

The first erase control transistor ECT1 may be interposed between the serially connected ground selection transistors GSTa and GSTb and the common source line CSL, and may be connected with the first erase control line ECL 1. The second erase control transistor ECT2 may be interposed between the series-connected string selection transistors SSTa and SSTb and the bit line BL1 or BL2, and may be connected with the second erase control line ECL 2. The first erase control transistor ECT1 and the second erase control transistor ECT2 may be controlled by a first erase control line ECL1 and a second erase control line ECL2, respectively. In one example embodiment, the first erase control transistor ECT1 and the second erase control transistor ECT2 may be configured to control a Gate Induced Drain Leakage (GIDL) current when the third memory block BLK3 is erased.

The third dummy memory cell DMC3 may be located between the memory cells MC1 to MC4 stacked in a direction perpendicular to the substrate, and may be connected with the third dummy word line DWL 3. For example, a third dummy memory cell DMC3 may be inserted between second memory cell MC2 and third memory cell MC 3. In one exemplary embodiment, when the third memory block BLK3 has a multi-layer stack structure, the third dummy memory cell DMC3 may be formed in a connection layer between a lower structure (e.g., a structure including ECT1, GSTa, GSTb, DMC1, MC1, and MC 2) and an upper structure (e.g., a structure including ECT2, SSTa, SSTb, DMC2, MC4, and MC 3).

In an exemplary embodiment, the third memory block BLK3 of fig. 10 is exemplary, and the inventive concept is not limited thereto. For example, the third memory block BLK3 may not include at least one of the components shown in fig. 10. Optionally, the third memory block BLK3 may also include additional components. For example, the third memory block BLK3 shown in fig. 10 is exemplary, and it is understood that the structure of the memory block may be changed or modified differently.

Fig. 11A to 11D are diagrams illustrating a row decoder according to an embodiment of the inventive concept. For convenience of description, the configuration of the row decoders 221-1, 221-2, 221-3, and 221-4 will be described with reference to the third memory block BLK3 of fig. 10, and additional descriptions associated with the above-described components will be omitted to avoid redundancy. In fig. 11A to 11D, lines connected to the block non-selection circuit among various lines connected to the third memory block BLK3 are shown by solid lines for clarity of the drawings.

As shown in fig. 11A through 11D, the row decoder 221-1, 221-2, 221-3, or 221-4 may be connected to the third memory block BLK3 through various lines. The row decoder 221-1, 221-2, 221-3, or 221-4 may include a block decoder 221a-1, 221a-2, 221a-3, or 221a-4, a block selection circuit 221b-1, 221b-2, 221b-3, or 221b-4, a block non-selection circuit 221c-1, 221c-2, 221c-3, or 221c-4, and a line driver 221d-1, 221d-2, 221d-3, or 221 d-4. The block decoders 221a-1, 221a-2, 221a-3, and 221a-4, the block selection circuits 221b-1, 221b-2, 221b-3, and 221b-4, and the line drivers 221d-1, 221d-2, 221d-3, and 221d-4 are similar to the above-described components, and thus additional description will be omitted to avoid redundancy.

As shown in fig. 11A, the block non-selection circuit 221c-1 may be connected with the second erase control line ECL2, and may be configured to supply the off voltage VOFF to the second erase control line ECL2 when the third memory block BLK3 is a non-selected block. For example, unlike the above embodiment, the block unselect circuit 221c-1 of fig. 11A may supply the off-voltage VOFF to the second erase control line ECL2 located above the string selection line instead of the string selection line. For example, the block non-selection circuit 221c-1 may not be connected to any string selection line of the third memory block BLK 3. In one example embodiment, the second erase control line ECL2 may indicate a line commonly connected to cell transistors immediately adjacent to the bit lines BL1 and BL2 (i.e., the second erase control transistor ECT 2).

As shown in fig. 11B, the block unselected circuit 221c-2 may be connected to the second dummy word line DWL2, and may be configured to provide the off voltage VOFF to the second dummy word line DWL2 when the third memory block BLK3 is an unselected block. For example, unlike the above embodiments, the block non-selection circuit 221c-2 of fig. 11B may supply the off-voltage VOFF to the second dummy word line DWL2 interposed between the string selection line and the word line, instead of the string selection line.

As shown in fig. 11C, the block unselected circuit 221C-3 may be connected to the third dummy word line DWL3, and may be configured to provide the off voltage VOFF to the third dummy word line DWL3 when the third memory block BLK3 is an unselected block. For example, unlike the above embodiments, the block unselected circuit 221C-3 of fig. 11C may provide the off-voltage VOFF to the third dummy word line DWL3 interposed between the word lines instead of the string select line.

As shown in fig. 11D, the block non-selection circuit 221c-4 may be connected with the first erase control line ECL1, and may be configured to supply the off voltage VOFF to the first erase control line ECL1 when the third memory block BLK3 is a non-selected block. For example, unlike the above embodiment, the block non-selection circuit 221c-4 of fig. 11D may supply the off-voltage VOFF to the first erase control line ECL1 located below the ground selection line instead of the string selection line. In one example embodiment, the first erase control line ECL1 may indicate a line commonly connected to cell transistors (i.e., the first erase control transistor ECT1) immediately adjacent to the common source line CSL.

As described above, the row decoder of the nonvolatile memory device according to the embodiment of the inventive concept may supply the off-voltage VOFF to only a portion of various signal lines connected to unselected blocks according to various ways of implementing the memory cell array. In this case, the number of transistors of the block non-selection circuit included in the row decoder can be reduced, thereby reducing the size of the nonvolatile memory device. This enables the nonvolatile memory device to be realized in a reduced size and at a reduced cost.

Fig. 12 is a block diagram illustrating a memory system including a nonvolatile memory device according to an embodiment of the inventive concepts. Referring to fig. 12, a storage system 1000 may include a host 1100 and a storage apparatus 1200.

The storage apparatus 1200 exchanges a signal SIG with the host 1100 through the signal connector 1201 and is supplied with power PWR through the power connector 1202. The storage apparatus 1200 includes a Solid State Drive (SSD) controller 1210, a plurality of nonvolatile memories (NVM)1221 to 122n, an auxiliary power source 1230, and a buffer memory 1240. In one exemplary embodiment, each of the nonvolatile memories 1221 to 122n may include any one of the nonvolatile memory devices described with reference to fig. 1 to 8, 9A, 9B, 10, and 11A to 11D.

The SSD controller 1210 may control the nonvolatile memories 1221 to 122n in response to a signal SIG received from the host 1100. The plurality of nonvolatile memories 1221 to 122n may operate under the control of the SSD controller 1210. The secondary power source 1230 is connected to the host 1100 through the power connector 1202. The auxiliary power source 1230 may be charged by power PWR from the host 1100. The auxiliary power source 1230 may supply power to the storage device 1200 when the power PWR is not smoothly supplied from the host 1100.

According to an embodiment of the inventive concept, the size of a row decoder including a block non-selection circuit may be reduced by connecting the block non-selection circuit to only some of the string selection lines of the memory block. Accordingly, a non-volatile memory device having reduced cost is provided.

Further, by connecting the block non-selection circuit with only some of the various signal lines (e.g., erase control lines, dummy word lines, etc.) connected with the memory block, the size of the row decoder including the block non-selection circuit can be reduced. Accordingly, a non-volatile memory device having reduced cost is provided.

Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.