阅读说明：本技术 一种动态反馈读出放大电路 (Dynamic feedback reading amplifying circuit ) 是由 王韬 于 2019-03-27 设计创作，主要内容包括：本发明实施例公开了一种动态反馈读出放大电路,包括：第一负载电路,第二负载电路,反馈电路,以及比较放大电路；第一负载电路的输入端耦接至电源,第一负载电路与第二负载电路耦接,第一负载电路适于转换流经第一负载电路的参考电流为参考电压,并通过第一负载电路的输出端输出参考电压；第二负载电路的输入端耦接至电源,第二负载电路适于转换流经第二负载电路的数据电流为数据电压,并通过第二负载电路的输出端输出所述数据电压；反馈电路与第二负载电路耦接,反馈电路接入第二负载电路的输出端,反馈电路适于输出与数据电压的变化趋势正相关的反馈信号至第二负载电路号。本发明实施例中的技术方案可以提升读出放大电路的数据读取速度。(The embodiment of the invention discloses a dynamic feedback reading amplifying circuit, which comprises: the circuit comprises a first load circuit, a second load circuit, a feedback circuit and a comparison amplifying circuit; the input end of the first load circuit is coupled to a power supply, the first load circuit is coupled with the second load circuit, and the first load circuit is suitable for converting reference current flowing through the first load circuit into reference voltage and outputting the reference voltage through the output end of the first load circuit; the input end of the second load circuit is coupled to the power supply, and the second load circuit is suitable for converting the data current flowing through the second load circuit into data voltage and outputting the data voltage through the output end of the second load circuit; the feedback circuit is coupled with the second load circuit, the feedback circuit is connected to the output end of the second load circuit, and the feedback circuit is suitable for outputting a feedback signal positively correlated with the variation trend of the data voltage to the second load circuit. The technical scheme in the embodiment of the invention can improve the data reading speed of the reading amplifying circuit.)

1. A dynamic feedback sense amplifier circuit, comprising: the circuit comprises a first load circuit, a second load circuit, a feedback circuit and a comparison amplifying circuit; wherein the content of the first and second substances,

the input end of the first load circuit is coupled to a power supply, the first load circuit is coupled to the second load circuit, and the first load circuit is suitable for converting a reference current flowing through the first load circuit into a reference voltage and outputting the reference voltage through the output end of the first load circuit;

an input terminal of the second load circuit is coupled to the power supply, and the second load circuit is adapted to convert a data current flowing through the second load circuit into a data voltage and output the data voltage through an output terminal of the second load circuit;

the feedback circuit is coupled with the second load circuit, the feedback circuit is connected to the output end of the second load circuit, and the feedback circuit is suitable for outputting a feedback signal positively correlated with the variation trend of the data voltage to the second load circuit;

the comparison amplifying circuit is coupled to the first load circuit and the second load circuit, and the comparison amplifying circuit is adapted to compare the reference voltage and the data voltage to output a comparison result signal.

2. The dynamic feedback sense amplification circuit of claim 1, wherein the feedback circuit comprises a capacitive circuit having an input coupled to the output of the second load circuit and an output coupled to the control of the second load circuit, the capacitive circuit adapted to couple the feedback signal to the second load circuit.

3. The dynamic feedback sense amplification circuit of claim 2, wherein the first load circuit comprises a first NMOS transistor and the second load circuit comprises a second NMOS transistor;

the drain electrode of the first NMOS tube is coupled to a power supply, the grid electrode of the first NMOS tube is coupled to the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube is coupled to the grid electrode of the first NMOS tube and the comparison and amplification circuit, and the first NMOS tube outputs the reference voltage;

the drain electrode of the second NMOS tube is coupled to a power supply, the source electrode of the second NMOS tube is coupled to the comparison amplification circuit, and the second NMOS tube outputs the data voltage.

4. The dynamic feedback sense amplification circuit of claim 2, wherein the capacitance circuit comprises at least one capacitor.

5. The dynamic feedback sense amplifier circuit of claim 2, wherein the feedback circuit further comprises an inverter circuit, an input of the inverter circuit is coupled to the output of the second load circuit, an output of the inverter circuit is coupled to the input of the capacitor circuit, and the inverter circuit is adapted to invert the data voltage and output the inverted data voltage.

6. The dynamic feedback sense amplification circuit of claim 5, wherein the inverting circuit comprises an inverter.

7. The dynamic feedback sense amplification circuit of claim 5, wherein the first load circuit comprises a first PMOS transistor and the second load circuit comprises a second PMOS transistor;

the source electrode of the first PMOS tube is coupled to a power supply, the grid electrode of the first PMOS tube is coupled to the grid electrode of the second PMOS tube, the drain electrode of the first PMOS tube is coupled to the grid electrode of the first PMOS tube and the comparison amplification circuit, and the first PMOS tube outputs the reference voltage;

the source electrode of the second PMOS tube is coupled to a power supply, the drain electrode of the second PMOS tube is coupled to the comparison amplification circuit, and the second PMOS tube outputs the data voltage.

8. The dynamic feedback sense amplifier circuit of claim 1, wherein the feedback circuit outputs a feedback signal for boosting the data voltage if the trend of the data voltage is a voltage increase, and outputs a feedback signal for decreasing the data voltage if the trend of the data voltage is a voltage decrease.

9. The dynamic feedback sense amplification circuit of claim 1, wherein the compare amplification circuit comprises a voltage compare amplifier having one input coupled to the first load circuit and a second input coupled to the second load circuit, the voltage compare circuit adapted to compare the reference voltage and the data voltage and output the comparison result signal.

10. The dynamic feedback sense amplification circuit of claim 1, further comprising: a clamp circuit, a bit line selection circuit, at least one data cell circuit and at least one reference cell circuit;

the clamp circuit is coupled with the first load circuit and the second load circuit, and is suitable for clamping bit line voltages of the data unit circuit and the reference unit circuit;

the bit line selection circuit is coupled to the clamp circuit, the data cell circuit, and the reference cell circuit, respectively, and is adapted to select the data cell circuit and the reference cell circuit to be read;

the data cell circuit is adapted to store dynamic data;

the reference cell circuit is adapted to store reference data for reference by the dynamic data.

11. The dynamic feedback sense amplification circuit of claim 10, wherein the data cell circuit is in circuit configuration with the reference cell circuit.

Technical Field

The invention relates to the field of circuits, in particular to a dynamic feedback reading amplifying circuit.

Background

Magnetic Random Access Memory (MRAM) is an emerging non-volatile Memory technology. It has high read-write speed and high integration and can be written repeatedly.

When data is read from the MRAM cell, the data cell and the reference cell are simultaneously applied with the same current (or voltage) to detect their corresponding voltages (or currents), and then compared to determine the information stored in the data cell.

How to increase the data reading speed of the sense amplifier circuit becomes an urgent problem to be solved.

Disclosure of Invention

The invention aims to improve the data reading speed of the reading amplifying circuit.

To solve the above problems, the present invention provides a dynamic feedback sense amplifier circuit, comprising: the circuit comprises a first load circuit, a second load circuit, a feedback circuit and a comparison amplifying circuit; wherein an input terminal of the first load circuit is coupled to a power supply, the first load circuit is coupled to the second load circuit, and the first load circuit is adapted to convert a reference current flowing through the first load circuit into a reference voltage and output the reference voltage through an output terminal of the first load circuit; an input terminal of the second load circuit is coupled to the power supply, and the second load circuit is adapted to convert a data current flowing through the second load circuit into a data voltage and output the data voltage through an output terminal of the second load circuit; the feedback circuit is coupled with the second load circuit, the feedback circuit is connected to the output end of the second load circuit, and the feedback circuit is suitable for outputting a feedback signal positively correlated with the variation trend of the data voltage to the second load circuit; the comparison amplifying circuit is coupled to the first load circuit and the second load circuit, and the comparison amplifying circuit is adapted to compare the reference voltage and the data voltage to output a comparison result signal.

Optionally, the feedback circuit includes a capacitor circuit, an input terminal of the capacitor circuit is coupled to the output terminal of the second load circuit, an output terminal of the capacitor circuit is coupled to the control terminal of the second load circuit, and the capacitor circuit is adapted to couple the feedback signal to the second load circuit.

Optionally, the first load circuit includes a first NMOS transistor, and the second load circuit includes a second NMOS transistor; the drain electrode of the first NMOS tube is coupled to a power supply, the grid electrode of the first NMOS tube is coupled to the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube is coupled to the grid electrode of the first NMOS tube and the comparison and amplification circuit, and the first NMOS tube outputs the reference voltage; the drain electrode of the second NMOS tube is coupled to a power supply, the source electrode of the second NMOS tube is coupled to the comparison amplification circuit, and the second NMOS tube outputs the data voltage.

Optionally, the capacitance circuit comprises at least one capacitor.

Optionally, the feedback circuit further includes an inverter circuit, an input terminal of the inverter circuit is coupled to the output terminal of the second load circuit, an output terminal of the inverter circuit is coupled to the input terminal of the capacitor circuit, and the inverter circuit is adapted to invert the accessed data voltage and output the inverted data voltage.

Optionally, the inverting circuit comprises an inverter.

Optionally, the first load circuit includes a first PMOS transistor, and the second load circuit includes a second PMOS transistor; the source electrode of the first PMOS tube is coupled to a power supply, the grid electrode of the first PMOS tube is coupled to the grid electrode of the second PMOS tube, the drain electrode of the first PMOS tube is coupled to the grid electrode of the first PMOS tube and the comparison amplification circuit, and the first PMOS tube outputs the reference voltage; the source electrode of the second PMOS tube is coupled to a power supply, the drain electrode of the second PMOS tube is coupled to the comparison amplification circuit, and the second PMOS tube outputs the data voltage.

Optionally, if the trend of the data voltage is voltage increase, the feedback circuit outputs a feedback signal for increasing the data voltage, and if the trend of the data voltage is voltage decrease, the feedback circuit outputs a feedback signal for decreasing the data voltage.

Optionally, the comparison amplifying circuit includes a voltage comparison amplifier, one input terminal of the voltage comparison amplifier is coupled to the first load circuit, a second input terminal of the voltage comparison amplifier is coupled to the second load circuit, and the voltage comparison circuit is adapted to compare the reference voltage and the data voltage and output the comparison result signal.

Optionally, the dynamic feedback sense amplifier circuit further includes: a clamp circuit, a bit line selection circuit, at least one data cell circuit and at least one reference cell circuit; the clamp circuit is coupled with the first load circuit and the second load circuit, and is suitable for clamping bit line voltages of the data unit circuit and the reference unit circuit; the bit line selection circuit is coupled to the clamp circuit, the data cell circuit, and the reference cell circuit, respectively, and is adapted to select the data cell circuit and the reference cell circuit to be read; the data cell circuit is adapted to store dynamic data; the reference cell circuit is adapted to store reference data for reference by the dynamic data.

Optionally, the data unit circuit and the reference unit circuit have the same circuit structure.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in an embodiment of the present invention, a dynamic feedback sense amplifier circuit includes a first load circuit, a second load circuit, a feedback circuit, and a comparison amplifier circuit, wherein the first load circuit is adapted to generate a reference voltage, the second load circuit is adapted to generate a data voltage, the feedback circuit is adapted to be connected to an output terminal of the second load circuit, and output a feedback signal positively correlated to a variation trend of the data voltage to the second load circuit, and the comparison circuit is adapted to compare the reference voltage and the data voltage. The feedback circuit outputs a feedback signal positively correlated with the variation trend of the data voltage to the second load circuit, and the feedback signal can control the second load circuit to generate the data voltage in a direction positively correlated with the variation trend of the data voltage, so that the increase speed of the difference between the data voltage and the reference voltage can be increased, and the reading speed of the readout amplifying circuit can be increased.

Further, the feedback circuit comprises a capacitor circuit, the data voltage comprises a direct current voltage and an alternating current voltage, the direct current voltage can be isolated through the capacitor circuit, the alternating current voltage is coupled to the second load circuit, the direct current voltage of the data voltage can be prevented from being loaded on the second load circuit, the direct current voltage can be prevented from influencing the current passing through the load circuit, and therefore the accuracy of the circuit can be improved.

Drawings

FIG. 1 is a schematic diagram of a sense amplifier circuit;

FIG. 2 is a schematic diagram of a dynamic feedback sense amplifier circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a dynamic feedback sense amplifier circuit according to an embodiment of the invention;

FIG. 4 is a schematic diagram of a dynamic feedback sense amplifier circuit according to another embodiment of the present invention

Detailed Description

As can be seen from the background art, how to increase the data reading speed of the sense amplifier circuit is an urgent problem to be solved.

In an MRAM, data information can be stored by changing the resistance state of an MRAM memory cell circuit so that it can be switched between a high resistance state RH and a low resistance state RL, e.g., RH for a data bit "1" and RL for a data bit "0", or vice versa.

A memory cell circuit may be composed of a data storage circuit which may have both resistance states of RL and RH and an access control circuit which may include an NMOS word line select transistor, and such a circuit structure of the memory cell circuit may be referred to as a 1R1T structure.

As shown in FIG. 1, in an MRAM, an MRAM memory may include two memory cell circuits, one being a data cell circuit 14 whose resistance state is variable, which may be denoted as R_dataFor storing binary data; the other is a reference cell circuit 15, whose resistance state is known and can be denoted as R_refFor reading data, a decision reference is provided to the data cell circuit 14.

When reading data, the data cell circuit 14 and the reference cell circuit 15 may be detected by applying the same current to them at the same time, or by applying the same voltage to them, and then by comparing them with the comparison amplifier 16, the data information stored in the data cell circuit 14 is judged.

Specifically, the load circuit 11 may be a PMOS transistor (load resistance value R)_load) Data current I of data unit circuit 14_dataAnd a reference current I of the reference cell circuit 15_refConverted into a data voltage V_data＝I_data×R_loadAnd a reference voltage V_ref＝I_ref×R_loadAnd (6) outputting.

For the sense amplifier circuit shown in fig. 1, the gate of the first PMOS transistor P0 and the gate of the second PMOS transistor P1 of the load circuit 11 are coupled to pass the data current I when data reading is not performed_dataAnd a reference current I_refSince the first PMOS transistor P0 and the second PMOS transistor P1 are identical, the data voltage V converted by the load circuit 11 is equal to each other_dataAnd a reference voltage V_refAre equal.

When data is read, if the resistance R of the data unit circuit 14_dataIn the low resistance state RL, the data voltage V of the access point of the amplifier 16 and the load circuit 11 is compared_dataWill be due to the resistance R of the low resistance state RL_dataPulled low, data voltage V, compared to the state without data read_dataReduced and showing a reduced tendency to be detected by the comparison amplifier 16Measure the data voltage V of the data cell circuit 14_dataIs less than reference voltage V of reference cell circuit 15_refThe decision data unit circuit 14 stores a data bit of "0".

If the resistance R of the data cell circuit 14_dataIn a high impedance state RH, the data voltage V connected to the access point of the comparison amplifier 16 and the load circuit 11 is compared_dataWill be due to the resistance R of the high-resistance state RH_dataPulled high, data voltage V, compared to the state without data read_dataIncreasing, presenting an increasing trend. The data voltage V of the data cell circuit 14 can be detected by the comparison amplifier 16_dataGreater than reference voltage V of reference cell circuit 15_refThe decision data unit circuit 14 stores a data bit of "1", or vice versa.

In the sense amplifier circuit shown in fig. 1, a bit line selection circuit 13 selects a data cell circuit 14 and a reference cell circuit 15 to be read, and a clamp circuit 12 is used to clamp bit line voltages of the data cell circuit 14 and the reference cell circuit 15.

Due to the data voltage V_dataAnd a reference voltage V_refThe difference between the two is small, so that the judgment window of the sense amplifying circuit is small, and the read time is needed to obtain the proper judgment margin, so that the time needed by the sense amplifying circuit to read data is long.

In an embodiment of the present invention, a dynamic feedback sense amplifier circuit includes a first load circuit, a second load circuit, a feedback circuit, and a comparison amplifier circuit, wherein the first load circuit is adapted to generate a reference voltage, the second load circuit is adapted to generate a data voltage, the feedback circuit is adapted to be connected to an output terminal of the second load circuit, and output a feedback signal positively correlated to a variation trend of the data voltage to the second load circuit, and the comparison circuit is adapted to compare the reference voltage and the data voltage. The feedback circuit outputs a feedback signal positively correlated with the variation trend of the data voltage to the second load circuit, and the feedback signal can control the second load circuit to generate the data voltage in a direction positively correlated with the variation trend of the data voltage, so that the increase speed of the difference between the data voltage and the reference voltage can be increased, and the reading speed of the readout amplifying circuit can be increased.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 shows a schematic structural diagram of a dynamic feedback sense amplifying circuit in an embodiment of the present invention, and in a specific implementation, the dynamic feedback sense amplifying circuit 20 may include: a first load circuit 21, a second load circuit 22, a feedback circuit 23, and a comparison amplification circuit 24.

Wherein an input terminal of the first load circuit 21 is coupled to a power supply, the first load circuit 21 is coupled to the second load circuit 22, and the first load circuit 21 is adapted to convert a reference current flowing through the first load circuit 21 into a reference voltage and output the reference voltage through an output terminal of the first load circuit 21;

an input terminal of the second load circuit 22 is coupled to the power supply, and the second load circuit 22 is adapted to convert the data current flowing through the second load circuit 22 into a data voltage and output the data voltage through an output terminal of the second load circuit 22;

the feedback circuit 23 is coupled to the second load circuit 22, and the feedback circuit 23 is adapted to be connected to an output end of the second load circuit 22 and output a feedback signal positively correlated to the variation trend of the data voltage to the second load circuit 22;

the comparing and amplifying circuit 24 is coupled to the first load circuit 21 and the second load circuit 22, respectively, and the comparing and amplifying circuit 24 is adapted to compare the reference voltage and the data voltage to output a comparison result signal.

The term "coupled" in the embodiments of the present invention refers to direct connection or indirect connection, and the meaning of "coupled" in the following is consistent and will not be described one by one.

In a specific implementation, the output terminal of the first load circuit 21 is coupled to the control terminal of the first load circuit 21 and the control terminal of the second load circuit 22, so as to control the magnitude of the reference current flowing through the first load circuit 21 and the magnitude of the data current flowing through the second load circuit 22 by the reference voltage.

It will be understood by those skilled in the art that "first" and "second" in the embodiments of the present invention are merely for convenience of description and do not represent specific limitations on the implementation thereof.

As described above, the variation tendency of the data voltage is related to the resistance state of the data cell circuit of the sense amplifier circuit. If the data cell circuit is a high resistance and the variation trend of the data voltage is a voltage increase, the positive correlation with the variation trend of the data voltage may be related to the voltage increase trend of the data voltage; if the data unit circuit is a low resistance and the variation trend of the data voltage is a voltage decrease, the positive correlation with the variation trend of the data voltage may be related to a trend of a voltage decrease of the data voltage.

In a specific implementation, if the trend of the data voltage is a voltage increase, the feedback circuit 23 outputs a feedback signal for increasing the data voltage, and if the trend of the data voltage is a voltage decrease, the feedback circuit 23 outputs a feedback signal for decreasing the data voltage. The following detailed description is given with reference to specific embodiments.

With continued reference to fig. 2, in an implementation, the feedback circuit 23 may include a capacitor circuit 231, an input terminal of the capacitor circuit 231 is coupled to the output terminal of the second load circuit 22, an output terminal of the capacitor circuit 231 is coupled to the control terminal of the second load circuit 22, and the capacitor circuit 231 is adapted to couple the feedback signal to the second load circuit 22.

In a specific implementation, the data voltage may include a dc voltage and an ac voltage, and the capacitor circuit 231 may isolate the dc voltage, generate a feedback signal including the ac voltage, and couple the feedback signal to the second load circuit 231.

Fig. 3 shows a schematic structure of a dynamic feedback sense amplifier circuit in an embodiment of the present invention, in which the first load circuit 22 may include a first NMOS transistor MN0, and the second load circuit 23 may include a second NMOS transistor MN 1.

In a specific implementation, the drain of the first NMOS transistor MN0 is coupled to a power supply VDD, the gate of the first NMOS transistor MN0 is coupled to the gate of the second NMOS transistor MN1, the source of the first NMOS transistor MN0 is coupled to the gate of the first NMOS transistor MN0 and the comparing and amplifying circuit 24, and the first NMOS transistor MN0 outputs the reference voltage V_ref. A drain of the second NMOS transistor MN1 is coupled to a power supply VDD, a source of the second NMOS transistor MN1 is coupled to the comparison amplifier circuit 24, and the second NMOS transistor MN1 outputs the data voltage V_data。

In a specific implementation, the capacitor circuit 231 may include at least one capacitor C1, the capacitor C1 is adapted to isolate a dc voltage of the data voltages, and couple the ac voltage to the gate of the second NMOS transistor MN1 to adjust the data current I passed by the second NMOS transistor MN1 according to the ac voltage_dataThe size of (2).

The direct current voltage is isolated through the capacitor, the alternating current voltage is coupled to the grid electrode of the second NMOS tube, and the direct current voltage of the data voltage is prevented from being loaded on the grid electrode of the second NMOS tube and influencing the current passing through the second NMOS tube.

With continued reference to fig. 2, in another specific implementation of the present invention, the feedback circuit 23 may further include an inverting circuit 232, an input terminal of the inverting circuit 232 is coupled to the output terminal of the second load circuit 22, an output terminal of the inverting circuit 232 is coupled to an input terminal of the capacitor circuit 231, and the inverting circuit 232 is adapted to invert the accessed data voltage and output the inverted data voltage.

Fig. 4 is a schematic diagram of a dynamic feedback sense amplifier circuit according to another embodiment of the present invention. In a specific implementation, the first load circuit 21 may include a first PMOS transistor P0, and the second load circuit 22 may include a second PMOS transistor P1.

In specific implementations, the first PA source of the MOS transistor P0 is coupled to a power supply VDD, a gate of the first PMOS transistor P0 is coupled to a gate of the second PMOS transistor P1, a drain of the first PMOS transistor P0 is coupled to a gate of the first PMOS transistor P0 and the comparison and amplification circuit 24, the first PMOS transistor P0 outputs the reference voltage V_ref。

A source of the second PMOS transistor P1 is coupled to a power VDD, a drain of the second PMOS transistor P1 is coupled to the comparison and amplification circuit 24, and the second PMOS transistor P1 outputs the data voltage V_data。

In a specific implementation, the inverter circuit 232 may include an inverter I1, an input terminal of the inverter I1 is coupled to the drain of the second PMOS transistor P1, and the inverter I1 is adapted to receive the data voltage V_dataInverting and outputting the inverted data voltage V_dataTo the capacitor C1.

Capacitor C1 isolates inverted data voltage V_dataThe ac voltage is coupled to the gate of the second PMOS transistor P1 to control the data current I passing through the second PMOS transistor P1_dataThe size of (2).

It will be understood by those skilled in the art that the above "capacitor" and "inverter" are merely examples, and in other embodiments, the "capacitor" may also be a capacitive device, and the "inverter" may also be a device with an inverting function, which is not limited thereto.

With continued reference to fig. 2, in a specific implementation, the dynamic feedback sense amplifier circuit 20 may further include: a clamp circuit 25, a bit line select circuit 26, at least one reference cell circuit 27, and at least one data cell circuit 28.

In a specific implementation, the clamp circuit 25 is coupled to the first load circuit 21 and the second load circuit 22, and the clamp circuit 25 is adapted to clamp the bit line voltages of the data cell circuit 27 and the reference cell circuit 28.

Referring to fig. 3 in combination, in a specific implementation, the clamp circuit 25 may include a third NMOS transistor N0 and a fourth NMOS transistor N1. The drain electrode of the third NMOS transistor N0 and the source electrode of the first NMOS transistor MN0A gate of the third NMOS transistor N0 is coupled to a clamp control signal V_{BL_clamp}A drain of the fourth NMOS transistor N1 is coupled to a source of the second NMOS transistor MN1, and a gate of the fourth NMOS transistor N1 is adapted to be coupled to a clamp control signal V_{BL_clamp}The third NMOS transistor N0 and the fourth NMOS transistor N1 are adapted to clamp the same control signal V_{BL_clamp}The bit line voltages of the reference cell circuit 27 and the data cell circuit 28 are clamped to avoid the reference cell circuit 27 and the data cell circuit 28 from being damaged due to the excessive bit line voltages caused by the misoperation.

In a specific implementation, the bit line selection circuit 26 is coupled to the clamp circuit 25, the reference cell circuit 27, and the data cell circuit 28, respectively, and the bit line selection circuit 26 is adapted to select the reference cell circuit 27 and the data cell circuit 28 to be read.

With continued reference to FIG. 3, in particular implementations, the bit line select circuit 26 may include a first bit line select switch YMUX_refAnd a second bit line selection switch YMUX_cellThe first bit line selection switch YMUX_refIs coupled to a source of the third NMOS transistor N0, and the first bit line selection switch YMUX_refIs coupled to the reference cell circuit 27, the first bit line selection switch YMUX_refFor selecting a reference cell circuit 27 to be read, the second bit line select switch YMUX_cellAnd the first connection terminal of the second bit line selection switch is coupled to the source of the fourth NMOS transistor N1, and the second bit line selection switch YMUX_cellIs coupled to the data cell circuit 28, and the second bit line selection switch YMUX_cellFor selecting the data cell circuit 28 to be read.

In a specific implementation, the data cell circuit 28 is adapted to store dynamic data and the reference cell circuit 27 is adapted to store reference data for reference of the dynamic data. The data cell circuit 28 corresponds to the circuit structure of the reference cell circuit 27.

In a specific implementation, the reference cell circuit 27 may include a resistor R_refAnd a fifth NMOS tube Cell_ref. The resistor R_refIs coupled to the first bit line selection switch YMUX_refSaid resistance R_refAdapted to store reference data. The fifth NMOS tube Cell_refIs coupled to the resistor R_refThe fifth NMOS tube Cell_refIs coupled to a word line WL, the fifth NMOS Cell_refThe source electrode of the fifth NMOS tube Cell is grounded with VSS_refAdapted to be switched on or off under control of a signal for switching on the word line WL in order to read said resistance R_refStored reference data.

The data cell circuit 28 may include a resistor R_dataAnd a sixth NMOS tube Cell_data. The resistor R_dataCan be a high resistance state resistance or a low resistance state resistance, and the resistance R_dataIs coupled to the second bit line selection switch YMUX_cellSaid resistance R_dataIs adapted to store dynamic data. The sixth NMOS tube Cell_dataIs coupled to the resistor R_dataThe sixth NMOS tube Cell_dataIs coupled to a word line WL, the sixth NMOS Cell_dataThe sixth NMOS tube Cell, and the source electrode of VSS_dataAdapted to be switched on or off under control of a signal for switching on the word line WL in order to read said resistance R_dataThe stored dynamic data.

Those skilled in the art will appreciate that, in one implementation, the fifth NMOS tube Cell is coupled to_refAnd a word line WL coupled to the sixth NMOS Cell_dataThe word lines WL of the gates may be the same word line, and the signal accessing the word lines WL may be the same signal.

In a specific implementation, the circuit structures of the clamp circuit 25, the bit line selection circuit 26, the reference cell circuit 27, and the data cell circuit 28 of the dynamic feedback sense amplifier circuit shown in fig. 4 are the same as the circuit structures of the clamp circuit 25, the bit line selection circuit 26, the reference cell circuit 27, and the data cell circuit 28 of the dynamic feedback sense amplifier circuit shown in fig. 3, and specific descriptions may refer to the description corresponding to fig. 3, which is not repeated herein.

In the dynamic feedback sense amplifier circuit described with reference to fig. 3 or 4, in a specific implementation, the comparison amplifier circuit 24 may include a voltage comparison amplifier VC, one input terminal of the voltage comparison amplifier VC is coupled to the first load circuit 21, a second input terminal of the voltage comparison amplifier VC is coupled to the second load circuit 22, and the voltage comparison circuit VC is adapted to compare the reference voltage V_refAnd the data voltage V_dataComparing and outputting the comparison result signal.

In one embodiment, if the data voltage V is_dataLess than reference voltage V_refThen the stored dynamic data can be judged to be "0"; if the data voltage V_dataGreater than a reference voltage V_refThen the stored dynamic data may be decided to be "1", or vice versa.

The technical solution of the present invention is described in detail by the specific embodiments shown in fig. 3 and fig. 4, respectively.

Referring to FIG. 3, in one embodiment, if the resistance R of the data cell circuit 28 is greater than the threshold value_dataIf the voltage is in the low resistance state, the data voltage V output by the second NMOS transistor NM1_dataThe voltage of the capacitor C1 is decreased, and the data voltage V is output_dataA feedback signal with a positive trend correlation coupled to the gate of the second NMOS transistor NM1 for controlling the second NMOS transistor NM1 to reduce the data current I passing through_dataSo that the second NMOS transistor NM1 can convert the data current I_dataThe resulting data voltage V_dataAnd decreases. By repeating the above steps, the data voltage V can be controlled_dataThe voltage value of the voltage is quickly reduced, and the reference voltage V can be realized_refAnd a data voltage V_dataThe rapid increase in the difference between.

Accordingly, if the resistance R of the data cell circuit 28_dataIn a high impedance state, the data voltage V output by the second NMOS transistor NM1_dataThe voltage increases, the capacitor C1 outputs the data voltage V_dataIncreasing a feedback signal with positive trend correlation, the feedback signal being coupled to the gate of the second NMOS transistor NM1, controlling the second NMOS transistor NM1 to increase the data current I passing through_dataSo that the second NMOS transistor NM1 can convert the data current I_dataThe resulting data voltage V_dataAnd (4) increasing. By repeating the above steps, the data voltage V can be controlled_dataThe voltage value of the voltage can be rapidly increased, and the reference voltage V can be realized_refAnd a data voltage V_dataThe rapid increase in the difference between.

Referring to FIG. 4, in another embodiment of the present invention, if the resistance R of the data cell circuit 28_dataIf the voltage is in low resistance state, the data voltage V output by the second PMOS transistor P1_dataThe voltage of the inverted data voltage input into the capacitor C1 is changed in a decreasing trend, and the inverted data voltage is inverted by the inverter I1 and is changed in an increasing trend. The capacitor C1 outputs a feedback signal (corresponding to the data voltage V) positively correlated to the inverse data voltage increasing tendency_dataA feedback signal with a positive trend correlation) coupled to the gate of the second PMOS transistor P1, controlling the second PMOS transistor P1 to reduce the data current I passing through_dataThereby enabling the second PMOS transistor P1 to convert the data current I_dataThe resulting data voltage V_dataAnd decreases. By repeating this, the data voltage V can be made to be_dataThe voltage value of the voltage is quickly reduced, and the reference voltage V can be realized_refAnd a data voltage V_dataThe rapid increase in the difference between.

Accordingly, if the resistance R of the data cell circuit 28_dataIf the voltage is in a high impedance state, the data voltage V output by the second PMOS transistor P1_dataThe voltage of the data line is increased, and the inverted data voltage input into the capacitor C1 after being inverted by the inverter I1 is decreased. The capacitor C1 outputs a feedback signal (corresponding to the data voltage V) positively correlated to the inverse data voltage decrease tendency_dataIncreasing a feedback signal with a positive trend correlation), the feedback signal being coupled to the gate of the second PMOS transistor P1, controlling the second PMOS transistor P1 to increase the data current I passing through_dataThereby enabling the second PMOS transistor P1 to convert the data current I_dataThe resulting data voltage V_dataAnd (4) increasing. By repeating this, the data voltage V can be made to be_dataThe voltage value of the voltage can be rapidly increased, and the reference voltage V can be realized_refAnd a data voltage V_dataThe rapid increase in the difference between.

The feedback circuit outputs a feedback signal positively correlated with the variation trend of the data voltage to the second load circuit, and the feedback signal can control the second load circuit to generate the data voltage according to the direction positively correlated with the variation trend of the data voltage, so that the increase speed of the difference between the data voltage and the reference voltage can be increased, and the reading speed of the readout amplifying circuit can be increased.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.