阅读说明：本技术 具有更强健读/写效能的自旋力矩转移磁性随机存取存储器散热器及磁性屏蔽结构设计 (Spin torque transfer MRAM heat sink and magnetic shield design with more robust read/write performance ) 是由 锺汤姆 杰斯明·哈克 邓忠建 于 2018-12-28 设计创作，主要内容包括：封装整合多个MTJ接面的STT-MRAM装置以其能消散由重复读/写程序产生的热量且同时屏蔽邻近装置的外部磁场。另外,可建构封装层以降低已证明会影响DR/R及Hc的顶部引线应力。我们提供一种可同时解决所有此些问题的装置设计及其制备方法。(STT-MRAM devices that incorporate multiple MTJ junctions are packaged to enable them to dissipate heat generated by repeated read/write procedures while shielding external magnetic fields of neighboring devices. Additionally, the encapsulation layer may be constructed to reduce top lead stress that has been shown to affect DR/R and Hc. We provide a device design and method of making that can address all of these problems simultaneously.)

1. A method of forming a magnetic thin film device, comprising:

providing a film deposit;

patterning the thin film deposition to produce a plurality of separate stacks;

conformally depositing a first encapsulation layer over all exposed top and side surfaces of the patterned deposit, the encapsulation layer being an oxidation protection layer, and the encapsulation layer thereby forming oxidation protection sidewalls against the patterned side surfaces of the deposit;

conformally forming a second packaging layer above the first packaging layer, wherein the second packaging layer is a heat dissipation layer;

conformally forming a third packaging layer on the second packaging layer, wherein the third packaging layer is a hard mask layer for patterning the heat dissipation layer;

removing an upper portion of the heat spreading layer by creating a self-aligned etching process using the hard mask layer, the etching process leaving a remaining side portion of the heat spreading layer to surround the first encapsulation layer still conformally covering the patterned deposition; followed by

Filling all spaces within the patterned deposit with an interlayer dielectric; and

creating a flat top surface of the encapsulated deposit by a CMP process that removes portions of the encapsulated patterned deposit including upper portions of the first encapsulation layer and the heat spreader layer and exposes a conductive portion of the deposit where an electrical connection can be made; followed by

Forming a conductive bit line over the planarized surface to electrically contact all exposed upper portions of the deposits.

2. A method of forming a magnetic thin film device, comprising:

providing a film deposit;

patterning the thin film deposition to produce a plurality of separate stacks;

conformally depositing a first encapsulation layer over all exposed top and side surfaces of the patterned deposit, the encapsulation layer being an oxidation protection layer, and the encapsulation layer thereby forming oxidation protection sidewalls against the patterned side surfaces of the deposit;

conformally forming a second packaging layer above the first packaging layer, wherein the second packaging layer is a heat dissipation layer;

conformally forming a third encapsulating layer over the second encapsulating layer, the third encapsulating layer being a magnetic shielding layer;

conformally forming a fourth packaging layer over the third packaging layer, the fourth packaging layer being a hard mask layer for patterning the heat dissipation layer;

removing the heat spreader layer and the upper portion of the magnetic shield layer by creating a self-aligned etch process using the hard mask layer, the etch process leaving the remaining side portions of the heat spreader layer and the magnetic shield layer to surround the first encapsulation layer which still conformally covers the patterned deposition; followed by

Filling all spaces within the patterned deposit with an interlayer dielectric; and

creating a flat top surface of the encapsulated deposit by a CMP process that removes portions of the encapsulated patterned deposit including upper portions of the first encapsulation layer, the heat spreader layer and the magnetic shield layer and exposes a conductive portion of the deposit that can make an electrical connection; followed by

Forming a conductive bit line over the planarized surface to electrically contact all exposed upper portions of the deposits.

3. A method of forming a magnetic thin film device, comprising:

providing a film deposit;

patterning the thin film deposition to produce a plurality of separate stacks;

conformally depositing a first encapsulation layer over all exposed top and side surfaces of the patterned deposit, the encapsulation layer being an oxidation protection layer, and the encapsulation layer thereby forming oxidation protection sidewalls against the patterned side surfaces of the deposit;

conformally forming a second packaging layer above the first packaging layer, wherein the second packaging layer is a heat dissipation layer;

conformally forming a third encapsulating layer over the second encapsulating layer, the third encapsulating layer being a magnetic shielding layer;

conformally forming a fourth packaging layer over the third packaging layer, the fourth packaging layer being a hard mask layer for patterning the heat dissipation layer;

removing the heat spreader layer and the upper portion of the magnetic shield layer by creating a self-aligned etch process using the hard mask layer, the etch process leaving the remaining side portions of the heat spreader layer and the magnetic shield layer to surround the first encapsulation layer which still conformally covers the patterned deposition; followed by

Filling all spaces within the patterned deposit with an interlayer dielectric; and

creating a flat top surface of the encapsulated deposit by a CMP process that removes portions of the encapsulated patterned deposit including the first encapsulation layer and upper portions of the heat spreader layer, but leaves the upper portions of the magnetic shield layer intact, whereby the magnetic shield layer provides a conductive portion of the deposit that can make an electrical connection; followed by

Forming a conductive bit line on the planarized surface to electrically contact all exposed upper portions of the deposits.

4. The method of claim 1, wherein the thin film deposition is an MTJ stack.

5. The method of claim 2, wherein the thin film deposition is an MTJ stack.

6. The method of claim 3, wherein the thin film deposition is an MTJ stack.

7. The method of claim 4, wherein the MTJ stack is patterned to form at least two separate stacks of the same size.

8. The method of claim 5, wherein the MTJ stack is patterned to form at least two separate stacks of the same size.

9. The method of claim 6, wherein the MTJ stack is patterned to form at least two separate stacks of equal size.

10. The method of claim 7, wherein the patterned MTJ stack comprises a stack of horizontal and planar layers including, from bottom to top, a pinned layer, a tunnel barrier layer, a free layer, a first hard mask layer, and a second hard mask layer.

11. The method of claim 8, wherein the patterned MTJ stack comprises a stack of horizontal and planar layers comprising, from bottom to top, a pinned layer, a tunnel barrier layer, a free layer, a first hard mask layer, and a second hard mask layer.

12. The method of claim 9, wherein the patterned MTJ stack comprises a stack of horizontal and planar layers including, from bottom to top, a pinned layer, a tunnel barrier layer, a free layer, a first hard mask layer, and a second hard mask layer.

13. The method of claim 1, wherein the first packaging layer is a SiN, SiO formed to a thickness between about 20 to 200A₂AlO, AlN or MgO layers.

14. The method of claim 2, wherein the first packaging layer is a SiN, SiO formed to a thickness between about 20 to 200A₂AlO, AlN or MgO layers.

15. The method of claim 3, wherein the first packaging layer is a SiN, SiO formed to a thickness between about 20-200A₂AlO, AlN or MgO layers.

16. The method of claim 1, wherein the heat spreading layer is formed to a thickness of between about 20 to 100A of a material selected from the group of materials having high thermal conductivity: ti, TiN, Cu, Ta, TaN, W, Al and AlN.

17. The method of claim 2, wherein the heat spreading layer is formed to a thickness of between about 20 to 100A of a material selected from the group of materials having high thermal conductivity: ti, TiN, Cu, Ta, TaN, W, Al and AlN.

18. The method of claim 3, wherein the heat spreading layer is formed to a thickness of between about 20 to 100A of a material selected from the group of materials having high thermal conductivity: ti, TiN, Cu, Ta, TaN, W, Al and AlN.

19. The method of claim 1 wherein said interlevel dielectric fill material is SiO₂Or SiN.

20. The method of claim 2 wherein said interlevel dielectric fill material is SiO₂Or SiN.

21. The method of claim 3 wherein said interlevel dielectric fill material is SiO₂Or SiN.

22. The method of claim 1, wherein the third encapsulation layer used as a hard mask layer is formed as a SiO of a thickness between about 50-300A₂Or a SiN layer.

23. The method of claim 2, wherein the fourth packaging layer used as a hard mask layer is formed as a SiO of a thickness between about 50-300A₂Or a SiN layer.

24. The method of claim 3, wherein the fourth packaging layer used as a hard mask layer is formed as a SiO with a thickness between about 50-300A₂Or a SiN layer.

25. The method of claim 1, wherein the heat sink layer is a material selected from NiFe or CoFe having magnetic permeability thereby serving as a magnetic shield and a heat sink.

26. The method of claim 2, wherein the magnetic shielding layer is a material having magnetic permeability selected from the group consisting of NiFe or CoFe, thereby serving as a magnetic shield and a heat sink.

27. The method of claim 3, wherein the magnetic shielding layer is a material having magnetic permeability selected from the group consisting of NiFe or CoFe, thereby serving as a magnetic shield and a heat sink.

28. The method of claim 1, wherein the heat spreading layer is selected to have a coefficient of thermal expansion that provides stress relief during device operation.

29. The method of claim 2, wherein the heat spreading layer is selected to have a coefficient of thermal expansion that provides stress relief during device operation.

30. The method of claim 3, wherein the heat spreading layer is selected to have a coefficient of thermal expansion that provides stress relief during device operation.

31. A packaged MTJ device, comprising:

a separate patterned plurality of MTJ stacks; wherein

The plurality of stacks are electrically connected by a continuous bit line, the continuous bit line contacts the exposed upper surface of each stack; wherein

Each of the stacks is compositionally encapsulated by three sequentially formed layers, wherein the sequence of the three layers comprises:

a first layer protecting each of the stacks from oxidation;

a second layer conformally contacting the first layer and serving multiple purposes depending on the function of its material composition; a hard mask layer used to pattern the second layer; wherein

An interlayer dielectric material filling all spaces between and around the patterned MTJ stacks; and wherein

A planar interface has been created between the bit line and an upper surface of each of the MTJ stacks created by a CMP process, wherein each of the upper surfaces is an exposed surface of a conductive layer of the MTJ stack, thereby establishing an electrical connection between the bit line and each of the MTJ stacks.

32. A packaged MTJ device, comprising:

a separate patterned plurality of MTJ stacks; wherein

The plurality of stacks are electrically connected by a continuous bit line, the continuous bit line contacts the exposed upper surface of each stack; wherein

Each of the stacks is compositionally encapsulated by four sequentially formed layers, wherein the sequence of the three layers includes:

a first layer protecting each of the stacks from oxidation; a second layer conformally contacting the first layer and serving as a heat sink layer;

a third layer conformally contacting the second layer and serving as a magnetic shield;

a fourth layer which is a hard mask layer used to pattern the second layer and the third layer; wherein

An interlayer dielectric material filling all spaces between and around the patterned MTJ stacks; and wherein

A planar interface has been created between the bit line and an upper surface of each of the MTJ stacks created by a CMP process, wherein each of the upper surfaces is an exposed surface of a conductive layer of the MTJ stack, thereby establishing an electrical connection between the bit line and each of the MTJ stacks.

33. The device of claim 31, wherein the first encapsulation layer is a SiN, SiO formed to a thickness between about 20 to 200A₂AlO, AlN or MgO layers.

34. The device of claim 31, wherein the second layer is a material selected from the following group of materials with high thermal conductivity: ti, TiN, Cu, Ta, TaN, W, Al, and AlN, and wherein the second layer serves as a heat dissipation layer formed to a thickness between about 20 to 100A.

35. The apparatus of claim 31 wherein said interlevel dielectric fill material is SiO formed to a thickness of between about 20-200A₂Or SiN.

36. The device of claim 31, wherein the fourth packaging layer used as a hard mask layer is formed as a SiO of a thickness between about 50-300A₂Or a SiN layer.

37. The device of claim 31, wherein the magnetic shielding layer is a material having magnetic permeability selected from NiFe or CoFe formed to a thickness between about 20 to 100A.

38. The device of claim 31, wherein the heat spreading layer is selected to have a coefficient of thermal expansion that provides stress relief during device operation.

Technical Field

The present disclosure relates generally to magnetic memory devices, and more particularly to STT-MRAM (spin torque transfer-magnetic random access memory) devices and methods of improving thermal stability thereof.

Background

STT-MRAM is becoming an increasingly promising candidate for the next-generation non-volatile working memory (non-volatile memory) to replace embedded flash memory and embedded SRAM (static random access memory). However, there are challenges in scaling this technology down to 20nm (nanometer) sizes and smaller. This challenge enhances the thermal stability of smaller MTJ (magnetic tunnel junction) devices, which are one type of memory cell used in MRAM. Studies have reported the self-heating of MTJ junctions that occurs during read/write cycles (see, e.g., IEEE Transactions on Electron Device, Vol. 59, No. 3, month S.Chatterjee, S.Salahuddin, S.Kumar, and S.Mukhopadhyay, Vol. 3, month 3, 2016, Y.Wang, H.Cai, L.Navine, Y.Zhang, X.ZHao, E.Deng, J.Klein, and IEEE Transaction on Electron Device, Vol. 63, No. 4, month 4, W.Guo, G.Presat, V.Javerliac, M.Baraji, N.Mestier, C.Baraduc, Journal of Physics D, Applied Physics, 2010, page 25, page 43 (3521), pages 25, p. 21, pages 21, p

As both read/write speed and pattern density increase, self-heating is expected to become a greater problem. On the one hand, self-heating may help to reduce switching current, but on the other hand, self-heating may also reduce device thermal stability and even device reliability. Another challenge of STT-MRAM is switching interference caused by stray magnetic fields from neighboring devices. Such and other problems related to STT-MRAM operation, such as undesirable stress, have been considered in the prior art (e.g., in all of the following patents):

U.S. Pat. No. 20150091109(Allinger et al)

United states patent 9,024,399(Guo)

United states patent 7,262,069(Chung et al)

United states patent application 2007/0058422(Phillips et al)

U.S. Pat. No. 8,194,436(Fukami et al)

US patent 9,081,669(Tadepalli et al)

United states patent 8,125,057(Bonin et al)

U.S. Pat. No. 7,829,980(Molla et al)

U.S. patent application 2006/0273418(Chung et al).

It is indeed desirable to effectively address the problems of self-heating, thermal stability, stress and switching disturbances. It would be further advantageous if such problems could be solved in a combined and efficient manner. While the above prior art has discussed such problems, it does not address such problems in a comprehensive, practical, and effective manner as in the present disclosure.

Disclosure of Invention

A first object of the present disclosure is to provide a method of protecting STT-MRAM devices from adverse thermal effects, such as those due to self-heating induced by read/write operations.

It is a second object of the present disclosure to provide a method of protecting STT-MRAM devices from adverse switching effects caused by the magnetic field of neighboring devices.

It is a third object of the present disclosure to provide a mechanism for reducing stress caused by adverse thermal effects in certain regions of STT-MRAM devices.

It is a fourth object of the present disclosure to use the same heat dissipation design to act as a stress buffer for an MTJ device.

A fifth object of the present disclosure is to provide a method that is capable of producing all of the above objects simultaneously.

Such objectives would be achieved by designing and fabricating a heat dissipation structure for STT-MRAM devices that would improve the thermal stability of the STT-MRAM devices. The heat dissipation structure is used as a magnetic shield and a stress buffer of the magnetic device. An internal study has shown that top lead stress can affect DR/R and Hc. Fig. 1 shows such results. Therefore, we have empirical evidence that the same thermal design can also be used as a stress buffer for MTJ devices, where the stress includes intrinsic film (intrinsic film) tensile and compressive stress plus stress induced by differential expansion/contraction between the BIT line and the bulk stack.

The present disclosure provides a heat dissipation structure design and method of making the same for MTJ devices, such as MTJ devices that may be integrated into STT-MRAM devices, such that heat generated by such MTJ devices during read/write cycles may be dissipated more quickly than MTJ devices made using current methods. Thus, MTJ devices so designed and fabricated have improved read/write reliability.

Drawings

FIGS. 1 a-1 b show data indicating how top lead stress may affect DR/R and Hc.

Fig. 2 lists a table of layer names and their equivalent functions corresponding to the "old" MTJ preparation scheme shown in fig. 4 a-4 e and currently used (table 1).

Figure 3 lists a table (table 2) of process flow steps corresponding to the preparation schemes shown in figures 4a to 4 e.

Fig. 4a to 4e show schematic diagrams of a Magnetic Tunneling Junction (MTJ) structure and a fabrication process for fabricating the same according to the present disclosure.

Fig. 5 lists a table (table 3) of layer names and their equivalent functions corresponding to the preparation schemes of the present disclosure shown in fig. 7a to 7 f.

Fig. 6 lists a table (table 4) of process flow steps corresponding to the preparation protocol of the present disclosure shown in fig. 7a to 7 f.

Fig. 7a to 7f show a set of schematic diagrams of a Magnetic Tunneling Junction (MTJ) structure and a fabrication process for fabricating the same according to the present disclosure.

Fig. 8 a-8 d show a set of schematic views of alternative Magnetic Tunneling Junction (MTJ) structures and fabrication processes for making the same that provide the same properties as those shown in fig. 7 a-7 f.

Description of reference numerals:

10: pinning layer

11: barrier layer

12: free layer

13: first hard mask layer/Magnetic Tunnel Junction (MTJ) device

14: a second hard mask layer

15: patterned layer of photoresist

16: encapsulation layer

17: space-filling interlayer dielectric film (ILD)

18: bit line

19: second packaging layer/Heat sink layer

19 a: magnetic shielding layer

20: third encapsulation layer

130,140: interface (I)

Detailed Description

Fig. 2 illustrates a current integration scheme (i.e., prior art) for fabricating MTJ junctions of integrated MTJ devices that include multiple junctions that are individually formed and packaged. Such devices may be used to form STT-MRAM logic devices. The layer names and general process integration steps are listed in table 1 (fig. 2) and table 2 (fig. 3), respectively. In the current method, the first step is to deposit a basic unpatterned MTJ film stack and an etch stop hard mask to pattern the stack into a plurality of smaller stacks within the basic unpatterned MTJ film stack so that it can be integrated into a larger device.

Referring to the table shown in fig. 2 and the corresponding schematic of fig. 4a, we see that the deposition of the film stack is a series of 5 layers 14 to 10, where 10 is a pinned layer (pin layer), 11 is a barrier layer (barrier layer), 12 is a free layer (free layer), 13 is a first hard mask layer (such as tantalum (Ta), titanium nitride (TiN), or other conductive material), and 14 is a second hard mask layer (such as a non-conductive material silicon oxynitride (SiON) or a conductive material titanium nitride (TiN)). Layers 13 and 14 may be deposited using the same tool as deposition 10-12, or they may be deposited using a different tool. It should BE noted that the fabricated device can BE easily integrated into a desired circuit, provided that the stack is formed on an appropriate substrate, such as a conductive Bottom Electrode (BE), upon completion of all process steps.

Step 2 is to deposit a patterned layer of photoresist 15 over layer 14, according to the process steps listed in the table of fig. 3 and corresponding shown in fig. 4 b. Step 3 is to etch the MTJ deposit resulting in two separate stacks as shown in fig. 4 c. It should be noted that in this description and the following description, we pattern the initial MTJ stack into two separate stacks. For clarity, the two stacks are shown isolated, assuming of course that they rest on a substrate, but the substrate is not shown. The example of two stacks is arbitrary and chosen for simplicity, and any number of stacks may be processed using such methods.

Step 4 is to deposit an encapsulation layer (16 in fig. 4 d) which is a layer of dielectric material, such as silicon nitride (SiN), silicon dioxide (SiO2), aluminum oxide (Al2O3), magnesium oxide (MgO), or the like, to a thickness between about 20 to 200A to protect the patterned MTJ stack. The encapsulation layer also covers the substrate on which the stack rests and is not shown in fig. 7 c. This encapsulation layer 16 may be deposited in situ in the same tool used to etch the MTJ devices, or it may be deposited using a separate tool. The encapsulation layer is typically a dielectric material such as SiN, SiO2, Al2O3, MgO, or the like. The packaging layer can also be deposited as a metal layer and then oxidized to a dielectric layer. The encapsulation layer functions not only to prevent shorting of the MTJ devices, but also to preserve the magnetic properties and thermal stability of each MTJ device. Therefore, the material of the layer cannot be chosen randomly among the dielectric materials.

Referring finally to FIG. 4e, step 5 is shown for preparing the connection of the BIT line (BIT) line (shown as 18) to the MTJ device. This is typically accomplished by first depositing a space-filling interlayer dielectric film (ILD), shown as 17, and then performing Chemical Mechanical Polishing (CMP) to planarize and open the MTJ device. Finally, BIT line 18 is formed to connect to the MTJ. It should be noted that the CMP process removes the upper surface of the encapsulation layer 16 and the second hard mask 14, opening the device to make electrical contact between the metal BIT line and the first hard mask 13. It should be noted that the BIT lines are typically formed by a dual Cu-damascone process (dual Cu-damascone process) which is well known in the art and will not be described further herein.

The encapsulation layer 16 typically has a very low thermal conductivity. The interlayer dielectric material 17 also has a very low thermal conductivity. Candidates for layer 17 are typically SiN and SiO 2. Because of the low thermal conductivity of the encapsulation layer and the ILD layer, most of the heat generated during the read/write procedure of the finished device can only BE dissipated by passing through the interface 130 between the MTJ and BIT line or the interface 140 between the MTJ and BE (bottom electrode). As the MTJ size decreases, the interface area between the MTJ and the BIT line and between the MTJ and the BE also decreases. As a result, such interfaces become less efficient at dissipating heat, which can become a more serious problem as read/write speeds increase.

Fig. 7 a-7 f illustrate a new integration scheme for fabricating MTJ devices that will meet the objectives described herein. For ease of discussion, the table in fig. 5 and the table in fig. 6 list the layer descriptions and process steps, respectively. The key difference between the currently used (prior art) method and the new method to be described, just described and shown in fig. 4a to 4e, is step 4 and step 5 of table 4 and their corresponding figures in fig. 7d to 7 e. In step 4 shown in fig. 7d, instead of depositing a single layer of encapsulation dielectric 16 as in fig. 4d of the prior art method, two additional encapsulation layers 19 and 20 are added to augment layer 16, still depositing layer 16 to a thickness of between about 20 and 200A. The second encapsulation layer (19 in fig. 7 d) is typically a layer of metallic material (conductive or non-conductive and possibly magnetic) with high thermal conductivity deposited to a thickness of between about 20 to 100A, which will act as a heat sink layer. The third encapsulating layer 20 in fig. 7d is made of SiO₂Or SiN is formed as a hard mask layer to be used for the patterned layer 19, between about 50 and 300A thick. The process for patterning layer 19 (step 5 shown in fig. 7e) is typically accomplished by the usual self-alignment spacer etching (step 5) method of aligned etching using layer 20 as a hard mask, the etching being directed such that it stops at layer 16 and leaves segments of layers 20 and 19 along the sidewalls. Note that the etch is a RIE etch with a good selectivity between layer 19/20 and layer 16. In layer 20 and 16 may be formed of the same dielectric material, alternative etch schemes employing different gases may be used after etching layer 20. After etching, layer 19 will be isolated from the MTJ etching apparatus. During patterning, each individual layer 19 will act as a small "bell jar" to surround each MTJ device. Layer 19 will then act as a heat sink layer. After patterning layer 19 in step 5 (FIG. 7e), ILD layer 17 will be deposited (step 6 of FIG. 7 f), and then a CMP process is performed to simultaneously open both the heat sink layer 19 and the MTJ device 13. Thereafter, a BIT line (18 in fig. 7 f) will be prepared to electrically connect to the MTJ and layer 19 using a similar process as step 5 in fig. 4e (prior art method). It should be noted that the etch process has removed layers 19 and 20 from both patterned MTJ stacks except for their sides, while the CMP process removes the top of layer 16 and the entire layer 14, so BIT line connections can be made.

When a magnetically permeable material, such as nickel-iron alloy (NiFe), etc., is used for layer 19, this layer may then be used as a magnetic shield to absorb stray magnetic flux from neighboring devices and protect the MTJ device. Depending on the choice of magnetic material (which should have good thermal conductivity), this structure can be used as both a heat sink and a magnetic shield. At the same time, the ambient stress on the MTJ device can be tuned by inserting layers 19 formed of materials with different elastic constants.

Referring next to the schematic diagrams of fig. 8 a-8 d, there is shown and described (using the steps in the table of fig. 6) an alternative design of a heat sink and magnetically shielded MTJ device (second embodiment) that also meets the objectives set forth above.

Fig. 8a to 8d schematically show a second embodiment of the method starting from the end of step 3 shown in fig. 7 c. We assume that steps 1, 2 and 3 of this second embodiment are identical to the three steps previously shown in fig. 7a to 7c and described in the table of fig. 6. Fig. 8a now follows the structure shown in fig. 7c and shows a packaging process that replaces that in fig. 7d and is depicted as step 4 in the table of fig. 6. In FIG. 8a of this alternative embodiment, the patterned MTJ stack of FIG. 7c has been encapsulated by layer 16, now then three additional layers 19, 19a, and 20 are encapsulated in succession. Layer 19 is a heat sink layer and layer 19a is a magnetic shield. They are now formed in two different layers (19 and 19a) each of a thickness between 20 and 100A, and if the previous single layer was both magnetic and thermally conductive, it could serve as both a heat sink layer and a magnetic shield layer. The deposition sequence between 19 and 19a may be changed. But regardless of their deposition sequence, these two layers are now patterned independently using a self-aligned etch process by first patterning layer 19, then depositing layer 19a, and etching layer 19a using another photo-etch process.

Fig. 8d shows an alternative method for replacing fig. 8 c. Except that the magnetic shield layer is patterned in a separate step of removing the encapsulation layer 19 so that the magnetic shield layer 19a now remains exposed on top of the MTJ stack where it may contact the BIT line 18.

The detailed description given above illustrates the disclosure rather than limits it, as will be ultimately understood by those skilled in the relevant art. Modifications and variations may be made in methods, materials, structures, and dimensions used in forming and providing thermally and magnetically shielded MTJ devices while still forming and providing structures in accordance with the spirit and scope of the invention as defined by the appended claims.