阅读说明：本技术 发光二极管 (Light emitting diode ) 是由 李剡劤 申赞燮 梁明学 李珍雄 于 2018-07-30 设计创作，主要内容包括：一种发光二极管,其包括：半导体叠层体,包括第一导电型半导体层和台面,台面包括活性层和第二导电型半导体层；ZnO层；下绝缘层,覆盖ZnO层和台面,并具有使第一导电型半导体层暴露的开口部和使ZnO层暴露的开口部；第一焊盘金属层,与第一导电型半导体层电接通；第一凸起焊盘,布置于下绝缘层上,并通过下绝缘层的开口部电接通于第一导电型半导体层；以及第二凸起焊盘,布置于下绝缘层上,与第一凸起焊盘在水平方向上隔开,并通过下绝缘层的开口部电接通于ZnO层,下绝缘层的开口部之下的ZnO层的厚度比被下绝缘层覆盖的ZnO层的厚度薄,第一凸起焊盘包括从第二凸起焊盘凸出的区域,第二凸起焊盘包括凹陷的区域,并且形成为包围第一焊盘金属层。(A light emitting diode, comprising: a semiconductor stacked body including a first conductivity type semiconductor layer and a mesa including an active layer and a second conductivity type semiconductor layer; a ZnO layer; a lower insulating layer covering the ZnO layer and the mesa, and having an opening exposing the first conductive semiconductor layer and an opening exposing the ZnO layer; a first pad metal layer electrically connected to the first conductive type semiconductor layer; a first bump pad disposed on the lower insulating layer and electrically connected to the first conductive type semiconductor layer through an opening portion of the lower insulating layer; and a second bump pad disposed on the lower insulating layer, spaced apart from the first bump pad in a horizontal direction, and electrically connected to the ZnO layer through an opening of the lower insulating layer, a thickness of the ZnO layer below the opening of the lower insulating layer being thinner than a thickness of the ZnO layer covered by the lower insulating layer, the first bump pad including a region protruding from the second bump pad, the second bump pad including a recessed region, and being formed to surround the first pad metal layer.)

1. A light emitting diode comprising:

a semiconductor stack including a first conductive type semiconductor layer and a mesa located on the first conductive type semiconductor layer, the mesa including an active layer and a second conductive type semiconductor layer;

a ZnO layer on the second conductive type semiconductor layer;

a lower insulating layer covering the ZnO layer and the mesa, and having an opening portion exposing the first conductive type semiconductor layer and an opening portion exposing the ZnO layer;

a first pad metal layer electrically connected to the first conductive type semiconductor layer;

a first bump pad disposed on the lower insulating layer and electrically connected to the first conductive type semiconductor layer through an opening portion of the lower insulating layer; and

a second bump pad disposed on the lower insulating layer, spaced apart from the first bump pad in a horizontal direction, and electrically connected to the ZnO layer through an opening portion of the lower insulating layer,

the thickness of the ZnO layer under the opening of the lower insulating layer is smaller than the thickness of the ZnO layer covered by the lower insulating layer,

the first bump pad includes a region protruding from the second bump pad,

the second bump pad includes a recessed region and is formed to surround the first pad metal layer.

2. The light emitting diode of claim 1,

the thickness of the ZnO layer under the opening of the lower insulating layer is 40nm to 100nm thinner than the thickness of the ZnO layer covered by the lower insulating layer.

3. The light emitting diode of claim 2,

the ZnO layer under the opening of the lower insulating layer has a thickness of 100nm or more.

4. The light emitting diode of claim 1,

the lower insulating layer exposes the first conductive type semiconductor layer along the mesa edge.

5. The light emitting diode of claim 4,

the first pad metal layer is in contact with the first conductive type semiconductor layer exposed along the mesa edge.

6. The light emitting diode of claim 1,

the lower insulating layer includes a plurality of opening portions exposing the first conductive type semiconductor layer along edges of the mesa,

the first pad metal layer is connected to the first conductive type semiconductor layer through the plurality of openings.

7. The light emitting diode of claim 6,

the mesa includes a plurality of grooves disposed along a side,

the plurality of opening portions of the lower insulating layer are arranged corresponding to the plurality of grooves.

8. The light emitting diode of claim 1,

the first pad metal layer has a shape that is long along a length direction of the light emitting diode.

9. The light emitting diode of claim 1,

the first bump pad and the second bump pad have a width narrower than a width of the mesa.

10. The light emitting diode of claim 9,

the first bump pad is defined in an upper region of the mesa.

Technical Field

The present invention relates to a light emitting diode, and more particularly, to a high efficiency light emitting diode.

Background

Generally, nitrides of group iii elements such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and a direct transition band (band) structure, and therefore, have recently attracted attention as light source materials in the visible and ultraviolet regions. In particular, blue and green light emitting diodes using indium gallium nitride (InGaN) are applied to various application fields such as large-scale natural color flat panel display devices, signal lamps, indoor lighting, automotive headlamps, high-density light sources, high-resolution output systems, and optical communications.

The light emitting diode requires an electrode for inputting current. Further, since the p-type gallium nitride-based semiconductor layer has high resistivity, a problem of current concentration occurs, and in order to compensate for this problem, Indium Tin Oxide (ITO) in ohmic contact is generally used for the p-type gallium nitride-based semiconductor layer.

However, in the case of a high-power light emitting diode such as a chip-scale light emitting diode, an insulating layer for protecting the light emitting diode is formed, and an additional metal layer such as an electrode pad is formed on the insulating layer. In this case, in order to electrically connect the electrode pad and the transparent electrode layer, the insulating layer needs to be etched to expose ITO, and the ITO may be damaged by an etchant during etching of the insulating layer. In particular, ITO has a relatively high light absorption rate, is difficult to increase in thickness, and has a thickness of approximately about 100 nm. Since the thickness of ITO is relatively thin, the p-type gallium nitride-based semiconductor layer may be exposed when the insulating layer is etched, and thus, p-ohmic characteristics may be deteriorated, possibly resulting in defects.

In order to prevent this problem, an additional metal layer may be additionally formed on the ITO or a metal ohmic layer may be used instead of the ITO before the insulating layer is evaporated. However, when an additional metal layer is added to ITO or a metal ohmic layer is used instead of ITO, the manufacturing process becomes complicated and the manufacturing cost increases.

On the other hand, in general lighting such as L ED filament lamps, light emitting diodes are used, and a plurality of light emitting diodes are electrically connected to a rod-shaped base by bonding wires.

Disclosure of Invention

The present invention is directed to provide a light emitting diode using a transparent ohmic layer and having a simple structure and improved structural stability and process stability.

Another object of the present invention is to provide a light emitting diode having a simple chip scale package structure that can prevent the occurrence of defects such as disconnection.

The present invention provides a light emitting diode, comprising: a semiconductor stack including a first conductive type semiconductor layer and a mesa located on the first conductive type semiconductor layer, the mesa including an active layer and a second conductive type semiconductor layer; a ZnO layer on the second conductive type semiconductor layer; a lower insulating layer covering the ZnO layer and the mesa, and having an opening portion exposing the first conductive type semiconductor layer and an opening portion exposing the ZnO layer; a first pad metal layer electrically connected to the first conductive type semiconductor layer; a first bump pad disposed on the lower insulating layer and electrically connected to the first conductive type semiconductor layer through an opening portion of the lower insulating layer; and a second bump pad disposed on the lower insulating layer, spaced apart from the first bump pad in a horizontal direction, and electrically connected to the ZnO layer through an opening of the lower insulating layer, a thickness of the ZnO layer under the opening of the lower insulating layer being thinner than a thickness of the ZnO layer covered by the lower insulating layer, the first bump pad including a region protruding from the second bump pad, the second bump pad including a recessed region, and being formed to surround the first pad metal layer.

A light emitting diode according to an embodiment of the present invention includes: a semiconductor stack including a first conductive type semiconductor layer and a mesa located on the first conductive type semiconductor layer, the mesa including an active layer and a second conductive type semiconductor layer; a ZnO layer on the second conductive type semiconductor layer; a lower insulating layer covering the ZnO layer and the mesa and having an opening portion exposing the ZnO layer; a first pad metal layer disposed on the lower insulating layer and electrically contacted with the first conductive type semiconductor layer; a second pad metal layer electrically connected to the ZnO layer through an opening of the lower insulating layer and spaced apart from the first pad metal layer in a horizontal direction; and an upper insulating layer covering the first pad metal layer and the second pad metal layer and having a first opening and a second opening exposing the first pad metal layer and the second pad metal layer, respectively, wherein a thickness of the ZnO layer under the opening of the lower insulating layer is thinner than a thickness of the ZnO layer covered by the lower insulating layer.

A light emitting diode according to another embodiment of the present invention includes: a semiconductor stack including a first conductive type semiconductor layer and a mesa located on the first conductive type semiconductor layer, the mesa including an active layer and a second conductive type semiconductor layer; a ZnO layer on the second conductive type semiconductor layer; a lower insulating layer covering the ZnO layer and the mesa, and having an opening portion exposing the first conductive type semiconductor layer and an opening portion exposing the ZnO layer; a first bump pad disposed on the lower insulating layer and electrically connected to the first conductive type semiconductor layer through an opening of the lower insulating layer; and a second bump pad disposed on the lower insulating layer, spaced apart from the first bump pad in a horizontal direction, and electrically connected to the ZnO layer through an opening of the lower insulating layer, a thickness of the ZnO layer below the opening of the lower insulating layer being thinner than a thickness of the ZnO layer covered by the lower insulating layer.

According to the embodiment of the present invention, a ZnO layer having low light absorption rate is used as the transparent electrode layer, so that a thick transparent electrode layer can be formed. Thus, even if the thickness of the ZnO layer under the opening of the lower insulating layer is formed to be smaller than the thickness of the ZnO layer covered by the lower insulating layer, the thickness of the ZnO layer under the opening of the lower insulating layer can be made sufficiently thick. Therefore, it is not necessary to form an additional metal reflective layer on the transparent electrode layer or a metal reflective layer instead of the transparent electrode layer before forming the lower insulating layer, and thus a light emitting diode having a simple process and improved structural stability can be provided. Further, according to the embodiments of the present invention, a small light emitting diode capable of flip chip bonding without a wire bonding can be provided.

Other advantages and effects of the present invention will be more apparent from the detailed description.

Drawings

Fig. 1 is a schematic top view for explaining a light emitting diode according to an embodiment of the present invention.

Fig. 2 is a sectional view taken along the section line a-a' of fig. 1.

Fig. 3 is a sectional view taken along the section line B-B' of fig. 1.

Fig. 4a to 4e are plan views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention.

Fig. 5 is a schematic top view for explaining a light emitting diode according to another embodiment of the present invention.

Fig. 6 is a sectional view taken along the section line C-C' of fig. 5.

Fig. 7 is a sectional view taken along the section line D-D' of fig. 5.

Fig. 8a to 8e are schematic plan views for explaining a method of manufacturing a light emitting diode according to another embodiment of the present invention.

Fig. 9 is a schematic top view for explaining a light emitting diode according to still another embodiment of the present invention.

Fig. 10 is a sectional view taken along the section line E-E' of fig. 9.

Fig. 11 is a sectional view taken along the cut line F-F' of fig. 9.

Fig. 12a to 12e are schematic plan views for explaining a method of manufacturing a light emitting diode according to still another embodiment of the present invention.

Fig. 13 is a schematic top view for explaining a light emitting diode according to still another embodiment of the present invention.

Fig. 14 is a sectional view taken along the sectional line G-G' of fig. 13.

Fig. 15 is a schematic cross-sectional view for explaining an L ED lamp according to an embodiment of the present invention.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below are provided as examples in order to enable those skilled in the art to fully understand the concept of the present invention. Therefore, the present invention is not limited to the embodiments described below, and can be embodied in other forms. In the drawings, the widths, lengths, thicknesses, and the like of constituent elements are exaggerated in some cases for convenience. Note that the description that one constituent element is "above" or "on" another constituent element includes not only the case where each portion is "directly above" or "directly on" another portion, but also the case where another constituent element is interposed between each constituent element and another constituent element. Like reference numerals refer to like elements throughout the specification.

According to an embodiment of the present invention, there is provided a light emitting diode including: a semiconductor stack including a first conductive type semiconductor layer and a mesa located on the first conductive type semiconductor layer, the mesa including an active layer and a second conductive type semiconductor layer; a ZnO layer on the second conductive type semiconductor layer; a lower insulating layer covering the ZnO layer and the mesa and having an opening portion exposing the ZnO layer; a first pad metal layer disposed on the lower insulating layer and electrically contacted with the first conductive type semiconductor layer; a second pad metal layer electrically connected to the ZnO layer through an opening of the lower insulating layer and spaced apart from the first pad metal layer in a horizontal direction; and an upper insulating layer covering the first pad metal layer and the second pad metal layer and having a first opening and a second opening exposing the first pad metal layer and the second pad metal layer, respectively, wherein a thickness of the ZnO layer under the opening of the lower insulating layer is thinner than a thickness of the ZnO layer covered by the lower insulating layer.

By using a ZnO layer having a low light absorption rate, the ZnO layer under the opening of the lower insulating layer can be left sufficiently thick, and the structural stability can be improved. In addition, a metal reflecting layer is not required to be used below the lower insulating layer, so that the manufacturing process is simple and the process stability is improved.

The thickness of the ZnO layer under the opening of the lower insulating layer may be 40nm to 100nm thinner than the thickness of the ZnO layer covered by the lower insulating layer.

Further, the thickness of the ZnO layer under the opening of the lower insulating layer may be 100nm or more. By ensuring the thickness of the ZnO layer below the opening of the lower insulating layer to be 100nm or more, stable ohmic contact can be ensured. The upper limit of the thickness of the ZnO layer under the opening of the lower insulating layer is not particularly limited, and may be, for example, 500nm or less.

On the other hand, the lower insulating layer may expose the first conductive type semiconductor layer along the circumference of the mesa, and the first pad metal layer may be in contact with the first conductive type semiconductor layer exposed along the circumference of the mesa.

In particular, the lower insulating layer may include a plurality of opening portions exposing the first conductive type semiconductor layer along the circumference of the mesa, and the first pad metal layer may be in contact with the first conductive type semiconductor layer through the plurality of opening portions.

Further, the mesa may include a plurality of grooves arranged along a side surface, and the plurality of opening portions of the lower insulating layer may be arranged corresponding to the plurality of grooves. This makes it possible to increase the light emitting area in a predetermined area of the light emitting diode.

In the semiconductor device according to the present invention, the mesa may have a through hole exposing the first conductive type semiconductor layer through the second conductive type semiconductor layer and the active layer, the lower insulating layer may have an opening exposing the first conductive type semiconductor layer in the through hole, and the first pad metal layer may be connected to the first conductive type semiconductor layer in the through hole.

In one embodiment, the mesa may have a plurality of through holes, the lower insulating layer may have an opening portion exposing the first conductive type semiconductor layer in each of the through holes, and the first pad metal layer may be in contact with the first conductive type semiconductor layer in each of the through holes.

In another embodiment, the through hole may have a shape that is long along a length direction of the light emitting diode. Further, the first pad metal layer may cover the through-hole, and a part of the second pad metal layer may be disposed on both sides of the through-hole along a longitudinal direction of the through-hole. By arranging the second pad metal layers on both sides of the through-hole along the length direction of the through-hole, current dispersion in the ZnO layer can be facilitated.

In some embodiments, the lower insulating layer may expose the first conductive type semiconductor layer along a circumference of the mesa, and the first pad metal layer may be further connected to the first conductive type semiconductor layer exposed along the circumference of the mesa.

In some embodiments, the first opening portion and the second opening portion of the upper insulating layer may define a pad region of the light emitting diode. Therefore, the bump pad can be omitted, thereby providing a light emitting diode with a simple manufacturing process.

In another embodiment, the light emitting diode may further include first and second bump pads disposed on the upper insulating layer and electrically communicated with the first and second pad metal layers, respectively.

Further, the second pad metal layer may be surrounded by the first pad metal layer, the lower insulating layer may be exposed at a boundary region of the first pad metal layer and the second pad metal layer, and the exposed lower insulating layer may be covered by the upper insulating layer.

Therefore, it may be that the first pad metal layer and the second pad metal layer are formed together in the same process.

In an embodiment, the second pad metal layer is disposed in a plurality of portions, and the first pad metal layer surrounds the plurality of portions, respectively.

Further, the first bump pad and the second bump pad are respectively disposed across portions of the second pad metal layer. The second bump pads are electrically connected to portions of the second pad metal layer, respectively.

In one embodiment, the lower insulating layer may include a plurality of opening portions exposing the ZnO layer. In this way, the second pad metal layer can be connected to the ZnO layer at a plurality of points, and the second pad metal layer can contribute to current dispersion in the ZnO layer.

In one embodiment, the lower insulating layer may be a distributed bragg reflector. Therefore, light transmitted through the ZnO layer can be reflected by the lower insulating layer.

In another embodiment, the lower insulating layer may be made of SiO₂And forming the first pad metal layer and the second pad metal layer to comprise metal reflecting layers. Thereby, light transmitted through the ZnO layer and the lower insulating layer can be reflected by the first pad metal layer and the second pad metal layer.

In one embodiment, the second opening portion of the upper insulating layer may be located on an opening portion of the lower insulating layer exposing the ZnO layer, and the first opening portion of the upper insulating layer may be laterally spaced apart from the opening portion of the lower insulating layer exposing the ZnO layer.

In contrast, both the first opening portion and the second opening portion of the upper insulating layer may be laterally spaced from the opening portion of the lower insulating layer that exposes the ZnO layer.

According to still another embodiment of the present invention, there is provided a light emitting diode including: a semiconductor stack including a first conductive type semiconductor layer and a mesa located on the first conductive type semiconductor layer, the mesa including an active layer and a second conductive type semiconductor layer; a ZnO layer on the second conductive type semiconductor layer; a lower insulating layer covering the ZnO layer and the mesa, and having an opening portion exposing the first conductive type semiconductor layer and an opening portion exposing the ZnO layer; a first bump pad disposed on the lower insulating layer and electrically connected to the first conductive type semiconductor layer through an opening of the lower insulating layer; and a second bump pad disposed on the lower insulating layer, spaced apart from the first bump pad in a horizontal direction, and electrically connected to the ZnO layer through an opening of the lower insulating layer, a thickness of the ZnO layer below the opening of the lower insulating layer being thinner than a thickness of the ZnO layer covered by the lower insulating layer.

The thickness of the ZnO layer under the opening of the lower insulating layer may be 40nm to 100nm thinner than the thickness of the ZnO layer covered by the lower insulating layer.

Further, the thickness of the ZnO layer under the opening of the lower insulating layer may be 100nm or more.

Further, the lower insulating layer may include a distributed bragg reflector.

On the other hand, it may be that the first bump pad and the second bump pad have a width narrower than a width of the mesa.

Further, the first bump pad may be defined in an upper region of the mesa.

On the other hand, the refractive index of the ZnO layer under the opening exposing the ZnO layer may be smaller than the refractive index of the ZnO layer in the other region covered with the lower insulating layer.

Hereinafter, the detailed description will be given with reference to the drawings.

Fig. 1 is a schematic plan view for explaining a light emitting diode according to an embodiment of the present invention, fig. 2 is a sectional view taken along a cut line a-a 'of fig. 1, and fig. 3 is a sectional view taken along a cut line B-B' of fig. 1.

Referring to fig. 1 to 3, the light emitting diode includes a substrate 21, a semiconductor stack 30, a ZnO layer 31, a lower insulating layer 33, a first pad metal layer 35a, a second pad metal layer 35b, an upper insulating layer 37, a first bump pad 39a, and a second bump pad 39 b. The semiconductor stack 30 includes the first conductive type semiconductor layer 23, the active layer 25, and the second conductive type semiconductor layer 27.

The substrate 21 is not particularly limited as long as it is a substrate on which the gallium nitride semiconductor layer can be grown, and may be, for example, a sapphire substrate, a SiC substrate, a GaN substrate, a Si substrate, or the like. The substrate 21 may in particular be a patterned sapphire substrate.

The substrate 21 may have a rectangular or square outer shape as shown in the top view of fig. 1, but is not necessarily limited thereto, the size of the substrate 21 is not particularly limited and may be variously selected, in the present embodiment, the substrate 21 may be, for example, 800 × 800 μm²Above, especially 1100 × 1100 μm²。

The first conductive type semiconductor layer 23 is disposed on the substrate 21. The first conductive type semiconductor layer 23 is a layer grown on the substrate 21, and includes a gallium nitride based semiconductor layer doped with an impurity, for example, Si.

An active layer 25 and a second conductive type semiconductor layer 27 are disposed on the first conductive type semiconductor layer 23. The active layer 25 is disposed between the first conductive type semiconductor layer 23 and the second conductive type semiconductor layer 27. The active layer 25 and the second conductive type semiconductor layer 27 may have a smaller area than the first conductive type semiconductor layer 23. The active layer 25 and the second conductive type semiconductor layer 27 may be mesa-formed on the first conductive type semiconductor layer 23 by mesa etching. Thereby, an upper portion of the first conductive type semiconductor layer 23 is exposed. For example, the first conductive type semiconductor layer 23 may be exposed along the mesa circumference. In addition, the mesa may be formed in various shapes, and the region where the first conductive type semiconductor layer 23 is exposed may be variously deformed according to the mesa shape. The mesa may further have a through hole 30a penetrating the second conductive type semiconductor layer 27 and the active layer 25 as shown in fig. 1 and 2. The through-hole 30a surrounds the second conductive type semiconductor layer 27 and the active layer 25. In the present embodiment, the through-hole 30a has a substantially circular shape, but the present invention is not limited thereto and may have various shapes.

The active layer 25 may have a single quantum well structure or a multiple quantum well structure. In the active layer 25, the composition and thickness of the well layer determine the wavelength of the generated light. In particular, by adjusting the composition of the well layer, an active layer that generates ultraviolet, blue, or green light can be provided.

On the other hand, the second conductivity type semiconductor layer 27 includes a gallium nitride based semiconductor layer doped with a p-type impurity, for example, Mg. The first conductive type semiconductor layer 23 and the second conductive type semiconductor layer 27 may be single layers, but are not limited thereto, and may be multiple layers or include a superlattice layer. The first conductive type semiconductor layer 23, the active layer 25, and the second conductive type semiconductor layer 27 may be formed by growing on the substrate 21 in a chamber by a known method such as Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE).

On the other hand, the ZnO layer 31 is disposed on the second conductive type semiconductor layer 27, and is electrically in contact with the second conductive type semiconductor layer 27. The ZnO layer 31 may be disposed across almost the entire region of the second conductive type semiconductor layer 27 in an upper region of the second conductive type semiconductor layer 27. However, although fig. 1 shows that the boundary of the ZnO layer 31 overlaps with the second conductivity type semiconductor layer 27, the boundary does not necessarily overlap completely. That is, the boundary of the ZnO layer 31 may be located inside the region surrounded by the boundary of the second conductive type semiconductor layer 27, and thus the region of the ZnO layer 31 may be smaller than the region of the second conductive type semiconductor layer 27.

The ZnO layer 31 may be formed by a hydrothermal synthesis method, and thus, the lower region of the ZnO layer 31 may have more cavities than the upper region.

The lower insulating layer 33 covers the ZnO layer 31 and covers the mesa. The lower insulating layer 33 exposes a partial region of the first conductive type semiconductor layer 23. For example, the lower insulating layer 33 may expose the first conductive type semiconductor layer 23 along the mesa circumference. The lower insulating layer 33 has an opening 33a that exposes the first conductive type semiconductor layer 23 in the through hole 30 a.

On the other hand, the lower insulating layer 33 further has an opening 33b exposing the ZnO layer 31. The opening 33b is defined in the ZnO layer 31. The plurality of openings 33b may be arranged on the ZnO layer 31. The thickness T2 of the ZnO layer 31 located below the opening 33b of the lower insulating layer 33 is smaller than the thickness T1 of the ZnO layer 31 covered by the lower insulating layer 33. For example, the thickness T2 of the ZnO layer 31 may be 40nm to 100nm less than the thickness T1 of the ZnO layer 31. However, the thickness T2 of the ZnO layer 31 may be 100nm or more, and thus, good ohmic characteristics may be maintained. The upper limit of the thickness T2 of the ZnO layer 31 is not particularly limited, and may be 500nm or less, for example.

On the other hand, since the ZnO layer 31 has more cavities in the lower region than the upper region thereof, the ZnO layer 31 having the thickness T2 has a refractive index smaller than the ZnO layer 31 having the thickness T1. As a result, the difference in refractive index between the second conductive type semiconductor layer 27 and the ZnO layer 31 under the opening 33b is larger than the difference in refractive index between the second conductive type semiconductor layer 27 and the ZnO layer 31 in the other region. Therefore, in the interface between the second conductive type semiconductor layer 27 and the ZnO layer 31, the critical angle at which total internal reflection occurs is smaller in the region below the opening 33b than in the other regions, and more total internal reflection occurs.

The lower insulating layer 33 may include silicon oxide or silicon nitride. The lower insulating layer 33 may be formed as a single layer or a multiple layer. Further, the lower insulating layer 33 may include a distributed bragg reflector in which first material layers having a first refractive index and second material layers having a second refractive index are alternately stacked. For example, to reflect blue generated in the active layer 25The lower insulating layer 33 may be a distributed bragg reflector having a high reflectance in a wavelength band of 400nm to 500 nm. Further, the lower insulating layer 33 may be a distributed bragg reflector having a high reflectance in the entire wavelength band of about 400nm to 700nm in order to reflect not only light generated in the active layer 25 but also visible light including light wavelength-converted by a wavelength conversion layer such as a phosphor. Here, the first material layer may be SiO₂Layer or MgF₂The layer, the second material layer may be a material layer having a higher refractive index than the first material layer. The second layer of material may be, for example, TiO₂、Nb₂O₅Or ZrO₂. A single first material layer and a single second material layer may be alternately stacked, but not limited thereto, and two or more first material layers or two or more second material layers may be used.

A first pad metal layer 35a and a second pad metal layer 35b are disposed on the lower insulating layer 33. A boundary area 35ab, where the lower insulating layer 33 is exposed, may be formed between the first pad metal layer 35a and the second pad metal layer 35 b.

The first pad metal layer 35a surrounds the second pad metal layer 35b, covers the lower insulating layer 33, and is in contact with the first conductive type semiconductor layer 23 exposed through the opening 33a of the lower insulating layer 33. the first pad metal layer 35a can be in contact with the first conductive type semiconductor layer 23 along the mesa circumference, thereby enabling current distribution over a wide area of the first conductive type semiconductor layer 23. furthermore, the first pad metal layer 35a can be in contact with the first conductive type semiconductor layer 23 in the through hole 30a formed inside the mesa, and the first pad metal layer 35a can be in contact with the first conductive type semiconductor layer 23 in the mesa circumference and the through hole 30a, thereby enabling 800 μm 800 × 800 μm in particular²The current dispersion performance is improved in the above large-sized light emitting diode.

The second pad metal layer 35b is in contact with the ZnO layer 31 through the opening 33b of the lower insulating layer 33. The first pad metal layer 35a and the second pad metal layer 35b may be formed of the same material through the same process. Further, as shown in the figure, the second pad metal layer 35b may be arranged in divided portions. Each portion of the second pad metal layer 35b is in contact with the ZnO layer 31 through the opening 33b of the lower insulating layer 33. On the other hand, the first pad metal layer 35a may surround respective portions of the second pad metal layer 35 b. Therefore, most of the area of the lower insulating layer 33 except for the boundary area 35ab is covered with the first pad metal layer 35a and the second pad metal layer 35 b.

The first and second pad metal layers 35a, 35b may include a reflective layer such as an Ag layer or an Al layer, and the reflective layer may be formed on an adhesive layer of Ti, Cr, Ni, or the like. Especially, when the lower insulating layer 33 is made of SiO₂Such as a transparent insulating layer, the first and second pad metal layers 35a, 35b include a metal reflective layer. On the other hand, a protective layer having a single-layer or composite-layer structure of Ni, Cr, Au, or the like may be formed on the reflective layer.

On the other hand, since the refractive index of the ZnO layer 31 under the opening 33b is smaller than that of the ZnO layer 31 in the other region, the amount of light incident on the second pad metal layer 35b from the region under the opening 33b through the ZnO layer 31 can be reduced. Therefore, light loss caused by the second pad metal layer 35b can be reduced.

The upper insulating layer 37 covers the first and second pad metal layers 35a, 35 b. The upper insulating layer 37 also covers the boundary area 35ab between the first pad metal layer 35a and the second pad metal layer 35 b. Further, the upper insulating layer 37 may cover the side of the first pad metal layer 35a along the mesa circumference.

The upper insulating layer 37 has a first opening portion 37a exposing the first pad metal layer 35a and a second opening portion 37b exposing the second pad metal layer 35 b. The upper insulating layer 37 may have a plurality of first opening portions 37a and a plurality of second opening portions 37 b. The first opening portion 37a may be disposed to overlap the through hole 30a and the opening portion 33a of the lower insulating layer, and the second opening portion 37b may be disposed to overlap the opening portion 33b of the lower insulating layer 33. However, the present invention is not limited thereto, and the first opening portion 37a and the second opening portion 37b may be laterally spaced apart from the opening portions 33a, 33b of the lower insulating layer 33.

On the other hand, the upper insulating layer 37 covers the side surface of the first pad metal layer 35a, preventing the side surface of the first pad metal layer 35a from being exposed. The upper insulating layer 37 may be formed to entirely cover the first conductive type semiconductor layer 23 located on the periphery of the mesa surface, or may be formed to expose the first conductive type semiconductor layer 23.

The upper insulating layer 37 may be made of SiO₂Or Si₃N₄Is formed. In particular, the upper insulating layer 37 may be of Si₃N₄Is formed.

On the other hand, the first bump pad 39a may be in electrical contact with the first pad metal layer 35a exposed through the first opening 37a of the upper insulating layer 37, and the second bump pad 39b may be in electrical contact with the second pad metal layer 35b exposed through the second opening 37 b. The first bump land 39a covers and seals the entire first opening 37a of the upper insulating layer 37, and the second bump land 39b covers and seals the entire second opening 37b of the upper insulating layer 37.

As shown in fig. 1, the first bump pad 39a and the second bump pad 39b may be formed across portions of the second pad metal layer 35 b. According to this arrangement, the current can be easily dispersed across a wide area of the light emitting diode by the second pad metal layer 35 b.

The first bump pad 39a and the second bump pad 39b may be formed of solder or AuSn.

On the other hand, the structure of the light emitting diode is more clearly described by the method of manufacturing the light emitting diode described below.

Fig. 4a to 4e are schematic plan views for explaining a method of manufacturing a light emitting diode according to the embodiment of fig. 1 to 3.

First, referring to fig. 2, 3, and 4a, a semiconductor stack 30 including a first conductive type semiconductor layer 23, an active layer 25, and a second conductive type semiconductor layer 27 is grown on a substrate 21. The substrate 21 is not particularly limited as long as it is a substrate on which a gallium nitride semiconductor layer can be grown.

The first conductive type semiconductor layer 23 may include, for example, an n-type gallium nitride-based layer, and the second conductive type semiconductor layer 27 may include a p-type gallium nitride-based layer. On the other hand, the active layer 25 may be a single quantum well structure or a multiple quantum well structure, and may include a well layer and a barrier layer. In addition, the well layer may have its constituent elements selected according to a desired wavelength of light, and may include, for example, AlGaN, GaN, or InGaN.

Next, a ZnO layer 31 is formed on the semiconductor stacked body 30. The ZnO layer 31 may be formed on the second conductive type semiconductor layer 27 by a hydrothermal synthesis method using a seed layer after the second conductive type semiconductor layer 27 is grown. That is, a ZnO seed layer may be formed on the second conductive semiconductor layer 27, and a ZnO bulk layer may be formed thereon by hydrothermal synthesis. The ZnO seed layer may be formed by hydrothermal synthesis, sputtering, or sol-gel method. Thus, the ZnO layer 31 can be formed of a film-like continuous single crystal, and thus can provide a transparent electrode layer having a very low light absorption rate. In particular, by forming the ZnO seed layer by a sol-gel method, the interface characteristics between the ZnO layer 31 and the second conductive type semiconductor layer 27 can be improved, and the forward voltage of the light emitting diode can be reduced, thereby improving the reliability.

For example, the ZnO layer 31 may be formed by hydrothermal synthesis using a solution containing a ZnO precursor, and the ZnO layer 31 formed by hydrothermal synthesis may be formed on N₂The heat treatment is carried out under an atmosphere at a temperature of about 200 to 300 ℃. By the heat treatment, the surface resistance of the ZnO layer 31 can be reduced, and the light transmittance can be improved. The ZnO layer 31 can be formed, for example, about due to low light absorptionTo a relatively large thickness in the range of about 1 μm.

On the other hand, the ZnO layer 31 may contain a dopant. The ZnO layer 31 may include a metallic dopant, and may include at least one of silver (Ag), indium (In), tin (Sn), zinc (Zn), cadmium (Cd), gallium (Ga), aluminum (Al), magnesium (Mg), titanium (Ti), molybdenum (Mo), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), iridium (Ir), ruthenium (Ru), and palladium (Pd), for example. In one embodiment, the ZnO layer 31 may be formed of Ga-doped ZnO (gzo). The ZnO layer 31 contains a metallic dopant, and thus can reduce the surface resistance and more uniformly disperse the current in the horizontal direction. However, the present invention is not limited thereto, and the ZnO layer 31 may be formed of undoped ZnO.

After the ZnO layer 31 is formed, the ZnO layer 31 and the semiconductor stacked body 30 are patterned to form a mesa. In fig. 4a, reference numeral 27(31) denotes a boundary region of the mesa, reference numeral 30a denotes a through hole 30a, and the through hole 30a penetrates the second conductive type semiconductor layer 27 and the active layer 25 to expose the first conductive type semiconductor layer 23.

The ZnO layer 31 may be patterned by wet etching using a photolithography pattern, and the second conductive type semiconductor layer 27 and the active layer 25 may be dry etched using the same photolithography pattern, forming a mesa together with the through hole 30 a. Since the ZnO layer 31 is patterned by wet etching, the boundary of the ZnO layer 31 may be located inside of the boundary of the second conductive type semiconductor layer 27.

On the other hand, an upper face of the first conductive type semiconductor layer 23 is partially exposed along the mesa circumference. In order to improve current dispersion, the through-holes 30a may be arranged at a plurality of portions of the mesa.

Referring to fig. 2, 3 and 4b, a lower insulating layer 33 covering the ZnO layer 31 and the mesa is formed. The lower insulating layer 33 covers, in particular, the side surfaces of the mesa, preventing the second conductive type semiconductor layer 27 and the active layer 25 from being exposed.

The lower insulating layer 33 may be formed of a transparent insulating layer or a distributed bragg reflector. The lower insulating layer 33 may be formed using a technique such as a chemical vapor deposition technique or an electron beam evaporation method.

On the other hand, the lower insulating layer 33 may be patterned using photolithography and etching techniques. By patterning the lower insulating layer 33, an opening 33a for exposing the first conductive type semiconductor layer 23 and an opening 33b for exposing the ZnO layer 31 are formed in the through hole 30a, and the first conductive type semiconductor layer 23 is exposed along the mesa circumference. In fig. 4b, the first conductive type semiconductor layer 23 is shown to be continuously exposed in a ring shape along the circumference of the mesa, but the present invention is not limited thereto and may be intermittently exposed at a plurality of portions at the circumference of the mesa.

However, since the ZnO layer 31 is vulnerable to an acidic solution, the lower insulating layer 33 is patterned using a dry etching technique instead of wet etching. On the other hand, the ZnO layer 31 exposed under the opening 33b of the lower insulating layer 33 becomes thinner as the lower insulating layer 33 is excessively etched. The thickness T2 of the ZnO layer under the lower insulating layer 33 may be approximately 40nm to 100nm smaller than the thickness T1 of the ZnO layer 31 covered by the lower insulating layer 33 without being etched. However, the thickness T2 of the ZnO layer under the opening 33b can be kept approximately 100nm to 500nm, and thus, good ohmic characteristics can be ensured.

Referring to fig. 2, 3 and 4c, a first pad metal layer 35a and a second pad metal layer 35b are formed on the lower insulating layer 33.

The first pad metal layer 35a electrically contacts the first conductive type semiconductor layer 23 exposed through the opening 33a of the lower insulating layer 33. For example, the first pad metal layer 35a is in contact with the first conductive type semiconductor layer 23 exposed along the mesa circumference, and is in contact with the first conductive type semiconductor layer 23 exposed through the opening portion 33a in the through hole 30 a. The first pad metal layer 35a may be continuous as shown, but is not limited thereto and may be divided into a plurality of portions.

The first pad metal layer 35a is formed over a wide area, and can easily disperse current in the light emitting diode.

The second pad metal layer 35b covers the opening 33b of the lower insulating layer 33 and is in contact with the ZnO layer 31. The second pad metal layer 35b may include a plurality of portions spaced apart from each other. Each part of the second pad metal layer 35b is in contact with the ZnO layer 31. In the present embodiment, although the second pad metal layer 35b is illustrated and described as being divided into a plurality of portions, it is not limited thereto, and a single relatively wide second pad metal layer 35b may cover the entirety of the plurality of opening portions 33 b.

A boundary area 35ab is formed between the first pad metal layer 35a and the second pad metal layer 35b, and the lower insulating layer 33 is exposed at the boundary area 35 ab.

The first pad metal layer 35a and the second pad metal layer 35b may be formed together in the same process with the same material. For example, the first and second pad metal layers 35a, 35b may be formed using a lift-off technique.

The first pad metal layer 35a and the second pad metal layer 35b may include Ti, Cr, Ni, or the like as an adhesive layer, and may include a metal reflective layerContains Ag or Al. Further, the first pad metal layer 35a and the second pad metal layer 35b may contain Au as an oxidation preventing layer. The first pad metal layer 35a and the second pad metal layer 35b may be made of, for example, Cr/Al/Ni/Ti/Ni/Ti/Au(2μm)/TiAnd (4) forming.

Referring to fig. 2, 3 and 4d, an upper insulating layer 37 covering the first and second pad metal layers 35a and 35b is formed. The upper insulating layer 37 also covers the first conductive type semiconductor layer 23 along the mesa circumference. The upper insulating layer 37 may be made of SiO₂Or Si₃N₄Etc. are formed to protect the first and second pad metal layers 35a, 35 b.

The upper insulating layer 37 may be patterned using photolithography and etching techniques, thereby forming a first opening portion 37a exposing the first pad metal layer 35a and a second opening portion 37b exposing the second pad metal layer 35 b. Further, the upper insulating layer 37 is removed along the circumference of the mesa, and the first conductive type semiconductor layer 23 or the substrate 21 can be exposed at the edge portion of the substrate 21.

As shown in fig. 4d, the first opening portion 37a and the second opening portion 37b are arranged opposite to each other in the region above the mesa. For example, the first opening portion 37a is arranged near the upper side edge, and the second opening portion 37b is arranged near the lower side edge.

Referring to fig. 2, 3 and 4e, first bump pads 39a and second bump pads 39b are formed on the upper insulating layer 37, and the substrate 21 is divided, thereby completing the light emitting diode shown in fig. 1 to 3. The upper insulating layer 37 of the scribe line portion for dividing the substrate 21 may be removed in advance, and thus, the first conductive type semiconductor layer 23 or the upper surface of the substrate 21 may be exposed at the edge of the light emitting diode.

On the other hand, the first bump pad 39a is electrically connected to the first pad metal layer 35a through the opening 37a of the upper insulating layer 37, and the second bump pad 39b is electrically connected to the second pad metal layer 35b through the opening 37b of the upper insulating layer 37.

The first and second bump pads 39a, 39b may be formed using a lift-off technique, for example, may be formed using AuSn or solder.

Fig. 5 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention, fig. 6 is a sectional view taken along a cut-off line C-C 'of fig. 5, and fig. 7 is a sectional view taken along a cut-off line D-D' of fig. 5.

Referring to fig. 5, 6 and 7, the light emitting diode according to the present embodiment is substantially similar to the light emitting diode described above with reference to fig. 1 to 3, but differs in the shape of the light emitting diode and the mesa, the positions of the openings 33a and 33b of the lower insulating layer 33, and the shapes of the openings 37a and 37b of the upper insulating layer 37, and further, in the present embodiment, the first and second bump pads 39a and 39b are omitted. Hereinafter, differences from the above-described examples will be mainly described.

First, the light emitting diode according to the present embodiment is a small light emitting diode having a long axis direction and a short axis direction, and a length of the long axis direction is 600 μm or less, for example, the light emitting diode may have a length of 540 × 240 μm or less, for example²The size of (c).

Further, in the above-described embodiment, the edge of the substrate 21 and the edge of the first conductive type semiconductor layer 23 are shown to coincide, but in the present embodiment, the edge of the first conductive type semiconductor layer 23 is located inside the region surrounded by the edge of the substrate 21.

On the other hand, a mesa is located on the first conductivity type semiconductor layer 23, and a ZnO layer 31 is disposed on the mesa. Reference numerals 27(31) denote the outer shapes of the mesas. As described above, the boundary of the ZnO layer 31 may be located inside the second conductive type semiconductor layer 27.

Although the mesa has a long rectangular shape, a plurality of grooves are formed in the side surface. However, in this embodiment, the through hole (30 a in fig. 1) surrounded by the second conductive type semiconductor layer 27 and the active layer 25 is omitted.

On the other hand, the lower insulating layer 33 has openings 33a, 33b, and the openings 33a are intermittently arranged along the circumference of the mesa. The opening portions 33a may be arranged near the sides of the stage surface in the long axis direction, and near the four corners of the stage surface. The opening portion 33a may have a long shape and be arranged in the vicinity of the groove portion of the mesa.

On the other hand, the opening 33b is located in the mesa upper region and exposes the ZnO layer 31. The openings 33b may be arranged on the center line along the long axis direction of the light emitting diode. By arranging the openings 33a on the side surfaces of the mesa and arranging the openings 33b on the center line, the current can be uniformly dispersed in the light emitting diode.

A first pad metal layer 35a and a second pad metal layer 35b are disposed on the lower insulating layer 33, the first pad metal layer 35a surrounding the second pad metal layer 35 b. In the present embodiment, a single second pad metal layer 35b is arranged in the region above the mesa and is in contact with the ZnO layer 31 through the opening 33 b. When the first pad metal layer 35a surrounds the second pad metal layer 35b, the opening 33a of the lower insulating layer 33 is covered, and the first conductive type semiconductor layer 23 is electrically connected thereto.

On the other hand, the second pad metal layer 35b may include a projection projecting in the long axis direction, and one of the opening portions 33b of the lower insulating layer 33 may be arranged under the projection. The first pad metal layer 35a may have a groove portion to receive the second pad metal layer 35 b. That is, it may have a shape in which the groove portion of the first pad metal layer 35a and the protrusion portion of the second pad metal layer 35b match each other. Such a shape is advantageous to sufficiently secure the first pad area.

The upper insulating layer 37 covers the first pad metal layer 35a and the second pad metal layer 35b, and has a first opening portion 37a and a second opening portion 37b that expose them, respectively. In the present embodiment, the first opening portion 37a and the second opening portion 37b may define the first pad region and the second pad region, and thus, have a relatively large size. In particular, as shown in fig. 5, the first opening portion 37a defining the first pad region has a shape of a protruding portion wrapping the second pad metal layer 35 b.

In the present embodiment, the bump pads are omitted, and the first and second pad metal layers 35a, 35b exposed through the opening portions 37a, 37b of the upper insulating layer 37 function as the bonding pads.

Fig. 8a to 8e are plan views for explaining the method of manufacturing the light emitting diode explained with reference to fig. 5 to 7. The method for manufacturing the light emitting diode according to the present embodiment is substantially the same as the method for manufacturing the light emitting diode described with reference to fig. 4a to 4e, and therefore, detailed description of the same is omitted.

Referring to fig. 6, 7, and 8a, as described with reference to fig. 4a, the semiconductor stacked body 30 is formed on the substrate 21, the ZnO layer 31 is formed thereon, and the ZnO layer 31, the second conductivity type semiconductor layer 27, and the active layer 25 are patterned to form a mesa.

The mesa is formed to have a plurality of grooves on a side surface along the longitudinal direction. Regions depressed inward are also formed at the four corners of the mesa.

Referring to fig. 6, 7 and 8b, the first conductive type semiconductor layer 23 exposed at the periphery of the mesa is patterned to expose the substrate 21. This process is commonly referred to as an isolation process. It is illustrated and described in the above embodiment that the isolation process is not additionally performed and the first conductive type semiconductor layer 23 covers the front surface of the substrate 21, but in the present embodiment, the isolation process is performed to expose the edge of the substrate 21.

Referring to fig. 6, 7, and 8c, the lower insulating layer 33 is deposited and patterned by photolithography and dry etching techniques to form openings 33a and 33 b. The lower insulating layer 33 also covers the first conductive type semiconductor layer 23 and the substrate 21 exposed at the periphery of the mesa, but an opening 33a exposing the first conductive type semiconductor layer 23 is formed in a region corresponding to the groove portion of the mesa. On the other hand, the opening 33b is formed above the ZnO layer 31 to expose the ZnO layer 31.

Referring to fig. 6, 7, and 8d, a first pad metal layer 35a and a second pad metal layer 35b are formed on the lower insulating layer 33. The first pad metal layer 35a is in contact with the first conductive type semiconductor layer 23 through the opening 33a of the lower insulating layer 33, and the second pad metal layer 35b is in contact with the ZnO layer 31 through the opening 33 b.

In the present embodiment, the lower insulating layer 33 is exposed to the outside of the first pad metal layer 35 a.

Referring to fig. 6, 7 and 8e, an upper insulating layer 37 covering the first and second pad metal layers 35a and 35b is formed. Further, the upper insulating layer 37 covers the edge of the first pad metal layer 35a, and covers the lower insulating layer 37 exposed to the outside of the first pad metal layer 35 a.

The upper insulating layer 37 may be patterned using photolithography and etching techniques, thereby forming a first opening portion 37a exposing the first pad metal layer 35a and a second opening portion 37b exposing the second pad metal layer 35 b.

Next, the substrate 21 is divided, thereby completing the light emitting diode.

Fig. 9 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention, fig. 10 is a sectional view taken along a cut line E-E 'of fig. 9, and fig. 11 is a sectional view taken along a cut line F-F' of fig. 9.

Referring to fig. 9, 10, and 11, the light emitting diode according to the present embodiment is substantially similar to the light emitting diode described above with reference to fig. 6 to 8e, and differs in that the first pad metal layer 35a is in contact with the first conductive type semiconductor layer 23 in the through hole 30a instead of being in contact with the first conductive type semiconductor layer 23 along the mesa circumference.

That is, the mesa is formed in a rectangular shape with smooth side surfaces, and a through hole 30a is formed to penetrate the second conductive type semiconductor layer 27 and the active layer 25 and expose the first conductive type semiconductor layer 23. In the present embodiment, the through-hole 30a has a shape elongated along the long axis direction of the light emitting diode, but the present invention is not limited thereto, and a plurality of through-holes 30a may be arranged along the long axis direction.

The ZnO layer 31 is on the mesa, the ZnO layer 31 having the same shape as the mesa.

The lower insulating layer 33 covers the ZnO layer 31 and the mesa, and covers the first conductive type semiconductor layer 23 and the substrate 21 exposed at the circumference of the mesa. The lower insulating layer 33 has an opening 33a that exposes the first conductive type semiconductor layer 23 in the through hole 30a, and an opening 33b that exposes the ZnO layer 31. The opening 33a is formed in a shape similar to the through-hole 30a, and the opening 33b is arranged around the through-hole 30 a.

The first pad metal layer 35a is in contact with the first conductive type semiconductor layer 23 exposed in the through hole 30a, and the second pad metal layer 35b is in contact with the ZnO layer 31 exposed in the opening 33 b. In the present embodiment, the first pad metal layer 35a does not surround the second pad metal layer 35 b. Further, the first pad metal layer 35a includes a narrow and long protruding region, and the second pad metal layer 35b has a groove portion that accommodates the narrow and long region of the first pad metal layer 35 a.

On the other hand, the upper insulating layer 37 covers the first and second pad metal layers 35a, 35b and covers the lower insulating layer 33 exposed at the periphery of the mesa. Further, the upper insulating layer 37 has a first opening portion 37a exposing the first pad metal layer 35a and a second opening portion 37b exposing the second pad metal layer 35b, and these first and second opening portions 37a and 37b define a first pad region and a second pad region, respectively.

In the present embodiment, the second pad region has a shape wrapping the first pad metal layer 35a, and the first pad region includes a protruding region along the long axis direction.

Fig. 12a to 12e are schematic plan views for explaining the method of manufacturing the light emitting diode described with reference to fig. 9 to 11. The method of manufacturing the light emitting diode according to the present embodiment is substantially similar to the method of manufacturing the light emitting diode described with reference to fig. 8a to 8e, but there is a difference in that the mesa is formed to have the through hole 30 a.

First, referring to fig. 10, 11, and 12a, a semiconductor stacked body 30 is formed on a substrate 21, a ZnO layer 31 is formed thereon, and the ZnO layer 31, the second conductivity type semiconductor layer 27, and the active layer 25 are patterned to form a mesa.

The mesa side surface may be formed smoothly, and a through hole 30a having a shape elongated in the longitudinal direction may be formed inside. The through-hole 30a is surrounded by the second conductive type semiconductor layer 27 and the active layer 25. Both ends of the through-hole 30a in the longitudinal direction have a smooth shape. On the other hand, in order to sufficiently secure the size of the second pad region, the end of the through-hole 30a near the second pad region may be formed relatively small.

Referring to fig. 10, 11 and 12b, the first conductive type semiconductor layer 23 exposed at the circumference of the mesa is patterned through an isolation process to expose the substrate 21.

Referring to fig. 10, 11, and 12c, the lower insulating layer 33 is deposited and patterned by photolithography and dry etching techniques to form openings 33a and 33 b. The lower insulating layer 33 also covers the first conductive type semiconductor layer 23 and the substrate 21 exposed at the circumference of the mesa. The opening 33a exposes the first conductive type semiconductor layer 23 in the through hole 30a, and the opening 33b is formed above the ZnO layer 31 to expose the ZnO layer 31.

Referring to fig. 10, 11, and 12d, a first pad metal layer 35a and a second pad metal layer 35b are formed on the lower insulating layer 33. The first pad metal layer 35a is in contact with the first pad metal layer 35a through the opening 33a of the lower insulating layer 33, and the second pad metal layer 35b is in contact with the ZnO layer 31 through the opening 33 b.

In the present embodiment, the lower insulating layer 33 is exposed at the outer sides of the first and second pad metal layers 35a and 35 b. Further, in the present embodiment, the first pad metal layer 35a and the second pad metal layer 35b are laterally spaced apart from each other by the boundary area 35ab, and the first pad metal layer 35a does not surround the second pad metal layer 35 b. However, the present invention is not limited to this, and the first pad metal layer 35a may surround the second pad metal layer 35b, and conversely, the second pad metal layer 35b may surround the first pad metal layer 35 a.

Referring to fig. 10, 11, and 12e, an upper insulating layer 37 is formed covering the first and second pad metal layers 35a and 35 b. Further, the upper insulating layer 37 covers edges of the first and second pad metal layers 35a and 35b and covers the lower insulating layer 33 exposed at outer sides of the first and second pad metal layers 35a and 35 b.

The upper insulating layer 37 may be patterned using photolithography and etching techniques, thereby forming a first opening portion 37a exposing the first pad metal layer 35a and a second opening portion 37b exposing the second pad metal layer 35 b.

Next, the substrate 21 is divided, thereby completing the light emitting diode.

Fig. 13 is a schematic top view for explaining a light emitting diode according to still another embodiment of the present invention, and fig. 14 is a sectional view taken along a cut line G-G' of fig. 13.

Referring to fig. 13 and 14, the light emitting diode according to the present embodiment is substantially similar to the light emitting diode described above with reference to fig. 1 to 3, and there is a difference in omitting the first pad metal layer 35a and the second pad metal layer 35 b. Hereinafter, differences from the above-described examples will be mainly described.

First, the light emitting diode according to the present embodiment is a small light emitting diode having a long axis direction and a short axis direction, and a length of the long axis direction is 600 μm or less.

In addition, in the present embodiment, the edge of the first conductive type semiconductor layer 23 may be located inside the region surrounded by the edge of the substrate 21.

On the other hand, a mesa is located on the first conductivity type semiconductor layer 23, and a ZnO layer 31 is disposed on the mesa. Reference numerals 27(31) denote the outer shapes of the mesas. The ZnO layer 31 may have a planar shape similar to the second conductive type semiconductor layer 27. As shown in fig. 14, the boundary of the ZnO layer 31 may be located inside the second conductive type semiconductor layer 27.

The mesa has a substantially long rectangular shape along the substrate 21, but may have a recessed portion exposing the first conductive type semiconductor layer 23. However, this embodiment is not limited to this, and a through hole surrounded by the second conductive type semiconductor layer 27 and the active layer 25 may be formed in the mesa.

On the other hand, the lower insulating layer 33 covers the mesa and the ZnO layer 31. In addition, the lower insulating layer 33 may cover the first conductive type semiconductor layer 23 and the substrate 21. The lower insulating layer 33 has openings 33a and 33b, the opening 33a exposes the first conductive type semiconductor layer 23, and the opening 33b exposes the ZnO layer 31 on the mesa surface. As shown, the opening portions 33a, 33b may be arranged to face each other along the long axis direction.

The lower insulating layer 33 may be formed of various materials and structures as described above, and particularly, may be formed of a distributed bragg reflector. As described with reference to fig. 3, the thickness of the ZnO layer 31 located below the opening 33b of the lower insulating layer 33 is smaller than the thickness of the ZnO layer covered by the lower insulating layer 33. Since the ZnO layer 31 has more cavities in the lower region than in the upper region, the refractive index of the ZnO layer 31 located below the opening 33b is smaller than that of the ZnO layer 31 in the other region. Thus, the amount of light incident on the ZnO layer 31 through the region below the opening 33b can be reduced by total internal reflection, and the light loss due to the second bump pad 139b can be reduced.

On the other hand, the first bump pads 139a and the second bump pads 139b are directly disposed on the lower insulating layer 33. That is, the first pad metal layer 35a and the second pad metal layer 35b mentioned in the above embodiments are omitted. Further, the upper insulating layer 37 may be omitted.

As shown in fig. 13, the widths of the first and second bump pads 139a and 139b may be smaller than the width of the mesa. Further, the second bump pads 139b may be arranged to be defined in the upper region of the mesa, but are not limited thereto.

According to the present embodiment, the first pad metal layer and the second pad metal layer are omitted, so that a light emitting diode of a simpler structure can be provided.

The light emitting diode according to the above-described embodiment can be used for various purposes, for example, various application fields such as a large-scale natural color flat panel display device, a signal lamp, an indoor lighting, an automobile headlamp, a high-density light source, a high-resolution output system, and optical communication, and in particular, the small light emitting diode described with reference to fig. 5 to 7, 9 to 11, or 13 and 14 can be effectively used for an L ED filament bulb, etc. conventionally, the light emitting diode used for a L ED filament bulb is electrically connected using a bonding wire, and when the filament is not a flat plate but a bent or flexible filament, the wire may be broken to cause a defect.

Fig. 15 is a schematic cross-sectional view for explaining an L ED lamp according to an embodiment of the present invention.

Referring to fig. 15, the L ED lamp includes a bulb socket 3000, a center post 3100, a L ED filament 3200, and a light transmissive bulb 3300.

The bulb socket 3000 may have the same electrode structure as that used in a conventional light bulb (light bulb). In addition, passive and active elements such as an AC/DC converter may be incorporated in the bulb socket 3000.

Since the bulb socket 3000 has the same electrode structure as a conventional bulb, the L ED lamp according to the embodiment of the present invention can use a conventional socket, and thus can save the additional equipment installation cost associated with the use of the L ED lamp.

The central post 3100 is fixed to the bulb socket 3000 and arranged in the center of an L ED lamp the central post 3100 may comprise a support portion, a post portion and an upper end portion the central post 3100 is for supporting L ED filament 3200, which may be formed of glass, for example.

L ED filament 3200 is a flexible light strip, including a base, conductive wiring, and light emitting diodes the small light emitting diodes described with reference to fig. 5 to 7, 9 to 11, or 13 and 14. L ED filament 3200 is formed from a flexible light strip, so that L ED filament 3200 can be deformed in various shapes.

On the other hand, the L ED filament 3200 may be electrically connected to an electrode of the bulb holder 3000 by a lead wire, not shown.

The light-transmissive bulb 3300 encloses L ED filament 3200, and is separated from the external environment, the light-transmissive bulb 3300 may be formed of glass or plastic, and the light-transmissive bulb 3300 may have various shapes, or may have the same shape as that of a conventional bulb.

While various embodiments of the present invention have been described above, the present invention is not limited to these embodiments. Note that the contents and constituent elements described in one embodiment can be applied to other embodiments without departing from the technical idea of the present invention.