阅读说明：本技术 补偿非易失存储元件编程时电荷流失与源极线偏置的方法 (Method for compensating charge loss and source line bias during programming of nonvolatile memory element ) 是由 杜君毅 蔡明璋 翁瑞隆 于 2019-01-31 设计创作，主要内容包括：一种补偿非易失性存储元件在编程时电荷流失与源极线偏置的方法,其步骤包含以第一参考电压读取前次编程页来产生原前次编程模式、将该原前次编程模式与当前编程模式合并以产生合并后编程模式、以第二参考电压读取该前次编程页来产生检验后前次编程模式、以及将该检验后前次编程模式与该合并后编程模式合并以产生补偿后当前编程模式,其中该第二参考电压高于该第一参考电压。(A method for compensating charge loss and source line bias during programming of a non-volatile memory device includes reading a previous program page at a first reference voltage to generate an original previous program pattern, merging the original previous program pattern with a current program pattern to generate a merged subsequent program pattern, reading the previous program page at a second reference voltage to generate a verified previous program pattern, and merging the verified previous program pattern with the merged subsequent program pattern to generate a compensated current program pattern, wherein the second reference voltage is higher than the first reference voltage.)

1. A method for compensating for charge loss and source line bias in programming a non-volatile memory device, comprising:

reading a previous programming page with a first reference voltage to generate an original previous programming mode, wherein the previous programming page comprises a plurality of memory cells;

merging the original previous programming mode with the current programming mode to generate a merged programming mode;

reading the previous programming page with a second reference voltage to generate a post-verification previous programming mode; and

the post-verify previous programming mode is merged with the merged programming mode to generate a compensated current programming mode, wherein the second reference voltage is higher than the first reference voltage.

2. The method of claim 1, wherein reading the previously programmed page with the first reference voltage to generate the previously programmed mode further comprises:

reading the voltage of each memory cell in the previously programmed page, the memory cell being in the "L" state when the voltage of the memory cell is lower than the first reference voltage, the memory cell being in the "H" state when the voltage of the memory cell is higher than the first reference voltage, and

the original previous programming pattern is stored at the first node.

3. The method of claim 2, wherein the step of combining the previous programming pattern with the current programming pattern to generate the combined post-programming pattern further comprises:

loading the current programming mode to a second node, wherein the second node is connected to a drain of a combining gate having a source connected to a first voltage;

controlling the merge gate according to the previous programming mode, wherein the merge gate is turned on when the memory cell in the previous programming mode is in the "H" state, and the merge gate is turned off when the memory cell in the previous programming mode is in the "L" state.

4. The method of claim 3, wherein reading said previously programmed page at said second reference voltage to generate said verify-before-program mode further comprises:

reading the voltage of each memory cell in the previously programmed page, the memory cell being in the "L" state when the voltage of the memory cell is lower than the second reference voltage, the memory cell being in the "H" state when the voltage of the memory cell is higher than the second reference voltage, and

the verified previous programming pattern is stored at the second node.

5. The method of claim 4, wherein merging said verify-before-program mode with said merged-after-program mode to generate said compensated current program mode further comprises:

controlling the merge gate according to the merged programming mode, the merge gate being turned on when the memory cell in the merged programming mode is in the "H" state and turned off when the memory cell in the merged programming mode is in the "L" state, wherein the source of the merge gate is connected to a second voltage.

6. The method of claim 1, wherein the first reference voltage is used to determine whether each memory cell is "H" or "L" and the second reference voltage is the lowest distribution voltage default in the distribution curve of the number of bits in "H" state under ideal conditions.

7. The method of claim 6, wherein said first reference voltage is 0V.

8. The method of claim 6, wherein the second reference voltage is 1.8 volts.

9. The method of claim 6, wherein a difference between the second reference voltage and the first reference voltage is a default discrimination margin for a mode of reading the memory cell.

10. The method of claim 1, further comprising performing a current programming operation according to the compensated current programming mode.

Technical Field

The present invention relates generally to a method of programming a non-volatile memory device, and more particularly, to a method of programming a non-volatile memory device to compensate for charge loss and source line bias after multiple programming.

Background

Solid-state memories (solid-state memories) capable of storing electrical charges in a non-volatile manner, particularly in the form of electrically erasable programmable read-only memories (EEPROMs) and flash EEPROMs, are recently becoming the storage solution of choice for a variety of mobile or handheld devices, particularly information devices and consumer electronics. Unlike Random Access Memory (RAM), which is also a solid-state memory, flash memory is non-volatile in nature, and is capable of retaining stored data even after power is turned off. Despite the higher cost, an increasingly high proportion of flash memory is used in mass storage applications. Whether built-in or external, flash memory is very suitable for use in mobile or handheld device storage applications because of its advantages of small size, low power consumption, high speed, high reliability, etc.

The EEPROM or Erasable Programmable Read Only Memory (EPROM) is a type of nonvolatile memory, in which data stored in a memory cell can be erased and new data can be written or "programmed". Both employ a (unconnected) floating gate in a field effect transistor structure that is placed in the semiconductor substrate over the channel region between the source and drain. A control gate is provided over the floating gate, and the threshold voltage characteristics of the transistor are controlled by the amount of charge retained in the floating gate. That is, when the amount of charge in the floating gate is at a certain level, a corresponding threshold voltage must be applied to the control gate to open the transistor, so that current can flow between the source and the drain.

One common problem with non-volatile memory devices is charge loss. The programmed memory cell has an individual accumulated charge that is held in the cell in sufficiently discrete quantum domain form that the programmed state of the cell can be clearly and accurately determined when a threshold read voltage is applied to the programmed memory cell. When accessing data in high speed and high performance mode, the amount of charge accumulated in a programmed flash memory cell changes over time (charge drift). Various environmental or operational factors may affect the charge drift rate in a flash memory cell. In particular, the charge loss of a memory cell after maintaining its programmed state for a certain period of time can occur, and the charge level in the cell is continuously shifted down with the leakage of the floating gate. For example, the intrinsic charge loss is caused by electrons leaking from the tunnel oxide layer adjacent to the floating gate after the memory cell is subjected to a programming pulse.

V L is the lowest distribution voltage in the number distribution of an ideal program state (shown as a dashed line) and VR is the reference voltage for reading, such as 0 volts, which is used as a decision level to divide the cell into a first program state (e.g., "H" state) or a second program state (e.g., "L") based on the read voltage, the spacing M1 between the lowest distribution voltage V L and the reference voltage VR is predetermined to avoid a read error decision margin, it can be seen from the figure that the charge loss problem results in a portion of the number distribution curve extending toward the decision margin region (shown as a solid line), which results in a portion of the cell that would have been divided into "H" states (less conductive) being mistakenly divided into "H" states (more conductive L), in other words, the charge loss problem reduces the probability of a decision between different program states (e.g., M → 1), which increases the margin for reading 59 2.

Another common problem with non-volatile memory devices is source line bias, which is particularly prevalent in memory architectures that connect the sources of a large number of memory cells to a source line and ground, where a common source line is used to read the cells in parallel, thereby allowing current to flow through the source line. However, since the source line itself has a certain resistance, a certain voltage difference is generated between the real ground and the source line connected to many memory cells. During reading, the threshold voltage provided by the control gate is based on the source line, whereas the system power terminal is based on the true ground terminal, so the read and detected voltage value becomes inaccurate due to the source line bias phenomenon.

It is clear from the figure that the distribution of the quantity (shown as a dashed line) in an ideal state, including the lowest distribution voltage V L, is shifted to the left (shown as a solid line) due to the source line bias, which results in a reduced margin of discrimination between the lowest distribution voltage V L and the reference voltage VR (e.g., M1 → M2) as in the above-described charge loss.

Therefore, in view of the wide demand of high performance and high reliability of the nonvolatile memory in the market today, a programming scheme for the nonvolatile memory is needed to compensate for the charge loss and source line bias problems occurring during the memory reading and programming operations.

Disclosure of Invention

In order to solve the above problems of charge loss and source line bias error, a novel method for programming a memory cell is provided. The method is characterized by a pre-read step for marking problem cells in a previous program pattern, and a two-pattern merging step for combining and compensating a current program pattern according to a result of the verified previous program pattern generated by the pre-read step.

The method comprises reading a previous program page at a first reference voltage to generate an original previous program mode, combining the original previous program mode with a current program mode to generate a combined post program mode, reading the previous program page at a second reference voltage to generate a verified previous program mode, and combining the verified previous program mode with the combined post program mode to generate a compensated current program mode, wherein the second reference voltage is higher than the first reference voltage.

These and other objects of the present invention will become more readily apparent to the reader after reviewing the detailed description of the preferred embodiments set forth below in various figures and drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, further serve to explain the embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description of the embodiments below, serve to explain its principles. In these illustrations:

FIGS. 1A and 1B show the charge loss and source line bias phenomena of a non-volatile memory device during programming in terms of bits versus read voltage, respectively;

FIG. 2 illustrates a schematic diagram of a non-volatile memory in the form of an EEPROM cell having a floating gate for storing charge;

FIG. 3 is a schematic diagram illustrating the read/write circuits operating simultaneously on a full page of memory cells;

FIG. 4 is a flowchart of a method for compensating for charge loss and source line bias during programming of a non-volatile memory device according to a preferred embodiment of the present invention.

FIG. 5 is a diagram illustrating the operation of the pre-read module in step S1 according to the preferred embodiment of the present invention;

FIG. 6 is a diagram illustrating the operation of the pre-read module in step S2 according to the preferred embodiment of the present invention;

FIG. 7 is a diagram illustrating the operation of the pre-read module in step S3 according to the preferred embodiment of the present invention; and

FIG. 8 is a diagram illustrating the operation of the pre-read module in step S4 according to the preferred embodiment of the present invention.

It should be noted that all the figures in this specification are schematic in nature, and that for the purposes of clarity and convenience in description, components in the figures may be shown exaggerated or reduced in size or in proportion, and generally, the same reference signs are used to identify corresponding or similar components in various embodiments after change or modification.

Detailed Description

Memory devices typically include one or more memory chips mounted on a memory card, each such memory chip including an array of memory cells that assist in the operation of peripheral circuits such as decoding, erasing, writing, reading circuits, and the like. More complex memory devices may be accompanied by a controller for intelligent or advanced memory operations or interface links. There are many commercially successful non-volatile solid-state memory devices in existence today. Such memory devices may employ different types of memory cells, each of which may have one or more charge storage elements.

Fig. 2 is a schematic diagram of a non-volatile memory in the form of an electrically erasable programmable read-only memory (EEPROM) cell having a floating gate for storing charge, the amount of current that can flow from the source to the drain depending on the voltage on the control gate CG and the amount of charge stored in the floating gate in the medium. EEPROM is similar in structure to EPROM, but additionally provides a mechanism for loading and removing charge from the floating gate by applying a quantitative voltage, without the need for exposure to ultraviolet light or the like.

In practice, the memory state (or programmed state) of a memory cell is typically read by applying a reference voltage to the control gate to sense the conduction voltage or current through the source to drain of the cell. Thus, the conduction voltage or current of its corresponding floating gate, and the amount of charge stored therein, can be detected relative to a fixed control gate reference voltage. Similarly, the range of amounts of charge programmed into the floating gate also determines the tolerance of its corresponding threshold voltage or conduction current.

For a typical two-state EEPROM cell, at least one voltage or current level is established to divide the sensed conductivity value into two regions. When a certain predetermined voltage is applied to the memory cell, its source/drain current is settled into a memory state by comparing the level (reference voltage VR or reference current IR). If the read voltage or current is above this level, the cell is determined to be a logic state (e.g., "0"). On the other hand, if the read voltage or current is below this level, the cell is determined to be in another logic state (e.g., a "1" state). Thus, a two-state memory cell can store 1 bit of information. An EEPROM cell can be designed to have a greater variety of storage states, such as four-state cells (e.g., "0", "1", "2", "3", etc. storage states), whose reference values can be derived from external programming and are typically provided as part of a memory system to generate voltage levels.

FIG. 3 illustrates a schematic diagram of the read/write circuits operating simultaneously on a full page of memory cells. A program page (page) may include a plurality of columns of memory cells 12 (e.g., 128 bits), and each sense module 14 in the read/write circuit 10 is coupled to its corresponding memory cell 12 via a bit line 16. For example, sense module 14 senses the conduction voltage V1 of memory cell 12, the conduction current of which flows from sense module 14 to the drain of the memory cell via bit line 16 and from the source to ground via source line 18. In an integrated circuit chip, the memory cells in the memory array are coupled to branches of a source line 18, which is connected to ground terminals external to the chip.

In contrast to conventional and conventional read/program schemes, the read/program method of the present invention employs a pre-read step and a merge step prior to the conventional program step to compensate for currently programmed cells by detecting defective cells, such as those with severe charge loss or source line bias problems.

FIG. 4 is a flowchart of a method for compensating for charge loss and source line bias during programming of a non-volatile memory device according to a preferred embodiment of the present invention. The steps of this pre-reading method are summarized as follows:

step S1: reading a previous programming page with a first reference voltage to generate an original previous programming mode, wherein the previous programming page comprises a plurality of memory cells.

Step S2: the original previous programming pattern is merged with the current programming pattern to produce a merged programming pattern.

Step S3: the previously programmed page is read with a second reference voltage to generate a post-verify previous programming mode.

Step S4: the verified previous programming pattern is merged with the merged programming pattern to produce a compensated current programming pattern.

A detailed description of the above steps will now be described in the following preferred embodiment with reference to fig. 5-8.

Referring first to FIG. 5, a schematic diagram of a pre-read module 100 according to a preferred embodiment of the present invention is shown, in which an exemplary programming page with 8 memory cells (8 bits) is used to express the change of the memory states during the read and merge operations in the pre-read method of the present invention, the first reference voltage VR at this stage is set to 0V, which is used as a voltage level to determine whether the memory cells are in the first programming state (e.g., "H" state) or the second programming state (e.g., "L" state). ideally, the lowest distribution voltage V L in the distribution curve of the number of bits in "H" state is set to 1.8V, so that a predetermined 1.8V determination margin region exists between the two memory states.

In step S1, the previously programmed page 101 having the individual cell voltages (1.2, 3, -1, -1, -1, -1, -1, -1) is read by the pre-read module 100 at the first reference voltage VR, in which the individual cells having the cell voltages lower than the first reference voltage VR are all programmed to the "L" state, and the cells having the cell voltages higher than the first reference voltage VR are all programmed to the "H" state, so that the program pattern read from the previously programmed page 101 by the pre-read module 100 has the storage states of the individual cells (H, H, L) because the first reference voltage VR in the read step is set to 0V, for the sake of convenience of explanation, the program pattern determined according to the first reference voltage VR will be hereinafter referred to as the previously programmed pattern 103. thereafter, the previously read program pattern 103 is transferred to and stored at the node N1.

As shown, although the first memory cell in the previously programmed page 101 was programmed to the "H" state in this step, it has only a voltage level of 1.2 volts below the lowest distribution voltage V L (1.8 volts) predetermined in the bit quantity distribution curve for the "H" state under ideal conditions, which means that the first memory cell of the previously programmed page 101 may be a problem cell, with severe charge loss and source line bias problems, and it may be divided into "L" states after multiple programming.

In step S2, the old previous program pattern 103 stored on node N1 is merged with the current program pattern 105 to generate a merged program pattern 111. This step involves a number of actions. Referring to FIG. 6, first, the current programming pattern 105 is loaded to node N2 by the read-ahead module 100. The node N2 is connected to the drain of the merge gate 109. The merge gate 109 is switched at node N1 and has its source connected to voltage V1, where voltage V1 is set at 0 volts (i.e., a logic "0" voltage) at this stage.

Referring again to FIG. 6, after the current programming pattern 105 is loaded onto node N2, the previous programming pattern 103 stored on node N1 is applied as a gate voltage pulse to the merge gate 109 having respective storage states in the previous programming pattern 103 that individually switch the merge gate 109 of its corresponding memory cell, for example, the first and second memory cells in the previous programming pattern 103 are "H" states, the high "H" voltage level in these two cells turns on the merge gate 109, allowing the voltage V1 at the source terminal of the merge gate 109 to be connected to node N2. on the other hand, the third through eighth memory cells in the previous programming pattern 103 are "L" states, whose low "L" voltage levels do not turn on the merge gate 109, so the voltage V1 at the source terminal of the merge gate 109 cannot be connected to node N2.

The merged gate 109 is turned on during programming of the corresponding first and second memory cells, the "H" state of the first and second memory cells in the current programming mode 105 is replaced with the "L" state, while the memory states of the other memory cells remain unchanged, the modified current programming mode 105 in node N2 is hereinafter referred to as the merged programming mode 111, as shown in FIG. 6. the merged programming mode 111 includes the memory states of the combined individual cells in the programming page. the merging is intended to change all the memory cells in the current programming mode 105 corresponding to the "H" state in the previous programming mode 103 to the "L" state, even though a plurality of "H" states in the previous programming mode 101 above the predetermined minimum distribution voltage V L are transferred to the merged node in the merged programming mode 39111 after the merging mode 111 is transferred to the node 1 after the previous programming mode 111.

At step S3, as shown in FIG. 7, the previously programmed page 101 having (1.2, 3, -1, -1, -1, -1) individual cell voltages is again read, however, at this stage, it is read with reference to a second reference voltage VR set at 1.8 volts identical to the lowest distribution voltage V L in the ideal "H" state bit quantity distribution curve, which means that the memory cells in the programmed page having charge or source line offset issues (e.g., the first memory cells having a smaller voltage of 1.2 volts) are all programmed to the "L" state during the verify pre-read operation, thus, the program mode read (L, H, L) is different from the program mode read at step S1. the program mode determined using the relatively high second reference voltage VR is referred to as the post-program mode 113, which means that the program mode read in the previously programmed page and the memory cells in the prior program mode are both transferred to the verify node N.S 1 and the program mode read after the verify mode is merged with the program mode read at the same time as the verify mode read at step S2.

In step S4, the verified previous programming pattern 113 stored in node N2 is merged with the merged programming pattern 111 stored in node N1 to generate the compensated current programming pattern 115. This step involves a number of actions. Referring to FIG. 8, the merged post-program pattern 111 stored at node N1 is first applied as a gate voltage pulse to the merge gate 109. the merge gate 109 has its source connected to voltage V2, which is set to the power supply voltage (i.e., the voltage of logic "1") at this stage. Note that the voltage V2 in step S4 is different from the voltage V1 in step S2.

The voltage pulses having the respective states in the post-merger programming mode 111 switch the merge gates 109 of their corresponding memory cells. For example, the last three memory cells in the merged program mode 111 are in the "H" state, and the voltages at the "H" states of the three memory cells turn on the merge gate 109, such that the source terminal V2 of the merge gate 109 is connected to the node N2.

Since the merge gate 109 is turned on during the programming of the corresponding last three memory cells in the program page, the "L" state of the last three memory cells in the verified previous program pattern 113 is replaced by the "H" state of the connected source voltage V2, while the storage states of the other memory cells remain unchanged, so that the verified previous program pattern 113 stored at the node N2 is modified to the compensated current program pattern 115. compared to the original current program pattern 105, the compensated current program pattern 115 includes the first cell marked as having the "L" state, and the other cells remain unchanged, and the current program operation is subsequently performed according to the compensated current program pattern 115.

By verifying the memory cell with smaller discrimination margin corresponding to the previous program result in the current program page and marking it as "L", the marked "L" state problem cell can be compensated and reprogrammed with correct voltage level in the subsequent program, so that the charge loss and source line bias problems of the "H" state quantity distribution curve after multiple programming and long-term storage in the memory shown in fig. 1A and 1B can be significantly improved.

The preferred embodiments of the present invention are described above, and all equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

[ notation ] to show

10 read/write circuit

12 memory cell

14 detection module

16 bit line

18 source line

100 pre-reading module

101 last programmed page

103 former previous programming mode

105 current programming mode

109 merging grid

111 merged post program mode

113 verify last program mode

CG control grid

D source electrode

M1, M2 discriminant tolerance

N1, N2 node

S1, S2, S3, S4

V1, V2 voltage

Minimum distribution voltage of V L

VR reference voltage