阅读说明：本技术 制造光电子半导体器件的方法及光电子半导体器件 (Method for producing an optoelectronic semiconductor component and optoelectronic semiconductor component ) 是由 M·R·贝林格 C·克莱姆 于 2020-03-05 设计创作，主要内容包括：在一种实施方式中,该方法用于制造光电子半导体器件并且包括以下步骤：A)提供具有接触侧(20)的光电子半导体芯片(2),B)在所述接触侧(20)上产生涂层区域(21)和保护区域(22),C)将液体涂层材料(30)施加到接触侧(20)上,其中涂层材料(30)润湿所述涂层区域(21)并且不润湿所述保护区域(22),以及D)在所述涂层区域(21)上将所述涂层材料(30)固化为至少一个电接触结构(31),使得在按规定使用时穿过所述至少一个接触结构(31)地向所述半导体芯片(2)通电。(In one embodiment, the method is used for producing an optoelectronic semiconductor component and comprises the following steps: A) providing an optoelectronic semiconductor chip (2) having a contact side (20), B) producing a coating region (21) and a protective region (22) on the contact side (20), C) applying a liquid coating material (30) onto the contact side (20), wherein the coating material (30) wets the coating region (21) and does not wet the protective region (22), and D) curing the coating material (30) on the coating region (21) to at least one electrical contact structure (31) such that, in the intended use, an electrical current is passed through the at least one contact structure (31) to the semiconductor chip (2).)

1. A method for producing an optoelectronic semiconductor component (1) has the following steps:

A) providing at least one optoelectronic semiconductor chip (2) having at least one contact side (20),

B) producing at least one coating region (21) and at least one protective region (22) on the contact side (20) or on at least one of the contact sides (20),

C) applying at least one liquid coating material (30) onto the at least one contact side (20), wherein the at least one coating material (30) wets the at least one coating region (21) and does not wet the at least one protective region (22), and

D) curing the at least one coating material (30) to at least one electrical contact structure (31) on the at least one coating region (21) such that, in the intended use, electrical current is passed through the at least one contact structure (31) to the semiconductor chip (2).

2. The method of claim 1, wherein the first and second light sources are selected from the group consisting of,

wherein the at least one coating region (21) and the at least one protective region (22) are each a constituent part of a finished semiconductor component (1), and the coating material (30) is applied both on the at least one coating region (21) and on the at least one protective region (22) and is withdrawn from the at least one protective region (22) as a result of wetting properties,

wherein the at least one semiconductor chip (2) is formed by a light-emitting diode chip or a laser diode chip, and

wherein the at least one semiconductor chip (2) has an average side length of at most 0.1mm, as seen in a plan view of the at least one contact side (20).

3. The method according to any one of the preceding claims,

wherein the at least one coating region (21) is formed by a smooth semiconductor surface area or by a metallization (39) of the semiconductor chip (2) and the at least one protective region (22) is formed by a rough semiconductor surface area or by a rough protective coating (42) of the semiconductor chip (2),

wherein the roughness of the roughened protective region (22) is between 5nm and 100nm, inclusive.

4. The method according to claim 1 or 2,

wherein the at least one coating region (21) is formed by a semiconductor surface area or by a metallization (39) of the semiconductor chip (2) and the at least one protection region (22) is formed by at least one protective coating (42),

wherein the protective coating (42) is smooth and comprises or consists of a perfluorinated plastic or oxide.

5. The method according to any one of the preceding claims,

wherein the at least one coating region (21) and the at least one protective region (22) are still produced in the wafer composite,

wherein a plurality of semiconductor chips (2) are present at a distance from one another in the wafer composite, as originally grown.

6. The method according to any one of the preceding claims,

wherein in step C) In that the at least one coating material (30) is applied simultaneously maskless at least 10⁵A semiconductor chip (2).

7. The method according to any one of the preceding claims,

wherein the coating material (30) or at least one of the coating materials (30) is applied in step C) by means of spraying, printing, spin coating or drop coating.

8. The method according to any one of the preceding claims,

wherein in step C) the coating material (30) or at least one of the coating materials (30) is applied by means of immersion.

9. The method according to any one of the preceding claims,

wherein the completed contact structure (31) or at least one completed contact structure (31) is metallic and light-tight.

10. The method of claim 9, wherein the first and second light sources are selected from the group consisting of,

wherein the coating material (30) or at least one of the coating materials (30) is a solder.

11. The method according to any one of the preceding claims,

wherein further contact structures (32) are produced on the contact side (20) in addition to the contact structures (31), wherein the contact side (20) has a different height in the region of the contact structures (31) and in the region of the further contact structures (32) such that at least one step (23) is present between these regions.

12. The method of claim 11, wherein the first and second light sources are selected from the group consisting of,

wherein the further contact structure (32) is produced from the liquid phase in a further step C) and a further step D).

13. The method according to any one of the preceding claims,

wherein the contact structure (31) or at least one of the contact structures (31) is/are an electrical contact surface for external electrical contacting of the finished semiconductor component (1) directly on the semiconductor layer sequence (26) of the semiconductor chip (2).

14. The method according to any one of the preceding claims,

wherein the finished semiconductor component (1) further comprises a carrier (5) and in step a) the at least one semiconductor chip (2) is mounted on the carrier (5), wherein the contact structure (31) or at least one of the contact structures (31) is an electrical printed circuit from the semiconductor chip (2) in question up to an electrical contact site (51) of the carrier (5) and the contact site (51) is located beside the semiconductor chip (2) in question as seen in a top view of the contact side (20).

15. The method of claim 14, wherein the first and second light sources are selected from the group consisting of,

wherein the contact structure (31) or at least one of the contact structures (31) forms a conductive network such that the contact structure (31) electrically connects a plurality of the semiconductor chips (2) with a common contact site (51),

wherein the coating material (30) is applied planarly in step C).

16. The method according to any one of the preceding claims,

wherein the contact structure (31) or at least one of the contact structures (31) forms a contact frame (29) such that a light exit window (25) surrounded by the contact structure (31) is formed in the center of the contact side (20).

17. The method according to any one of the preceding claims,

wherein the contact structure (31) or at least one of the contact structures (31) comprises at least one optically effective additive (33),

wherein the additive (33) is a luminescent substance, a diffuser, a dye, a filter substance, a thermally conductive substance, a refractive index adaptor and/or a thermal expansion coefficient adaptor.

18. The method according to any one of the preceding claims,

wherein the contact structure (31) or at least one of the contact structures (31) is light-transmissive and shaped as a lens.

19. An optoelectronic semiconductor component (1) produced using a method according to one of the preceding claims, having:

an optoelectronic semiconductor chip (2) with a contact side (20),

-a coating region (21) and a protection region (22) on the contact side (20), and

-an electrical contact structure (31) on the coating region (21) such that the protective region (22) is free of the contact structure (31),

wherein the contact structure (31) tapers in a meniscus shape towards the protective region (22) at the edge of the coating region (21).

Technical Field

A method for producing an optoelectronic semiconductor component is described. Furthermore, an optoelectronic semiconductor component is specified.

Disclosure of Invention

The object to be solved is to specify a method by means of which electrical contacting of an optoelectronic semiconductor chip can be effected.

This object is achieved, inter alia, by a method and an optoelectronic semiconductor component having the features of the independent claims. Preferred extensions are the subject of the remaining claims.

According to at least one embodiment, the method is used for producing an optoelectronic semiconductor component. The finished semiconductor device is, for example, a light emitting diode (LED for short), preferably having a plurality of light emitting cells. The completed semiconductor device is, for example, a display or a display device. The finished semiconductor component can furthermore be a pixelated headlight, for example for the targeted illumination of individual regions, for example in a residence or on a stage, or also in an adaptive headlight in a motor vehicle.

According to at least one embodiment, the method comprises the step of providing one or more optoelectronic semiconductor chips. The at least one semiconductor chip is preferably a light-emitting diode chip. Laser diode chips, such as vertical emitting lasers (shortly called VCSELs), can also be used. If a plurality of semiconductor chips are provided, these semiconductor chips may be identical in structure to each other. Alternatively, different types of semiconductor chips may be mounted.

Preferably, the at least one semiconductor chip is arranged to generate visible light, for example to generate blue light. There may also be semiconductor chips for generating green or yellow or orange or red light. Furthermore, a semiconductor chip for generating near-ultraviolet radiation or near-infrared radiation may be provided. The radiation emitted by the semiconductor chip during operation can be generated directly in the semiconductor layer sequence of the semiconductor chip. It is furthermore possible to dispense at least one phosphor with which the radiation generated in the semiconductor layer sequence can be partially or completely converted into radiation of a different wavelength into the semiconductor chip. Furthermore, there may be sensors such as photo sensors or temperature sensors.

According to at least one embodiment, the semiconductor chip comprises one or more contact sides. The at least one contact side is provided for energizing the semiconductor chip.

According to at least one embodiment, the method comprises the step of producing at least one coating region and at least one protective region on the contact side or on at least one of the contact sides or on a plurality or all of the contact sides. The at least one coating region and the at least one protective region differ from each other, in particular with respect to their wetting properties with respect to the material. For example, the areas of the coating layer are designed to be hydrophobic while the protective areas are hydrophilic, or vice versa.

According to at least one embodiment, the method comprises the step of applying at least one liquid coating material to the at least one contact side. Preferably, the coating material is applied planarly, i.e. in particular without the aid of a masking material. By applying the coating material itself, no structuring of the coating material is achieved in this case. Alternatively, the coating material can only be applied locally, for example along the areas in which the printed tracks should be formed.

According to at least one embodiment, the at least one coating material has wetting properties with respect to the coating area. That is, the coating material wets and covers at least one coating region. The protective area thus has a non-wetting effect, so that the coating material eventually avoids said protective area.

Here, the coating material is also applied at least in regions on the protective region. This preferably also applies to the case where the coating material is applied in a roughly structured manner, for example in the form of a printed circuit. This means that the coating material preferably automatically leaves the protective area again. During the step of applying the coating material, the coating material may still be withdrawn from the protected area. Alternatively, the withdrawal is performed when the coating material is cured, for example due to a temperature change.

According to at least one embodiment, the method comprises the step of curing the at least one coating material. Solidification is, for example, cooling and thus solidification, hardening (for example thermally or photochemically), drying (by evaporation of the solvent) and/or alloying, for example by reacting the coating material with constituents of the coating region, in particular with a change in the melting point. Prior to curing, the coating material is withdrawn from the protected area due to the different wetting properties.

The electrical contact structure is thus produced by curing of the coating material on the at least one coating region. The contact structure is preferably located directly on the coating region. Thus, when used as intended, electrical power may be supplied to the semiconductor chip through the at least one contact structure. This means that the contact structure forms a current-carrying component in the finished optoelectronic semiconductor component.

In at least one embodiment, the method is used for producing an optoelectronic semiconductor component and comprises the following steps, in particular in the order indicated:

A) providing at least one optoelectronic semiconductor chip having at least one contact side,

B) at least one coating region and at least one protective region are produced on the contact side or on at least one of the contact sides,

C) at least one liquid coating material is applied to the at least one contact side in a planar or roughly pre-structured manner, wherein the at least one coating material wets the at least one coating region and does not wet the at least one protective region, wherein the coating material is preferably applied both on the at least one coating region and on the at least one protective region and is withdrawn from the at least one protective region as a result of the wetting properties, and

D) curing the at least one coating material to at least one electrical contact structure on the at least one coating area such that, in use as intended, the semiconductor chip is energized through the at least one contact structure.

Using the method described herein, fast and inexpensive electrical contacting of a large number of semiconductor chips, such as LED chips, is possible. The term "a large number" means, for example, at least ten and/or at most 10⁸A semiconductor chip.

The formation of structured electrical contact lines or contact surfaces is necessary in common contact methods such as wire bonding, producing planar printed wiring connections or flip chip soldering. Furthermore, the semiconductor chip needs to be accurately placed. This contacting method requires considerable effort, in particular when very many semiconductor chips with small geometries have to be contacted.

In the method described herein, the LED chip can be contacted with the electrical conductor from above, for example, using a pressable or printable or sprayable or infusible or drippable or spin-coatable coating material, first in liquid form and then in solid form. For this purpose, the electrical conductor may be transparent or opaque or may also be reflective. Transparent for example means that the permeability to radiation emitted by the semiconductor chip is at least 50% or at least 80% or at least 90%. Reflection means in particular a reflectivity of at least 50% or 80% or 90% for the radiation emitted by the semiconductor chip.

In the case of non-transparent electrical conductors, care is taken in particular that the material used for the lines does not cover too much semiconductor chip area and therefore does not overly mask the emission. For this purpose, regions can be provided on the LED chip and prepared by structuring, to which the electrical conductors should be connected. For this purpose, the region can be metallized, for example, with contact pads, so that the electrical connection to the LED chip takes place with little loss, and on the other hand there is sufficient area for the conductors to be attached to these locations. The region may be located on a main side and/or a side of the LED chip.

Furthermore, the surface of the LED chip, where the conductor should not be applied, may be coated in a manner that repels the liquid of the coating material. So that, for example, when using water-based coating materials, the surfaces involved can be designed to be hydrophobic. This can be done, for example, by coating the involved sites that should later be free of conductors with an oxide such as silicon dioxide, and then etching these sites, for example with hydrofluoric acid, or coating these sites with a hydrophobic material such as a perforated hydrocarbon (e.g., polytetrafluoroethylene).

In the case of transparent lines, the light-emitting diode chip can be structured and coated on the contact side before being placed on a subsequent carrier, i.e. while still in the wafer composite, so that a good electrical connection to the semiconductor material is made at suitable points of the semiconductor chip. The material forming the connection to the conductor and thus to the carrier or to the current source at the outer side on the semiconductor chip is provided for connecting to this conductor with a low resistance. The corresponding points can be connected to one another in an electrically conductive manner.

Even if transparent conductors are used, the regions on the semiconductor chip can be treated such that these regions repel the coating material, as described in the case of non-transparent conductors, in particular metallic conductors. In addition, additional substances having other functions may be added to the transparent conductor, if necessary. For example, a diffuser and/or a light-emitting substance that scatters light may be added. For example, the diffuser may produce RGB image points with particularly good color mixing when jointly contacting red, green and blue LED emitters. It is thus possible to implement both functions, i.e. to improve the optical properties and the electrical coupling, in one working process in a cost-effective manner.

Furthermore, the refractive-index-dependent geometry, in particular the geometry of the transparent conductor, can simultaneously serve as an outcoupling structure, also referred to as an on-chip lens. Thereby the efficiency and/or directivity, i.e. the emission characteristics, can be influenced. Thus, with the application of the contact structure, optical compensation can be performed simultaneously.

Steps may also be encapsulated in the semiconductor chip. In addition, the side edges of the semiconductor chip may be coated according to the outer shape thereof. Here, other parameters such as surface tension, viscosity or glass transition point may be important for the coating material to be applied first in liquid form.

Thus, inexpensive, parallelized contacting and wiring, mounting and compensation of semiconductor chips, such as LED chips, can be achieved with low adjustment requirements for the semiconductor chips and the conductors for electrical contacting using the methods described herein. The semiconductor chip can be mounted on a carrier or a base and can be provided with a coating material for electrical contacting, effectively from the side facing away from the carrier or the base.

According to at least one embodiment, the at least one coating region and/or the at least one protective region are each an integral component of the finished semiconductor component. This means that the coating region and/or the protective region are not only temporary components, such as a photoresist or a mask layer. This means that the coating region and the protection region can be identified in the finished semiconductor device, preferably just as a measure to achieve a difference between the coating region and the protection region.

According to at least one embodiment, the at least one semiconductor chip has an average side length of at most 0.2mm or 0.1mm or 50 μm, when viewed in a top view of at least one contact side. The average side length of the semiconductor chips is preferably at most 30 μm or 15 μm or 10 μm. Alternatively or additionally, the semiconductor chip has an average side length of at least 1 μm or 2 μm or 5 μm. This means that the semiconductor chip is relatively small. Viewed in plan view on the contact side, the average side length, in particular the sum of all side lengths, is divided by the number of edges.

According to at least one embodiment, the or at least one or all of the coating areas are formed by smooth semiconductor surface areas of the semiconductor chip. Smooth means in particular a roughness of at most 3nm or 2nm or 1 nm. In the present case, roughness is understood in particular to mean a shape deviation of the fourth order, i.e. roughness in the form of grooves, scales and projections, see DIN 4760.

According to at least one embodiment, the or at least one or all protection regions are formed by a rough semiconductor surface area of the semiconductor chip. Instead of a semiconductor surface area, a passivation layer, such as an oxide layer, may also be used in the protection area.

The roughness of the corresponding surface area of the protective area is preferably at least 5nm or 10nm or 20 nm. Alternatively or additionally, the surface roughness is at most 150nm or 100nm or 50nm or 30 nm. In particular, the roughness is significantly smaller than usual roughening for the region of the protective region in order to improve the light outcoupling efficiency.

The so-called lotus effect is achieved by this surface roughness. That is to say that the surface structure has a periodicity which is significantly smaller than the droplet diameter of the coating material in a direction parallel to the main direction of extension of the surface. Significantly less means, for example, at most one fifth or one tenth or one thirty.

According to at least one embodiment, the at least one coating zone and/or the at least one protective zone or at least some coating zones and/or at least some protective zones are still produced in the wafer composite. That is, the creation of the coating region and/or the protective region can take place before the semiconductor chips are separated from the wafer composite. A large number of semiconductor chips are present in the wafer composite and are preferably at a distance from one another, as originally grown. In this case, these semiconductor chips can still be located on the growth substrate or on an alternative carrier, wherein in the latter case the relative position of the semiconductor chips to one another is not or not significantly changed compared to the growth.

According to at least one embodiment, the coating region or at least one or all of the coating regions is formed by metallization. The metallization preferably directly contacts the semiconductor surface area for the coated area. The thickness of the metallization is, for example, at least 5nm or 10nm or 20nm and/or at most 2 μm or 1 μm or 0.3 μm.

According to at least one embodiment, the protective zone or one or all of the protective zones is formed by one or more protective coatings. The protective coating may have a smooth surface or may also be provided with a surface roughness. At least one protective coating comprises, for example, a fluorinated or perfluorinated plastic, such as polytetrafluoroethylene. Alternatively, the at least one protective coating comprises an oxide, such as silica or alumina. The protective coating may be composed of one or more of these materials.

According to at least one embodiment, the coating material is applied in step C) mask-free, over a large area and/or unstructured. In this case, the coating material is preferably applied simultaneously and continuously to a plurality of semiconductor chips. The number of semiconductor chips on which the coating material is applied is preferably at least 10³Or 10⁵Or 10⁷Or 10⁸. Alternatively or additionally, the number is at most 10¹⁰Or 10⁹Or 10⁸。

According to at least one embodiment, the coating material or at least one coating material is applied in step C) by means of spraying, printing, spin coating or drop coating. The printing includes, for example, screen printing methods or inkjet printing methods, with which a rough structuring can optionally be carried out.

During dispensing, the semiconductor chip is at a relatively low temperature relative to the evaporation temperature of the coating material or of the solvent of the coating material. That is, the coating material may condense on the semiconductor chip from the vapor phase, thereby effectively depositing as a liquid.

According to at least one embodiment, the application of the or at least one coating material in step C) is carried out by means of immersion. That is to say, for example, the semiconductor chips applied on the carrier, still on the growth wafer or on the temporary substrate can be incorporated predominantly or completely into the liquid coating material. After or during the lifting, the coating material is preferably withdrawn onto the coating region.

According to at least one embodiment, the or at least one or all of the completed contact structures are metallic. For example, the contact structure consists of one or more metals or of one or more metal alloys and/or metal layers. For example, the contact structure or structures are made of one or more of the following metals: al, Cu, Zn, Ni, Ag, Au, Pt, Ti, In, Cr, Mo, W, Fe, Mn, Cu, Ge, Si. In this context, the semiconductor materials Ge and Si are understood to be metals. Furthermore, Hg can be used as a metal for the contact structure.

According to at least one embodiment, the or at least one coating material is a solder. That is, the coating material may be metallic and may be applied in liquid form. The solder may not change or significantly change its chemical composition during curing.

Furthermore, the coating material may be metallic and change its chemical composition during curing. For example, mercury (Hg for short) or a gallium indium tin alloy is then used as coating material. Mercury can be applied in liquid form at room temperature or evaporated to form a liquid. By using Hg, it is possible to produce an amalgam on at least one coating region in a targeted manner, alone or in combination with other coating materials in addition to Hg or Hg-containing compounds. A gallium indium tin alloy is an in particular eutectic alloy consisting of gallium, indium and preferably also tin. Here, an alloy consisting of 68% to 69% Ga, 21% to 22% In, and 9.5% to 10.5% Sn has a particularly low melting point of about-19.5 ℃.

Hg at room temperature has a very high surface tension of about 470mN/m compared to water having a surface tension of about 70mN/m at room temperature, whereas GaInSn is about 720 mN/m. In contrast, the surface tension of a solvent of n-hexane or acetone is about 20mN/m at room temperature.

According to at least one embodiment, further contact structures are produced on the contact side. For example, the contact structure is designed as a cathode and the further contact structure as an anode, or vice versa. The contact structure and the further contact structure are preferably not electrically short-circuited. It is possible that the only electrical connection between the contact structure and the further contact structure within the semiconductor device is given via the semiconductor chip.

According to at least one embodiment, the contact structure and the further contact structure have different heights on the contact side. That is, the semiconductor chip may be thicker in the region of the contact structure than in the region of the further contact structure, or vice versa.

According to at least one embodiment, the semiconductor chip has one or more steps between the contact structure and the further contact structure. Such a step may extend over the entire active area of the semiconductor chip.

According to at least one embodiment, the further contact structures are produced in a further step C) and a further step D). That is, both the contact structure and the other contact structure may be produced from a liquid phase. Thereby, the at least one semiconductor chip can be contacted from one or more liquid phases on the anode side and the cathode side. In the present case, a liquid phase is also understood to be deposited from a gas phase, wherein a liquid is formed from the gas phase, for example by condensation.

According to at least one embodiment, the contact structure or at least one contact structure or all contact structures and/or at least one further contact structure each form an electrical contact surface for external electrical contacting of the completed semiconductor device. It is possible here that the contact structure and/or the further contact structure can be in direct contact with the semiconductor layer sequence of the semiconductor chip concerned. The contact structure then consists, for example, of a gallium indium tin alloy.

In accordance with at least one embodiment, a completed semiconductor device includes a carrier. The carrier is for example a circuit board such as a printed circuit board (PCB for short).

According to at least one embodiment, one or more semiconductor chips are mounted on the carrier in step a). For this purpose, the carrier can have electrical contact surfaces, for example a common anode or a common cathode, or electrical contact surfaces which can be electrically controlled individually for each semiconductor chip. If the carrier has a large number of individually controllable contact surfaces, the carrier may be a silicon substrate, which comprises electronic components, such as transistors and/or switches, for targeted control and addressing of the individual semiconductor chips.

According to at least one embodiment, the or at least one of the contact structures or all of the electrical contact structures are electrically printed wires. In other words, conductor structures, such as printed circuits, can be formed from the semiconductor chip concerned to the electrical contact points of the carrier via the at least one contact structure. The associated electrical contact points of the carrier, to which the contact structures in the form of the conductor tracks extend, are preferably located next to the semiconductor chip concerned, in particular outside the region of the plurality of semiconductors, when viewed in a plan view of the contact side.

According to at least one embodiment, the contact structure or at least one of the contact structures forms a conductive network. In this way, a single contact structure can electrically connect a plurality of semiconductor chips to a common contact point, in particular on a carrier.

According to at least one embodiment, the contact structure or at least one of the contact structures forms a contact frame. The contact frame preferably surrounds the contact side on the edge. Thereby, a light exit window may be formed in the center of the contact side, which light exit window is surrounded by and/or framed by the contact structure.

According to at least one embodiment, the contact structure or at least one of the contact structures comprises one or more optically effective additives. The at least one additive is in particular selected from the group consisting of: luminescent substances, diffusers, dyes, filter substances, heat-conducting substances, substances for adapting the refractive index, substances for adapting the coefficient of thermal expansion.

According to at least one embodiment, the or at least one of the contact structures is formed from a light-transmissive material. The contact structure then consists, for example, of a transparent conductive oxide (TCO for short), for example ITO or ZnO.

Metallic, light-transmitting contact structures are also possible. In this case, the thickness of at least one of the contact structures concerned is preferably at most 20nm or 10nm or 5 nm.

According to at least one embodiment, the contact structure is designed as an optical element. For example, the contact structure may be shaped as a lens, such as a converging lens or a diverging lens.

According to at least one embodiment, the semiconductor chip includes an optical body. The optical body may be a luminescent substance. It is furthermore possible that the optical body can be formed by a light-transmissive growth substrate for a semiconductor layer sequence of a semiconductor chip.

An optoelectronic semiconductor component is also described. The semiconductor device is in particular manufactured using a method as described in connection with one or more of the above embodiments. Thus, features of the semiconductor device are also disclosed for the method and vice versa.

In at least one embodiment, the optoelectronic semiconductor component comprises an optoelectronic semiconductor chip having a contact side. On the contact side, a coating region and a protective region are present. An electrical contact structure is mounted on the coated region such that the protective region is free of contact structures. The contact structure may taper in a meniscus towards the protective region at the edge of the coating region. That is, the contact structure may be designed to act like a water droplet at least towards the protection area, which water droplet rests on the base. The contact structure preferably does not contact the protective region, but due to the meniscus design, the contact structure may partially cover the protective region when viewed in top view from the contact side.

Drawings

The method described here and the optoelectronic semiconductor component described here are explained in more detail below on the basis of exemplary embodiments with reference to the drawings. Herein, like reference numerals denote like elements in the respective drawings. However, references to scale are not shown herein, but rather, various elements may be shown exaggerated for better understanding.

Fig. 1 to 12 show schematic diagrams of method steps of the method described here, wherein fig. 1, 5, 7, 9 and 11 show schematic top views, fig. 2, 3, 4, 6, 8, 10 and 12 show schematic cross-sectional views,

figures 13 to 15 show schematic top views of method steps of embodiments of the method described herein,

figures 16 to 19 show schematic top views of semiconductor chips of embodiments of the methods described herein,

figures 20 and 21 show schematic cross-sectional views of embodiments of the optoelectronic semiconductor device described herein,

FIG. 22 shows a schematic cross-sectional view of a semiconductor layer sequence for an embodiment of the optoelectronic semiconductor component described here, an

Fig. 23 and 24 show schematic cross-sectional views of method steps of an embodiment of the method described herein.

Detailed Description

Fig. 1 and 2 show an exemplary embodiment of a method for producing an optoelectronic semiconductor component 1. An optoelectronic semiconductor chip 2 used for this method is shown in a plan view in fig. 1. The semiconductor chip 2 is preferably a light emitting diode chip (LED chip for short). Viewed in a plan view of the contact side 20, the side length L of the semiconductor chip 2 is in the range of approximately 10 μm. The semiconductor chip 2 is therefore comparatively small and may be a μ LED.

The contact side 20 comprises a centrally located protection area 22 and a frame-like coating area 21 surrounding the contact side 20 at the edges. The coated areas 21 thus form a contact frame 29. The protection area 22 represents a light exit window 25 of the semiconductor chip 2. During operation, the semiconductor chip 2 preferably emits a major fraction of its radiation at the light-exit window 25, for example at least 70% or at least 90%.

Fig. 2 to 4 show schematic cross-sectional views of possible implementations of the semiconductor chip 2, as shown in the top view of fig. 1. In the following embodiments, all variants of the semiconductor chip 2 can be used, as shown in connection with fig. 2 to 4, even if these embodiments are explicitly shown for only one of these designs.

In the case of the semiconductor chip 2 of fig. 2, the contact side 20 is provided with a protective coating 42 in the protective region 22. The protective coating 42 covers the entire protective area 22. The side faces of the semiconductor chip 2 may optionally also be covered by a passivation layer 24. As an alternative to such a passivation layer 24, the protective coating 42 may extend to the side. In contrast to the illustration in fig. 2, the protective coating 42 or the passivation layer 24 can reach all the way to the further electrical contact structures 32 on the lower side of the semiconductor chip 2.

The protective coating 42 is preferably relatively thin. The thickness of the protective coating 42 is in particular at most 200nm or 100nm or 50nm or 20nm, the protective coating 42 may be smooth. The protective coating 42 is preferably made of a perfluorinated plastic or oxide such as silica.

These statements relating to the protective coating 42 and the passivation layer 24 of fig. 2 apply correspondingly to all the remaining embodiments.

Metallization 39 is optionally present in the coating region 21. The metallization 39 can be applied directly to the semiconductor material of the semiconductor chip 2. The optional metallization 39 is also preferably relatively thin. The metallization 39 may completely cover the coating region 21.

According to fig. 3, the protection zone 22, symbolically indicated by hatched lines, is formed by a roughness 41. A lotus effect can be achieved by the roughness 41, so that liquid rolls off the roughness 41 and collects in the coating region 21. For this reason, the roughness 41 preferably has a small average roughness, particularly several tens of nm.

Fig. 3 shows that roughness 41 can be produced directly from the semiconductor material of semiconductor chip 2. In contrast to this, the roughness 41 can also be produced in a protective coating, not shown in fig. 1. That is to say that the protective coating in which the roughness 41 is produced is then situated directly on the semiconductor material.

Such roughness 41 is produced, for example, by depositing a silicon dioxide layer which is etched with hydrofluoric acid (HF for short) in order to achieve the lotus effect on the surface. Such structuring can be demonstrated, for example, by means of atomic force microscopy or electron microscopy.

In fig. 2 and 3, the coating region 21 and the protective region 22 are approximately in a common plane. In contrast, it is shown in fig. 4 that a major portion of the protection region 22 may rise above the plane defined by the coating region 21. The side faces of the semiconductor layer sequence 26 and the raised side faces of the semiconductor chip 2 can be provided with roughness, protective coatings and/or passivation layers to ensure non-wetting properties with respect to coating materials, not shown.

The optical body 6 can be mounted on the semiconductor layer sequence 26. The optical body 6 is transparent to the radiation generated during operation of the semiconductor chip 2. In contrast to the illustration of fig. 4, the optical body can be designed in the form of a lens. The optical body 6 may be a separately produced body which is applied to the semiconductor layer sequence 26, wherein a connecting dielectric layer may be present. Furthermore, the optical body 6 can also be formed from a growth substrate for the semiconductor layer sequence.

As an alternative to a separate optical body, the elevations with the protective regions 22 can represent a part of the semiconductor layer sequence 26 of the semiconductor chip 2. For example, the n-type conductive semiconductor sub-layer of the semiconductor layer sequence 26 is etched back all around, so that a contact frame 29 is formed. Optionally, the semiconductor layer sequence 26 is provided with a metallization 39 around the elevations with the protective regions 22.

The carrier 5 is provided in the method step of fig. 5. The carrier 5 is for example a printed circuit board with integrated electronics or a silicon carrier. The carrier 5 has further electrical contact points 52, which are subsequently individually assigned to the semiconductor chips 2. Furthermore, electrical contact points 51 are present, for example as a common anode or as a common cathode. The contact locations 51, 52 may lie in a common plane on the carrier 5. The associated side view is shown in fig. 6.

In the method steps of fig. 7 and 8, the semiconductor chip 2 is applied to the further contact points 52. The semiconductor chip 2 can be applied from a wafer composite in which the semiconductor chip 2 is grown. The surface density of the semiconductor chips 2 can be gradually reduced, for example to at most one tenth and/or at least one thousandth, for example to about one hundredth, from a wafer, not shown, towards the carrier 5. That is to say that the semiconductor chips 2 are at a considerable distance from one another on the carrier 5, but are nevertheless arranged relatively densely, for example with an area share of at least 0.5% or 1% or 5% and/or at most 60% or 30% or 10%.

In the method steps of fig. 9 and 10, the coating material 30 is applied in a planar and initially unstructured manner. The coating material 30 is, for example, liquid solder or conductive ink with silver particles. In addition, an aqueous solution containing a zinc salt may be used so that it can be reduced to zinc. Likewise, a coating material 30 comprising aluminum hydroxide is also possible. In the case of the non-metallic coating material 30, zinc oxide may be flocculated from the aqueous phase, for example.

The method steps in fig. 11 and 12 illustrate that the coating material has already been removed onto the coating region 21 as a result of the anti-wetting effect of the protective region 22. The light-exit window 25 is thus free of coating material 30. Therefore, the coating material 30 on the semiconductor chip 2 preferably wets only the coating region 21.

In contrast to the illustrations in fig. 11 and 12, the coating material 30 can be in direct planar contact with the carrier 5. However, an electrical short to the other contact points 52 is to be avoided here. Preferably, however, the carrier 5 also has an anti-wetting effect on the coating material 30.

Thus, an electrical contact structure 31 is produced from the coating material 30, which electrical contact structure is configured in the form of a grid and electrically conductively connects the coating region 21 to a contact site 51 on the carrier 5.

Another exemplary method is shown in fig. 13-15. According to fig. 13, the semiconductor chip 2 is mounted on a carrier 5. To simplify the illustration, only one of the semiconductor chips 2 is shown, but many semiconductor chips 2 may also be mounted.

In the step of fig. 14, the coating material 30 is applied in a manner similar to a printed circuit and roughly pre-structured. In this case, the coating material 30, like the printed circuit, can be applied first to the entire semiconductor chip 2 and in particular to the entire protective region 22, for example using a printing method.

As can be seen in fig. 15, the coating material has been withdrawn from the light exit window 25 of the protection region 22 and is confined to the coating region 21 on the semiconductor chip 2. An electrical connection can thus be effectively established between the contact site 51 and the coating region 21 without the final form of the contact structure 21 having to be produced directly when the coating material 30 is applied. As in all other embodiments, the coating region 21 may optionally be provided with a metallization 39.

Fig. 16 to 19 show several exemplary embodiments of the design of the contact side 20 of the semiconductor chip 2 that can be used here.

In contrast to the exemplary embodiments in fig. 1 to 15, the coating region 21 in fig. 2 is not mounted in the form of a frame, but extends in an E-shape over the contact side 20. Thus, two protective regions 22 can be formed on the contact side 20, which are separated from one another.

According to fig. 17, the coating region 21 has a comparatively large circular region in the center of the contact side 20, which region is formed as an extension of the strip up to the edge of the contact side 20. A large-area electrical contact can thus be realized in the center of the contact side 20.

In fig. 18, there are individual coating regions 21, which are each designed in the form of a strip and are separated from one another by protective regions 22.

In the embodiment of fig. 19, the coating area 21 is limited to the corner area of the contact side 20. An optional contact extension 38 extends from the coating region 21, which contact extension is formed, for example, by means of a further metallization. The contact extension 38 may be designed so as not to be wetted by the coating material 30. That is, the protection region 22 may extend onto the contact extension 38.

The design of the contact side 20 in fig. 16 to 19 is to be understood as merely exemplary. Other geometries of the coating region 21 and the protection region 22 are also possible.

Fig. 20 shows that the semiconductor layer sequence 26 of the semiconductor chip 2 has an active region 27 for generating light. A step 23 is formed over the entire active region 27 so that the coating regions 21 for the contact structures 31, 32 are at different heights. There may be a metallization layer 39, respectively.

Starting from the coating region 21, contact structures 31, 32, which can each be deposited from a liquid phase, are provided. The contact structures 31, 32 may be manufactured in separate steps, so that electrical short circuits may be avoided. Optionally, the optical body 6, such as a growth substrate, remains on the semiconductor layer sequence 26.

The semiconductor layer sequence is preferably based on a group III-V compound semiconductor material. The semiconductor material is, for example, a nitrogen compound semiconductor material such as Al_nIn_1-n-mGa_mN-or phosphorus compound semiconductor materials, e.g. Al_nIn_1-n-mGa_mP or arsenic compound semiconductor material such as Al_nIn_1-n-mGa_mAs or Al_nGa_mIn_1-n-mAs_kP_1-kWherein n is more than or equal to 0 and less than or equal to 1, m is more than or equal to 0 and less than or equal to 1, n + m is less than or equal to 1, and k is more than or equal to 0<1. Preferably, 0 is used here for at least one or all layers of the semiconductor layer sequence<n≤0.8、0.4≤m<1 and n + m are less than or equal to 0.95 and 0<k is less than or equal to 0.5. The semiconductor layer sequence can have a dopant and additional components. For the sake of simplicity, however, only the essential constituents of the crystal lattice of the semiconductor layer sequence, i.e. Al, As, Ga, In, N or P, are illustrated, even if they can be partially replaced by and/or supplemented by small amounts of other substances.

The contact structure 31 is produced, for example, as explained in connection with fig. 1 to 12. The same method or a different method may be used for the other contact structures 32.

In a variant of the production method for one of the contact structures, the semiconductor chip 2 has a metallization 39 on one or both coating regions 21, which metallization is made of a metal that forms an amalgam with Hg and/or is reactive with a gallium indium tin alloy. For example, the corresponding metallization 39 is made of Al, Cu, Zn, Ni, Ag, Au, Pt, Ti and/or In. In the present case, a further metallization 39 is used, for example, for the contact points 31, which is made of a different metal that does not form an amalgam with Hg. The further metallization 39 is made of, for example, Cr, Mo, W, Fe, Mn, Co, Ge and/or Si.

If the semiconductor chip 2 is now placed on a carrier and is evaporated or immersed in Hg in a planar manner, then Hg forms an amalgam for one contact point 32 with the metallization 39 and the wetting is removed without the metallization of a different design reacting. In this way, electrical interconnections with a specific polarity can be produced in a targeted manner even in the case of many and small contact structures 31, 32, without the need for adjustment complexity.

Alternatively, HgCl may also be used₂Hg is applied in aqueous solution, wherein then no noble metals such as Au or Pt should be used.

A corresponding Hg-based manufacturing method can also be used in all embodiments.

On the left side of fig. 21, it is illustrated that a plurality of contact structures 31a, 31b may be deposited stacked one on top of the other. The coating material for the second resulting contact structure 31b preferably wets only the material of the first resulting contact structure 31 a. The contact structures 31a, 31b may widen in a direction away from the contact side 20. Thus, the protection region 22 may be partially covered by the contact structures 31a, 31b, when viewed in a top view of the contact side 20.

On the right side of fig. 21, it is shown that the contact structure 31 may be made of a light-transmitting material such as TCO. In this case, the contact structure 31 may be designed in the form of a lens and serve as an optical element. It is further shown in fig. 21 that the contact structures 31, 31a, 31b may each have a meniscus shape at the edge of the coating region 21. Thus, the shape of the contact structures 31, 31a, 31b, viewed in cross-section, resembles a droplet resting on the liquid-repellent material at the edges.

Fig. 22 shows an exemplary embodiment of a semiconductor layer sequence 26, which is provided with a light outcoupling structure 7. The light outcoupling structures 7 have an average structure size, for example, in the range of 0.5 μm to 5 μm. The light outcoupling structures 7 are therefore significantly larger than the structure of the roughness 41, the roughness 41 serving to protect the lotus effect of the region 22.

Fig. 23 shows that a coating region 21 and a protective region 22, symbolically indicated by shading, can still be produced in the wafer composite. In this case, the semiconductor layer sequence 26 with the region 2' for the semiconductor chip 2 is still situated on the growth substrate 6. The active region 27 grows continuously and parallel to the main side of the growth substrate 6.

According to fig. 24, the coating material 30 for producing the contact structures, not shown, is likewise still applied in the wafer composite, which is only shown in a simplified manner in fig. 24. Here, the mesa trenches 8 are preferably already shaped so that the semiconductor chips 2 are present individually, but still on the growth substrate 6. The side faces of the semiconductor chip 2 may be provided with a passivation layer 24, in particular in the region of the mesa trench 8. The electrical contact surfaces can be formed directly on the semiconductor layer sequence 26 by means of the coating material 30.

Unlike fig. 23 and 24, the coating region 21 and the protection region 22 may be formed after the mesa groove 8 is created. Furthermore, although less preferred, the coating material 30 may be applied prior to creating the mesa trenches 8.

This patent application claims priority from german patent application 102019106546.1, the disclosure of which is incorporated herein by reference.

The invention described herein is not limited by the description based on the embodiment. Rather, the invention encompasses any novel feature and any combination of features, in particular any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.

List of reference numerals

1 optoelectronic semiconductor component

2 optoelectronic semiconductor chip

Semiconductor layer sequence region of a 2' semiconductor chip

20 contact side

21 coating region

22 protection area

23 step

24 passivation layer

25 light exit window

26 semiconductor layer sequence

27 active region

29 contact frame

30 coating material

31 electric contact structure

32 other electrical contact structure

33 additive

38 contact extension

39 metallization

40 smooth regions of a semiconductor surface

41 roughness

42 protective coating

5 vectors

51 electrical contact site

52 other electrical contact points

6 optical body

7 light out-coupling structure

8 mesa trench

And L is long.