阅读说明：本技术 Led芯片及其制备方法 (LED chip and preparation method thereof ) 是由 朱玲 吴懿平 吕卫平 胡俊华 于 2019-11-18 设计创作，主要内容包括：本发明涉及一种LED芯片及其制备方法,LED芯片上形成有由依次贯穿n型材料层、多量子阱层和p型材料层的纳米柱组成的第一纳米柱区域和第二纳米柱区域。这种LED芯片上形成有第一纳米柱区域和第二纳米柱区域,结合实验数据,纳米柱的直径变化可以改变纳米柱内的多量子阱层的发光波长,通过第一纳米柱区域内的纳米柱的直径大于第二纳米柱区域内的纳米柱的直径,从而可以使得第一纳米柱区域和第二纳米柱区域分别发出波长不同的光,从而使得这种LED芯片可以实现多彩显示。(The invention relates to an LED chip and a preparation method thereof.A first nanorod area and a second nanorod area which are composed of nanorods penetrating through an n-type material layer, a multi-quantum well layer and a p-type material layer in sequence are formed on the LED chip. The LED chip is provided with the first nanorod area and the second nanorod area, the diameter change of the nanorods can change the light emitting wavelength of a multi-quantum well layer in the nanorods by combining experimental data, the diameter of the nanorods in the first nanorod area is larger than that of the nanorods in the second nanorod area, so that the first nanorod area and the second nanorod area can respectively emit light with different wavelengths, and the LED chip can realize colorful display.)

1. An LED chip is characterized by comprising a base layer, a first metal layer, a p-type material layer, a multi-quantum well layer, an n-type material layer and a second metal layer which are sequentially stacked;

and a first nanorod area and a second nanorod area which are formed by nanorods penetrating through the n-type material layer, the multi-quantum well layer and the p-type material layer in sequence are formed on the LED chip, and the diameter of the nanorod in the first nanorod area is larger than that of the nanorod in the second nanorod area.

2. The LED chip of claim 1, wherein the first nanopillar region and the second nanopillar region are both triangular or hexagonal;

the diameter of the nano-column in the first nano-column region is 100 nm-1500 nm, and the diameter of the nano-column in the second nano-column region is 10 nm-800 nm.

3. The LED chip according to claim 1 or 2, wherein the light emission wavelength of the mqw layer is 560nm to 770 nm.

4. The LED chip according to claim 3, wherein the p-type material layer is a p-GaN layer, the n-type material layer is an n-GaN layer, and the MQW layer is a MQW layer having InGaN/GaN as a laminated unit;

the base layer is a silicon dioxide base layer, the first metal layer is Ni/Au or Ni/Ag, and the second metal layer is Ti/Al.

5. A preparation method of an LED chip, which is used for preparing the LED chip as claimed in any one of claims 1 to 4, and comprises the following steps:

providing an LED wafer, wherein the LED wafer comprises a p-type material layer, a multi-quantum well layer, an n-type material layer and a substrate which are sequentially stacked;

forming a first metal layer on the p-type material layer, and then disposing a base layer on the first metal layer such that the base layer, the first metal layer, and the p-type material layer are sequentially stacked;

removing the substrate, and then carrying out primary flattening treatment on the n-type material layer;

forming a mask layer with a required pattern on the n-type material layer, and then etching to form a first nanorod area and a second nanorod area, wherein the first nanorod area and the second nanorod area are respectively composed of nanorods penetrating through the n-type material layer, the multi-quantum well layer and the p-type material layer in sequence, and the diameter of the nanorods in the first nanorod area is larger than that of the nanorods in the second nanorod area; and

and performing secondary flattening treatment on the n-type material layer to obtain a semi-finished product, and forming a second electrode layer on the n-type material layer to obtain the LED chip.

6. The method of manufacturing an LED chip according to claim 5, wherein the substrate is a sapphire substrate, and the removing the substrate is performed by: removing the substrate by a laser lift-off technology, wherein a laser beam adopted in the laser lift-off technology is a deep ultraviolet laser beam with the wavelength of 266 nm;

or, the substrate is a silicon substrate, and the removing the substrate is performed by: and removing the substrate by wet etching.

7. The method for preparing the LED chip according to claim 5, wherein the first planarization treatment for the n-type material layer comprises: and thinning the n-type material layer by adopting dry etching, and enabling the surface roughness of the thinned n-type material layer to be less than 10 nm.

8. The method of claim 5, wherein the step of forming a mask layer with a desired pattern on the n-type material layer comprises: coating photoresist on the n-type material layer to form a photoresist layer, and transferring a required pattern onto the photoresist layer by adopting a nano-imprinting method, wherein the photoresist layer is the mask layer;

alternatively, the mask having a desired pattern is formed on the n-type material layerThe operation of the film layer is as follows: disposing a Ni etch mask on the n-type material layer, followed by disposing SiO on the Ni etch mask ₂Layer for transferring a desired pattern to SiO by nanoimprint ₂Layer, followed by etching to remove the desired pattern from the SiO ₂The layer is transferred onto the Ni etch mask to obtain sidewall-vertical nanopillars by high etch selectivity between the Ni etch mask and the n-type material layer.

9. The method for preparing the LED chip according to claim 5, wherein the second planarization treatment for the n-type material layer comprises: and filling a dielectric material in the first nano-pillar region and the second nano-pillar region, and then thinning the dielectric material to expose the n-type material layer.

10. The method according to claim 5, wherein the step of forming the second electrode layer on the n-type material layer comprises: and after the semi-finished product is obliquely installed, the second electrode layer is formed on the n-type material layer by evaporation.

Technical Field

The invention relates to the technical field of display, in particular to an LED chip and a preparation method thereof.

Background

micro-LED is an LED device that can be used for screen display, and realizes illumination and display by emitting light through a single LED chip.

However, due to the property of the LED device emitting monochromatic light, in order to realize a multicolor display, a plurality of LED chips emitting different colors are required to be combined.

That is, a single LED chip cannot realize a multicolor display.

Disclosure of Invention

In view of this, it is necessary to provide an LED chip that can emit two or more kinds of light, thereby realizing a multicolor display.

An LED chip comprises a base layer, a first metal layer, a p-type material layer, a multi-quantum well layer, an n-type material layer and a second metal layer which are sequentially stacked;

and a first nanorod area and a second nanorod area which are formed by nanorods penetrating through the n-type material layer, the multi-quantum well layer and the p-type material layer in sequence are formed on the LED chip, and the diameter of the nanorod in the first nanorod area is larger than that of the nanorod in the second nanorod area.

A preparation method of an LED chip is used for preparing the LED chip and comprises the following steps:

providing an LED wafer, wherein the LED wafer comprises a p-type material layer, a multi-quantum well layer, an n-type material layer and a substrate which are sequentially stacked;

forming a first metal layer on the p-type material layer, and then disposing a base layer on the first metal layer such that the base layer, the first metal layer, and the p-type material layer are sequentially stacked;

removing the substrate, and then carrying out primary flattening treatment on the n-type material layer;

forming a mask layer with a required pattern on the n-type material layer, and then etching to form a first nanorod area and a second nanorod area, wherein the first nanorod area and the second nanorod area are respectively composed of nanorods penetrating through the n-type material layer, the multi-quantum well layer and the p-type material layer in sequence, and the diameter of the nanorods in the first nanorod area is larger than that of the nanorods in the second nanorod area; and

and performing secondary flattening treatment on the n-type material layer to obtain a semi-finished product, and forming a second electrode layer on the n-type material layer to obtain the LED chip.

The LED chip is provided with the first nanorod area and the second nanorod area, the diameter change of the nanorods can change the light emitting wavelength of a multi-quantum well layer in the nanorods by combining experimental data, and the diameters of the nanorods in the first nanorod area and the second nanorod area are larger than those of the nanorods in the second nanorod area, so that the first nanorod area and the second nanorod area can respectively emit light with different wavelengths, and the single LED chip can realize colorful display.

In addition, compared with the traditional LED which emits light with different colors, the LED chip can simultaneously emit more than two kinds of light through the first nano-pillar region and the second nano-pillar region, so that the display resolution and the color rendering index CRI (which can reach 100) of a device adopting the LED chip are obviously superior to those of the traditional device.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Wherein:

fig. 1 is a schematic cross-sectional structure diagram of an LED chip according to an embodiment.

Fig. 2 is a process diagram for manufacturing the LED chip shown in fig. 1.

Fig. 3 is a photoluminescence spectrum of a white left region, a first nanopillar region, a second nanopillar region, a third nanopillar region, and a fourth nanopillar region of the LED chip prepared in example 1.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The LED chip according to the embodiment shown in fig. 1 includes a base layer 10, a first metal layer 20, a p-type material layer 30, a multiple quantum well layer 40, an n-type material layer 50, and a second metal layer 60, which are sequentially stacked.

Referring to fig. 1, a first nanopillar region 101 and a second nanopillar region 102 composed of nanopillars sequentially penetrating through the n-type material layer 50, the multiple quantum well layer 40, and the p-type material layer 30 are formed on the LED chip, and the diameter of the nanopillars in the first nanopillar region 101 is greater than that of the nanopillars in the second nanopillar region 102.

Referring to fig. 1, the first nanopillar region 101 may be provided with a plurality of nanopillars spaced apart from each other, or may be provided with only one nanopillar, each of which includes, from top to bottom, an n-type material layer 50, a multiple quantum well layer 40, and a p-type material layer 30.

Likewise, the second nanopillar region 102 may be provided with a plurality of nanopillars spaced apart from each other, or may be provided with only one nanopillar, each of which includes, from top to bottom, the n-type material layer 50, the multiple quantum well layer 40, and the p-type material layer 30.

In combination with experimental data, we found that the diameter of the nanopillar can be changed to change the light emission wavelength of the mqw layer in the nanopillar, and generally, as the diameter of the nanopillar is reduced, the light emission wavelength of the mqw layer in the nanopillar is also reduced.

In addition, compared with the traditional LED which emits light with different colors, the LED chip can simultaneously emit more than two kinds of light through the first nano-pillar region and the second nano-pillar region, so that the display resolution and the color rendering index CRI (which can reach 100) of a device adopting the LED chip are obviously superior to those of the traditional device.

In the LED chip disclosed in the present application, the diameter of the nanopillar in the first nanopillar region 101 is greater than the diameter of the nanopillar in the second nanopillar region 102, so that the first nanopillar region 101 and the second nanopillar region 102 can emit light with different wavelengths respectively, thereby enabling the LED chip to realize colorful display.

Preferably, each of the first nanorod region 101 and the second nanorod region 102 is a triangle or a hexagon (hexagon) formed by a plurality of nanorods. By adopting a triangular or hexagonal structure, the adjacent regions can be closely arranged, and the active area of the multiple quantum well layer 40 can be saved to the maximum extent.

In other embodiments, the first nanopillar region 101 and the second nanopillar region 102 may have other shapes such as a circle, a quadrangle, and a pentagon formed by a plurality of nanopillars.

The first nanopillar region 101 described in the present application has a hexagonal shape or the like, and means a shape of the first nanopillar region 101 in a plan view.

Preferably, the diameter of the nanopillar in the first nanopillar region 101 is 100nm to 1500nm, and the diameter of the nanopillar in the second nanopillar region 102 is 10nm to 800 nm.

Specifically, a white space may be further disposed on the LED chip, and no nano-pillars are formed in the white space, so that the white space may emit light of a third color.

The white light leaving area, the first nano-column area and the second nano-column area respectively emit light of three different colors, and the LED chip can emit light of three colors of red, yellow and blue after proper adjustment, so that three primary colors of light are formed, and the LED chip can realize full-color light emission.

Compared with the traditional full-color micro-display scheme, the LED chip has the following advantages: 1) the nano-pillars can relieve stress, improve light extraction efficiency and meet the requirement of high resolution of small pixels of the LED chip; 2) the LED color-changing material realizes full color on a single LED chip, does not depend on an external luminescent material or an optical component, has stable and uniform color and small volume, and is easy to integrate; 3) the large-scale micro-nano processing with low cost can be carried out by adopting nano-imprinting, so that the full-color LED micro display array scheme has the potential of practical application.

Preferably, the emission wavelength of the multiple quantum well layer is 560nm to 770 nm. Because the nano-pillars can shorten the light-emitting wavelength of the multi-quantum well, the multi-quantum well (red light, orange light and yellow light) with longer light-emitting wavelength is generally selected, so that the nano-pillars have better adjusting space.

In this embodiment, the p-type material layer 30 is a p-GaN layer, the n-type material layer 50 is an n-GaN layer, and the multi-quantum well layer 40 is a multi-quantum well layer (preferably, stacked six times) having InGaN/GaN as a stacked unit.

In other embodiments, other types of multiple quantum wells may be employed.

When the MQW 40 is a MQW having InGaN/GaN as a laminated unit, the number of times of lamination may be 3 to 20.

In the present application, the only standard for selecting the multiple quantum well layer 40 is the light emission wavelength thereof, and the parameters of the multiple quantum well layer 40, such as specific materials, doping ratios, stacking units, and stacking times, can be randomly matched, and only light with the light emission wavelength required by people needs to be emitted.

In this embodiment, the base layer 10 is a silica base layer, the first metal layer 20 is Ni/Au or Ni/Ag, and the material of the second metal layer 60 is Ti/Al. Here, "/" represents the meaning of lamination.

With reference to fig. 2, the present application further discloses a method for manufacturing the LED chip, which includes the following steps:

and S10, providing an LED wafer.

Referring to fig. 2a, the LED die includes a p-type material layer 30, a multiple quantum well layer 40, an n-type material layer 50, and a substrate 200, which are sequentially stacked.

The LED dies are usually purchased directly, and only the LED dies meeting the requirement of the light emission wavelength need to be purchased.

S20, the first metal layer 20 is formed on the p-type material layer 30, and then the base layer 10 is disposed on the first metal layer 20, such that the base layer 10, the first metal layer, and the p-type material layer 30 are sequentially stacked.

Referring to fig. 2b and 2c, the first metal layer 20 is typically formed by electron beam evaporation.

The first metal layer 20 is generally made of a metal material selected to have a high reflectivity so that the first metal layer 20 functions as a reflective layer.

The operation of disposing the base layer 10 on the first metal layer 20 may be: SiO by silica gel ₂The substrate (base layer 10) and the first metal layer 20 are bonded together.

S30, the substrate 200 is removed, and then the first planarization process is performed on the n-type material layer 50.

In this embodiment, the substrate 200 is a sapphire substrate. Removing the substrate 200 operates as: the substrate 200 is removed by a laser lift-off technique (LLO) in which a laser beam used in the laser lift-off technique is a deep ultraviolet laser beam having a wavelength of 266 nm.

The removal of the substrate 200 by laser lift-off (LLO) can avoid crosstalk effects and improve the heat dissipation capability of the LED chip and the current density of each pixel unit.

The laser beam adopted in the laser lift-off technology is a deep ultraviolet laser beam with the wavelength of 266nm to penetrate through the sapphire substrate and be strongly absorbed by the n-GaN layer, so that the interface between the n-GaN layer and the sapphire substrate is ablated.

In other embodiments, the substrate 200 may also be a silicon substrate, and the removing the substrate 200 is performed by: the substrate 200 is removed by wet etching.

In this embodiment, the first leveling process is performed on the n-type material layer by: and thinning the n-type material layer 50 by adopting dry etching, and enabling the surface roughness of the thinned n-type material layer 50 to be less than 10 nm.

After LLO removal of the substrate 200, the n-GaN interface becomes very rough, but excellent surface flatness is necessary for the nanoimprint process. By researching the influence of ICP parameters on the surface Roughness (RMS) and adopting dry etching to thin the n-type material layer, the surface Roughness (RMS) can be reduced to 10 nm. In addition, in order to further restore the smoothness of the etched surface to a level close to that of epitaxial growth, further reduction of RMS using chemical treatment and annealing treatment is required.

S40, a mask layer 300 having a desired pattern is formed on the n-type material layer 50, followed by etching to form the first nanopillar region 101 and the second nanopillar region 102.

Referring to fig. 2f, 2g and 2h, the first and second nanopillar regions 101 and 102 are composed of nanopillars sequentially penetrating the n-type material layer 50, the multiple quantum well layer 40 and the p-type material layer 30, and the diameter of the nanopillars in the first nanopillar region 101 is greater than that of the nanopillars in the second nanopillar region 102.

In this embodiment, the mask layer 300 is a photoresist layer 300.

In this embodiment, the operation of forming a mask layer having a desired pattern on the n-type material layer 50 after the first planarization process is: a photoresist layer 300 is formed by coating a photoresist on the n-type material layer 50, and then a desired pattern is transferred onto the photoresist layer 300 using a nano-imprinting method.

In other embodiments, the operation of forming a mask layer with a desired pattern on the n-type material layer 50 after the first planarization process is further performed by: a Ni etch mask is provided on the n-type material layer 50, followed by SiO deposition on the Ni etch mask ₂Layer, byMimeograph to convert desired patterns to SiO ₂Layer, followed by etching to remove the desired pattern from SiO ₂The layer is transferred to a Ni etch mask to obtain sidewall-vertical nanopillars by high etch selectivity between the Ni etch mask and the n-type material layer. The scheme can ensure that the etched nano-pillars are vertical and have smooth profiles.

S50, performing a second planarization process on the n-type material layer 50 to obtain a semi-finished product, and forming a second electrode layer 60 on the n-type material layer 50 to obtain the desired LED chip.

Referring to fig. 2i, the second electrode layer 60 is generally formed by electron beam evaporation.

Preferably, the second planarization process is performed on the n-type material layer 50 by: and filling a dielectric material in the first nano-pillar region 101 and the second nano-pillar region 102, and performing thinning treatment to expose the n-type material layer. The dielectric material may be a polyimide glass material. The filling dielectric material may fill the gap between the first nano-pillar region 101 and the second nano-pillar region 102, facilitating the preparation of the second electrode layer 60.

Preferably, the operation of forming the second electrode layer 60 on the semi-finished n-type material layer 50 is: after the semi-finished product is mounted obliquely, a second electrode layer 60 is formed on the n-type material layer 50 by evaporation.

The semi-finished product is installed obliquely, so that the metal electron beam can fill the gap obliquely in the evaporation process.