Method and device for controlling programming noise

文档序号：1557872 发布日期：2020-01-21 浏览：15次中文

阅读说明：本技术 一种控制编程噪声的方法和装置 (Method and device for controlling programming noise ) 是由李琪于 2019-09-04 设计创作，主要内容包括：本发明提供了一种控制编程噪声的方法。所述方法包括：对所述Nand flash存储器中存储链与其所处的位线之间的选通管施加第一预设电压,使得选通管导通,在选通管导通的情况下,对Nand flash存储器中存储链所处的位线施加第二预设电压,其中,通过施加第二预设电压,使得Nand flash存储器中存储链的沟道电压从0变为第一初始电压。本发明在预备编程的阶段使得不需要编程的存储链的沟道电压变高,就可以使得在编程的过程中不需要编程的存储单元的浮栅与沟道之间的电压差变得更低,消除了编程过程中引入的编程噪声,提高了Nand Flash的读取精度。(The invention provides a method for controlling programming noise. The method comprises the following steps: applying a first preset voltage to a gate tube between a memory chain in the Nand flash memory and a bit line where the memory chain is located to enable the gate tube to be conducted, and applying a second preset voltage to the bit line where the memory chain in the Nand flash memory is located under the condition that the gate tube is conducted, wherein the channel voltage of the memory chain in the Nand flash memory is changed from 0 to the first initial voltage by applying the second preset voltage. In the pre-programming stage, the voltage of the channel of the memory chain which does not need to be programmed is increased, so that the voltage difference between the floating gate and the channel of the memory unit which does not need to be programmed in the programming process is reduced, programming noise introduced in the programming process is eliminated, and the reading precision of the Nand Flash is improved.)

1. A method for controlling programming noise, the method is applied to a Nand flash memory, and the Nand flash memory comprises: a register and a memory unit, the register being a device for temporarily storing desired program data, the method comprising:

in the case where the data to be programmed is already stored in the register, in preparation for writing to the memory cells:

applying a first preset voltage to a gate tube between a storage chain and a bit line where the storage chain is located in the Nand flash memory, so that the gate tube between the storage chain and the bit line where the storage chain is located is conducted;

under the condition that a gate tube between a memory chain and a bit line where the memory chain is located is conducted, applying a second preset voltage to the bit line where the memory chain is located in the Nand flash memory;

wherein, the channel voltage of the memory chain in the Nand flash memory is changed from 0 to the first initial voltage by applying the second preset voltage.

2. The method of claim 1, wherein after applying a second preset voltage to a bit line in the Nand flash memory where a memory chain is located, the method further comprises:

receiving a programming instruction, and applying gating working voltage to a gate tube between a storage chain in the Nand flash memory and a bit line where the storage chain is located;

applying a power supply voltage to a bit line where the memory chain which does not need to be programmed is located, wherein a gate tube between the memory chain which does not need to be programmed and the bit line where the memory chain does not need to be programmed is turned off through the applied gating working voltage and the applied power supply voltage;

under the condition that a gate tube between the storage chain which does not need to be programmed and a bit line where the storage chain which does not need to be programmed is closed, applying a conducting voltage to a word line where the storage chain which does not need to be programmed is located, wherein the conducting voltage and the first initial voltage act together to change the channel voltage of the storage chain which does not need to be programmed into a first high channel voltage, and further reducing the voltage difference between a floating gate and a channel of the storage unit which does not need to be programmed.

3. The method according to claim 2, wherein the first high channel voltage is a sum of the first initial voltage and a first original voltage, the first original voltage is a channel voltage of the non-programming memory chain when the second preset voltage is not applied to the bit line where the non-programming memory chain is located, and the gate tube between the non-programming memory chain and the bit line where the non-programming memory chain is located is turned off, the power supply voltage is directly applied to the bit line where the non-programming memory chain is located, and the on voltage is applied to the word line where the non-programming memory chain is located.

4. The method of claim 1, further comprising:

receiving an enabling signal, wherein the enabling signal is used for starting or closing a function of applying a third preset voltage to a word line where a storage chain in the Nand flash memory is located, and the third preset voltage is used for increasing the channel voltage of the storage chain in the Nand flash memory;

under the condition that the enable signal is at a high level, applying a third preset voltage to a word line where a storage chain in the Nand flash memory is located;

under the condition that the second preset voltage and the third preset voltage are applied, the second preset voltage and the third preset voltage act together to enable the channel voltage of the memory chain which does not need to be programmed to be changed from 0 to a second initial voltage, and the second initial voltage is determined by the magnitude between the sum of the third preset voltage and the absolute value of the threshold voltage of the memory cell in the Nand flash memory.

5. The method of claim 4, wherein after applying a second preset voltage to a bit line in the Nand flash memory where a memory chain is located, the method further comprises:

receiving a programming instruction, and applying the gating working voltage to a gating tube between a storage chain in the Nand flash memory and a bit line where the storage chain is located;

applying a power supply voltage to a bit line where the memory chain which does not need to be programmed is located, wherein a gate tube between the memory chain which does not need to be programmed and the bit line where the memory chain does not need to be programmed is closed through the applied gating working voltage and the applied power supply voltage;

and under the condition that a gate tube between the storage chain which does not need to be programmed and the bit line of the storage chain is closed, applying a turn-on voltage to the word line where the storage chain which does not need to be programmed is located, wherein the turn-on voltage and the second initial voltage act together to change the channel voltage of the storage chain which does not need to be programmed into a second high channel voltage, and further reducing the voltage difference between a floating gate and a channel of the storage unit which does not need to be programmed.

6. The method according to claim 5, wherein the second high channel voltage is a sum of the second initial voltage and a second original voltage, the second original voltage is a channel voltage of the memory chain not requiring programming when the second preset voltage is not applied to the bit line where the memory chain not requiring programming is located, and the gate tube between the memory chain not requiring programming and the bit line where the memory chain not requiring programming is located is turned off, the power supply voltage is directly applied to the bit line where the memory chain not requiring programming is located, and the difference between the on voltage and the third preset voltage is applied to the word line where the memory chain not requiring programming is located.

7. The method of claim 4, wherein the second initial voltage is greater than the first initial voltage;

under the condition that the sum of the third preset voltage and the absolute value of the threshold voltage of the storage unit in the Nand flash memory is larger than the second preset voltage, the second initial voltage is equal to the absolute value of the threshold voltage of the storage unit in the Nand flash memory;

and under the condition that the sum of the third preset voltage and the absolute value of the threshold voltage of the storage unit in the Nand flash memory is not larger than the second preset voltage, the second initial voltage is equal to the sum of the third preset voltage and the absolute value of the threshold voltage of the storage unit in the Nand flash memory.

8. A method for controlling programming noise, the method is applied to a Nand flash memory, and the Nand flash memory comprises: a register and a memory unit, the register being a device for temporarily storing desired program data, the method comprising:

in the case where the data to be programmed is already stored in the register, in preparation for writing to the memory cells:

applying a first preset voltage to a word line where a memory chain in the Nand flash memory is located, wherein the first preset voltage is used for increasing the channel voltage of the memory chain in the Nand flash memory;

applying a second preset voltage to a gate tube between a storage chain in the Nand flash memory and a bit line where the storage chain is located, so that the gate tube between the storage chain in the Nand flash memory and the bit line where the storage chain is located is conducted;

under the condition that a gate tube between a memory chain in the Nand flash memory and a bit line where the memory chain is located is conducted, applying a third preset voltage to the bit line where the memory chain in the Nand flash memory is located, so that the channel voltage of the memory chain in the Nand flash memory is changed from 0 to an initial voltage, wherein the initial voltage is determined by the sum of the first preset voltage and the absolute value of the threshold voltage of a memory cell in the Nand flash memory.

9. An apparatus for controlling a programming noise, wherein the apparatus is applied to a Nand flash memory, and the Nand flash memory comprises: a register and a memory unit, the register being a device for temporarily storing desired program data, the apparatus comprising:

in the case where the data to be programmed is already stored in the register, in preparation for writing to the memory cells:

the gate tube pressurizing module is used for applying a first preset voltage to a gate tube between a storage chain in the Nand flash memory and a bit line where the storage chain is located so as to enable the gate tube between the storage chain and the bit line where the storage chain is located to be conducted;

the bit line pressurizing module is used for applying a second preset voltage to the bit line of the memory chain in the Nand flash memory under the condition that a gate tube between the memory chain and the bit line is conducted;

wherein, the channel voltage of the memory chain in the Nand flash memory is changed from 0 to the first initial voltage by applying the second preset voltage.

10. An apparatus for controlling a programming noise, wherein the apparatus is applied to a Nand flash memory, and the Nand flash memory comprises: a register and a memory unit, the register being a device for temporarily storing desired program data, the apparatus comprising:

in the case where the data to be programmed is already stored in the register, in preparation for writing to the memory cells:

the word line pressurizing module is used for applying a first preset voltage to a word line where a storage chain in the Nand flash memory is located, and the first preset voltage is used for increasing the channel voltage of the storage chain in the Nand flash memory;

the bit line gate tube pressurizing module is used for applying a second preset voltage to a gate tube between a storage chain in the Nand flash memory and a bit line where the storage chain is located, so that the gate tube between the storage chain in the Nand flash memory and the bit line where the storage chain is located is conducted;

and the unselected bit line pressurizing module is used for applying a third preset voltage to the bit line of the Nand flash memory where the memory chain is located under the condition that a gate tube between the memory chain in the Nand flash memory and the bit line where the memory chain is located is conducted, so that the channel voltage of the memory chain in the Nand flash memory is changed from 0 to an initial voltage, and the initial voltage is determined by the sum of the first preset voltage and the absolute value of the threshold voltage of the memory cell in the Nand flash memory.

Technical Field

The present invention relates to the field of storage, and in particular, to a method and apparatus for controlling programming noise.

Background

The Nand Flash memory is a nonvolatile memory, and the memory capacity of the Nand Flash memory is large, and 1Gb/2Gb/4Gb/16Gb/32Gb and the like are common in the market. The Nand Flash reads and writes the memory array unit according to the Page capacity, and the common Page capacity is 1KB/2KB/4KB/16KB and the like. When the size of the data required to be written by the user is smaller than the capacity of the Page, a Page segment needs to be programmed multiple times to fill the whole Page, for example: assuming that the size of data written by a user for the first time is 2KB, but the page capacity of Nand Flash used by the user is 4KB, the data of 2KB is written into page0 of Nand Flash for the first time (assuming that page0 is the first page of Nand Flash), and then the size of data written by the user for the second time is 4KB, according to the characteristics of Nand Flash, 2KB of the data of 4KB is written into page0, and the rest 2KB is written into page 1.

However, when the same page is programmed for many times, larger programming noise is introduced to enable the threshold value of a '1' memory cell (cell) to be high, and then the reading precision of Nand Flash is influenced, in addition, when a user alternately programs and erases the Nand Flash for thousands of times continuously, the cell is easier to program and more difficult to erase due to the introduction of 'defects' in the cell, and when the programming becomes easier, the larger programming noise is introduced to enable the threshold value of the '1' cell to be high, and then the reading precision of the Nand Flash is influenced.

Disclosure of Invention

In view of the above problems, the present invention provides a method for controlling programming noise, which solves the problem that the threshold of a "1" memory cell becomes high due to the introduction of programming noise during programming.

In order to solve the above technical problem, an embodiment of the present invention provides a method for controlling a programming noise, where the method is applied to a Nand flash memory, and the Nand flash memory includes: a register and a memory unit, the register being a device for temporarily storing desired program data, the method comprising:

in the case where the data to be programmed is already stored in the register, in preparation for writing to the memory cells:

wherein, the channel voltage of the memory chain in the Nand flash memory is changed from 0 to the first initial voltage by applying the second preset voltage.

Optionally, after applying a second preset voltage to the bit line where the memory chain in the Nand flash memory is located, the method further comprises:

receiving a programming instruction, and applying gating working voltage to a gate tube between a storage chain in the Nand flash memory and a bit line where the storage chain is located;

Optionally, the first high channel voltage is a sum of the first initial voltage and a first original voltage, the first original voltage is the channel voltage of the storage chain which does not need to be programmed when the second preset voltage is not applied to the bit line where the storage chain which does not need to be programmed is located, and when the gate tube between the storage chain which does not need to be programmed and the bit line where the storage chain which does not need to be programmed is turned off, the power supply voltage is directly applied to the bit line where the storage chain which does not need to be programmed is located, and the turn-on voltage is applied to the word line where the storage chain which does not need to be programmed is located.

Optionally, the method further comprises:

under the condition that the enable signal is at a high level, applying a third preset voltage to a word line where a storage chain in the Nand flash memory is located;

Optionally, after applying a second preset voltage to the bit line where the memory chain in the Nand flash memory is located, the method further comprises:

receiving a programming instruction, and applying the gating working voltage to a gating tube between a storage chain in the Nand flash memory and a bit line where the storage chain is located;

applying a power supply voltage to a bit line where the memory chain which does not need to be programmed is located, wherein a gate tube between the memory chain which does not need to be programmed and the bit line where the memory chain does not need to be programmed is closed through the applied gating working voltage and the applied power supply voltage;

Optionally, the second high channel voltage is a sum of the second initial voltage and a second original voltage, the second original voltage is the channel voltage of the storage chain not requiring programming when the second preset voltage is not applied to the bit line where the storage chain not requiring programming is located, and the power supply voltage is directly applied to the bit line where the storage chain not requiring programming is located and the difference between the turn-on voltage and the third preset voltage is applied to the word line where the storage chain not requiring programming is located when the gate tube between the storage chain not requiring programming and the bit line where the storage chain is located is turned off.

Optionally, the second initial voltage is greater than the first initial voltage;

the second initial voltage is equal to the absolute value of the threshold voltage of the memory cell which does not need to be programmed under the condition that the sum of the third preset voltage and the absolute value of the threshold voltage of the memory cell which does not need to be programmed is greater than the second preset voltage;

and under the condition that the sum of the third preset voltage and the absolute value of the threshold voltage of the memory cell which does not need to be programmed is not greater than the second preset voltage, the second initial voltage is equal to the sum of the third preset voltage and the absolute value of the threshold voltage of the memory cell which does not need to be programmed.

The embodiment of the invention also provides another method for controlling programming noise, which is applied to a Nand flash memory, and the Nand flash memory comprises the following steps: a register and a memory unit, the register being a device for temporarily storing desired program data, the method comprising:

in the case where the data to be programmed is already stored in the register, in preparation for writing to the memory cells:

The embodiment of the invention also provides a device for controlling programming noise, which is applied to a Nand flash memory, wherein the Nand flash memory comprises: a register and a memory unit, the register being a device for temporarily storing desired program data, the apparatus comprising:

in the case where the data to be programmed is already stored in the register, in preparation for writing to the memory cells:

wherein, the channel voltage of the memory chain in the Nand flash memory is changed from 0 to the first initial voltage by applying the second preset voltage.

Optionally, the apparatus further comprises:

the programming bit line gate tube pressurizing module is used for receiving a programming instruction and applying a gate working voltage to a gate tube between a storage chain in the Nand flash memory and a bit line where the storage chain is located;

the unselected bit line plus power supply voltage module is used for applying power supply voltage to the bit line where the memory chain which does not need to be programmed is located, wherein the gate tube between the memory chain which does not need to be programmed and the bit line where the memory chain which does not need to be programmed is turned off through the applied gating working voltage and the applied power supply voltage;

and the word line pressurization turning-on module is used for applying a turning-on voltage to the word line where the storage chain which does not need to be programmed is located under the condition that a gate tube between the storage chain which does not need to be programmed and a bit line where the storage chain which does not need to be programmed is turned off, and the turning-on voltage and the first initial voltage act together to change the channel voltage of the storage chain which does not need to be programmed into a first high channel voltage, so that the voltage difference between a floating gate and a channel of the storage unit which does not need to be programmed is reduced.

Optionally, the apparatus further comprises:

and the first high channel voltage dereferencing module is used for dereferencing the first high channel voltage, wherein the first high channel voltage is the sum of the first initial voltage and a first original voltage, the first original voltage is the channel voltage of the storage chain which does not need to be programmed when the second preset voltage is not applied to the bit line where the storage chain which does not need to be programmed is positioned, and the power supply voltage is directly applied to the bit line where the storage chain which does not need to be programmed is positioned under the condition that a gate tube between the storage chain which does not need to be programmed and the bit line where the storage chain which does not need to be programmed is closed, and the conduction voltage is applied to the word line where the storage chain which does not need to be programmed is positioned.

Optionally, the apparatus further comprises:

the enable module is used for receiving an enable signal, the enable signal is used for starting or closing a function of applying a third preset voltage to a word line where a memory chain in the Nand flash memory is located, and the third preset voltage is used for increasing the channel voltage of the memory chain in the Nand flash memory;

the high-level word line pressurizing module is used for applying a third preset voltage to the word line where the storage chain in the Nandflash memory is located under the condition that the enabling signal is at a high level;

under the condition that the second preset voltage and the third preset voltage are applied, the second preset voltage and the third preset voltage act together to enable the channel voltage of a memory chain in the Nand flash memory to be changed from 0 to a second initial voltage, and the second initial voltage is determined by the sum of the third preset voltage and the absolute value of the threshold voltage of a memory cell in the Nand flash memory and the magnitude of the absolute value of the threshold voltage of the memory cell in the Nand flash memory.

Optionally, the apparatus further comprises:

the high-level programming bit line gate tube pressurizing module is used for receiving a programming instruction and applying the gate working voltage to a gate tube between a storage chain in the Nand flash memory and a bit line where the storage chain is located;

the high-level unselected bit line plus power supply voltage module is used for applying power supply voltage to the bit line where the storage chain which does not need to be programmed is located, wherein a gate tube between the storage chain which does not need to be programmed and the bit line where the storage chain which does not need to be programmed is turned off through the applied gating working voltage and the applied power supply voltage;

and the high-level word line pressurization turning-on module is used for applying a turning-on voltage to the word line where the storage chain which does not need to be programmed is located under the condition that a gate tube between the storage chain which does not need to be programmed and the bit line where the storage chain which does not need to be programmed is turned off, and the turning-on voltage and the second initial voltage act together to change the channel voltage of the storage chain which does not need to be programmed into a second high channel voltage so as to reduce the voltage difference between the floating gate and the channel of the storage unit which does not need to be programmed.

Optionally, the apparatus further comprises:

and the second high-channel voltage value taking module is used for taking the second high-channel voltage, the second high-channel voltage is the sum of the second initial voltage and a second original voltage, the second original voltage is the channel voltage of the storage chain which does not need to be programmed when the second preset voltage is not applied to the bit line where the storage chain which does not need to be programmed is located, and the power supply voltage is directly applied to the bit line where the storage chain which does not need to be programmed is located under the condition that a gate tube between the storage chain which does not need to be programmed and the bit line where the storage chain which does not need to be programmed is turned off, and the channel voltage of the storage chain which does not need to be programmed is applied to the word line where the storage chain which does not need to be programmed is located when the difference between the conduction voltage and the.

Optionally, the apparatus further comprises:

a second initial voltage dereferencing module, configured to dereference the second initial voltage, where the second initial voltage is greater than the first initial voltage;

The embodiment of the invention also provides another device for controlling programming noise, which is applied to a Nand flash memory, and the Nand flash memory comprises: a register and a memory unit, the register being a device for temporarily storing desired program data, the apparatus comprising:

in the case where the data to be programmed is already stored in the register, in preparation for writing to the memory cells:

The invention provides a method for controlling programming noise, which is characterized in that under the condition that data to be programmed is ready to be written into a storage unit, a first preset voltage is applied to a gate tube between a storage chain and a bit line where the storage chain is located in a Nand flash memory, so that the gate tube between the storage chain and the bit line where the storage chain is located is conducted; under the condition that a gate tube between a memory chain and a bit line where the memory chain is located is conducted, applying a second preset voltage to the bit line where the memory chain is located in the Nand flash memory; so that the channel voltage of the memory chain in the Nandflash memory is changed from 0 to the first initial voltage. Namely, the channel voltage of the memory chain in the Nandflash memory is increased in the pre-programming stage, so that the voltage difference between the floating gate and the channel of the memory unit which does not need to be programmed in the programming process is reduced, programming noise introduced in the programming process is eliminated, and the reading precision of Nandflash is improved.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic diagram of a cell with two Bit Lines (BL) connected in a memory cell of a Nand flash memory and an equivalent capacitor thereof;

FIG. 2 is a timing diagram illustrating the programming process of memory cells that need not be programmed in the current Nand flash memory;

FIG. 3 is a diagram illustrating the effect of current programming noise on the threshold distribution of a cell;

FIG. 4 is a flow chart of a method of controlling programming noise in accordance with an embodiment of the present invention;

FIG. 5 is a timing diagram of a memory cell that does not need to be programmed in a first method for controlling program noise according to an embodiment of the present invention;

FIG. 6 is a timing diagram of a memory cell that does not need to be programmed in the second method for controlling the programming noise according to the embodiment of the present invention;

fig. 7 is a block diagram of an apparatus for controlling program noise according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.

The inventor finds that programming noise is introduced into the memory cell of the Nand flash memory during the programming operation, which causes the accuracy of the read operation of the Nand flash memory to be low, and the reason for the problem is that: the high voltage difference between the floating gate and the channel of the "1" cell makes the threshold of the "1" cell high, resulting in a decrease in the accuracy of the read operation of the Nand flash memory.

Firstly, the programming operation process of the memory unit of the current Nand flash memory is analyzed as follows:

referring to fig. 1, a schematic diagram of a cell in which two Bit Lines (BL) of a memory cell in a Nand flash memory are connected and an equivalent capacitance schematic diagram thereof are shown; referring to FIG. 2, a timing diagram of the programming process of memory cells that currently do not need to be programmed in Nand flash memory is shown. Assuming that m cells (m cells form a memory chain) are respectively connected in series to two BLs, and an nth cell on BL1 needs to be programmed, during programming, a program voltage Vpgm, that is, WLn is Vpgm, is applied to a floating gate of the cell, and a pass voltage Vpass is applied to other cells that do not need to be programmed, that is, WL0 to WLn-1 are Vpass, and WLn +1 to WLm are Vpass, and the Vpass enables the other cells that do not need to be programmed to pass through, so that channels (channels) of the same BL series connected cells are all connected together, and during programming:

since the nth cell in BL1 needs to be programmed, a voltage 0 needs to be applied to BL1, and a gate operating voltage needs to be applied to a gate tube (Sgd) of BL1, so that the gate tube (i.e., the gate tube between the memory chain and the bit line BL1 where the gate tube is located) is turned on, when a floating gate boosting program voltage WLn of the cell needing to be programmed is Vpgm, and when other cell boosting pass voltages WL _ unsel that do not need to be programmed are Vpass, a Channel voltage of the cell in series with BL1 is 0, a voltage difference between the floating gate and the Channel of the cell needing to be programmed is Vpgm, electrons in the Channel of the cell needing to be programmed pass through the floating gate from the Channel thereof under the action of the voltage Vpgm, at this time, a threshold of the cell needing to be programmed is raised to a positive value, and the cell needing to be programmed is programmed. The voltage difference between the floating gate and the channel of the cell which does not need to be programmed is Vpass, but the voltage Vpass is not enough to cause electrons in the channel of the cell which does not need to be programmed to tunnel into the floating gate, and the cell which does not need to be programmed still keeps a negative value, namely, the cell which does not need to be programmed cannot be programmed.

According to the characteristics of the Nand flash memory storage unit, WLn is applied to the nth cell in the BL1, and WLn is also applied to the nth cell in the BL 2. Since no cell in series connected to BL2 needs to be programmed, a power supply voltage vdd needs to be applied to BL2, and similarly, a gate operating voltage is also applied to a gate tube (Sgd) of BL2, so that the gate tube of BL2 is turned off, and in the case that a floating gate boosting programming voltage WLn of an nth cell of BL2 is Vpgm and a floating gate boosting turn-on voltage WL _ unsel of other cells that do not need to be programmed is Vpass, an original voltage vch on a channel of a cell in series connected to BL2 is [1/m Vpgm + (m-1)/m Vpass ] [ c1/(c1+ c2) ], where c1 is an equivalent capacitance of a floating gate to a channel of a cell in series connected to BL2, and c2 is an equivalent capacitance of a channel to a substrate of a cell in series connected to BL 2. At this time, the voltage difference between the floating gate and the channel of the nth cell in BL2 is Vpgm-vch, electrons in the channel of the nth cell in BL2 cannot tunnel to the floating gate under the action of the Vpgm-vch voltage, the threshold of the nth cell in BL2 is kept as a negative number, and the nth cell in BL2 is not programmed.

Based on the above programming process, the inventors further found that the specific reasons and effects of the programming noise introduced during the programming operation are:

when the same page is programmed for multiple times, Vpgm-vch is continuously pressed between the floating gate and the channel for multiple times for cells that do not need to be programmed, a small amount of electrons are tunneled from the channel to the floating gate, so that the threshold of the originally-unneeded programmed "1" cell is increased, i.e. programming noise is introduced. It can be understood that programming noise is caused to the data programmed for the 1 st time when the 2 nd time of the same page is programmed, programming noise is caused to the data programmed for the 1 st time and the 2 nd time when the 3 rd time of the same page is programmed, and so on, and in order to ensure the reliability of reading data, the industry generally stipulates that the number of times of programming the same page is not more than 4 times, which limits the effective use of the Nand Flash memory with large capacity in an application place with a smaller unit data amount.

In addition, when a user alternately programs and erases the Nand Flash memory for thousands of times, a defect is introduced into an oxide layer between a floating gate and a channel of a cell, so that a small amount of electrons still move from the channel to the floating gate under the voltage difference Vpgm-vch of the cell which does not need to be programmed, and the threshold value of the cell which does not need to be programmed is increased, which is also the introduction of programming noise. Under the influence, the programming and erasing times of most Nand Flash memories in the industry are generally varied from hundreds to tens of thousands.

Referring to fig. 3, which illustrates a schematic diagram of an influence of a current programming noise on a cell threshold distribution, where "1" in fig. 3 indicates a cell that does not need to be programmed, and "0" indicates a cell that is programmed, the programming noise may cause the threshold distribution of the cell of the Nand Flash memory to shift to the right, that is, the threshold of the "1" cell becomes larger, assuming that the voltage when the Nand Flash memory reads data is Vrd, when the threshold voltage of the "1" cell becomes larger, a difference V _ m between a maximum value of the threshold distribution of the "1" cell and the Vrd is smaller to be V _ m1 shown in fig. 3, so that an error becomes larger when the Nand Flash memory reads data, and the accuracy is reduced.

Based on the above problems, the inventor of the present invention has made extensive research, combines the characteristics of the cell in the Nand flash memory, and through a large number of field tests and simulation calculations, and has creatively proposed to apply a preset voltage to the bit line of the cell that does not need to be programmed in the preliminary programming stage, thereby increasing the channel voltage of the cell that does not need to be programmed, and reducing the voltage difference between the floating gate and the channel of the cell that does not need to be programmed in the programming process, thereby solving the above problems. The solution proposed by the inventors is explained and illustrated in detail below.

FIG. 4 shows a flow chart of a method of controlling programming noise in accordance with an embodiment of the invention. The method is applied to a Nand flash memory, and the Nand flash memory comprises the following steps: the register is a device for temporarily storing required programming data, and the method for controlling the programming noise comprises the following steps:

in the case where the data to be programmed is already stored in the register, ready to be written to the memory cell:

step 101: and applying a first preset voltage to a gate tube between a memory chain and a bit line where the memory chain is located in the Nand flash memory, so that the gate tube between the memory chain and the bit line where the memory chain is located is conducted.

In the embodiment of the invention, according to the characteristics of the Nand flash memory, in the whole programming operation process of the Nand flash memory, data required to be programmed is firstly put in the register, and then the relevant instruction is received, so that the data required to be programmed is written into the corresponding cell from the register, and the stage is called a pre-programming stage.

In the preliminary programming stage, a first preset voltage is applied to the gate tube between the memory chain and the bit line where the memory chain is located in the Nand flash memory, so that the gate tube between the memory chain and the bit line where the memory chain is located is conducted, the first preset voltage is greater than the gate working voltage for conducting the gate tube under general conditions, the reason why the first preset voltage is greater than the gate working voltage and the purpose of conducting the gate tube at this stage are explained in the corresponding places below, and are not described in detail herein.

Step 102: and under the condition that a gate tube between the memory chain and the bit line where the memory chain is positioned is conducted, applying a second preset voltage to the bit line where the memory chain is positioned in the Nand flash memory.

In the embodiment of the invention, in the preliminary programming stage, under the condition that a gate tube between a memory chain and a bit line where the memory chain is located is conducted, a second preset voltage Vbl is applied to the bit line where the memory chain is located in the Nand flash memory. Because the gate tube between the memory chain and the bit line where the memory chain is located is conducted, and the threshold values of the memory cells in the Nand flash memory are negative values, and no voltage (0) is applied to the word lines where the memory cells in the Nand flash memory are located, the second preset voltage Vbl is loaded to the memory cells in the Nand flash memory through the conducted gate tube, so that the memory cells in the Nand flash memory are all conducted, the communication of the memory cells in the Nand flash memory is connected and conducted, at the moment, the communication voltage of the memory chain in the Nand flash memory is changed from 0 to a first initial voltage, and the value of the first initial voltage is the absolute value of the threshold voltage of the memory cells in the Nand flash memory: vth |.

Because the second preset voltage Vbl is applied to the bit line where the storage chain in the Nand flash memory is located, the conduction of the gate tube on the bit line where the storage chain which does not need to be programmed is ensured only by increasing the voltage of the gate tube on the bit line where the storage chain in the Nand flash memory is located, so that the first preset voltage is greater than the gating working voltage for conducting the gate tube under the ordinary condition. The specific value of the first preset voltage is determined by a second preset voltage Vbl, the specific value of the second preset voltage Vbl is an empirical value obtained through a large number of actual tests and simulation calculations, the value of the empirical value is smaller than the power supply voltage and larger than 0, and different Nand flash memories may cause different second preset voltages Vbl according to different processes.

In the above process, the channel voltage of the memory chain in the Nand flash memory is changed from 0 to the first initial voltage by applying the second preset voltage Vbl to the bit line where the memory chain in the Nand flash memory is located, that is, the channel voltage of the memory chain in the Nand flash memory becomes high at a stage when the programming process is not yet performed.

Optionally, after applying a second preset voltage to the bit line where the memory chain in the Nand flash memory is located, and increasing the channel voltage of the memory chain in the Nand flash memory, the method for controlling the programming noise further includes the following steps:

step 103: and receiving a programming instruction, and applying gating working voltage to a gate tube between a memory chain and a bit line where the memory chain is located in the Nand flash memory.

In the embodiment of the invention, after the operation is completed in the preliminary stage, a formal programming stage is entered, namely, a stage of writing data required to be programmed into a cell in a Nand flash memory. The operating method of the stage and the current programming stage is that the programming instruction is received, and the gating working voltage is applied to the gating tube between the memory chain in the Nand flash memory and the bit line where the memory chain is located, so that the gating tube on the bit line where the cell needing to be programmed is located is conducted.

Step 104: and applying a power supply voltage to the bit line where the memory chain which does not need to be programmed is located, wherein the gate tube between the memory chain which does not need to be programmed and the bit line where the memory chain does not need to be programmed is closed through the applied gating working voltage and the applied power supply voltage.

In the embodiment of the invention, in the programming stage, a power supply voltage is required to be applied to the bit line where the memory chain which does not need to be programmed is located, and the power supply voltage and the gating working voltage enable the gating tube on the bit line where the memory chain which does not need to be programmed is located to be turned off.

Step 105: under the condition that a gate tube between a storage chain which does not need to be programmed and a bit line where the storage chain does not need to be programmed is turned off, a conducting voltage is applied to a word line where the storage chain which does not need to be programmed is located, and the conducting voltage and a first initial voltage act together, so that the channel voltage of the storage chain which does not need to be programmed is changed into a first high channel voltage, and the voltage difference between a floating gate and a channel of a storage unit which does not need to be programmed is further reduced.

In the embodiment of the invention, under the condition that the gate tube on the bit line where the programmed memory chain is positioned is not required to be turned off, as can be seen from the above operation principle, the channel voltage of the memory chain not requiring programming should be the first original voltage vch [1/m × Vpgm + (m-1)/m × Vpass ] [ c1/(c1+ c2) ], but because the channel voltage of the memory chain that does not need to be programmed is changed from 0 to the first initial voltage | Vth | in the preliminary programming stage, the channel voltage of the memory chain not requiring programming at this time becomes the first high channel voltage vch1, the first high channel voltage vch1 takes the value of the sum of the first initial voltage and the first initial voltage vch, the first high channel voltage vch1 takes the value of vch1 ═ 1/m × Vpgm + (m-1)/m × Vpass ], [ c1/(c1+ c2) ] + | Vth |.

The gate on the bit line of the memory chain to be programmed is turned on and the voltage applied to the bit line of the memory chain to be programmed is 0, so that the channel voltage raised in the preliminary stage is discharged to 0 again.

In summary, the method can reduce Vth | programming noise, that is, in the programming phase, the channel voltage of the memory chain which does not need to be programmed becomes high, and the channel voltage of the memory chain which does not need to be programmed becomes high, so that the voltage difference between the floating gate and the channel of the memory cell which does not need to be programmed is reduced, compared with the voltage difference Vpgm-vch between the floating gate and the channel of the memory cell which does not need to be programmed at present, the voltage difference Vpgm-vch1 between the floating gate and the channel of the memory cell which does not need to be programmed is lower, and the lower voltage difference does not cause electrons of the memory cell which does not need to be programmed to tunnel from the channel to the floating gate, so that the programming noise is not introduced in the programming process.

Optionally, the method may solve the problem of program noise introduced in the programming process of the Nand Flash memory in general, but when a user alternately programs and erases the Nand Flash memory ten thousand times, a "defect" is introduced in an oxide layer between a floating gate and a channel of a cell, which may cause that a threshold of the cell that does not need to be programmed may gradually approach 0 from a negative value, that is, an absolute value | Vth | of the threshold of the cell that does not need to be programmed becomes smaller or even 0, and at this time, the problem of program noise cannot be solved by using the above method, so that, on the basis of the above method, the embodiment of the present application provides a second method for controlling program noise, which solves the problem of program noise, and specifically includes:

step 201: and receiving an enabling signal, wherein the enabling signal is used for starting or closing a function of applying a third preset voltage to a word line where a memory chain in the Nand flash memory is located, and the third preset voltage is used for increasing the channel voltage of the memory chain in the Nand flash memory.

Step 202: under the condition that the enabling signal is at a high level, applying a third preset voltage to a word line where a storage chain in the Nand flash memory is located;

under the condition that a second preset voltage and a third preset voltage are applied, the second preset voltage and the third preset voltage act together to enable the channel voltage of a memory chain in the Nand flash memory to be changed from 0 to a second initial voltage, and the second initial voltage is determined by the sum of the third preset voltage and the absolute value of the threshold voltage of a memory cell in the Nand flash memory and the absolute value of the threshold voltage of the memory cell in the Nand flash memory.

In the embodiment of the invention, because the performance indexes of each cell are normal at the initial use stage of the Nand Flash memory, the purpose can be achieved by only using the former method, so that an enable signal can be set, the enable signal is used for turning on or turning off the function of applying the third preset voltage V1 to the word line where the memory chain in the Nand Flash memory is located, namely, when the function of applying the third preset voltage to the word line where the memory chain in the Nand Flash memory is located is turned on, the second method for controlling the programming noise is adopted. It may be defined that the function is turned on when the enable signal is at a high level, and is turned off when the enable signal is at a low level, or it may be defined that the function is turned on when the enable signal is at a low level, and is turned off when the enable signal is at a high level, which is not limited in this embodiment of the present invention.

In the above method, when the threshold of the memory cell is negative, the second preset voltage Vbl is loaded to the memory cell through the conducting gate tube, and at this time, no voltage (0) is applied to the word line of the memory chain in the Nand flash memory, so that the memory cells can be all conducted, but when the threshold of the memory cell is increased and gradually approaches or even equals to 0, the second preset voltage Vbl is loaded to the memory cell through the conducting gate tube, so that the memory cells cannot be all conducted, and therefore, the third preset voltage V1 is applied to the word line of the memory chain in the Nand flash memory, that is, the voltage of the word line of the memory chain in the Nand flash memory is increased, so that the memory cells are all conducted, in this way, the channel voltage of the memory chain in the Nand flash memory is changed from 0 to the second initial voltage by the cooperation of the second preset voltage Vbl and the third preset voltage V1.

Wherein, the second initial voltage is determined by the magnitude between the sum of the third preset voltage V1 and the absolute value | Vth | of the threshold voltage of the memory cell not requiring programming. When V1+ | Vth | > Vbl, the second initial voltage is equal to Vbl; when V1+ | Vth | < ═ Vbl, the second initial voltage is equal to V1+ | Vth |. The specific value of the third preset voltage V1 is an empirical value obtained through a large number of actual tests and simulation calculations, the value of the third preset voltage V1 is smaller than the turn-on voltage and larger than 0, and different Nand flash memories may cause different third preset voltages V1 according to different processes.

Similarly, after the preliminary programming stage, the stage of the programming process is entered, which includes the following steps:

step 203: receiving a programming instruction, and applying gating working voltage to a gate tube between a storage chain in a Nand flash memory and a bit line where the storage chain is located in the Nand flash memory;

step 204: applying a power supply voltage to a bit line where a memory chain which does not need to be programmed is located, wherein a gate tube between the memory chain which does not need to be programmed and the bit line where the memory chain does not need to be programmed is turned off by the applied gating working voltage and the applied power supply voltage;

step 205: under the condition that a gate tube between a storage chain which does not need to be programmed and a bit line where the storage chain does not need to be programmed is turned off, a conducting voltage is applied to a word line where the storage chain which does not need to be programmed is located, and the conducting voltage and a second initial voltage act together, so that the channel voltage of the storage chain which does not need to be programmed is changed into a second high channel voltage, and the voltage difference between a floating gate and a channel of a storage unit which does not need to be programmed is further reduced.

In the embodiment of the present invention, in the stage of the programming process, in the case that the gate transistor on the bit line of the memory chain not requiring programming is turned off, the pass voltage applied to the word line of the memory chain not requiring programming is Vpass-V1, and the program voltage applied to the word line of the memory chain requiring programming is Vpgm-V1, according to the above-mentioned operation principle, the channel voltage of the memory chain not requiring programming should be the second original voltage δ Vch [ [1/m × Vpgm + (m-1)/m × Vpass ] [ [ c1/(c1+ c2) ] -V1 [ c1/(c1+ c2) ], but since the channel voltage of the memory chain not requiring programming is changed from 0 to the second original voltage in the preliminary programming stage, the channel voltage of the memory chain not requiring programming at this time is changed to the second high channel voltage Vch2, the value of the second high channel voltage Vch2 is the sum of the second initial voltage and the second original voltage δ Vch, and the value of the second high channel voltage Vch2 is:

when V1+ | Vth | > Vbl:

vch2＝[1/m*Vpgm+(m-1)/m*Vpass]*[c1/(c1+c2)]+Vbl-V1*[c1/(c1+c2)]；

when V1+ | Vth | < ═ Vbl:

vch2＝[1/m*Vpgm+(m-1)/m*Vpass]*[c1/(c1+c2)]+|Vth|+V1-V1*[c1/(c1+c2)]。

in summary, the second method can reduce the programming noise of Vbl-V1 [ c1/(c1+ c2) ] when V1+ | Vth | > Vbl; at V1+ | Vth | < ═ Vbl, the programming noise of | Vth | + V1 [ c2/(c1+ c2) ] can be reduced, that is, in the programming stage, the channel voltage of the memory chain which does not need to be programmed becomes high, and the channel voltage of the memory chain which does not need to be programmed becomes high, so that the voltage difference between the floating gate and the channel of the memory cell which does not need to be programmed is reduced, compared with the voltage difference Vpgm-vch1 between the floating gate and the channel of the memory cell which does not need to be programmed in the prior method, the voltage difference between the floating gate and the channel of the memory cell which does not need to be programmed is lower than Vpgm-vch1, the lower voltage difference can not be close to or even become 0 when the threshold value of the memory cell which does not need to be programmed becomes high, electrons of the memory cells which are not required to be programmed tunnel into the floating gate from the channel, so that programming noise is not introduced in the programming process.

The first method and the second method are explained and explained in conjunction with the timing diagrams, respectively.

Referring to fig. 5, a timing diagram of a memory cell that does not need to be programmed in a first method for controlling program noise according to an embodiment of the present invention is shown, in which phase one refers to a preliminary programming phase, phase two refers to a phase of a programming process, sgd refers to a gate tube between a memory chain and a bit line, vsg refers to a first preset voltage, vsgd refers to a gate voltage, WLn refers to a program voltage, WL _ unsel refers to a turn-on voltage, sgs refers to a source terminal common to the memory chain, 1data channel refers to a channel voltage of the memory chain that does not need to be programmed, and 0data channel refers to a channel voltage of the memory chain that needs to be programmed.

Under the method, the threshold value of a storage unit in the Nand flash memory is kept normal and is a negative value, and in the first stage: vsg is applied to a gate tube of a memory chain in the Nand flash memory and a bit line where the memory chain is located, so that the gate tube between the memory chain and the bit line where the memory chain is located is conducted, a second preset voltage Vbl is applied to the bit line where the memory chain in the Nand flash memory is located, WLn and WL _ unsel of the memory chain in the Nand flash memory are both 0, and since a threshold value of a memory cell in the Nand flash memory is a negative number, memory cells in the memory chain in the Nand flash memory are both conducted, and channels of the memory cells in the Nand flash memory are connected. When sgd is turned on, according to the characteristics of the memory cells in the Nand flash memory, the 1data channel voltage changes from 0 to the absolute value of the threshold of the memory cells in the Nand flash memory: vth |.

In the second stage: applying vsgd to a gate tube between a memory chain and a bit line where the memory chain is located in the Nand flash memory, applying a power supply voltage vdd to the bit line where the memory chain which does not need to be programmed is located, so that sgd is turned off, applying a voltage Vpgm to a word line of a memory cell which does not need to be programmed and is the same as the memory cell which needs to be programmed, and applying a voltage Vpass to word lines of the remaining memory cells which do not need to be programmed, the 1data channel voltage becomes: vch [1/m × Vpgm + (m-1)/m × Vpass ] × [ c1/(c1+ c2) ].

Since the initial value | Vth | is loaded on the 1data channel in the first phase, the voltage of the 1data channel in the final programming process is: vch1 ═ Vch + | Vth | ([ 1/m × Vpgm + (m-1)/m × Vpass ] - [ c1/(c1+ c2) ] + | Vth |;

that is, the voltage difference between the floating gate and the channel of the memory cell which does not need to be programmed at the stage of the programming process is Vpgm-vch1, the voltage difference between the floating gate and the channel of the memory cell which does not need to be programmed is reduced, and electrons of the memory cell which does not need to be programmed are not tunneled from the channel to the floating gate by the lower voltage difference, so that the programming noise is not introduced in the programming process.

Referring to fig. 6, a timing diagram of a memory cell that does not need to be programmed in the second method for controlling program noise according to the embodiment of the invention is shown, in which phase one refers to a preliminary program phase, phase two refers to a phase of a program process, sgd refers to a gate tube between a memory chain and a bit line, vsg refers to a first preset voltage, vsgd refers to a gate voltage, WLn refers to a program voltage, WL _ unsel refers to a turn-on voltage, sgs refers to a source terminal common to the memory chain, 1data channel refers to a channel voltage of the memory chain that does not need to be programmed, and 0data channel refers to a channel voltage of the memory chain that needs to be programmed.

Under the method, the threshold value of the storage unit in the Nand flash memory approaches to 0, and the storage units in the Nand flash memory cannot be conducted by adopting the first method, so that in the first stage: and applying a third preset voltage V1 to floating gates of the storage units in the Nand flash memory, wherein the other steps are the same as the first method, so that the storage units in the Nand flash memory are all conducted, and channels of the storage units in the Nand flash memory are connected. When sgd is turned on, according to the characteristics of the memory cell in the Nandflash memory, the 1data channel voltage is: when V1+ | Vth | > Vbl, the 1datachannel voltage is equal to Vbl; when V1+ | Vth | < ═ Vbl, the 1data channel voltage is equal to V1+ | Vth |.

In the second stage: applying vsgd to a gate tube between a memory chain and a bit line of the Nand flash memory, applying a power supply voltage vdd to the bit line of the memory chain which does not need to be programmed, so that sgd is turned off, applying a voltage Vpgm-V1 to a word line of a memory cell which does not need to be programmed and is the same as the memory cell which needs to be programmed, and applying a voltage Vpass-V1 to word lines of the rest memory cells which do not need to be programmed, the 1data channel voltage becomes: δ Vch [ [1/m × Vpgm + (m-1)/m × Vpass ] [ c1/(c1+ c2) ] -V1 [ [ c1/(c1+ c2) ]. Since the initial value is loaded on the 1data channel in the first phase, the voltage of the 1data channel in the final programming process is: when V1+ | Vth | > Vbl: vch2 [1/m × Vpgm + (m-1)/m × Vpass ] [ c1/(c1+ c2) ] + Vbl-V1 [ c1/(c1+ c2) ]; when V1+ | Vth | < ═ Vbl: vch2 [1/m × Vpgm + (m-1)/m × Vpass ] [ c1/(c1+ c2) ] + | Vth | + V1-V1 [ c1/(c1+ c2) ].

That is, the voltage difference between the floating gate and the channel of the memory cell which is not required to be programmed at the stage of the programming process is lower than the voltage difference Vpgm-vch1 of the first method, so that the voltage difference between the floating gate and the channel of the memory cell which is not required to be programmed is reduced, electrons of the memory cell which is not required to be programmed are not tunneled from the channel to the floating gate by the lower voltage difference, and programming noise is not introduced in the programming process.

It should be noted that, when the Nand flash memory is actually used, the second method for controlling the program noise may not be set, because the third preset voltage is directly applied to the word line of the memory chain in the Nand flash memory and does not affect the normal use of the Nand flash memory, so the second method for controlling the program noise may be used from the beginning, that is, the preset voltage is directly applied to the word line of the memory chain in the Nand flash memory without setting the enable signal, and the method specifically includes:

in the case where the data to be programmed is already stored in the register, ready to be written to the memory cell:

under the condition that a gate tube between a memory chain in the Nand flash memory and a bit line where the memory chain is located is conducted, a third preset voltage is applied to the bit line where the memory chain in the Nand flash memory is located, so that the channel voltage of the memory chain in the Nand flash memory is changed from 0 to an initial voltage, and the initial voltage is determined by the sum of the first preset voltage and the absolute value of the threshold voltage of a memory cell in the Nand flash memory.

It should be noted that the data illustrated in the above embodiment are only simple data for better explaining the embodiment of the present invention, and do not represent actual specific data of the Nand flash memory.

An embodiment of the present invention further provides a device for controlling programming noise, and referring to fig. 7, a block diagram of the device for controlling programming noise according to the embodiment of the present invention is shown, where the device is applied to a Nand flash memory, and the Nand flash memory includes: a register and a memory cell, the register being a device for temporarily storing desired program data, the apparatus for controlling program noise comprising:

in the case where the data to be programmed is already stored in the register, ready to be written to the memory cell:

the gate tube pressurizing module 310 is used for applying a first preset voltage to a gate tube between a memory chain in the Nand flash memory and a bit line where the memory chain is located, so that the gate tube between the memory chain and the bit line where the memory chain is located is conducted;

the bit line pressurizing module 320 is used for applying a second preset voltage to the bit line of the memory chain in the Nand flash memory under the condition that a gate tube between the memory chain and the bit line is conducted;

wherein, the channel voltage of the memory chain in the Nand flash memory is changed from 0 to the first initial voltage by applying the second preset voltage.

Optionally, the apparatus for controlling programming noise further comprises:

the unselected bit line power supply voltage adding module is used for applying power supply voltage to the bit line where the memory chain which does not need to be programmed is located, wherein the gate tube between the memory chain which does not need to be programmed and the bit line where the memory chain is located is turned off through the applied gating working voltage and the applied power supply voltage;

and the word line pressurization conducting module is used for applying a conducting voltage to the word line of the memory chain which does not need to be programmed under the condition that a gate tube between the memory chain which does not need to be programmed and the bit line of the memory chain which does not need to be programmed is turned off, and the conducting voltage and the first initial voltage act together to change the channel voltage of the memory chain which does not need to be programmed into a first high channel voltage, so that the voltage difference between the floating gate and the channel of the memory unit which does not need to be programmed is reduced.

Optionally, the apparatus for controlling programming noise further comprises:

the first high channel voltage value taking module is used for taking a value of a first high channel voltage, the first high channel voltage is the sum of a first initial voltage and a first original voltage, the first original voltage is a second preset voltage which is not applied to a bit line where a storage chain which does not need to be programmed is located, under the condition that a gate tube between the storage chain which does not need to be programmed and the bit line where the storage chain does not need to be programmed is turned off, a power supply voltage is directly applied to the bit line where the storage chain which does not need to be programmed is located, and when a turn-on voltage is applied to a word line where the storage chain which does not need to be programmed is located, a channel voltage of the storage chain which does not need to be.

Optionally, the apparatus for controlling programming noise further comprises:

the enabling module is used for receiving an enabling signal, the enabling signal is used for starting or closing a function of applying a third preset voltage to a word line where a storage chain in the Nand flash memory is located, and the third preset voltage is used for improving the channel voltage of the storage chain in the Nand flash memory;

the high-level word line pressurizing module is used for applying a third preset voltage to the word line where the storage chain in the Nand flash memory is located under the condition that the enabling signal is at a high level;

Optionally, the apparatus for controlling programming noise further comprises:

the high-level programming bit line gate tube pressurizing module is used for receiving a programming instruction and applying a gate working voltage to a gate tube between a storage chain which does not need to be programmed and a bit line of the Nand flash memory;

the high-level unselected bit line power supply voltage adding module is used for applying power supply voltage to the bit line where the memory chain which does not need to be programmed is located, wherein the gate tube between the memory chain which does not need to be programmed and the bit line where the memory chain is located is turned off through the applied gating working voltage and the applied power supply voltage;

and the high-level word line pressurization conducting module is used for applying a conducting voltage to the word line of the memory chain which does not need to be programmed under the condition that a gate tube between the memory chain which does not need to be programmed and the bit line of the memory chain is switched off, and the conducting voltage and the second initial voltage act together to change the channel voltage of the memory chain which does not need to be programmed into a second high channel voltage so as to reduce the voltage difference between the floating gate and the channel of the memory unit which does not need to be programmed.

Optionally, the apparatus for controlling programming noise further comprises:

and the second high channel voltage value taking module is used for taking the value of a second high channel voltage, the second high channel voltage is the sum of a second initial voltage and a second original voltage, the second original voltage is the channel voltage of the storage chain which does not need to be programmed when a second preset voltage is not applied to the bit line where the storage chain which does not need to be programmed is located, and the power supply voltage is directly applied to the bit line where the storage chain which does not need to be programmed is located under the condition that a gate tube between the storage chain which does not need to be programmed and the bit line where the storage chain which does not need to be programmed is switched off, and the channel voltage of the storage chain which does not need to be programmed is applied to the word line where the storage chain which does not need to be.

Optionally, the apparatus for controlling programming noise further comprises:

the second initial voltage value taking module is used for taking the value of a second initial voltage, and the second initial voltage is greater than the first initial voltage;

The embodiment of the invention also provides another device for controlling programming noise, which is applied to a Nand flash memory, wherein the Nand flash memory comprises: a register and a memory cell, the register being a device for temporarily storing desired program data, the apparatus for controlling program noise comprising:

in the case where the data to be programmed is already stored in the register, ready to be written to the memory cell:

the bit line gate tube pressurizing module is used for applying a second preset voltage to a gate tube between a storage chain in the Nand flash memory and the bit line where the storage chain is located, so that the gate tube between the storage chain in the Nand flash memory and the bit line where the storage chain is located is conducted;

and the unselected bit line pressurizing module is used for applying a third preset voltage to the bit line of the memory chain in the Nand flash memory under the condition that a gate tube between the memory chain in the Nand flash memory and the bit line is conducted, so that the channel voltage of the memory chain in the Nand flash memory is changed from 0 to an initial voltage, and the initial voltage is determined by the sum of the first preset voltage and the absolute value of the threshold voltage of the memory cell in the Nand flash memory.

Through the embodiment, under the condition that data required to be programmed is ready to be written into the memory unit, the first preset voltage is applied to the gate tube between the memory chain and the bit line where the memory chain is located in the Nandflash memory, so that the gate tube between the memory chain and the bit line where the memory chain is located is conducted; under the condition that a gate tube between a memory chain and a bit line where the memory chain is located is conducted, applying a second preset voltage to the bit line where the memory chain is located in the Nand flash memory; so that the channel voltage of the memory chain in the Nand flash memory is changed from 0 to the first initial voltage. Namely, the channel voltage of the memory chain in the Nand Flash memory is increased in the pre-programming stage, so that the voltage difference between the floating gate and the channel of the memory unit which does not need to be programmed in the programming process is reduced, programming noise introduced in the programming process is eliminated, and the reading precision of the Nand Flash is improved.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

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