阅读说明：本技术 层叠陶瓷电容器 (Multilayer ceramic capacitor ) 是由 生方晴菜 并木聪子 柳泽笃博 山藤知德 于 2019-05-30 设计创作，主要内容包括：本发明涉及一种层叠陶瓷电容器,包括：具有平行六面体形状的层叠芯片,其中多个电介质层中的每一层和多个内部电极层中的每一层交替地层叠,并且该多个内部电极层的每一层交替地露出至层叠芯片的两个端面,该多个电介质层的主要成分是陶瓷；以及形成在两个端面上的一对外部电极；其中：该一对外部电极具有在底层上形成镀层的结构；底层的主要成分是包含Ni和Cu中的至少一种的金属或合金；并且,底层的镀层侧表面的至少一部分包括含Mo的夹杂物。(the present invention relates to a laminated ceramic capacitor comprising: a laminated chip having a parallelepiped shape in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately laminated and each of the plurality of internal electrode layers is alternately exposed to both end faces of the laminated chip, a main component of the plurality of dielectric layers being ceramic; and a pair of external electrodes formed on both end faces; wherein: the pair of external electrodes has a structure in which a plating layer is formed on a base layer; the primary component of the underlayer is a metal or alloy containing at least one of Ni and Cu; and at least a part of the plating layer side surface of the undercoat layer includes an inclusion containing Mo.)

1. A laminated ceramic capacitor comprising:

A laminated chip having a parallelepiped shape in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately laminated and each of the plurality of internal electrode layers is alternately exposed to both end faces of the laminated chip, a main component of the plurality of dielectric layers being ceramic; and

A pair of external electrodes formed on the two end faces;

Wherein:

The pair of external electrodes has a structure in which a plating layer is formed on a base layer;

The primary component of the underlayer is a metal or alloy containing at least one of Ni and Cu; and is

At least a part of the plating layer side surface of the undercoat layer includes an inclusion containing Mo.

2. The laminated ceramic capacitor of claim 1, wherein the plating layer comprises a Sn-plated layer.

3. The laminated ceramic capacitor as claimed in claim 1 or 2, wherein the principal component metal of the bottom layer is Ni.

4. The laminated ceramic capacitor as claimed in any one of claims 1 to 3, wherein a main component of the internal electrode layers is Ni.

5. The laminated ceramic capacitor as claimed in any one of claims 1 to 4, wherein the ceramic of the dielectric layer has a perovskite structure.

Technical Field

Certain aspects of the present invention relate to a laminated ceramic capacitor.

Background

the laminated ceramic capacitor has a laminated structure in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated, and a pair of external electrodes formed on end faces of the laminated structure and electrically connected to the internal electrode layers led out to the end faces. The external electrode has a structure in which the underlying layer is subjected to plating. Japanese patent application laid-open No. H01-80011 discloses that hydrogen generated in plating is adsorbed into the internal electrode layers, whereby the insulation resistance of the dielectric layers deteriorates due to reduction caused by hydrogen. And this patent document discloses that the metal Ni (nickel) can be added to suppress adsorption of hydrogen to the internal electrode whose main component is a noble metal. On the other hand, japanese patent application laid-open No. 2016-.

Disclosure of Invention

In order to suppress the influence of hydrogen, it is desirable to suppress the intrusion of hydrogen from the external electrode serving as an intrusion path of hydrogen.

The purpose of the present invention is to provide a multilayer ceramic capacitor capable of suppressing the intrusion of hydrogen from an external electrode.

According to an aspect of the present invention, there is provided a laminated ceramic capacitor including: a laminated chip having a parallelepiped shape in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately laminated and each of the internal electrode layers is alternately exposed to both end faces of the laminated chip, a main component of the plurality of dielectric layers being ceramic; and a pair of external electrodes formed on both end faces; wherein: the pair of external electrodes has a structure in which a plating layer is formed on a base layer; the primary component of the underlayer is a metal or alloy containing at least one of Ni and Cu; and at least a part of the plating layer side surface of the undercoat layer includes an inclusion containing Mo.

Drawings

Fig. 1 shows a partial perspective view of a laminated ceramic capacitor;

FIG. 2 shows a cross-sectional view taken along line A-A in FIG. 1;

FIG. 3 is a flowchart showing a method of manufacturing a laminated ceramic capacitor;

FIG. 4A shows the underlayer and Cu plated layer viewed using STEM;

Fig. 4B shows Mo distribution in the underlayer and the Cu plated layer measured using STEM-EDS.

FIG. 5A shows measurement points; and is

Fig. 5B shows the measurement result of the Mo concentration at the cross section taken along the line B.

Detailed Description

Embodiments will be described with reference to the accompanying drawings.