阅读说明：本技术 平面电容的制作方法及系统和平面电容 (Manufacturing method and system of planar capacitor and planar capacitor ) 是由 李峰 卢星华 杨柳 陶玉红 李露 周智勇 于 2021-07-12 设计创作，主要内容包括：一种平面电容的制作方法,平面电容包括第一平面电极、第二平面电极以及设置于第一平面电极与的第二平面电极之间的介质层,制作方法包括：制作形成介质层的介质层浆料；在第一平面电极和/或第二平面电极的表面涂布介质层浆料后形成介质薄膜；形成多层介质薄膜后将第一平面电极与第二平面电极进行覆合形成平面电容,介质层由多层介质薄膜相互叠置形成。本发明的平面电容的制作方法制作的平面电容具有较高的耐电压特性,提高了平面电容的良率,生产成本低。本发明还涉及一种平面电容及平面电容的制作系统。(A method for manufacturing a planar capacitor, the planar capacitor comprises a first planar electrode, a second planar electrode and a dielectric layer arranged between the first planar electrode and the second planar electrode, the method comprises the following steps: manufacturing dielectric layer slurry for forming a dielectric layer; coating dielectric layer slurry on the surface of the first planar electrode and/or the second planar electrode to form a dielectric film; and after the multilayer dielectric films are formed, the first plane electrode and the second plane electrode are combined to form a plane capacitor, and the dielectric layers are formed by mutually overlapping the multilayer dielectric films. The planar capacitor manufactured by the manufacturing method of the planar capacitor has higher voltage resistance, the yield of the planar capacitor is improved, and the production cost is low. The invention also relates to a planar capacitor and a manufacturing system of the planar capacitor.)

1. A method for manufacturing a planar capacitor, wherein the planar capacitor comprises a first planar electrode, a second planar electrode and a dielectric layer arranged between the first planar electrode and the second planar electrode, the method comprising:

manufacturing dielectric layer slurry for forming the dielectric layer;

coating the dielectric layer slurry on the surface of the first planar electrode and/or the second planar electrode to form a dielectric film;

and after a plurality of layers of dielectric films are formed, the first plane electrode and the second plane electrode are combined to form the plane capacitor, and the dielectric layers are formed by mutually overlapping the plurality of layers of dielectric films.

2. The method according to claim 1, wherein the dielectric layer paste is applied to the surface of the first planar electrode and/or the second planar electrode, and then pre-baked to form a semi-cured dielectric film, and the first planar electrode and the second planar electrode are covered after forming a plurality of semi-cured dielectric films.

3. The method of claim 2, wherein the step of laminating the first and second planar electrodes comprises:

pressing the first planar electrode and the second planar electrode at a preset temperature and a preset pressure to obtain the planar capacitor;

the preset temperature is 100-150 ℃, and the preset pressure is 3-6 kg/cm²。

4. The method according to claim 2 or 3, wherein after forming a layer of said dielectric film on the surface of said first planar electrode, coating said dielectric layer slurry on the surface of said dielectric film at least once to form a plurality of layers of said dielectric films stacked on each other on said first planar electrode;

and combining the first planar electrode and the second planar electrode on which the plurality of dielectric thin films are formed.

5. The method according to claim 2 or 3, wherein after forming a layer of said dielectric film on the surface of said second planar electrode, coating said dielectric layer slurry on the surface of said dielectric film at least once to form a plurality of layers of said dielectric films stacked on each other on said second planar electrode;

and overlaying the second planar electrode formed with the plurality of dielectric thin films and the first planar electrode.

6. The method according to claim 2 or 3, wherein after forming a layer of said dielectric film on the surface of said first planar electrode, coating said dielectric layer slurry on the surface of said dielectric film at least once to form a plurality of layers of said dielectric films stacked on each other on said first planar electrode;

and after at least one layer of dielectric film is formed on the surface of the second planar electrode, the first planar electrode with the multiple layers of dielectric films is combined with the second planar electrode.

7. The method of claim 1, wherein the dielectric layer paste is formed by a method comprising:

adding epoxy resin into a first solvent, and stirring for 15-35 min at the temperature of 20-40 ℃ to obtain a mixed solution;

stirring and dispersing inorganic filler in a second solvent to obtain a suspension, and stirring and dispersing the suspension in the mixed solution;

adding an auxiliary agent into the mixed solution, uniformly stirring to obtain a mixture of the dielectric layer slurry, pouring the mixture into a ball milling tank, and ball milling for 5-15 hours at a rotating speed of 100-200 rpm to obtain the dielectric layer slurry.

8. The method of manufacturing a planar capacitor as claimed in claim 7, wherein said epoxy resin comprises at least one of a glycidyl ether type epoxy resin, a glycidyl ester type epoxy resin, a glycidyl amine type epoxy resin, an alicyclic epoxy resin, an epoxidized olefin compound, a sugar cane polyol epoxy resin, and a mixed structure epoxy resin;

the inorganic filler comprises at least one of barium sodium titanate, barium titanate, copper calcium titanate, strontium titanate, barium strontium titanate, calcium titanate, barium calcium titanate, lead zirconate titanate, lead sodium titanate and lead titanate;

the auxiliary agent comprises at least one of a curing agent, a dispersing agent, a coupling agent, a flatting agent, a defoaming agent and an accelerating agent;

the first solvent and the second solvent comprise at least one of acetone, pentanone, alcohol and butanone.

9. A planar capacitor, wherein the planar capacitor is formed by the method of any one of claims 1 to 8.

10. A system for manufacturing a planar capacitor, the system being used for manufacturing the planar capacitor as claimed in claim 9, the system comprising a first transfer unit, a second transfer unit, a coating unit, a preheating chamber and a pressing unit, wherein:

the first conveying unit is used for conveying a first plane electrode or the first plane electrode at least provided with a layer of dielectric film to the coating unit, the preheating box and the pressing unit in sequence;

the coating unit is used for coating the dielectric layer slurry on the surface of the first planar electrode or on the dielectric film;

the preheating box is used for preheating the dielectric layer slurry coated on the first planar electrode or the dielectric film, so that the dielectric film is formed on the surface of the first planar electrode, or a layer of dielectric film is formed on the dielectric film;

the second conveying unit is used for conveying a second plane electrode or the second plane electrode at least provided with a layer of the medium film to the pressing unit;

the pressing unit is used for pressing the first plane electrode with the formed dielectric film with the second plane electrode or the second plane electrode with at least one layer of the dielectric film.

Technical Field

The invention relates to the technical field of planar capacitors, in particular to a manufacturing method and system of a planar capacitor and the planar capacitor.

Background

The planar capacitor is mainly applied to electronic products with high height, high precision, sharp and small aspects of MEMS microphone chip substrates at present, and along with the development of requirements, the requirements of consumers on the electronic products are higher and higher; for example, HAST (high-speed aging 130 ℃/85% RH) experiment requires more than 1000h, TCT (constant temperature 80 ℃ constant humidity 85% RH) experiment requires more than 1000h, and the like. The quality of the planar capacitor and the strength of the voltage resistance can directly influence the reliability test of the electronic product.

The planar capacitor is a planar capacitor prepared by mixing and dispersing a polymer material system based on barium titanate particles and epoxy resin, and matching copper foils (serving as two-end electrodes of the planar capacitor) and other auxiliary materials (such as a dispersing agent and a curing agent). The production of the planar capacitor is to uniformly disperse and coat dielectric layer slurry on the surface of a first copper foil substrate in a coating mode and the like, then pre-bake the dielectric layer slurry to form semi-cured dielectric layer slurry, then carry out leveling and high-temperature lamination on the dielectric layer slurry and a second copper foil substrate, and carry out curing treatment to obtain the planar capacitor; the dielectric layer slurry is positioned between the first copper foil base material and the second copper foil base material.

Due to factors such as low precision of domestic production equipment, imperfect production process and the like, the dielectric layer is difficult to have no air holes due to the influence of objective conditions such as the mobility of dielectric layer slurry and the volatilization of a solvent of the dielectric layer slurry in a pre-drying process (a non-vacuum air floating type pre-drying oven) in the production process of the planar capacitor; if the dielectric layer has air holes, the capacitance performance (such as reduced voltage resistance, reduced capacitance, reduced peel strength, etc.) of the planar capacitor is inevitably changed, which further affects the reliability test of the electronic product, even causes the function failure of the electronic product.

Disclosure of Invention

In view of the above, the present invention provides a method for manufacturing a planar capacitor, which has a high voltage withstanding characteristic, improves the yield of the planar capacitor, and has a low production cost.

A method for manufacturing a planar capacitor, the planar capacitor comprises a first planar electrode, a second planar electrode and a dielectric layer arranged between the first planar electrode and the second planar electrode, the method comprises the following steps: manufacturing dielectric layer slurry for forming a dielectric layer; coating dielectric layer slurry on the surface of the first planar electrode and/or the second planar electrode to form a dielectric film; and after the multilayer dielectric films are formed, the first plane electrode and the second plane electrode are combined to form a plane capacitor, and the dielectric layers are formed by mutually overlapping the multilayer dielectric films.

In the embodiment of the present invention, after the dielectric layer paste is coated on the surface of the first planar electrode and/or the second planar electrode, the dielectric layer paste is pre-baked to form a semi-cured dielectric film, and the first planar electrode and the second planar electrode are covered after a plurality of layers of semi-cured dielectric films are formed.

In an embodiment of the present invention, a method of laminating the first planar electrode and the second planar electrode includes:

pressing the first planar electrode and the second planar electrode at a preset temperature and a preset pressure to obtain the planar capacitor;

the preset temperature is 100-150 ℃, and the preset pressure is 3-6 kg/cm²。

In the embodiment of the invention, after a layer of dielectric film is formed on the surface of the first planar electrode, the dielectric layer slurry is coated on the surface of the dielectric film at least once, so that a plurality of layers of dielectric films which are mutually overlapped are formed on the first planar electrode;

and combining the first planar electrode and the second planar electrode on which the plurality of dielectric thin films are formed.

In the embodiment of the invention, after a layer of dielectric film is formed on the surface of the second planar electrode, the dielectric layer slurry is coated on the surface of the dielectric film at least once, so that a plurality of layers of dielectric films which are mutually overlapped are formed on the second planar electrode;

and overlaying the second planar electrode formed with the plurality of dielectric thin films and the first planar electrode.

In the embodiment of the invention, after a layer of dielectric film is formed on the surface of the first planar electrode, the dielectric layer slurry is coated on the surface of the dielectric film at least once, so that a plurality of layers of dielectric films which are mutually overlapped are formed on the first planar electrode;

and after at least one layer of dielectric film is formed on the surface of the second planar electrode, the first planar electrode with the multiple layers of dielectric films is combined with the second planar electrode.

In an embodiment of the invention, a method for manufacturing the dielectric layer slurry comprises the following steps:

adding epoxy resin into a first solvent, and stirring for 15-35 min at the temperature of 20-40 ℃ to obtain a mixed solution;

stirring and dispersing inorganic filler in a second solvent to obtain a suspension, and stirring and dispersing the suspension in the mixed solution;

adding an auxiliary agent into the mixed solution, uniformly stirring to obtain a mixture of the dielectric layer slurry, pouring the mixture into a ball milling tank, and ball milling for 5-15 hours at a rotating speed of 100-200 rpm to obtain the dielectric layer slurry.

In an embodiment of the present invention, the above epoxy resin includes at least one of a glycidyl ether type epoxy resin, a glycidyl ester type epoxy resin, a glycidyl amine type epoxy resin, an alicyclic epoxy resin, an epoxidized olefin compound, a sugar cane polyol epoxy resin, and a mixed structure epoxy resin;

the inorganic filler comprises at least one of barium sodium titanate, barium titanate, copper calcium titanate, strontium titanate, barium strontium titanate, calcium titanate, barium calcium titanate, lead zirconate titanate, lead sodium titanate and lead titanate;

the auxiliary agent comprises at least one of a curing agent, a dispersing agent, a coupling agent, a flatting agent, a defoaming agent and an accelerating agent;

the first solvent and the second solvent comprise at least one of acetone, pentanone, alcohol and butanone.

The invention also relates to a planar capacitor which is manufactured by the manufacturing method of the planar capacitor.

The invention also relates to a manufacturing system of the planar capacitor, which is used for manufacturing the planar capacitor and comprises a first conveying unit, a second conveying unit, a coating unit, a preheating box and a pressing unit, wherein:

the first conveying unit is used for conveying a first plane electrode or the first plane electrode at least provided with a layer of dielectric film to the coating unit, the preheating box and the pressing unit in sequence;

the coating unit is used for coating the dielectric layer slurry on the surface of the first planar electrode or on the dielectric film;

the preheating box is used for preheating the dielectric layer slurry coated on the first planar electrode or the dielectric film, so that the dielectric film is formed on the surface of the first planar electrode, or a layer of dielectric film is formed on the dielectric film;

the second conveying unit is used for conveying a second plane electrode or the second plane electrode at least provided with a layer of the medium film to the pressing unit;

the pressing unit is used for pressing the first plane electrode with the formed dielectric film with the second plane electrode or the second plane electrode with at least one layer of the dielectric film.

According to the manufacturing method of the planar capacitor, the first planar electrode and/or the second planar electrode are/is coated with the multi-layer dielectric film for multiple times, and the planar capacitor formed by laminating and pressing has high voltage resistance, so that the yield of the planar capacitor is improved, and the production cost is reduced.

Drawings

FIG. 1 is a flow chart of a method for fabricating a planar capacitor according to the present invention.

Fig. 2 is a schematic cross-sectional structural diagram of the planar capacitor of the present invention.

FIG. 3 is a schematic view of a partial cross-sectional structure of the planar capacitor according to the present invention when the air holes in the two dielectric films overlap.

Fig. 4 and 5 are schematic partial sectional views showing the arrangement of the air holes in the two dielectric films of the planar capacitor according to the present invention.

FIG. 6 is a schematic view of a partial cross-sectional structure of the triple dielectric film of the planar capacitor according to the present invention when the air holes are overlapped.

FIG. 7 is a schematic structural diagram of a system for fabricating a planar capacitor according to the present invention.

Detailed Description

The application provides a manufacturing method of a planar capacitor.

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In order to facilitate understanding of those skilled in the art, the present application provides a specific implementation process of the technical solution provided by the present application through the following embodiments.

Fig. 1 is a schematic flow chart of a manufacturing method of a planar capacitor of the present invention, fig. 2 is a schematic cross-sectional structure diagram of the planar capacitor of the present invention, as shown in fig. 1 and fig. 2, a manufacturing method of the planar capacitor, in which a planar capacitor 10 includes a first planar electrode 11, a second planar electrode 12, and a dielectric layer 13 disposed between the first planar electrode 11 and the second planar electrode 12, the manufacturing method includes:

making dielectric layer slurry 43 (see fig. 7) for forming the dielectric layer 13;

coating dielectric layer slurry 43 on the surface of the first planar electrode 11 and/or the second planar electrode 12 to form a dielectric film 131;

after the multi-layer dielectric films 131 are formed, the first planar electrode 11 and the second planar electrode 12 are laminated to form the planar capacitor 10, and the dielectric layer 13 is formed by stacking the multi-layer dielectric films 131, i.e. the multi-layer dielectric films 131 are stacked.

According to the manufacturing method of the planar capacitor, the multilayer dielectric film 131 is formed by coating on the first planar electrode 11 and/or the second planar electrode 12 for multiple times, and the planar capacitor 10 formed by laminating and pressing has high voltage resistance, so that the yield of the planar capacitor 10 is improved, and the production cost is reduced.

Further, the thickness of the dielectric layer 13 is d, the number of the dielectric films 131 constituting the dielectric layer 13 is n, and the thickness of each dielectric film 131 is d/n, wherein n is greater than or equal to 2.

Further, the first planar electrode 11 and the second planar electrode 12 are copper foil sheets.

Further, after the dielectric layer paste 43 is coated on the surface of the first planar electrode 11 and/or the second planar electrode 12, the dielectric layer paste 43 is pre-baked to form a semi-cured dielectric film 131, and after a plurality of semi-cured dielectric films 131 are formed, the first planar electrode 11 and the second planar electrode 12 are covered to form the planar capacitor 10.

Further, the method for laminating the first planar electrode 11 and the second planar electrode 12 includes:

pressing the first planar electrode 11 and the second planar electrode 12 at a preset temperature and a preset pressure to obtain a planar capacitor 10;

the preset temperature is 100-150 ℃, and the preset pressure is 3-6 kg/cm²。

Further, after a dielectric film 131 is formed on the surface of the first planar electrode 11, at least one dielectric layer paste 43 is coated on the surface of the dielectric film 131, so that a plurality of dielectric films 131 stacked on each other are formed on the first planar electrode 11;

the first planar electrode 11 formed with the multi-layer dielectric film 131 and the second planar electrode 12 are laminated to form the planar capacitor 10. In this embodiment, the dielectric film 131 is not formed on the surface of the second planar electrode 12, two or more layers of the dielectric films 131 may be formed on the first planar electrode 11, and the number of layers of the dielectric films 131 may be freely selected according to actual needs.

In another preferred embodiment, after forming a dielectric film 131 on the surface of the second planar electrode 12, coating the dielectric layer paste 43 at least once on the surface of the dielectric film 131, so as to form a plurality of dielectric films 131 stacked on each other on the second planar electrode 12;

the second planar electrode 12 formed with the multilayer dielectric film 131 is laminated with the first planar electrode 11 to form the planar capacitor 10. In this embodiment, the dielectric film 131 is not formed on the surface of the first planar electrode 11, two or more layers of the dielectric films 131 may be formed on the second planar electrode 12, and the number of layers of the dielectric films 131 may be freely selected according to actual needs.

In another preferred embodiment, after forming a dielectric film 131 on the surface of the first planar electrode 11, coating the dielectric layer paste 43 at least once on the surface of the dielectric film 131, so as to form a plurality of dielectric films 131 stacked on each other on the first planar electrode 11;

after at least one dielectric thin film 131 is formed on the surface of the second planar electrode 12, the first planar electrode 11 on which the dielectric thin films 131 are formed is laminated with the second planar electrode 12. In this embodiment, the first planar electrode 11 may form two or more layers of dielectric films 131, and the number of layers of the dielectric films 131 may be freely selected according to actual needs.

Further, the method for manufacturing the dielectric layer paste 43 includes:

adding epoxy resin into a first solvent, and stirring for 15-35 min at the temperature of 20-40 ℃ to obtain a mixed solution;

stirring and dispersing the inorganic filler in a second solvent to obtain a suspension, and stirring and dispersing the suspension in the mixed solution;

adding an auxiliary agent into the mixed solution, uniformly stirring to obtain a mixture of the dielectric layer slurry 43, pouring the mixture into a ball milling tank, and ball milling for 5-15 hours at a rotating speed of 100-200 rpm to obtain the dielectric layer slurry 43.

Further, the epoxy resin includes at least one of a glycidyl ether type epoxy resin, a glycidyl ester type epoxy resin, a glycidyl amine type epoxy resin, an alicyclic epoxy resin, an epoxidized olefin compound, a sugar cane polyol epoxy resin, and a mixed structure epoxy resin;

the inorganic filler comprises at least one of barium sodium titanate, barium titanate, copper calcium titanate, strontium titanate, barium strontium titanate, calcium titanate, barium calcium titanate, lead zirconate titanate, lead sodium titanate and lead titanate;

the auxiliary agent comprises at least one of a curing agent, a dispersing agent, a coupling agent, a flatting agent, a defoaming agent and an accelerating agent;

the first solvent and the second solvent comprise at least one of acetone, pentanone, alcohol and butanone

Further, fig. 3 is a schematic partial sectional structure of the planar capacitor of the present invention when the air holes in the two dielectric films overlap, fig. 4 and 5 are schematic partial sectional structures of the planar capacitor of the present invention when the air holes in the two dielectric films are staggered, and as shown in fig. 3, 4 and 5, the dielectric film 131 near the first planar electrode 11 has a thickness d₁(d₁10um), the dielectric strength of the dielectric layer paste 43 is E, assuming that the area S is 500mm × 600mm, i.e., 0.3m²The dielectric film 131 has one or more pores, and the length of the pores is equal to the thickness of the dielectric film 131, i.e. the length of the pores is d₁(d₁10um), area as Δ S₁) (ii) a The dielectric film 131 near the second planar electrode 12 has a thickness d₂(d₂10um), the dielectric strength of the dielectric layer paste 43 is E, assuming that the area S is 500mm × 600mm, i.e., 0.3m²The dielectric film 131 has one or more pores, and the length of the pores is equal to the thickness of the dielectric film 131, i.e. the length of the pores is d₂(d₂10um), area as Δ S₂) (ii) a The sub-plane capacitor C₀The dielectric layer 13 has a thickness d ═ d₁+d₂At this time, the breakdown voltage of the sub-plane capacitor has the following conditions:

first, as shown in FIG. 3, two air holes Δ V₁And Δ V₂Only partially clad, and 0<Overlapping area DeltaS is less than or equal to min (DeltaS)₁,ΔS₂) At this time, the sub-plane capacitor C₀Breakdown voltage U of₀Is substantially equal toBreakdown voltage U of air₀＝E₀X d 660V, the probability of this occurrence is P_ΔSWherein:

P_ΔS＝∫₀ ¹⁰(ΔS/S)²dΔS

by Δ S₁＝ΔS₂＝100mm²And S is 500mm × 600mm, P can be calculated_ΔS＝0.37×10^-5I.e., 3.7 ppm.

Second, as shown in FIGS. 4 and 5, the air hole Δ V₁And Δ V₂Just staggered completely, the sub-plane capacitance C₀Breakdown voltage U of₀At least can reach d₁Or d₂Thickness of the dielectric layer 13, i.e. U₀＝E×d₁＝1500V>660V。

Further, fig. 6 is a schematic partial sectional view showing the overlapping of the air holes in the three-layered dielectric film of the planar capacitor of the present invention, and as shown in fig. 6, the thickness of the dielectric film 131 near the first planar electrode 11 is d₁(d₁6.67um), the dielectric strength of the dielectric layer paste 43 itself is E, assuming that the area S is 500mm × 600mm, i.e., 0.3m²The dielectric film 131 has one or more pores, and the length of the pores is equal to the thickness of the dielectric film 131, i.e. the length of the pores is d₁(d₁6.67um), area Δ S₁) (ii) a The dielectric film 131 near the second planar electrode 12 has a thickness d₂(d₂6.67um), the dielectric strength of the dielectric layer paste 43 is E, assuming that the area S is 500mm × 600mm, i.e., 0.3m²The dielectric film 131 has one or more pores, and the length of the pores is equal to the thickness of the dielectric film 131, i.e. the length of the pores is d₂(d₂6.67um), area Δ S₂) (ii) a The thickness of the intermediate dielectric film 131 is d₃(d₃6.67um), the dielectric strength of the dielectric layer paste 43 is E, assuming that the area S is 500mm × 600mm, i.e., 0.3m²The dielectric film 131 has one or more pores, and the length of the pores is equal to the thickness of the dielectric film 131, i.e. the length of the pores is d₃(d₃6.67um) area ofΔS₃) (ii) a The dielectric layer 13 of the sub-planar capacitor has a thickness d ═ d₁+d₂+d₂When the breakdown voltage of the sub-plane capacitor is 20um, Δ S is assumed₁＝ΔS₂＝ΔS₃＝100mm²And then:

first, as shown in FIG. 6, the vent Δ V₁、ΔV₂、ΔV₃Has a part corresponding to the cladding, and 0<Overlapping area DeltaS is less than or equal to min (DeltaS)₁，ΔS₂，ΔS₃) At this time, the sub-plane capacitor C₀Breakdown voltage U of₀Substantially equal to the breakdown voltage U of air₀＝E₀X d 660V, the probability of this occurrence is P_ΔSWherein:

P_ΔS＝∫₀ ¹⁰(ΔS/S)³dΔS

i.e. by Δ S₁＝ΔS₂＝ΔS₃＝100mm²And S is 500mm × 600mm, P can be calculated_ΔS＝0.093× 10^-8I.e. 0.093 × 10^-2ppm。

Second, the sub-plane capacitor C₀Comprising only one air hole (Δ V)₁、ΔV₂、ΔV₃One of three) is applied, the sub-plane capacitor C is applied₀Breakdown voltage U of₀At least reaching (2/3) x d thickness breakdown voltage of the dielectric layer 13, i.e. U₀＝E₀×(2/3)×d＝2000V。

Third, the sub-plane capacitor C₀Comprising only two pores (. DELTA.V)₁、ΔV₂、ΔV₃Three or two) at this time, the sub-plane capacitance C₀Breakdown voltage U of₀At least reaching (1/3) x d thickness breakdown voltage of the dielectric layer 13, i.e. U₀＝E×(2/3)×d＝1000V。

Fourth, the sub-plane capacitor C₀When no air hole is included, the sub-plane capacitor C₀Breakdown voltage U of₀The breakdown voltage of the dielectric layer 13 can be achieved to d thickness, i.e. U₀＝E×d＝3000V。

In summary, the sub-plane capacitor C₀Breakdown voltage ofU₀Probability of 660V is only P_ΔS＝ 0.093×10^-8I.e. 0.093 × 10^-2ppm, remaining sub-plane capacitance C₀Breakdown voltage U of₀Can reach more than 1000V.

The manufacturing method of the planar capacitor can greatly reduce the probability of capacitor breakdown, effectively improve the yield of the planar capacitor 10, improve the voltage resistance and the like.

Further, assume that the mother plane capacitor (mother plane capacitor area S) is obtained by coating the dielectric layer 13 n times (n ≧ 2), and each time the dielectric layer 13 is coated, there is a pore Δ V_n(the pore has a thickness of d/n and a cross-sectional area of Δ S_n) Then there is Δ V₁、ΔV₂、……、ΔV_nA plurality of; after the first planar electrode 11 and the second planar electrode 12 are covered, the air hole Δ V₁、ΔV₂、……、ΔV_nExactly there is a partial corresponding combination, and 0<Overlapping area DeltaS is less than or equal to min (DeltaS)₁,ΔS₂、……，ΔS_n)＝ΔS_maxAt this time, the sub-plane capacitor C₀Breakdown voltage U of₀Substantially equal to the breakdown voltage U of air (or vacuum)_{Air conditioner}The probability of this occurrence is P_ΔSWherein

Further, as shown in fig. 2, the present invention further relates to a planar capacitor 10, wherein the planar capacitor 10 is formed by the above-mentioned method for manufacturing a planar capacitor.

Specifically, the planar capacitor 10 includes a first planar electrode 11, a second planar electrode 12 and a dielectric layer 13, the first planar electrode 11 and the second planar electrode 12 are parallel and opposite to each other, the dielectric layer 13 is connected between the first planar electrode 11 and the second planar electrode 12, the dielectric layer 13 is formed by at least two dielectric films 131 which are mutually overlapped, the thickness of the dielectric layer 13 is d, the number of the dielectric films 131 forming the dielectric layer 13 is n, the thickness of each dielectric film 131 is d/n, wherein n is greater than or equal to 2.

Further, fig. 7 is a schematic structural diagram of a manufacturing system of a planar capacitor of the present invention, as shown in fig. 7, the present invention further relates to a manufacturing system of a planar capacitor, the manufacturing system adopts the above manufacturing method to manufacture the above planar capacitor 10, the manufacturing system includes a first conveying unit 20, a second conveying unit 30, a coating unit 40, a preheating box 50 and a pressing unit 60, wherein:

the first conveying unit 20 is used for conveying the first planar electrode 11 or the first planar electrode 11 at least formed with a layer of dielectric film 131 to the coating unit 40, the preheating box 50 and the pressing unit 60 in sequence;

the coating unit 40 is used for coating the dielectric layer slurry 43 on the surface of the first planar electrode 11 or on the dielectric film 131;

the preheating box 50 is used for preheating the dielectric layer slurry 43 coated on the first planar electrode 11 or the dielectric film 131, so that the dielectric film 131 is formed on the surface of the first planar electrode 11, or a layer of dielectric film 131 is formed on the dielectric film 131;

the second conveying unit 30 is used for conveying the second planar electrode 12 or the second planar electrode 12 at least formed with a layer of dielectric film 131 to the pressing unit 60;

the pressing unit 60 is configured to press the first planar electrode 11 with the dielectric film 131 and the second planar electrode 12 or the second planar electrode 12 with at least one dielectric film 131, and it is worth mentioning that after the first planar electrode 11 and the second planar electrode 12 are pressed, the number of layers of the dielectric film 131 is greater than or equal to 2.

Further, the first conveying unit 20 includes a first winding roller 21 and a plurality of conveying rollers 22, the first winding roller 21 is used for winding the first planar electrode 11 of the dielectric layer slurry 43 to be coated or the first planar electrode 11 at least formed with one layer of dielectric film 131, the first winding roller 21 is connected with a motor, and the first winding roller 21 cooperates with each conveying roller 22 to convey the first planar electrode 11 or the first planar electrode 11 at least formed with one layer of dielectric film 131 to the coating unit 40, the preheating box 50 and the laminating unit 60 in sequence.

Further, the coating unit 40 includes a slurry container 41 and a coating roller 42, the slurry container 41 is used for accommodating the dielectric layer slurry 43, one part of the coating roller 42 is disposed in the dielectric layer slurry 43, the other part of the coating roller 42 is located outside the slurry container 41 and is in contact with the surface of the first planar electrode 11 or the dielectric film 131, and the coating roller 42 rotates to coat the dielectric layer slurry 43 on the surface of the first planar electrode 11 or the dielectric film 131. In this embodiment, the coating unit 40 adopts one of a gravure roll method, a slot extrusion coating method, and a comma knife coating method, and further includes a size coating technique such as dip reverse coating, reverse kiss coating, and the like.

Further, the pressing unit 60 includes a silica gel roller 61 and a laminating roller 62, the silica gel roller 61 and the laminating roller 62 are disposed opposite to each other, a gap for the first planar electrode 11 and the second planar electrode 12 to pass through is formed between the silica gel roller 61 and the laminating roller 62, the silica gel roller 61 and/or the laminating roller 62 can move close to each other or away from each other, and the silica gel roller 61 and the laminating roller 62 move close to each other to realize laminating and pressing the first planar electrode 11 and the second planar electrode 12. In the present embodiment, a heater is provided in the laminating roller 62 to heat the laminating roller 62 to cure the semi-cured dielectric layer 13.

Further, the second conveying unit 30 includes a second material rolling roller 31 and a third material rolling roller 32, the second material rolling roller 31 and the third material rolling roller 32 are disposed at an interval, the pressing unit 60 is disposed between the second material rolling roller 31 and the third material rolling roller 32, the second material rolling roller 31 is used for rolling the second planar electrode 12 or the second planar electrode 12 at least formed with one layer of dielectric film 131, and the third material rolling roller 32 rolls the planar capacitor 10 formed by pressing.

Further, the second planar electrode 12 or the second planar electrode 12 formed with at least one dielectric film 131 may be sequentially transferred to the coating unit 40 and the preheating cabinet 50 by the first transfer unit 20, and then wound on the second take-up roll 31. The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention. The various features described in the foregoing detailed description may be combined in any suitable manner without departing from the scope of the invention. The invention is not described in detail in order to avoid unnecessary repetition.