阅读说明：本技术 电子部件、电路板装置以及制造电子部件的方法 (Electronic component, circuit board device, and method of manufacturing electronic component ) 是由 冈田晏珠 天野美娜 谷田川清志郎 福田贵久 于 2021-05-31 设计创作，主要内容包括：本发明涉及电子部件、电路板装置以及制造电子部件的方法。电子部件包括元件本体和在其上的至少一个外部电极。元件本体包括电介质和内部电极。每一个外部电极包括：连接到内部电极的基底层。基底层形成在元件本体的多个面上并包含金属和与金属混合的第一共材。每一个外部电极还包括形成在基底层的至少一个面上的镀层。每一个外部电极还包括氧化层,形成在基底层的除形成有镀层的面之外的一个或多个面上。氧化层具有由基底层的金属的氧化膜和第二共材形成的表面层。(The invention relates to an electronic component, a circuit board device and a method for manufacturing the electronic component. The electronic component includes an element body and at least one external electrode thereon. The element body includes a dielectric and an internal electrode. Each of the external electrodes includes: and a base layer connected to the internal electrode. The base layer is formed on a plurality of faces of the element body and contains a metal and a first common material mixed with the metal. Each of the external electrodes further includes a plating layer formed on at least one side of the base layer. Each of the external electrodes further includes an oxide layer formed on one or more faces of the base layer other than the face on which the plating layer is formed. The oxide layer has a surface layer formed of an oxide film of the metal of the base layer and a second co-material.)

1. An electronic component, comprising:

an element body including a dielectric and an internal electrode; and

at least one external electrode is provided on the substrate,

each of the at least one external electrode includes:

a base layer connected to the internal electrode, formed on a plurality of faces of the element body, and including a metal and a first common material mixed with the metal,

a plating layer formed on at least one surface of the base layer, an

An oxide layer formed on one or more faces of the base layer other than the at least one face of the base layer and having a surface layer formed of an oxide film of the metal of the base layer and a second co-material.

2. The electronic component of claim 1, wherein the first co-material included in the base layer and the second co-material included in the oxide layer have the same composition.

3. The electronic component according to claim 1 or 2, wherein a main component of the dielectric is an oxide ceramic.

4. The electronic component according to any one of claims 1 to 3, wherein the first co-material contained in the base layer and the second co-material contained in the oxide layer have the same composition as a main component of the dielectric.

5. The electronic component of any of claims 1-4, wherein the first common material continues to the second common material from the base layer to the oxide layer, and the first and second common materials have a continuous crystalline or amorphous structure.

6. The electronic component according to any one of claims 1-5, wherein the metal of the base layer is present in the form of crystalline or amorphous particles and the first co-material is also present in the form of crystalline or amorphous particles, such that the particles of the metal of the base layer are present in admixture with the particles of the first co-material.

7. The electronic component according to any one of claims 1 to 6, wherein a main component of the dielectric is barium titanate.

8. The electronic component according to any one of claims 1 to 7, wherein the oxide layer is formed on at least a part of a side surface of the base layer and a surface opposite to the at least one surface on which the plating layer is formed.

9. The electronic component according to any one of claims 1 to 8, wherein a ratio of the second common material to a surface of the oxidized layer is in a range of 20 at% to 75 at%.

10. The electronic component according to any one of claims 1 to 9, wherein the metal of the base layer is a metal or an alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn.

11. The electronic component of any of claims 1-10, wherein the first co-material is selected from at least one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate titanate, and titanium oxide.

12. The electronic component according to any one of claims 1 to 11, wherein the oxide layer comprises nickel oxide and barium titanate as viewed from a surface of the oxide layer.

13. The electronic component according to claim 12, wherein the oxide layer further contains a compound containing nickel, magnesium, and oxygen as viewed from a surface of the oxide layer.

14. The electronic component according to any one of claims 1 to 13, wherein the element body has a laminate in which at least one first internal electrode layer and at least one second internal electrode layer are alternately laminated with the dielectric interposed therebetween,

the at least one external electrode includes a first external electrode and a second external electrode, the first external electrode and the second external electrode being disposed on opposite sides of the stacked body such that the first external electrode is spaced apart from the second external electrode,

the at least one first internal electrode layer is connected to the first external electrode, and

the at least one second internal electrode layer is connected to the second external electrode.

15. The electronic component according to claim 14, wherein the plating layer is formed on one of faces of the substrate layer, the faces extending perpendicular to a stacking direction of the at least one first internal electrode layer, the at least one second internal electrode layer, and the dielectric.

16. A circuit board arrangement comprising:

a circuit board; and

the electronic component according to any one of claims 1 to 15 mounted on the circuit board, the electronic component being connected to the circuit board via a solder layer attached to a plated layer of the electronic component.

17. A method of manufacturing an electronic component, the method comprising the steps of:

forming an element body including a dielectric and an internal electrode;

applying a mixed material obtained by mixing a common material with a metal-containing electrode material to two opposite side faces of the element body and an edge surface of the element body adjacent to the side faces;

sintering the mixed material and forming a base layer where the metal and the co-material are mixed on the opposite side faces of the element body and the edge surface of the element body;

oxidizing the metal of the underlayer and forming an oxide film of the metal on a plurality of surfaces of the underlayer;

removing the oxide film from at least one of faces of the base layer while leaving the oxide film on at least a part of the edge surface of the element body; and

and forming a plating layer on the at least one surface from which the oxide film has been removed among the plurality of surfaces of the base layer.

18. The method of manufacturing an electronic component according to claim 17, wherein the step of removing the oxide film from at least one of the plurality of faces of the base layer comprises: the oxide film is sandblasted from at least one of the plurality of sides of the base layer to polish the at least one of the plurality of sides of the base layer.

19. The method of manufacturing an electronic component according to claim 17 or 18, wherein the step of forming the element body includes:

forming a sheet containing a dielectric ceramic as a main component; and

applying a conductive paste containing the metal of the base layer on the sheet, and

sintering the element body in a process of sintering the mixed material.

Technical Field

The invention relates to an electronic component, a circuit board device and a method for manufacturing the electronic component.

Background

In a case where there is a demand for downsizing electronic equipment, in order to reduce a mounting area of electronic parts, external electrodes are generally formed on an element body in which the internal electrodes are provided. The external electrodes are connected to the circuit board by soldering so that the electronic components are mounted on the circuit board.

The external electrodes may be formed not only on the mounting surface of the element body but also on the side surfaces and the upper surface of the element body. In this configuration, the wet solder may move up along the side of the external electrode and cause an increase in the mounting area.

In order to prevent the wet solder from moving upward along the side surfaces of the terminal electrodes, JP-2014-53599A discloses a configuration in which side surface portions of the first and second terminal electrodes formed on the side surfaces of the electronic component are covered with an oxide film.

Disclosure of Invention

However, if the side surface portion of the terminal electrode is covered with the oxide film and mechanical stress is applied to the oxide film, the oxide film may peel off along the interface between the terminal electrode and the oxide film. The oxide film may be suddenly peeled off from a large area of the terminal electrode.

An object of the present invention is to provide an electronic component in which an oxide layer formed on an external electrode is difficult to peel off from the external electrode. It is a further object of the invention to provide a method of manufacturing such an electronic component. Another object of the present invention is to provide a circuit board device in which an oxide layer formed on an external electrode of an electronic component mounted on a circuit board is difficult to peel off from the external electrode.

According to a first aspect of the present invention, there is provided an electronic component including an element body and at least one external electrode. The element body has a dielectric and an internal electrode. Each of the external electrodes includes a base layer connected to the internal electrode. The base layer is formed on a plurality of faces of the element body and contains a metal and a first common material mixed with the metal. Each of the external electrodes further includes a plating layer formed on at least one side of the base layer. Each of the external electrodes further includes an oxide layer formed on one or more faces of the base layer other than the face on which the plating layer is formed. The oxide layer has a surface layer formed of an oxide film of the metal of the base layer and a second co-material.

The first common material included in the base layer and the second common material included in the oxide layer may have the same composition.

The main component of the dielectric may be an oxide ceramic.

The first co-material included in the base layer and the second co-material included in the oxide layer may have the same composition as the main component of the dielectric.

The first common material may continue to the second common material from the base layer to the oxide layer, and the first common material and the second common material may have a continuous crystal structure or an amorphous structure.

The metal of the base layer may be present in the form of crystalline or amorphous particles and the first co-material may also be present in the form of crystalline or amorphous particles, such that the particles of the metal of the base layer are present in admixture with the particles of the first co-material.

The main component of the dielectric may be barium titanate.

The oxide layer may be formed on at least a part of a side surface of the base layer and on a surface opposite to a surface on which the plating layer is formed.

The ratio of the second common material on the surface of the oxide layer may be in a range of 20 at% to 75 at%.

The metal of the base layer may be a metal or an alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn.

The first co-material may be selected from at least one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate titanate, and titanium oxide.

The oxide layer may include nickel oxide and barium titanate as viewed from the surface of the oxide layer.

The oxide layer may further include a compound containing nickel, magnesium, and oxygen, as viewed from the surface of the oxide layer.

The element body may have a stacked body in which at least one first internal electrode layer and at least one second internal electrode layer are alternately stacked with a dielectric interposed therebetween. The at least one external electrode may include a first external electrode and a second external electrode, which are disposed on opposite sides of the stacked body such that the first external electrode is spaced apart from the second external electrode. The first internal electrode layer may be connected to the first external electrode, and the second internal electrode layer may be connected to the second external electrode.

The plating layer may be formed on one of the faces of the base layer, which extends perpendicular to the stacking direction of the first internal electrode layer, the second internal electrode layer, and the dielectric.

According to a second aspect of the present invention, there is provided a circuit board device in which the above-described electronic component is mounted on a circuit board, and the electronic component is connected to the circuit board via a solder layer attached to a plated layer of the electronic component.

According to a third aspect of the present invention, there is provided a method of manufacturing an electronic component. The method includes forming an element body including a dielectric and an internal electrode. The method further includes applying a mixed material obtained by mixing a co-material with the metal-containing electrode material to two opposite sides of the element body and edge surfaces of adjacent sides of the element body. The method further includes sintering the mixed material and forming a base layer of the mixed presence of the metal and the co-material on the opposite side of the element body and the edge surface of the element body. The method further includes oxidizing the metal of the base layer and forming an oxide film of the metal on a plurality of sides of the base layer. The method further includes removing the oxide film from at least one of the faces of the base layer while leaving the oxide film on at least a portion of the edge surface of the element body. The method further includes forming a plating layer on at least one of the plurality of sides of the base layer from which the oxide film has been removed.

The step of removing the oxide film from at least one face of the plurality of faces of the base layer may include: the oxide film is sandblasted from at least one of the faces of the base layer to polish the face of the base layer.

The step of forming the element body may comprise: forming a sheet containing a dielectric ceramic as a main component; and applying a conductive paste containing the metal of the base layer to the sheet. The element body may be sintered in the step of sintering the mixed material.

According to an aspect of the present invention, the oxide layer formed on each external electrode is hardly peeled off from the external electrode.

Drawings

Fig. 1 is a perspective view showing the configuration of a multilayer ceramic capacitor according to a first embodiment of the present invention.

Fig. 2 is a cross-sectional view obtained by longitudinally cutting the multilayer ceramic capacitor of fig. 1.

Fig. 3A is an enlarged cross-sectional view of the EA portion of the external electrode in fig. 2.

Fig. 3B is an enlarged cross-sectional view of an EB portion of the external electrode in fig. 2.

Fig. 4 is a schematic view showing an exemplary composition of the surface of the oxide layer of the external electrode shown in fig. 2.

Fig. 5 is a flowchart illustrating a method of manufacturing a multilayer ceramic capacitor according to a second embodiment of the present invention.

Fig. 6A is a cross-sectional view for describing a method of manufacturing a multilayer ceramic capacitor according to a second embodiment.

Fig. 6B is another cross-sectional view for describing a method of manufacturing a multilayer ceramic capacitor according to the second embodiment.

Fig. 6C is another cross-sectional view for describing a method of manufacturing a multilayer ceramic capacitor according to the second embodiment.

Fig. 6D is still another cross-sectional view for describing a method of manufacturing a multilayer ceramic capacitor according to the second embodiment.

Fig. 6E is another cross-sectional view for describing a method of manufacturing a multilayer ceramic capacitor according to the second embodiment.

Fig. 6F is another cross-sectional view for describing a method of manufacturing a multilayer ceramic capacitor according to the second embodiment.

Fig. 6G is another cross-sectional view for describing a method of manufacturing a multilayer ceramic capacitor according to the second embodiment.

Fig. 6H is another cross-sectional view for describing a method of manufacturing a multilayer ceramic capacitor according to the second embodiment.

Fig. 6I is another cross-sectional view for describing a method of manufacturing a multilayer ceramic capacitor according to the second embodiment.

Fig. 6J is another cross-sectional view for describing a method of manufacturing a multilayer ceramic capacitor according to the second embodiment.

Fig. 7A is a plan view illustrating the exemplary process of fig. 6I.

Fig. 7B is a cross-sectional view obtained by longitudinally cutting the structure of fig. 7A.

Fig. 8 is a cross-sectional view showing the configuration of a circuit board device mounting a multilayer ceramic capacitor on a circuit board according to a third embodiment.

Fig. 9 is a cross-sectional view showing the configuration of a multilayer ceramic capacitor according to a fourth embodiment.

Fig. 10 is a perspective view showing the configuration of an electronic component according to a fifth embodiment.

Fig. 11 is a perspective view showing the configuration of an electronic component according to a sixth embodiment.

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings. The following examples are not intended to limit the invention. The combination of all the features described in each embodiment is not always necessary for the present invention. The configuration of each embodiment may be modified and/or changed according to the design, specifications, and various conditions (use conditions, use environments, and the like) of the apparatus and device to which the present invention is applied. The technical scope of the present invention is defined by the appended claims, and is not limited by the following embodiments. Furthermore, the parts, components and elements shown in the drawings for use in connection with the following description may differ in structure, proportion and shape from the actual parts, components and elements for the purpose of easier understanding of the parts, components and elements.

First embodiment

Fig. 1 is a perspective view showing the configuration of a multilayer ceramic capacitor 1A according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1A of fig. 1 taken in the longitudinal direction of the multilayer ceramic capacitor 1A of fig. 1.

In fig. 1 and 2, a multilayer ceramic capacitor 1A includes an element body (element assembly) 2, an external electrode (external electrode) 6A, and another external electrode (external electrode) 6B. The element body 2 has a stacked body (or stack) 2A, a lower cover layer 5A, and an upper cover layer 5B. The multilayer body 2A has a plurality of internal electrode layers 3A, a plurality of other internal electrode layers 3B, and a plurality of dielectric layers 4.

The lowermost layer of the stacked body 2A is covered with the lower cover layer 5A, and the uppermost layer of the stacked body 2A is covered with the upper cover layer 5B. The plurality of internal electrode layers 3A and 3B are alternately laminated via the plurality of dielectric layers 4. The element body 2 may be substantially rectangular parallelepiped in shape, and the stacked body 2A may also be substantially rectangular parallelepiped in shape. The element body 2 may be chamfered along each edge (edge) of the element body 2. In the following description, a direction in which both side surfaces of the element body 2 face each other may be referred to as a longitudinal direction DL, a direction in which the front surface and the rear surface of the element body 2 face each other may be referred to as a width direction DW, and a direction in which the top surface and the bottom surface of the element body 2 face each other may be referred to as a stacking direction DS.

The external electrodes 6A and 6B are respectively located on opposite sides of the element body 2. The external electrodes 6A and 6B are spaced apart (separated) from each other. Each of the external electrodes 6A and 6B continuously extends from the side surface of the element body 2 to the front and rear surfaces and the top and bottom surfaces.

In the longitudinal direction DL, the internal electrode layers 3A and 3B are alternately arranged at different positions in the laminated body 2A. The internal electrode layers 3A may be arranged on one side of one side face of the element body 2 with respect to the internal electrode layers 3B, and the internal electrode layers 3B may be arranged on the opposite side face of the element body 2 with respect to the internal electrode layers 3A. The end portions of the internal electrode layers 3A are led out to the left ends of the respective dielectric layers 4 at one side surface (right side surface) in the longitudinal direction DL of the element body 2, and are connected to the external electrodes 6A. The end of the internal electrode layer 3B is led out to the right end of the dielectric layer 4 at the other side face in the longitudinal direction DL of the element body 2, and is connected to the external electrode 6B.

On the other hand, in a direction (width direction DW) perpendicular to a direction (length direction DL) in which the side surfaces of the element body 2 face each other, the end portions of the internal electrode layers 3A and 3B are covered with the dielectric layer 4. In the width direction DW, the positions of the end portions of the internal electrode layers 3A may be aligned with the positions of the end portions of the internal electrode layers 3B.

The external dimensions of the multilayer ceramic capacitor 1A have the following values, for example. The length is 1.0mm, the width is 0.5mm, and the height is 0.5 mm. The thickness of each of the internal electrode layers 3A, the internal electrode layers 3B, and the dielectric layers 4 in the stacking direction DS may be in the range of 0.05 μm to 5 μm, for example, 0.3 μm, respectively.

The material of the internal electrode layers 3A, 3B may be selected from metals such as Cu (copper), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), and may be an alloy containing these metals.

The main component of the material of the dielectric layer 4 is, for example, a ceramic material having a perovskite structure. The content of the main component may be 50 at% or more. The ceramic material of the dielectric layer 4 may be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate, and titanium oxide.

The main component of the material of the lower cover layer 5A and the upper cover layer 5B may be, for example, a ceramic material. The main component of the ceramic material of the lower cover layer 5A and the upper cover layer 5B may be the same as that of the dielectric layer 4.

As shown in fig. 1 and 2, the external electrodes 6A and 6B are spaced from each other in the length direction DL, and are formed on a plurality of faces of the element body 2. Each of the external electrodes 6A and 6B has a mounting face M1 and an upper face M3 facing each other in the stacking direction DS, a side face M2, a front face M4 and a rear face M4 facing each other in the width direction DW. Each of the external electrodes 6A and 6B includes a base layer (bottom layer) 7 and a plating layer 9 on the mount face M1. The side surface M2 of the external electrode 6A faces the side surface M2 of the external electrode 6B in the longitudinal direction DL. The mounting face M1 is a face facing the circuit board on which the multilayer ceramic capacitor 1A is mounted. The mounting face M1 is provided on the lower surface of the element body 2. The thickness of each of the external electrodes 6A and 6B on the mount face M1 in the stacking direction DS is, for example, in the range of 10 μ M to 40 μ M.

The base layer 7 is formed on those faces of each of the external electrodes 6A and 6B other than the mount face M1 (i.e., the side face M2, the upper surface M3, the front surface M4, and the rear surface M4), and the oxide layer 8 is formed on the surface of the base layer 7. The base layer 7 is continuously formed on the element body 2 such that the base layer 7 exists on the side surface M2 and extends from the side surface M2 to the mounting surface M1. The base layer 7 also extends from the side M2 onto the upper surface M3, the front surface M4 and the rear surface M4.

The base layer 7 includes a metal as a conductive material. For example, the metal of the base layer 7 contains at least one metal selected from the group consisting of Cu, Fe (iron), Zn (zinc), Al (aluminum), Ni, Pt, Pd, Ag, Au, and Sn (tin), or an alloy thereof as its main component. The base layer 7 also comprises particles of a co-material. The co-material reduces the difference in thermal expansion coefficient between the element body 2 and the base layer 7, and relieves the stress applied to the base layer 7. The common material is, for example, a ceramic component which is a main component of the dielectric layer 4. The base layer 7 may comprise a glass composition. The glass component is used for densification and the like of the base layer 7. The glass component is, for example, an oxide of Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), or B (boron). The base layer 7 is electrically connected to a plurality of internal electrode layers led out to the side surface of the element body.

The material of the oxide layer 8 includes an oxide film of a metal used as the conductive material of the base layer 7 and a material of a common material used for the base layer 7. The base layer 7 may have the same composition as the dielectric layer 4, for example barium titanate. The metal used as the conductive material of the base layer 7 is, for example, nickel. The oxide film of the metal used as the conductive material of the base layer 7 is, for example, nickel oxide, and its thickness is, for example, in the range of 0.05 μm to 3 μm.

Each of the base layer 7 and the oxide layer 8 may have a metal composition contained in the element body 2. The metal component contained in the element body 2 may include at least one of Mg, Ni, Cr, Sr, Al, Na, and Fe. For example, the metal component contained in the element body 2 is Mg. If the metal component is Mg, each of the base layer 7 and the oxide layer 8 may include a metal serving as a conductive material of the base layer 7, a compound of the metal contained in the element body 2, and oxygen. For example, the compound included in each of the base layer 7 and the oxide layer 8 contains Ni, Mg, and O.

The main component of the material of the plating layer 9 is, for example, a metal such as Cu, Ni, Al, Zn, and Sn, or an alloy containing at least two of Cu, Ni, Al, Zn, and Sn. The coating 9 may be a coating of a single metal composition or may comprise multiple coatings of different metal compositions. For example, as shown in fig. 2, the plating layer 9 may have a three-layer structure, that is, the plating layer 9 may include a Cu plating layer 9A formed on the base layer 7, a Ni plating layer 9B formed on the Cu plating layer 9A, and a Sn plating layer 9C formed on the Ni plating layer 9B. The Cu plating layer 9A can improve adhesion of the plating layer 9 to the underlying layer 7. The Ni plating layer 9B can improve the heat resistance of the external electrodes 6A, 6B at the time of welding. The Sn plating layer 9C can improve the wettability of the solder of the plating layer 9. The plating layer 9 is formed on a part of the base layer 7 so that the plating layer 9 is conductively connected to the internal electrode layers. For example, the plating layer 9 may be formed on one face of the base layer 7 extending in a direction perpendicular to the stacking direction DS. Further, the plating layer 9 is conductively connected to the terminal of the circuit board by solder. Incidentally, when the metal component of the base layer 7 is Cu, the Cu plating layer 9A may not be formed. If the Cu plating layer 9A is not formed, the plating layer 9 may have a two-layer structure, that is, the plating layer 9 may include a Ni plating layer 9B and a Sn plating layer 9C formed on the Ni plating layer 9B.

Fig. 3A is a cross-sectional view showing an enlarged configuration of an EA portion of the external electrode 6B shown in fig. 2, and fig. 3B is a cross-sectional view showing an enlarged configuration of an EB portion of the external electrode 6B shown in fig. 2. The external electrode 6A and the external electrode 6B have the same configuration.

As shown in fig. 3A and 3B, the conductor 12 and the co-material 11 are present in the base layer 7 in a mixed manner. The main component of the conductor 12 is a metal including at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, or an alloy thereof. The common material 11 is, for example, oxide ceramic as a main component of the dielectric layer 4.

As shown in fig. 3A, the surface of the conductor 12 of the base layer 7 on the side surface M2, the upper surface M3, the front surface M4, and the rear surface M4 of each of the external electrodes 6A and 6B is coated with an oxide film 8A. The oxide film 8A is an oxide film of a metal or an alloy used for the conductor 12. The oxide film 8A is divided by the common material particles 11 present up to the surface of the base layer 7. The oxide layer 8 may be configured to include an oxide film 8A and a surface layer defined by the co-material particles 11.

On the other hand, fig. 3B shows the base layer 7 on the mount face M1, the base layer 7 being made by a manufacturing method to be described below. As shown in fig. 3B, the oxide film 8A is not formed on the surface of the conductor 12 exposed from the base layer 7 on the mounting surface M1 of the external electrodes 6A and 6B. But a plating layer 9 is formed on the base layer 7. Thereby, the conductor 12 and the plating layer 9 are connected to each other, and the electrical conductivity of the mounting surface M1 of the external electrodes 6A, 6B is ensured.

In fig. 3A, an oxide film 8A of nickel oxide is formed on a conductor 12. In the depth direction of the base layer 7, the co-material particles 11 and the conductor 12 are mixed in a mosaic shape. The co-material particles 11 are distributed in the form of irregular islands in the conductor 12. The common material 11 continuously exists from the oxide layer 8 to the base layer 7, and may have a continuous crystal structure or an amorphous structure. Similarly, the conductor 12 exists continuously from the oxide layer 8 to the base layer 7, and may have a continuous crystalline structure or an amorphous structure.

Fig. 4 schematically shows an exemplary composition of the surface of the oxidized layer 8 of fig. 2. FIG. 4 shows that the metal used for the conductor 12 of the underlayer 7 is Ni and the oxide ceramic used for the co-material 11 is barium titanate (BaTiO)₃) The oxide film 8A is an example of nickel oxide.

In fig. 4, the co-material 11 and the oxide film 8A are present on the surface of the oxide layer 8 in a mixed manner. The co-material 11 and the oxide film 8A are mixed in the form of crystalline or amorphous particles, so that the particles of the co-material 11 are dispersed in the particles of the oxide film 8A. The co-material particles 11 are distributed in the form of islands over the entire surface of the oxide layer 8. The size (length) of one particle of the particulate material 11 is in the range of 0.1 μm to 8 μm in the major axis. The compounds 13 of Mg, Ni and O are separated in the form of particles on the surface of the oxide layer 8. When the oxide layer 8 is viewed from the surface as shown in fig. 4, the ratio of the common material to the entire composition is in the range of 20 at% to 75 at%. This can be confirmed by surface analysis of a sufficiently large area, for example by EDX (energy dispersive X-ray spectroscopy). A sufficiently large area is large enough to represent the surface composition of the oxide layer 8.

The common material 11 extends from the surface of the oxide layer 8 to the element body 2 through the base layer 7. The co-material 11 is made of a plurality of particles aggregated to a size of about 1 μm to 40 μm, and may be distributed in the depth direction. Therefore, even if mechanical stress is applied to the oxide layer 8, the common material 11 exposed on the surface of the oxide layer 8 is hardly peeled off. When mechanical stress is applied to the oxide layer 8, the common material 11 may act as a support for piercing into the oxide layer 8 and supporting the oxide layer 8 on the base layer 7.

The common material 11 is exposed on the surface of the oxide layer 8, and splits the oxide film 8A made of nickel oxide. Therefore, even when mechanical stress is applied to the oxide layer 8 and the oxide film 8A made of nickel oxide is peeled from the conductor 12, the peeling process of the oxide film 8A is prevented at the position of the co-material 11 exposed on the surface of the oxide layer 8.

Therefore, even in the case where mechanical stress is applied to the oxide layer 8, it is possible to reduce the possibility that the entire oxide layer 8 is immediately broken, and to reduce the possibility that the oxide film 8A (oxide layer 8) is peeled off from the external electrodes 6A, 6B.

Since the oxidized layer 8 includes the particle compound 13 of Mg, Ni, and O, the adhesion strength between the oxidized layer 8 and the base layer 7 can be improved. Therefore, the possibility of the oxide layer 8 peeling off from the external electrodes 6A and 6B can be further reduced.

According to the first embodiment described above, the oxide layer 8 includes the oxide film of the metal serving as the conductive material of the base layer 7 and the common material of the base layer 7. Therefore, the oxide layer 8 can be suppressed from peeling off from each of the external electrodes 6A and 6B. Since the multilayer ceramic capacitor 1A has the oxide layer 8 hardly peeled off on the surfaces of the side face M2, the upper face M3, the front face M4, and the rear face M4 of each of the external electrodes 6A and 6B, the wet solder does not move up to the faces of the external electrodes 6A, 6B other than the mount face M1, and the mounting of the capacitor 1A (electronic component) by soldering can be performed in a stable manner.

Second embodiment

Fig. 5 is a flowchart illustrating a method of manufacturing a multilayer ceramic capacitor. A method of manufacturing a multilayer ceramic capacitor will be described as a second embodiment of the present invention. Fig. 6A to 6J are a series of cross-sectional views illustrating an exemplary method of manufacturing a multilayer ceramic capacitor according to a second embodiment. Incidentally, fig. 6C to 6J show only two internal electrode layers 3A and two internal electrode layers 3B alternately laminated via dielectric layers 4 for the purpose of explanation.

In step S1 of fig. 5, an organic binder and an organic solvent as a dispersant and a molding aid are added to the dielectric material powder, and are pulverized and mixed to produce a slurry. The dielectric material powder includes, for example, a ceramic powder. The dielectric material powder may include one additive or a plurality of additives. The additive may be, for example, Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K or Si oxides or glasses. The organic binder is, for example, a polyvinyl butyral resin or a polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

Next, as shown in step S2 of fig. 5 and as shown in fig. 6A, a green sheet 24 is manufactured. Specifically, a slurry containing a ceramic powder is applied in a sheet form on a carrier film and dried to produce a green sheet 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. The application of the slurry is performed, for example, by a doctor blade method, a die coater method, or a gravure coater method. Step S2 is repeatedly performed to prepare a plurality of green sheets 24.

Then, as shown in step S3 of fig. 5 and as shown in fig. 6B, a conductive paste to be an internal electrode, which will form the internal electrode layers 3A and 3B shown in fig. 1, is applied in a predetermined pattern onto each of the green sheets 24 prepared in step S1 to form a plurality of internal electrode patterns 23 on the green sheet 24. In step S3, a plurality of internal electrode patterns 23 may be formed on a single green sheet 24 such that the internal electrode patterns 23 are separated from each other in the longitudinal direction of the green sheet 24. The conductive paste for internal electrodes includes metal powder serving as a material of the internal electrode layers 3A, 3B. For example, if the metal used as the material of the internal electrode layers 3A, 3B is Ni, the conductive paste for the internal electrodes includes Ni powder. Further, the conductive paste for the internal electrode includes a binder, a solvent, and (if necessary) an auxiliary agent. The conductive paste for the internal electrodes may include a ceramic material as a main component of the dielectric layer 4 as a co-material. The application of the conductive paste for the internal electrode may be performed by a screen printing method, an ink-jet printing method, or a gravure printing method. Therefore, step S3 may be referred to as a printing step. In this manner, a plurality of green sheets 24 having the internal electrode patterns 23 thereon are prepared.

Next, as shown in step S4 of fig. 5 and as shown in fig. 6C, the green sheet 24 on which the internal electrode patterns 23 are formed and the green sheet 24A on which the internal electrode patterns 23 are not formed are laminated in a predetermined order to form a block 25 of the green sheet 24. The green sheet 24A on which the internal electrode pattern 23 is not formed serves as an outer layer. In step S4, the green sheets 24 having the internal electrode patterns 23 thereon are divided into two groups, i.e., the green sheets 24 having the internal electrode patterns 23A thereon and the green sheets 24 having the internal electrode patterns 23B thereon. Then, the green sheet 24 having the internal electrode pattern 23A thereon and the green sheet 24 having the internal electrode pattern 23B thereon are alternately stacked in the stacking direction, so that the internal electrode pattern 23A on the green sheet 24 and the internal electrode pattern 23B on the next or adjacent green sheet 24 are alternately switched in the longitudinal direction of the green sheet 24. Further, three types of sections are defined in the green sheet block 25. Specifically, in the green sheet block 25, there are defined: a portion where only the internal electrode pattern 23A is stacked in the stacking direction, a portion where the internal electrode patterns 23A and 23B are alternately stacked in the stacking direction, and a portion where only the internal electrode pattern 23B is stacked in the stacking direction.

Next, as shown in step S5 of fig. 5 and shown in fig. 6D, the laminated block 25 obtained in the forming process of step S4 of fig. 5 is pressed, so that the green sheet 24 is pressed. Pressing the laminated block 25 may be performed by, for example, sandwiching the laminated block 25 between resin films and subjecting the laminated block 25 to hydrostatic pressure.

Then, as shown in step S6 of fig. 5 and shown in fig. 6E, the laminated block 25 being pressed is cut so that the block 25 is separated into a plurality of element bodies each having a rectangular parallelepiped shape. Each element body has six faces. As indicated by the plurality of vertical broken lines 27, the cutting of the laminated block 25 is performed at a portion where only the internal electrode pattern 23A exists in the stacking direction and a portion where only the internal electrode pattern 23B exists in the stacking direction. The cutting of the laminated block 25 is performed, for example, by blade cutting or the like. The resulting element body 2 is shown in fig. 6F.

As shown in fig. 6F, in each of the element bodies 2, the internal electrode layers 3A and 3B are alternately laminated via the dielectric layers 4. The internal electrode layers 3A are exposed on one side surface of each element body 2, and the internal electrode layers 3B are exposed on the other side surface of each element body 2.

Next, as shown in step S7 of fig. 5, the adhesive contained in each element body 2 obtained in step S6 of fig. 5 is removed. For example, the adhesive is removed by heating the element body 2 in an N2 atmosphere at about 350 ℃.

Next, as shown in step S8 of fig. 5, the conductive paste for the base layer (bottom layer) 7 is applied to both the side faces of each element body 2 from which the adhesive is removed and those edges of the remaining four faces of the element body 2 adjacent to the both side faces in step S7 of fig. 5. Then, the conductive paste is dried. The conductive paste for the base layer 7 includes metal powder or filler used as the conductive material of the base layer 7. For example, when the metal used as the conductive material of the base layer 7 is Ni, the conductive paste for the base layer includes powder or filler of Ni. The conductive paste used for the base layer includes, for example, a ceramic component as a main component of the dielectric layer 4 as a co-material. For example, oxide ceramic particles (D50 particle diameter of 0.8 μm to 4 μm) containing barium titanate as a main component are mixed as a co-material in the range of 10 wt% to 40 wt% in the conductive paste for the undercoat layer. In addition, the conductive paste for the base layer includes a binder and a solvent.

Next, as shown in step S9 of fig. 5 and as shown in fig. 6G, the element bodies 2 on which the conductive paste for the base layer is applied in step S8 of fig. 5 are subjected to a sintering process, so that in each element body 2, the internal electrode layers 3A and 3B are integrated with the dielectric layer 4, and the base layer 7 is formed and integrated with the element body 2. The sintering of the element body 2 is performed, for example, in a firing furnace (firing furnace) at a temperature range of 1000 ℃ to 1350 ℃ for 10 minutes to 2 hours. If a base metal such as Ni or Cu is used as the material of the internal electrode layers 3A, 3B, the sintering process may be performed in a firing furnace while the inside of the firing furnace is kept in a reducing atmosphere to prevent oxidation of the internal electrode layers 3A and 3B.

Next, as shown in step S10 of fig. 5 and as shown in fig. 6H, the metal exposed on the surface of each base layer 7 is oxidized to form an oxide layer 8 on the surface of the base layer 7, which includes an oxide film of the metal and the common material of the base layer 7. In the oxidation of the metal exposed on the surface of each base layer 7, a reoxidation treatment may be performed at 600 to 1000 ℃ in an N2 atmosphere, for example. Incidentally, in order to ensure that the oxide film of the metal exposed on the surface of each base layer 7 is formed to a sufficient thickness, oxygen may be added to the atmosphere gas of the reoxidation process.

Next, as shown in step S11 of fig. 5, four faces (i.e., the side face M2, the upper face M3, the front face M4, and the rear face M4) other than the mount face M1 of each base layer 7 are coated with a resist resin. The coating of the resist resin is performed, for example, by applying the resist resin by a transfer roll and thermally curing the resist resin.

Next, as shown in step S12 of fig. 5 and as shown in fig. 6J, the oxide film is removed from the mount face M1 of each base layer 7 by sandblasting (blast polishing) to expose the metal contained in the mount face M1 of the base layer 7. In the blasting process, the element body 2 is placed in the blasting device such that the mount face M1 faces upward, and then the blasting medium is applied onto the mount face M1 from directly above the element body 2. The blasting medium applied from directly above the element body 2 is wrapped around the side faces of the element body 2, but the side face M2, the upper face M3, the front face M4, and the rear face M4 of each of the two base layers 7 are covered with the resist resin. Accordingly, the oxide film may be maintained on the side M2, the upper surface M3, the front surface M4, and the rear surface M4 of each base layer 7. After the sandblasting, the resist resin is removed with a solvent or the like.

Next, as shown in step S13 of fig. 5 and as shown in fig. 6J, the plated layers 9 are formed on the mount face M1 of each base layer 7. In the process of forming the plating layer 9, for example, Cu plating, Ni plating, and Sn plating may be performed in this order. In this process, the element body 2 from which the oxide film on the mount face M1 of each base layer 7 is removed is placed in a barrel together with the plating solution, and power is supplied to the barrel while rotating the barrel, thereby forming the plated layer 9. In this process, an oxide film is present on the side surface M2, the upper surface M3, the front surface M4, and the rear surface M4 of each base layer 7, and thus no plating layer is formed on these surfaces.

Fig. 7A is a plan view illustrating the exemplary process of fig. 6I, and fig. 7B is a cross-sectional view obtained by cutting fig. 7A in the length direction DL.

In fig. 7A and 7B, a plurality of element bodies 2 are placed on a substrate 31, each element body 2 including an oxide film 8 formed on a surface of each base layer 7. When the element bodies 2 are placed on the base plate 31, the upper surface M3 of each element body 2 is attached to the base plate 31 by the fixing tape 32 such that the mounting surface M1 of each element body 2 faces upward. Then, a blasting medium 34 is applied (blasted) to the element body 2 from a nozzle 33 installed above the element body 2. The blasting media 34 are, for example, particles made of zircon or alumina.

The blasting conditions mainly set the blasting speed, the blasting amount and the blasting area. The blasting speed is adjusted by the pressure and path of the blasting media 34. The sand blasting amount is adjusted according to the medium circulation and the sand blasting time. The blasting area is adjusted by the shape of the nozzle 33 and the distance between the element body 2 and the nozzle 33.

In the sandblasting process, the side M2, the upper surface M3, the front surface M4, and the rear surface M4 of each base layer 7 were coated with a resist resin. Therefore, even when the blasting medium 34 ejected from the nozzles 33 is wrapped around the side face of each element body 2, the oxide film remains on the side face M2 and the upper surface M3 of each base layer 7, and the oxide film is removed from the mount face M1 of each base layer 7. Incidentally, the amount of removing (blasting) the oxide film from the mount face M1 of the base layer 7 may be set to a value or range capable of forming the plating layer 9 on the mount face M1 of the base layer 7.

According to the second embodiment described above, the ceramic component as the main component of the dielectric layer 4 is mixed in the conductive paste for the base layer. Therefore, an oxide film including a metal serving as a conductive material of the base layer 7 and the oxide layer 8 including an oxide of a metal serving as a common material of the base layer 7 can be formed on each base layer 7. Therefore, it is possible to manufacture the multilayer ceramic capacitor 1A, which is capable of reducing or eliminating the possibility of the oxide layer 8 peeling off from the external electrodes 6A and 6B while suppressing an increase in the number of manufacturing steps.

It should be noted that although the method of removing the oxide layer 8 on the mount faces M1 of the external electrodes 6A and 6B by sandblasting has been described in the above-described embodiment, isotropic dry etching such as plasma etching may be used instead of sandblasting, and chemical polishing (e.g., wet etching) may be used instead of sandblasting.

Third embodiment

Fig. 8 is a cross-sectional view showing a circuit board device according to a third embodiment of the present invention. The circuit board device includes a circuit board 41 and a multilayer ceramic capacitor 1A mounted on the circuit board 41.

In fig. 8, ground electrodes 42A and 42B are formed on a circuit board 41. The multilayer ceramic capacitor 1A is connected to the ground electrodes 42A and 42B via solder layers 43A and 43B attached to the tin plating layers 9C, 9C of the external electrodes 6A and 6B, respectively. The solder layer 43A is prevented by the oxide layer 8 from wetting (moving up) the side face M2, the upper surface M3, the front surface M4, and the rear surface M4 of the external electrode 6A. Similarly, solder layer 43B is prevented by oxide layer 8 from wetting side M2, upper surface M3, front surface M4, and rear surface M4 of external electrode 6B. Therefore, it is possible to prevent the space between the electronic components from being reduced due to the wetting of the solder layers 43A and 43B with the side faces M2 of the external electrodes 6A and 6B. This can increase the mounting density of electronic components on the circuit board 41.

Even if solder mounting on the circuit board 41 is performed in a reducing atmosphere in a reflow furnace and the oxide of the metal exposed on the surface of each oxidized layer 8 is reduced to the metal, the common material of each base layer 7 maintains its state on the surface of the oxidized layer 8. Therefore, it is possible to prevent the wet solder layer 43A from moving upward to the side M2 and the upper surface M3 of the external electrode 6A, and to prevent the wet solder layer 43B from moving upward to the side M2 and the upper surface M3 of the external electrode 6B.

Since the oxide layer 8 includes the common material of the base layer 7, the oxide layer 8 can improve its heat resistance. Further, since the base layer 7 is made of a common material from the base layer 7 to the surface of the oxide layer 8, the resistance to thermal history (thermal history) can be improved.

According to the third embodiment described above, the oxide layer 8 is provided on the side face M2, the upper surface M3, the front surface M4, and the rear surface M4 of each of the external electrodes 6A and 6B. Therefore, it is possible to improve the reliability of the multilayer ceramic capacitor 1A mounted on the circuit board 41 while increasing the mounting density of the electronic components on the circuit board 41.

Fourth embodiment

Fig. 9 is a cross-sectional view showing the structure of a multilayer ceramic capacitor 1B according to a fourth embodiment of the present invention. In fig. 9, a multilayer ceramic capacitor 1B includes an element main body 2 and two external electrodes 56A and 56B.

The external electrodes 56A and 56B are located on opposite sides of the element main body 2 and are separated (spaced) from each other. Each of the external electrodes 56A and 56B extends from the side face of the element main body 2 to the front surface, the rear surface, the upper surface, and the lower surface of the element main body 2.

Each of the external electrodes 56A and 56B includes a base layer 7 and three plated layers 59A, 59B, and 59C. Each of the external electrodes 56A and 56B has a mounting face M1, a side face M2, an upper face M3, a front face M4, and a rear face M4. The mounting surface M1 is a surface facing the circuit board (41) on which the multilayer ceramic capacitor 1B is mounted. The upper surface M3 is a surface opposite to the mounting surface M1. Although not shown in fig. 9, the multilayer ceramic capacitor 1B is mounted on the ground electrodes 42A and 42B on the circuit board 41 in the configuration shown in fig. 8.

The surface (i.e., the upper surface M3) other than the mounting surface M1, the side surface M2, the front surface M4, and the rear surface M4 of each of the external electrodes 56A and 56B is coated with the oxidized layer 58. The material of the oxide layer 58 is the same as that of the oxide layer 8 shown in fig. 1. Cu plating layers 59A, Ni, plating layers 59B and Sn plating layers 59C are formed in this order on the mount face M1, the side face M2, the front face M4 and the rear face M4 of the base layer 7 of each of the external electrodes 56A and 56B.

According to the fourth embodiment described above, the upper face M3 of each of the external electrodes 56A and 56B is coated with the oxide layer 58. Further, plating layers 59A, 59B, and 59C are formed on the mount face M1, the side face M2, the front face M4, and the rear face M4 of each of the external electrodes 56A and 56B. Therefore, when the multilayer ceramic capacitor 1B is mounted on the circuit board 41 of fig. 8, it is possible to allow the wet solder to move (extend) upward along the side surface M2 of each of the external electrodes 56A and 56B, while preventing the wet solder from moving upward onto the upper surface M3 of each of the external electrodes 56A and 56B. Therefore, even when solder is excessively applied to the ground electrodes 42A and 42B, it is possible to suppress or prevent the solder from extending outward (laterally) from the ground electrodes 42A and 42B while preventing the total height of the circuit board 41 and the multilayer ceramic capacitor 1B mounted on the circuit board 41 from exceeding the design value. Therefore, it is possible to reduce the distance between the electronic components mounted on the circuit board 41 while reducing the possibility of short-circuiting between the electronic components mounted on the circuit board 41. This enables electronic components to be mounted with high density.

Fifth embodiment

Fig. 10 is a perspective view showing the configuration of an electronic component according to a fifth embodiment of the present invention. Fig. 10 shows a chip inductor 61 as an example of an electronic component.

In fig. 10, a chip inductor 61 includes an element main body 62 and two external electrodes 66A and 66B. The element body 62 has a coil pattern 63, internal electrode layers 63A and 63B, and a magnetic material 64. The element body 62 may be substantially rectangular parallelepiped in shape. The external electrodes 66A and 66B are located on opposite sides of the element main body 62 and are separated from each other. Each of the external electrodes 66A and 66B extends from the associated side of the element main body 62 toward the front surface, the rear surface, the upper surface, and the lower surface of the element main body.

The coil pattern 63 and the internal electrode layers 63A and 63B are covered with a magnetic material 64. However, the end portion of the internal electrode layer 63A is exposed from the magnetic material 64 on one side surface of the element main body 62 and connected to the external electrode 66A. The end portion of the internal electrode layer 63B is exposed from the magnetic material 64 on the other side surface of the element main body 62 and connected to the external electrode 66B.

The material of the coil pattern 63, the internal electrode layers 63A, and the internal electrode layers 63B may be, for example, metals such as Cu, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or alloys containing these metals. The magnetic material 64 is, for example, ferrite.

Each of the external electrodes 66A and 66B includes a base layer 67 and a plating layer 69. Each of the external electrodes 66A and 66B has a mounting surface M1, a side surface M2, a top surface M3, a front surface M4, and a rear surface M4. The mounting surface M1 is a surface facing the circuit board on which the chip inductor 61 is mounted. The upper surface M3 is a surface opposite to the mounting surface M1.

The main component of the conductive material of the base layer 67 may be, for example, a metal including at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, or an alloy thereof. The base layer 67 comprises a common material. The common material is, for example, a ceramic component that is a main component of the magnetic material 64. The base layer 67 may comprise a glass composition. For example, the glass component is an oxide of Ba, Sr, Ca, Zn, Al, Si, or B.

The faces other than the mount face M1 of each of the external electrodes 66A and 66B (i.e., the side face M2, the upper face M3, the front face M4, and the rear face M4) are coated with the oxidized layer 68. The oxide layer 68 includes an oxide film of a metal serving as a conductive material of the underlayer 67 and an oxide containing a metal serving as a co-material of the underlayer 67. The plating layer 69 is formed on the mount face M1 of the base layer 67 of each of the external electrodes 66A and 66B. The base layer 67, oxide layer 68 and plating layer 69 may be constructed in a similar manner to the base layer 7, oxide layer 8 and plating layer 9, respectively, of fig. 1.

According to the above-described fifth embodiment, the oxide layer 68 includes the oxide film of the metal serving as the conductive material of the base layer 67 and the oxide containing the metal serving as the common material of the base layer 67, and therefore, the wet solder can be prevented from moving up to the faces of the external electrodes 66A, 66B on which the oxide layer 68 is formed. In addition, the oxide layer 68 can be suppressed or prevented from peeling off from the external electrodes 66A and 66B.

Sixth embodiment

Fig. 11 is a perspective view showing the configuration of an electronic component according to a sixth embodiment of the present invention. Fig. 11 shows a chip resistor 71 as an example of an electronic component.

In fig. 11, the chip resistor 71 includes an element main body 72, two external electrodes 76A and 76B, and a protective film 75. The element main body 72 has a resistor 73, an internal electrode layer 73B, and a substrate 74. The element body 72 may have a substantially rectangular parallelepiped shape. The external electrodes 76A and 76B are arranged on opposite sides of the element main body 72 and are separated from each other. Each of the external electrodes 76A and 76B extends from the associated side surface of the element body 72 to the upper and lower surfaces of the element body 72.

The resistor 73 and the internal electrode layer 73B are provided on the substrate 74 and covered with a protective film 75. One end of the resistor 73 is connected to the internal electrode layer 73B on the substrate 74. The internal electrode layer 73B is elongated to one side surface of the element main body 72 and connected to the external electrode 76B. Another internal electrode layer (not shown) connected to the other end of the resistor 73 extends to the other side face of the element main body 72 and is connected to the external electrode 76A.

The material of the resistor 73 may be selected from metals such as Ag and Pd, or may be an alloy containing these metals. Alternatively, the material of the resistor 73 may be a metal oxide, such as ruthenium oxide. The material of the internal electrode layer 73B may be a metal selected from metals such as Cu, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or may be an alloy containing these metals. The material of the substrate 74 is, for example, an oxide ceramic such as alumina. The material of the protective film 75 is, for example, glass or resin.

Each of the external electrodes 76A and 76B includes a base layer 77 and a plating layer 79. Each of the external electrodes 76A and 76B has a mounting face M1, a side face M2, and an upper face M3. The mounting surface M1 is a surface facing the circuit board on which the chip resistor 71 is mounted. The upper surface M3 is a surface opposite to the mounting surface M1.

The main component of the conductive material of the base layer 77 may be, for example, a metal including at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn or an alloy containing at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The base layer 77 includes a common material. The co-material is, for example, a ceramic component, which is a main component of the substrate 74. The substrate layer 77 may comprise a glass composition. For example, the glass component is an oxide of Ba, Sr, Ca, Zn, Al, Si, or B.

The faces (the side face M2 and the upper face M3) other than the mount face M1 of each of the external electrodes 76A and 76B are coated with the oxide layer 78. The oxide layer 78 includes an oxide film of a metal serving as a conductive material of the base layer 77 and an oxide containing a metal serving as a co-material of the base layer 77. The plating layer 79 is formed on the mount face M1 of the base layer 77 of each of the external electrodes 76A and 76B. The base layer 77, oxide layer 78 and plating layer 79 may be constructed similarly to the base layer 7, oxide layer 8 and plating layer 9, respectively, shown in fig. 1.

According to the above-described sixth embodiment, the oxide layer 78 includes the oxide film of the metal serving as the conductive material of the base layer 77 and the oxide containing the metal serving as the common material of the base layer 77. Therefore, it is possible to prevent the wet solder from moving up to those faces of the external electrodes 76A and 76B on which the oxide layer 78 is formed, and reduce the possibility of the oxide layer 78 peeling off from the external electrodes 76A and 76B.

It should be noted that although the electronic component described in each of the above embodiments has two terminals, the electronic component may have three or more terminals, such as transistors or transformers.

This application is based on and claims priority from Japanese patent application No. 2020-.