阅读说明：本技术 一种半导体器件结构 (Semiconductor device structure ) 是由 姜涛 于 2020-06-04 设计创作，主要内容包括：本发明公开了一种半导体器件结构,包括衬底层；第一N型层,位于所述衬底层的上表面；第一P型层,位于所述第一N型层的上表面；第二N型层,位于所述第一P型层的上表面；发光层,位于所述第一P型层与所述第二N型层之间形成的第一PN结处的预设位置上；第二P型层,位于所述第二N型层的上表面；第一电极,位于所述第二P型层的上表面；第二电极,位于所述第一N型层上以形成半导体器件结构。本发明提供的半导体器件结构,通过构建新的发光器件结构扭转了PN结反偏时不会发生电光转化的问题,将反偏PN结处的预设位置内作为发光区域,实现了高效率的电光转换。(The invention discloses a semiconductor device structure, which comprises a substrate layer; the first N-type layer is positioned on the upper surface of the substrate layer; the first P type layer is positioned on the upper surface of the first N type layer; the second N-type layer is positioned on the upper surface of the first P-type layer; the light emitting layer is positioned at a preset position of a first PN junction formed between the first P type layer and the second N type layer; the second P type layer is positioned on the upper surface of the second N type layer; the first electrode is positioned on the upper surface of the second P type layer; and the second electrode is positioned on the first N-type layer to form a semiconductor device structure. The semiconductor device structure provided by the invention solves the problem that electro-optic conversion cannot occur when a PN junction is reversed by constructing a new light-emitting device structure, and realizes high-efficiency electro-optic conversion by taking the preset position of the reversed PN junction as a light-emitting region.)

1. A semiconductor device structure, comprising:

a substrate layer (100);

a first N-type layer (1) located on the upper surface of the substrate layer (100);

the first P type layer (2) is positioned on the upper surface of the first N type layer (1);

the second N-type layer (3) is positioned on the upper surface of the first P-type layer (2);

the second P type layer (4) is positioned on the upper surface of the second N type layer (3);

the light emitting layer (5) is positioned at a preset position of a first PN junction (11) formed between the first P type layer (2) and the second N type layer (3);

the first electrode (6) is positioned on the upper surface of the second P type layer (4);

a second electrode (7) on the first N-type layer (1) to form a semiconductor device structure.

2. The semiconductor device structure of claim 1, characterized in that the predetermined position at the first PN junction (11) comprises:

is located at the first PN junction (11) interface;

or at a first predetermined depth (h) in said second N-type layer (3)₁) At least one of (1) and (b);

or at a second predetermined depth (h) in said first P-type layer (2)₂) At least one of (1) and (b);

the first preset depth (h)₁) And said second preset depth (h)₂) Are all within the depletion layer region at said first PN-junction (11).

3. The semiconductor device structure of claim 2, wherein the doping concentration of the light emitting layer (5) at the first PN junction (11) interface is 1E 14-1E 21 atoms/cm³；

Or the light-emitting layer (5) is positioned in the second N-type layer (3) at a first preset depth (h)₁) The doping concentration is 1E 14-1E 21 atoms/cm³；

Or the light-emitting layer (5) is positioned in the first P-type layer (2) at a second preset depth (h)₂) The doping concentration is 1E 14-1E 21 atoms/cm³。

4. The semiconductor device structure of claim 2, wherein the first predetermined depth (h) is₁) Is a depth starting from the first PN junction (11) interface and within the second N-type layer (3); the second preset depth (h)₂) Is a depth starting from the first PN junction (11) interface and within the first P-type layer (2).

5. The semiconductor device structure of claim 4, wherein the first predetermined depth (h) is₁) 0 to 10 μm; the second preset depth (h)₂) 0 to 10 μm.

6. A semiconductor device structure according to claim 1, characterized in that the light emitting layer (5) is also located at the second PN junction (22) interface formed between the first N-type layer (1) and the first P-type layer (2).

7. A semiconductor device structure according to claim 1, characterized in that the light emitting layer (5) is also located at the third PN junction (33) interface formed between the second N-type layer (3) and the second P-type layer (4).

8. The semiconductor device structure according to claim 1, wherein the second electrode (7) is located on an upper surface of the first N-type layer (1) to form a semiconductor device structure of a horizontal structure.

9. The semiconductor device structure according to claim 1, wherein the second electrode (7) is located on a lower surface of the first N-type layer (1) to form a vertical-structure semiconductor device structure.

10. The semiconductor device structure of claim 1, further comprising a third electrode (8), the third electrode (8) being located on an upper surface of the first P-type layer (2).

Technical Field

The invention belongs to the technical field of semiconductor photoelectric devices, and particularly relates to a semiconductor device structure.

Background

A light emitting diode is a commonly used light emitting device, which is early in 1962, and only emits red light with low light intensity in the early stage, and then other versions of monochromatic light are developed, and the light emitted so far is distributed throughout visible light, infrared light and ultraviolet light, and the light intensity is also improved to a corresponding light intensity. And the light emitting diode is also used as an indicator light, a display panel and the like in the beginning, and along with the continuous progress of the technology, the light emitting diode is widely applied to the fields of displays, illumination and medical devices.

Currently, light emitting diodes include LEDs and LDs, the core of which is a wafer composed of a P-type semiconductor and an N-type semiconductor with a transition layer, called a PN junction, between them. In the PN junction of some semiconductor materials, the injected minority carriers and majority carriers when they recombine release excess energy in the form of light, thereby directly converting electrical energy into light energy. The PN junction is added with reverse voltage, and minority carriers are difficult to inject, so that the LED does not emit light. When it is in forward working state (i.e. forward voltage is applied to two ends), when the current flows from anode to cathode of LED, the semiconductor crystal can emit light rays with different colors from ultraviolet to infrared, and the intensity of light is related to current. It can be seen by analyzing the working principle of the light emitting diode LED that the light emitting diode LED can emit light only when the PN junction is in forward conduction, but since only a small part of the majority carriers can be combined with the injected minority carriers when the PN junction is in forward conduction, and most of the majority carriers reach the electrode in a drift manner to form current, how to increase the combination of the majority carriers and the minority carriers is the key to improve the electro-optic conversion efficiency of the semiconductor light emitting device. The method for improving the electro-optic conversion efficiency of the semiconductor light-emitting device in the structural design of the LED comprises the following steps: firstly, the injection of holes in the LED is increased by designing a current blocking layer, and the method has certain effect; increasing the doping concentration of the P-type semiconductor material, and further increasing the hole concentration in the P-type material to achieve the purpose of improving the electro-optic conversion efficiency of the semiconductor light-emitting device; and thirdly, a quantum well structure is added at the interface of the P-type material and the N-type material, namely a light-emitting region is formed by thin layers of two semiconductor materials with different forbidden band widths which are alternately and periodically grown.

However, the above method of designing the current blocking layer essentially increases the number of holes participating in recombination as much as possible on the basis of the original hole concentration, and does not fundamentally solve the problem of hole concentration, i.e., the total number of holes; by the method for improving the doping concentration of the P-type semiconductor material, the P-type doping of the main-flow compound semiconductor material GaN for manufacturing the LED is not easy to realize, the P-type doping concentration is far lower than the N-type doping concentration, and no particularly effective method for further improving the P-type doping concentration exists at present; by adding the quantum well structure, the LED can not emit light when the existing LED structure has reverse bias.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a semiconductor device structure.

One embodiment of the present invention provides a semiconductor device structure, comprising:

a substrate layer;

the first N-type layer is positioned on the upper surface of the substrate layer;

the first P type layer is positioned on the upper surface of the first N type layer;

the second N-type layer is positioned on the upper surface of the first P-type layer;

the second P type layer is positioned on the upper surface of the second N type layer;

the light emitting layer is positioned at a preset position of a first PN junction formed between the first P type layer and the second N type layer;

the first electrode is positioned on the upper surface of the second P type layer;

and the second electrode is positioned on the first N-type layer to form a semiconductor device structure.

In one embodiment of the present invention, the predetermined position at the first PN junction includes:

located on the first PN junction interface;

or at a first preset depth in the second N-type layer;

or at a second predetermined depth in the first P-type layer;

the first preset depth and the second preset depth are both in the depletion layer region at the first PN junction.

In one embodiment of the present invention, the doping concentration of the light emitting layer on the first PN junction interface is 1E 14-1E 21 atoms/cm³；

Or the light emitting layer is positioned in the second N-type layerThe doping concentration at the first preset depth is 1E 14-1E 21 atoms/cm³；

Or the doping concentration of the luminescent layer at the second preset depth in the first P-type layer is 1E 14-1E 21 atoms/cm³。

In an embodiment of the present invention, the first predetermined depth is a depth within the second N-type layer starting from the first PN junction interface; the second predetermined depth is a depth within the first P-type layer starting from the first PN junction interface.

In one embodiment of the present invention, the first predetermined depth is 0 to 10 μm; the second preset depth is 0-10 mu m.

In one embodiment of the present invention, the light emitting layer is further located on a second PN junction interface formed between the first N-type layer and the first P-type layer.

In one embodiment of the present invention, the light emitting layer is further located on a third PN junction interface formed between the second N-type layer and the second P-type layer.

In one embodiment of the present invention, the second electrode is located on the upper surface of the first N-type layer to form a semiconductor device structure of a horizontal structure.

In one embodiment of the present invention, the second electrode is located on a lower surface of the first N-type layer to form a vertical-structure semiconductor device structure.

In one embodiment of the present invention, the device further comprises a third electrode, and the third electrode is located on the upper surface of the first P-type layer.

Compared with the prior art, the invention has the beneficial effects that:

according to the semiconductor device structure provided by the invention, a new light-emitting device structure is constructed, the limitation that the traditional semiconductor device structure can only be a diode is broken through, the problem that electro-optic conversion cannot occur when a PN junction is reversely biased is solved, particularly under the condition that the P-type doping concentration cannot be effectively improved temporarily, the preset position of the reverse-biased PN junction with high recombination rate is innovatively used as a light-emitting region, and the current flowing path between the positive electrode and the negative electrode is from the second P-type layer to the second N-type layer, then to the first P-type layer and then to the first N-type layer, so that the utilization rate of holes is greatly improved, high-efficiency electro-optic conversion is realized, and a brand-new device structure and a brand-new research idea are provided for the research in the field of semiconductor light-emitting devices.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic structural diagram of a semiconductor device structure according to an embodiment of the present invention;

FIGS. 2a to 2c are schematic structural diagrams of a light emitting layer at a first PN junction in a semiconductor device structure according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a light emitting layer at a second PN junction in a semiconductor device structure according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a light emitting layer at a third PN junction in a semiconductor device structure according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a semiconductor device structure based on a PNPN structure according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another semiconductor device structure provided by an embodiment of the present invention;

FIGS. 7a to 7c are schematic structural diagrams of a light emitting layer at a first PN junction in another semiconductor device structure provided by the embodiment of the invention;

fig. 8 is a schematic structural view of a light emitting layer at a second PN junction in another semiconductor device structure according to an embodiment of the present invention;

fig. 9 is a schematic structural view of a light emitting layer at a third PN junction in another semiconductor device structure according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another structure of a semiconductor device based on a PNPN structure according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a structure of a semiconductor device according to still another embodiment of the present invention;

fig. 12 is a schematic structural diagram of a structure of a semiconductor device based on a PNPN structure according to another embodiment of the present invention;

fig. 13 is a schematic structural diagram of another semiconductor device structure provided in an embodiment of the present invention;

fig. 14 is a schematic structural diagram of another structure of a semiconductor device based on a PNPN structure according to an embodiment of the present invention.

Description of reference numerals:

100-a substrate layer; 1-a first N-type layer; 2-a first P-type layer; 3-a second N-type layer; 4-a second P-type layer; 5-a light-emitting layer; 6-a first electrode; 7-a second electrode; 8-a third electrode; 11-a first PN junction; 22-a second PN junction; 33-a third PN junction; 100' -a first substrate layer; 1' -a third P-type layer; 2' -a third N-type layer; 3' -a fourth P-type layer; 4' -a fourth N-type layer; 5' -a first light-emitting layer; 6' -a fourth electrode; 7' -a fifth electrode; 8' -a sixth electrode; 11' -a fourth PN junction; 22' -fifth PN junction; 33' -sixth PN junction.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device structure according to an embodiment of the present invention. The present embodiment provides a semiconductor device structure including:

a substrate layer 100;

a first N-type layer 1 on the upper surface of the substrate layer 100;

the first P type layer 2 is positioned on the upper surface of the first N type layer 1;

the second N-type layer 3 is positioned on the upper surface of the first P-type layer 2;

the second P type layer 4 is positioned on the upper surface of the second N type layer 3;

the light emitting layer 5 is positioned at a preset position of a first PN junction 11 formed between the first P type layer 2 and the second N type layer 3;

the first electrode 6 is positioned on the upper surface of the second P type layer 4;

and a second electrode 7 positioned on the first N-type layer 1 to form a semiconductor device structure.

Specifically, the structure of a semiconductor light emitting device is commonly used at present, and the principle of the structure is that a P-type material and an N-type material are respectively obtained by doping a semiconductor material, when a high potential is applied to the P-type material and a low potential is applied to the N-type material, a PN junction starts to be conducted and current flows, electrons and holes are recombined near an interface between the P-type material and the N-type material, and photons are released when recombination occurs in a radiation recombination mode, that is, light emission is realized in the semiconductor device through which current flows. Many parameters of interest in evaluating the performance of semiconductor light emitting devices, such as forward on voltage, reverse breakdown voltage, ESD characteristics, concentration of light emitting wavelength, and light emitting efficiency, are concerned, and how to further improve the light emitting efficiency, that is, the conversion efficiency of electro-optic light, is the most important research point for most of the semiconductor light emitting devices under development and use.

In order to improve the conversion efficiency of converting electric energy into light energy, in the structural design of an LED, firstly, the injection of holes in the LED is increased by designing a current blocking layer; increasing the doping concentration of the P-type semiconductor material, and further increasing the hole concentration in the P-type material to achieve the purpose of improving the electro-optic conversion efficiency of the semiconductor light-emitting device; and thirdly, adding a quantum well structure at the interface of the P-type material and the N-type material. However, the method of designing the current blocking layer is essentially to increase the number of holes participating in recombination as much as possible on the basis of the original hole concentration, and the problem of the hole concentration, namely the total number of holes is not fundamentally solved; by the method for improving the doping concentration of the P-type semiconductor material, the P-type doping of the main-flow compound semiconductor material GaN for manufacturing the LED is not easy to realize, the P-type doping concentration is far lower than the N-type doping concentration, and no particularly effective method for further improving the P-type doping concentration exists at present; by adding the quantum well structure, the LED can not normally emit light when the conventional LED structure has a reverse bias condition.

Based on the existing problems, the present embodiment provides a semiconductor device structure, specifically, the structure sequentially includes, from bottom to top, a substrate layer 100, a first N-type layer 1, a first P-type layer 2, a second N-type layer 3, and a second P-type layer 4, the first N-type layer 1, the first P-type layer 2, the second N-type layer 3, and the second P-type layer 4 are respectively doped with a semiconductor material to obtain a corresponding P-type material and an N-type material, and then grow on the substrate layer 100 according to a NPNP stacking sequence from bottom to top, that is, the first P-type layer 2 is located on the upper surface of the first N-type layer 1, the second N-type layer 3 is located on the upper surface of the first P-type layer 2, the second P-type layer 4 is located on the upper surface of the second N-type layer 3, a second PN junction 22 is formed between the first N-type layer 1 and the first P-type layer 2, a first PN junction 11 is formed between the first P-type layer 2 and the second N-type layer 3, a third PN junction 33 is formed between the second N-type layer 3 and the second P-type layer 4, such an NPNP structure has been widely adopted in power electronic devices, such as an Insulated Gate Bipolar Transistor (IGBT), a Gate Turn-Off Thyristor (GTO), and the like.

In this embodiment, the first electrode 6 is located on the upper surface of the second P-type layer 4, and the second electrode 7 is located on the upper surface of the first N-type layer 1 to form a horizontal semiconductor device structure as an example.

In the NPNP structure, two layers of the first P-type layer 2 and the second N-type layer 3 are in a reverse bias state when the semiconductor light emitting device operates, the entire device is almost a depletion region in the two semiconductor layers, and holes injected from the second P-type layer 4 and electrons injected from the first N-type layer 1 almost conduct current by recombination in the vicinity of the interface of the first PN junction 11 formed by the first P-type layer 2 and the second N-type layer 3. The present embodiment inserts the light-emitting layer 5 of the quantum well structure at the predetermined position of the first PN junction 11, so that the holes and electrons injected by the first electrode 6 and the second electrode 7 are both gathered at the light-emitting layer 5 to be recombined, which is essentially different from the conventional light-emitting diode formed by a single PN junction: in the conventional light emitting diode with a single PN junction, light normally emits only when the light emitting diode is in forward conduction, and the compound electron-hole pairs participating in light emission only occupy a very small part of the overall current, and most of the current reaches the electrode through drift from most of the current carriers, however, in the semiconductor device structure provided by this embodiment, the PN junction where the light emitting layer 5 is located is a preset position of the first PN junction 11, and since the first PN junction 11 is in a reverse bias state during operation, most of the current carriers can emit in this regionThe current generation function is achieved in a composite current mode, so that the carrier recombination efficiency is greatly improved, the utilization rate of holes and electrons is greatly improved, high-efficiency electro-optic conversion is realized, and the electro-optic conversion rate is up to more than 90%. The material of the substrate layer 100 is not limited, and may include silicon (Si), silicon carbide (SiC), diamond, and sapphire (Al)₂O₃) Gallium arsenide (GaAs), aluminum nitride (AlN), gallium nitride (GaN), metals, metal oxides, compound semiconductors, glass, quartz, or composite materials, etc., and may further include single crystal materials having a specific crystal phase orientation, such as m-plane SiC or sapphire, α -plane sapphire, γ -plane sapphire, c-plane sapphire, and may further include semiconductor materials composed of undoped, n-type or p-type doped materials; the materials of the first N-type layer 1, the second N-type layer 3 or the first P-type layer 2 and the second P-type layer 4 respectively comprise III-V group or II-VI group semiconductor materials, such as gallium nitride, aluminum nitride, indium nitride, boron nitride, aluminum gallium nitrogen, indium gallium nitrogen, aluminum gallium indium nitrogen, boron gallium nitrogen, boron aluminum gallium nitrogen, boron indium gallium nitrogen, silicon, germanium, indium phosphide, gallium arsenide, aluminum gallium arsenic, aluminum gallium indium phosphide and the like; the light emitting layer 5 of the quantum well structure is a thin layer of two or more semiconductor materials with different forbidden band widths which alternately grow periodically, and can be a light emitting layer of the existing common quantum well structure, and the quantum well structure belongs to the general identification technology in the field of LEDs, and is not described herein any more.

Further, referring to fig. 2a to 2c, fig. 2a to 2c are schematic structural views of a light emitting layer located at a first PN junction in a semiconductor device structure according to an embodiment of the present invention, where the light emitting layer 5 is located at a predetermined position of the first PN junction 11, the predetermined position includes a first predetermined depth h located on an interface of the first PN junction 11 or located in the second N-type layer 3₁At or in the first P-type layer 2 to a second predetermined depth h₂To (3).

Specifically, the conventional single PN junction reverse bias is to generate reverse bias conducting current by the reverse bias depletion region to emit light, and the current conduction is completed by generating complex current in the reverse bias depletion region between the first P-type layer 2 and the second N-type layer 3 in the NPNP structure, and the current is conducted in the form of the complex current, so as to obtain higher light emitting efficiency. The present embodiment adds the light emitting layer 5 of the quantum well structure at the preset position at the first PN junction 11, specifically:

as shown in fig. 2a, the light emitting layer 5 of the quantum well structure of this embodiment may be located on the interface of the first PN junction 11, and at this time, the light emitting layer 5 may be an undoped quantum well structure, and more preferably, may be a half-doped quantum well structure, where N-type material doping is performed near the second N-type layer 3 and P-type material doping is performed near the first P-type layer 2.

Preferably, the doping concentration of the N-type material is 1E 14-1E 21 atoms/cm when the light-emitting layer 5 is located on the first PN junction 11 interface³The doping concentration of the P-type material is 1E 14-1E 21 atoms/cm³。

As shown in fig. 2b, the light emitting layer 5 of the quantum well structure of this embodiment may also be located in the second N-type layer 3 by a first predetermined depth h₁Here, the light emitting layer 5 may be an undoped quantum well structure, and more preferably, may be a quantum well structure doped with an N-type material. Wherein the first preset depth h₁In the depletion layer region where the second N-type layer 3 is located at the first PN junction 11, specifically, the first predetermined depth h₁Starting from the first PN junction 11 interface (the first predetermined depth h)₁0) and the depth within the second N-type layer 3.

Preferably, the first preset depth h₁0 to 10 μm.

Preferably, the light emitting layer 5 is located in the second N-type layer 3 to a first predetermined depth h₁The doping concentration is 1E 14-1E 21 atoms/cm³。

As shown in fig. 2c, the light emitting layer 5 of the quantum well structure of this embodiment may also be located at a second predetermined depth h in the first P-type layer 2₂Here, the light emitting layer 5 may be an undoped quantum well structure, and more preferably, may be a quantum well structure doped with a P-type material. Wherein the second preset depth h₂In the depletion layer region where the first P-type layer 2 is located at the first PN junction 11, specifically, the second predetermined depth h₂Starting from the first PN junction 11 interface (the second predetermined depth h)₂0) and a depth within the first P-type layer 2.

PreferablyA second predetermined depth h₂0 to 10 μm.

Preferably, the light emitting layer 5 is located in the first P-type layer 2 at a second predetermined depth h₂The doping concentration is 1E 14-1E 21 atoms/cm³。

Further, referring to fig. 3, fig. 3 is a schematic structural diagram of a light emitting layer located at a second PN junction in a semiconductor device structure according to an embodiment of the present invention, in which the light emitting layer 5 of this embodiment may also be located on an interface of the second PN junction 22, and at this time, the light emitting layer 5 may be an undoped quantum well structure, and more preferably, may be a half-and-half doped quantum well structure, where N-type material doping is performed near the first N-type layer 1, and P-type material doping is performed near the first P-type layer 2.

Preferably, the doping concentration of the N-type material is 1E 14-1E 21 atoms/cm when the light-emitting layer 5 is located on the second PN junction 22 interface³The doping concentration of the P-type material is 1E 14-1E 21 atoms/cm³。

Further, referring to fig. 4, fig. 4 is a schematic structural diagram of a light emitting layer located at a third PN junction in a semiconductor device structure according to an embodiment of the present invention, where the light emitting layer 5 of this embodiment may also be located on an interface of the third PN junction 33, and at this time, the light emitting layer 5 may be an undoped quantum well structure, and more preferably, may be a half-and-half doped quantum well structure, and N-type material doping is performed near the second N-type layer 3 and P-type material doping is performed near the second P-type layer 4.

Preferably, the doping concentration of the N-type material is 1E 14-1E 21 atoms/cm when the light-emitting layer 5 is located on the interface of the third PN junction 33³The doping concentration of the P-type material is 1E 14-1E 21 atoms/cm³。

In the semiconductor device structure proposed in this embodiment, the position, doping concentration, and the like of the light emitting layer 5 play a very important role in the photoelectric conversion efficiency of the semiconductor device structure of the present application.

In summary, the semiconductor device structure provided in this embodiment breaks through the limitation that the conventional semiconductor device structure can only be a diode by constructing a new light emitting device structure, and reverses the problem that electro-optical conversion does not occur when the PN junction is reverse biased, especially when P-type doping is performedIn the case that the concentration cannot be effectively increased temporarily, the present embodiment innovatively introduces a reverse biased PN junction interface (such as the first PN junction 11 interface) with a high recombination rate or a P-type N-type semiconductor material portion (the first predetermined depth h) in the depletion region of the reverse biased PN junction₁Or a second predetermined depth h₂) As a light-emitting region, the current between the positive electrode and the negative electrode flows through a path from the second P-type layer 4 to the second N-type layer 3 to the first P-type layer 2 and then to the first N-type layer 1, so that the utilization rate of holes is greatly improved, high-efficiency electro-optic conversion is realized, the theoretical electro-optic conversion rate can reach 100%, and a brand-new device structure and a research thought are provided for the research in the field of semiconductor light-emitting devices.

It should be noted that, the semiconductor device structure provided in this embodiment, no matter which method is used to prepare the epitaxial material of the substrate, or which substrate is used, or which epitaxial layer semiconductor material is grown according to which sequence, and the light emitting layer 5 is added at the reverse biased PN junction interface or in the depletion region at the reverse biased PN junction to form the semiconductor device structure according to this embodiment, all belong to the protection scope of this application, that is, this embodiment is not limited to the NPNP structure, for example, the reverse structure of PNPN may also be used, please refer to fig. 5, fig. 5 is a schematic structural diagram of a semiconductor device structure based on the PNPN structure provided in this embodiment of the present invention, and the semiconductor device structure includes:

a first substrate layer 100';

a third P-type layer 1 'on the top surface of the first substrate layer 100';

the third N-type layer 2 'is positioned on the upper surface of the third P-type layer 1';

a fourth P-type layer 3 'on the upper surface of the third N-type layer 2';

a fourth N-type layer 4 'on the upper surface of the fourth P-type layer 3';

the first light-emitting layer 5 'is positioned at a preset position of a fourth PN junction 11' formed between the third N-type layer 2 'and the fourth P-type layer 3';

a fourth electrode 6 'on the upper surface of the fourth N-type layer 5';

and a fifth electrode 7 'positioned on the upper surface of the third P-type layer 1' to form a horizontal structure of the PNPN structure-based semiconductor device structure.

Specifically, the semiconductor device structure based on the PNPN structure sequentially includes, from bottom to top, a first substrate layer 100 ', a third P-type layer 1 ', a third N-type layer 2 ', a fourth P-type layer 3 ', a fourth N-type layer 4 ', a third P-type layer 1 ', a third N-type layer 2 ', a fourth P-type layer 3 ', and a fourth N-type layer 4 ' by doping semiconductor materials, respectively, to obtain corresponding P-type materials and N-type materials, the material of the first substrate layer 100 ' is not limited, and specifically, the material of the first substrate layer 100 ', the third P-type layer 1 ', the third N-type layer 2 ', the fourth P-type layer 3 ', and the fourth N-type layer 4 ' are selected according to the semiconductor device structure of the NPNP structure. Similar to the semiconductor device structure of NPNP structure, in the semiconductor device structure of PNPN structure, a fourth PN junction 11 'formed between a third N-type layer 2' and a fourth P-type layer 3 'is reversely biased, and a first light emitting layer 5' is located at a preset position of the fourth PN junction 11 'formed between the third N-type layer 2' and the fourth P-type layer 3 ', the preset position including a first preset depth h located on an interface of the fourth PN junction 11' or in the third N-type layer 2₁At or in the fourth P-type layer 3' to a second predetermined depth h₂In the semiconductor device structure with NPNP structure, the light emitting layer 5 is located at the predetermined position of the first PN junction 11, the current conduction is completed by means of the composite current generated in the reverse bias depletion region between the third N-type layer 2 'and the fourth P-type layer 3' by the PNPN structure, and the current is conducted in the form of the composite current, so as to obtain higher light emitting efficiency.

The first light emitting layer 5 'may also be located on an interface of a fifth PN junction 22' formed between the third N-type layer 2 'and the third P-type layer 1', where the doping concentration of the light emitting layer 5 is located at a predetermined position of the second PN junction 22 in the semiconductor device structure of the NPNP structure; similarly, the first light emitting layer 5 'may also be located at the sixth PN junction 33' interface formed between the fourth N-type layer 4 'and the fourth P-type layer 3', and the doping concentration at this position refers to the predetermined position of the third PN junction 33 in the semiconductor device structure with NPNP structure described above for the light emitting layer 5. Specifically, the implementation principle of the semiconductor device structure based on the PNPN structure is similar to that of the semiconductor device structure of the NPNP structure, and is not described herein again.

Example two

On the basis of the first embodiment, please refer to fig. 6, where fig. 6 is a schematic structural diagram of another semiconductor device structure provided in the embodiment of the present invention, the another semiconductor device structure provided in the embodiment further includes a third electrode 8, specifically:

a substrate layer 100;

a first N-type layer 1 on the upper surface of the substrate layer 100;

the first P type layer 2 is positioned on the upper surface of the first N type layer 1;

the second N-type layer 3 is positioned on the upper surface of the first P-type layer 2;

the second P type layer 4 is positioned on the upper surface of the second N type layer 3;

the light emitting layer 5 is positioned at a preset position of a first PN junction 11 formed between the first P type layer 2 and the second N type layer 3;

the first electrode 6 is positioned on the upper surface of the second P type layer 4;

the second electrode 7 is positioned on the upper surface of the first N-type layer 1;

and a third electrode 8 positioned on the upper surface of the first P-type layer 2 to form a semiconductor device structure with a horizontal structure.

Specifically, in the first embodiment, the first electrode 6 and the second electrode 7 are respectively formed only on the first N-type layer 1 and the second P-type layer 4, no electrode is formed on the first P-type layer 2, and a semiconductor device structure with a horizontal structure and input at two ends is formed, whereas in the present embodiment, on the basis of the semiconductor device structure in the above-described embodiment, the third electrode 8 is led out from the upper surface of the first P-type layer 2, and the first electrode 6 formed on the upper surface of the first N-type layer 1 and the second electrode 7 formed on the upper surface of the second P-type layer 4 form a semiconductor device structure with a horizontal structure and input at three ends, and since the added third electrode 8 can be used as a control electrode, the semiconductor device structure is helped to be turned on at a lower turn-on voltage.

Further, referring to fig. 7a to 7c, fig. 8 and fig. 9, fig. 7a to 7c are schematic structural diagrams of a light emitting layer located at a first PN junction in another semiconductor device structure provided in an embodiment of the present invention, fig. 8 is a schematic structural diagram of a light emitting layer located at a second PN junction in another semiconductor device structure provided in an embodiment of the present invention, and fig. 9 is a schematic structural diagram of a light emitting layer located at a third PN junction in another semiconductor device structure provided in an embodiment of the present invention. It can be seen that, in the present embodiment, the semiconductor device structure of the third electrode 8 is added, and as in the first embodiment, the light emitting layer 5 of the quantum well structure may be inserted at a predetermined position located at the first PN junction 11 in the NPNP structure, and the light emitting layer 5 of the quantum well structure may be inserted at the interface located at the second PN junction 22 or the interface located at the third PN junction 33, and specific insertion positions, doping conditions, and the like are the same as those in the first embodiment, and are not described herein again.

Referring to fig. 10, fig. 10 is a schematic structural diagram of another semiconductor device structure based on a PNPN structure according to an embodiment of the present invention, in the semiconductor device structure based on a PNPN structure according to the present embodiment, a fourth electrode 6 ' is located on an upper surface of a fourth N-type layer 4 ', a fifth electrode 7 ' is located on an upper surface of a third P-type layer 1 ', and a sixth electrode 8 ' is further introduced on an upper surface of a third N-type layer 2 ' to form a semiconductor device structure with a horizontal structure and three-terminal input, in the same manner as in the first embodiment, a first light emitting layer 5 ' of a quantum well structure may be inserted at a preset position located at a fourth PN junction 11 ' in the PNPN structure, and a first light emitting layer 5 ' of the quantum well structure may be inserted at an interface of a fifth PN junction 22 ' or an interface of a sixth PN junction 33 ', and the specific insertion position, doping condition, etc. are the same as those of the semiconductor device structure based on a PNPN structure according to the first embodiment, and will not be described in detail herein.

The other semiconductor device structure provided in this embodiment may implement the embodiment of the semiconductor device structure in the first embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.

EXAMPLE III

On the basis of the second embodiment, please refer to fig. 11, fig. 11 is a schematic structural diagram of another semiconductor device structure according to an embodiment of the present invention, and the another semiconductor device structure according to the embodiment includes:

a substrate layer 100;

a first N-type layer 1 on the upper surface of the substrate layer 100;

the first P type layer 2 is positioned on the upper surface of the first N type layer 1;

the second N-type layer 3 is positioned on the upper surface of the first P-type layer 2;

the second P type layer 4 is positioned on the upper surface of the second N type layer 3;

the light emitting layer 5 is positioned at a preset position of a first PN junction 11 formed between the first P type layer 2 and the second N type layer 3;

the first electrode 6 is positioned on the upper surface of the second P type layer 4;

and a second electrode 7 positioned on the lower surface of the first N-type layer 1 to form a semiconductor device structure of a vertical structure.

Specifically, the first electrode 6 is located on the upper surface of the first N-type layer 1, the second electrode is located on the upper surface of the second P-type layer 4, and a semiconductor device structure with two input ends in a horizontal structure is formed in the first embodiment, but in the present embodiment, on the basis of the semiconductor device structure in the above-mentioned embodiment, the first electrode 6 is made on the lower surface of the first N-type layer 1, the second electrode 7 is made on the upper surface of the second P-type layer 4, and a semiconductor device structure with two input ends in a vertical structure is formed. In the first embodiment or the second embodiment, the light emitting layer 5 of the quantum well structure may be inserted at a predetermined position at the first PN junction 11, and the light emitting layer 5 of the quantum well structure may be inserted at the second PN junction 22 interface or the third PN junction 33 interface, where the specific insertion position, doping condition, and the like are the same as those in the first embodiment or the second embodiment, and refer to fig. 2a to 2c, fig. 3, and fig. 4, which are not described herein again.

Referring to fig. 12, fig. 12 is a schematic structural diagram of another semiconductor device structure based on a PNPN structure according to an embodiment of the present invention, in the semiconductor device structure based on the PNPN structure, a fourth electrode 6 ' is located on an upper surface of a fourth N-type layer 4 ', and a fifth electrode 7 ' is located on a lower surface of a third P-type layer 1 ', so as to form a semiconductor device structure with two input ends of a vertical structure, in the same embodiment, a first light emitting layer 5 ' of a quantum well structure may be inserted at a preset position located at a fourth PN junction 11 ' in the PNPN structure, and a first light emitting layer 5 ' of the quantum well structure may be inserted at an interface of a fifth PN junction 22 ' or an interface of a sixth PN junction 33 ', and specific insertion positions, doping conditions, and the like are the same as those of the semiconductor device structure based on the PNPN structure in the first embodiment, and are not repeated herein.

The semiconductor device structure provided in this embodiment may be implemented in the embodiments of the semiconductor device structure in the first embodiment and the embodiments of the semiconductor device structure in the second embodiment, which have similar implementation principles and technical effects, and are not described herein again.

Example four

On the basis of the third embodiment, please refer to fig. 13, and fig. 13 is a schematic structural diagram of another semiconductor device structure according to the third embodiment of the present invention. The structure of the semiconductor device proposed in this embodiment further includes a third electrode 8, specifically:

a substrate layer 100;

a first N-type layer 1 on the upper surface of the substrate layer 100;

the first P type layer 2 is positioned on the upper surface of the first N type layer 1;

the second N-type layer 3 is positioned on the upper surface of the first P-type layer 2;

the second P type layer 4 is positioned on the upper surface of the second N type layer 3;

the light emitting layer 5 is positioned at a preset position of a first PN junction 11 formed between the first P type layer 2 and the second N type layer 3;

the first electrode 6 is positioned on the upper surface of the second P type layer 4;

the second electrode 7 is positioned on the lower surface of the first N-type layer 1;

and a third electrode 8 positioned on the upper surface of the first P-type layer 2 to form a vertical semiconductor device structure.

Specifically, in the third embodiment, the first electrode 6 and the second electrode 7 are respectively formed only on the first N-type layer 1 and the second P-type layer 4, no electrode is formed on the first P-type layer 2, and a semiconductor device structure with a vertical structure input at two ends is formed, but in this embodiment, on the basis of the semiconductor device structure of the third embodiment, the third electrode 8 is led out from the upper surface of the first P-type layer 2, the first electrode 6 is formed on the lower surface of the first N-type layer 1, and the second electrode 7 is formed on the upper surface of the second P-type layer 4, so that the semiconductor device structure with a vertical structure input at three ends is formed, and since the added third electrode 8 can be used as a control electrode, the semiconductor device structure can be turned on at a lower turn-on voltage. In the same manner as in the first embodiment or the second embodiment or the third embodiment, the light emitting layer 5 of the quantum well structure may be inserted into the predetermined position at the first PN junction 11, and the light emitting layer 5 of the quantum well structure may be inserted into the predetermined position at the second PN junction 22 interface or the third PN junction 33 interface, where the specific insertion position, doping condition, and the like are the same as those in the first embodiment or the second embodiment or the third embodiment, and specifically refer to fig. 7a to 7c, fig. 8, and fig. 9, which are not described again here.

Referring to fig. 14, fig. 14 is a schematic structural diagram of another structure of a semiconductor device based on a PNPN structure according to an embodiment of the present invention, wherein in the structure of the semiconductor device based on the PNPN structure, the fourth electrode 6 'is positioned on the upper surface of the fourth N-type layer 4', the fifth electrode 7 'is positioned on the lower surface of the third P-type layer 1', and the sixth electrode 8 'is positioned on the upper surface of the third N-type layer 2', in the case of a three-terminal-input semiconductor device structure forming a vertical structure, the first light emitting layer 5 'of the quantum well structure may be inserted at a predetermined position at the fourth PN junction 11' in the PNPN structure as in the first embodiment, and inserting the first light emitting layer 5 ' of the quantum well structure at the interface of the fifth PN junction 22 ' or the interface of the sixth PN junction 33 ', the specific insertion position, doping condition, and the like are the same as those in the first embodiment or the second embodiment or the third embodiment, and details are not repeated here.

It should be noted that the semiconductor device structure provided by the present application is not only applicable to visible light semiconductor light emitting devices, but also particularly applicable to ultraviolet light, deep ultraviolet light, efficient green light, gallium nitride-based red light and other semiconductor light emitting devices.

It should be further noted that the semiconductor device structure proposed in the present application is also suitable for manufacturing a thyristor, which is a four-layer semiconductor structure from bottom to top of NPNP (see fig. 1), and has three poles: the thyristor is required to be applied with forward voltage when working, and the gate pole is provided with trigger current. The thyristor has the characteristics of a silicon rectifier device, can work under the conditions of high voltage and large current, can control the working process, and is widely applied to electronic circuits such as controllable rectification, alternating current voltage regulation, contactless electronic switches, inversion, frequency conversion and the like. However, the conventional thyristor has no electro-optical conversion capability, and the current flows through the whole device in the form of electron-hole recombination heating at the first PN junction formed between the first P-type layer and the second N-type layer, so that the thyristor has a large amount of heat generation, and a large amount of cooling devices are needed to ensure that the operating temperature of the thyristor is maintained within a certain range.

The semiconductor device structure provided in this embodiment may be implemented in the embodiment of the semiconductor device structure in the first embodiment, the embodiment of the semiconductor device structure in the second embodiment, and the embodiment of the semiconductor device structure in the third embodiment, which have similar implementation principles and technical effects, and are not described herein again.

It should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the specification, reference to the description of the term "one embodiment", "some embodiments", "an example", "a specific example", or "some examples", etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.