阅读说明：本技术 深紫外led芯片及其制造方法 (Deep ultraviolet LED chip and manufacturing method thereof ) 是由 范伟宏 毕京锋 郭茂峰 李士涛 马新刚 赵进超 于 2021-06-11 设计创作，主要内容包括：本申请公开了一种深紫外LED芯片及其制造方法,该深紫外LED芯片包括：外延结构,具有相对的第一表面和第二表面,外延结构包括P型半导体层、N型半导体层以及P型半导体层与N型半导体层所夹的多量子阱层,P型半导体层暴露于外延结构的第一表面；以及P型半导体层的空穴补偿层,位于外延结构的第一表面。该深紫外LED芯片利用P型半导体层的空穴补偿层保证了P型半导体层获得较高的空穴浓度的同时,减少了深紫外LED芯片内部结构对深紫外光的吸收。(The application discloses deep ultraviolet LED chip and manufacturing method thereof, the deep ultraviolet LED chip includes: the epitaxial structure is provided with a first surface and a second surface which are opposite, the epitaxial structure comprises a P-type semiconductor layer, an N-type semiconductor layer and a multi-quantum well layer sandwiched by the P-type semiconductor layer and the N-type semiconductor layer, and the P-type semiconductor layer is exposed on the first surface of the epitaxial structure; and the hole compensation layer of the P-type semiconductor layer is positioned on the first surface of the epitaxial structure. The deep ultraviolet LED chip utilizes the hole compensation layer of the P-type semiconductor layer to ensure that the P-type semiconductor layer obtains higher hole concentration, and simultaneously reduces the absorption of the internal structure of the deep ultraviolet LED chip to deep ultraviolet light.)

1. A deep ultraviolet LED chip, comprising:

an epitaxial structure having first and second opposing surfaces, the epitaxial structure including a P-type semiconductor layer, an N-type semiconductor layer, and a multi-quantum well layer sandwiched by the P-type semiconductor layer and the N-type semiconductor layer, the P-type semiconductor layer exposed at the first surface of the epitaxial structure; and

and the hole compensation layer of the P-type semiconductor layer is positioned on the first surface of the epitaxial structure.

2. The deep ultraviolet LED chip of claim 1, wherein the material of the P-type semiconductor layer is one of P-type doped AlGaN and BAlN.

3. The deep ultraviolet LED chip of claim 1, wherein the hole compensation layers of the P-type semiconductor layer are spaced apart.

4. The deep ultraviolet LED chip of claim 1, wherein the hole compensation layer of the P-type semiconductor layer comprises a plurality of spaced apart P-type silicon nanolayers.

5. The deep ultraviolet LED chip of claim 4, wherein each of the silicon nanolayers is comprised of silicon nanoparticles having a size between tens and hundreds of nanometers.

6. The deep ultraviolet LED chip of claim 4, wherein the plurality of silicon nanolayers are distributed in a uniform array or in a non-uniform array.

7. The deep ultraviolet LED chip of claim 4, further comprising a metal layer covering the P-type semiconductor layer and the plurality of silicon nanolayers,

and ohmic contact is formed between the metal layer and the P-type semiconductor layer.

8. The deep ultraviolet LED chip of claim 7, wherein the metal layer is comprised of metal nanowires.

9. The deep ultraviolet LED chip of claim 8, wherein the metal nanowires comprise Cu nanowires and a cladding layer wrapping the Cu nanowires,

wherein the material of the cladding layer comprises high work function metal Ni or Pt.

10. The deep ultraviolet LED chip of claim 7, further comprising a mirror layer covering the metal layer.

11. The deep ultraviolet LED chip of claim 10, wherein the reflector layer comprises: one of an Al mirror, an Rh mirror and an Mg mirror.

12. The deep ultraviolet LED chip of claim 10, further comprising a metal barrier layer covering the reflector layer.

13. The deep ultraviolet LED chip of claim 12, wherein the material of the metallic barrier layer comprises TiW or TiPt or TiNi.

14. The deep ultraviolet LED chip of claim 12, further comprising:

a substrate in contact with a second surface of the epitaxial structure;

at least one through hole extending from the metal barrier layer to the N-type semiconductor layer and exposing the N-type semiconductor layer;

at least one conductive part located in the corresponding through hole and contacting the exposed N-type semiconductor layer, wherein each conductive part is respectively separated from the P-type semiconductor layer, the multiple quantum well layer, the hole compensation layer of the P-type semiconductor layer, the metal layer, the reflector layer and the metal barrier layer;

the insulating layer is positioned on the metal barrier layer and filled in each through hole, and the insulating layer is provided with an N conductive channel exposing the surface of the conductive part and a P conductive channel exposing the surface of the metal barrier layer;

the N electrode is positioned on the insulating layer, and part of the N electrode penetrates through the N conductive channel to be connected with the conductive part; and

the P electrode is positioned on the insulating layer, part of the P electrode penetrates through the P conductive channel to be connected with the metal barrier layer,

wherein the N electrode is separated from the P electrode.

15. The deep ultraviolet LED chip of claim 14, further comprising at least one recess at an edge of the substrate extending from the metal barrier layer to the N-type semiconductor layer, the insulating layer further covering sidewalls of the recess and the N-type semiconductor layer.

16. The deep ultraviolet LED chip of claim 15, wherein the epitaxial structure further comprises a buffer layer, an AlN/AlGaN superlattice layer on the substrate,

wherein the buffer layer, the AlN/AlGaN superlattice layer, the N-type semiconductor layer, the MQW layer, and the P-type semiconductor layer are sequentially stacked in a direction from the second surface of the epitaxial structure toward the first surface.

17. The deep ultraviolet LED chip of claim 12, further comprising:

at least one through hole extending from the metal barrier layer to the N-type semiconductor layer and exposing the N-type semiconductor layer;

at least one conductive part located in the corresponding through hole and contacting the N-type semiconductor layer, wherein each conductive part is respectively separated from the P-type semiconductor layer, the multi-quantum well layer, the hole compensation layer of the P-type semiconductor layer, the metal layer, the reflector layer and the metal barrier layer;

the insulating layer covers the metal barrier layer and is filled in each through hole, and the insulating layer is provided with an N conductive channel exposing the surface of the conductive part;

the first bonding layer covers the insulating layer and penetrates through the N conductive channel to be connected with the conductive part;

the second bonding layer is positioned on the substrate and connected with the first bonding layer, and the substrate is used as an N electrode;

at least one groove is positioned at the edge of the substrate and extends from the second surface of the epitaxial structure to the metal barrier layer; and

and the P electrode is positioned in the groove and is connected with the metal barrier layer.

18. The deep ultraviolet LED chip of claim 17, wherein the epitaxial structure further comprises an AlN layer, an AlN/AlGaN superlattice layer,

wherein the AlN layer, the AlN/AlGaN superlattice layer, the N-type semiconductor layer, the MQW layer, and the P-type semiconductor layer are sequentially stacked in a direction from the second surface of the epitaxial structure toward the first surface.

19. The deep ultraviolet LED chip of claim 18, further comprising a passivation layer covering the second surface of the epitaxial structure and sidewalls of the recess.

20. The deep ultraviolet LED chip of claim 19, wherein the second surface of the epitaxial structure and the sidewalls of the recess are roughened surfaces.

21. The deep ultraviolet LED chip of claim 12, further comprising:

the first bonding layer is connected with the metal barrier layer;

the second bonding layer is respectively connected with a substrate and the first bonding layer, and the substrate is used as a P electrode;

a passivation layer covering the second surface of the epitaxial structure, the N-type semiconductor layer being exposed to the second surface of the epitaxial structure; and

and the N electrode penetrates through the passivation layer and is connected with the N-type semiconductor layer.

22. The deep ultraviolet LED chip of claim 21, further comprising a recess at an edge of the substrate extending from the second surface of the epitaxial structure onto the metallic barrier layer,

wherein the passivation layer also covers the sidewalls of the recess and extends over the metal barrier layer.

23. A manufacturing method of a deep ultraviolet LED chip comprises the following steps:

forming an epitaxial structure on a first substrate, wherein the epitaxial structure is provided with a first surface and a second surface which are opposite, the second surface is connected with the first substrate, the epitaxial structure comprises a P-type semiconductor layer, an N-type semiconductor layer and a multi-quantum well layer sandwiched by the P-type semiconductor layer and the N-type semiconductor layer, and the P-type semiconductor layer is exposed on the first surface of the epitaxial structure; and

and forming a hole compensation layer of the P-type semiconductor layer, wherein the hole compensation layer of the P-type semiconductor layer is positioned on the first surface of the epitaxial structure.

24. The method of manufacturing of claim 23, wherein the material of the P-type semiconductor layer is one of P-type doped AlGaN or BAlN material.

25. The manufacturing method according to claim 23, wherein the step of forming a hole compensation layer of the P-type semiconductor layer comprises:

forming a mask of a porous structure on the P-type semiconductor layer;

forming a P-type silicon nano layer in each hole of the mask by adopting a sputtering method; and

the mask is removed.

26. The method of claim 25, wherein the mask has apertures with a feature size in the range of 50-200 microns.

27. The manufacturing method according to claim 25, wherein the silicon nanolayer in each pore is composed of silicon nanoparticles having a size of between several tens nanometers and several hundreds nanometers.

28. The method of manufacturing of claim 25, wherein the plurality of apertures in the mask are one of uniformly distributed in an array, non-uniformly distributed in an array.

29. The manufacturing method according to claim 25, wherein the process of forming the porous structure mask comprises: step projection lithography, nanoimprint masks, or high temperature annealing of metals to form random nanoarray masks.

30. The manufacturing method of claim 25, further comprising forming a metal layer covering the P-type semiconductor layer and the plurality of silicon nanolayers,

and ohmic contact is formed between the metal layer and the P-type semiconductor layer.

31. The manufacturing method of claim 30, wherein the step of forming the metal layer comprises:

coating the Cu nanowire wrapped by the wrapping layer on the P-type semiconductor layer by adopting a spin coating process so as to cover the P-type semiconductor layer and the silicon nano layers; and

adopting an annealing process to form ohmic contact between the metal layer and the P-type semiconductor layer,

wherein the material of the cladding layer comprises high work function metal Ni or Pt.

32. The method of manufacturing of claim 31, further comprising forming a mirror layer overlying the metal layer.

33. The manufacturing method of claim 32, wherein the mirror layer comprises: one of an Al mirror, an Rh mirror and an Mg mirror.

34. The method of manufacturing of claim 32, further comprising forming a metallic barrier layer overlying the mirror layer.

35. The method of manufacturing of claim 34, wherein the material of the metallic barrier layer comprises TiW or TiPt or TiNi.

36. The method of manufacturing of claim 34, wherein prior to forming the metal layer, further comprising:

forming at least one via in the epitaxial structure, each via extending from a first surface of the epitaxial structure onto the N-type semiconductor layer; and

forming a conductive portion in each of the through holes, each of the conductive portions being in contact with the exposed N-type semiconductor layer,

wherein, after forming the metal barrier layer, the opening of each via extends to the metal barrier layer,

each of the conductive portions is spaced apart from the P-type semiconductor layer, the multiple quantum well layer, the hole compensation layer of the P-type semiconductor layer, the metal layer, the mirror layer, and the metal barrier layer.

37. The method of manufacturing of claim 36, wherein after forming the metallic barrier layer, the opening of each via extends to the metallic barrier layer, the method further comprising:

and forming an insulating layer on the metal barrier layer, wherein part of the insulating layer is filled in each through hole and covers the conductive part.

38. The method of manufacturing of claim 37, further comprising:

forming a P conductive via and an N conductive via through the insulating layer, the P conductive via exposing a portion of the metal barrier layer, the N conductive via exposing the conductive portion; and

forming a P electrode and an N electrode on the insulating layer, wherein the P electrode is connected with the metal barrier layer through the P conductive channel, the N electrode is connected with the conductive part through the N conductive channel,

wherein the N electrode is separated from the P electrode.

39. The manufacturing method according to claim 38, further comprising forming a groove at an edge of the epitaxial structure, a bottom surface of the groove being the N-type semiconductor layer,

the through hole and the groove are formed in the same etching step.

40. The method of manufacturing of claim 39, wherein the epitaxial structure further comprises a buffer layer, an AlN/AlGaN superlattice layer on the first substrate,

wherein the buffer layer, the AlN/AlGaN superlattice layer, the N-type semiconductor layer, the MQW layer, and the P-type semiconductor layer are sequentially stacked in a direction from the second surface of the epitaxial structure toward the first surface.

41. The method of manufacturing of claim 37, further comprising:

forming an N conductive via through the insulating layer, the N conductive via exposing the conductive portion; and

and forming a first bonding layer on the insulating layer, wherein part of the first bonding layer is filled in the N conductive channel and is connected with the conductive part.

42. The manufacturing method according to claim 41, further comprising:

forming a second bonding layer on a second substrate; and

bonding the first bonding layer with the second bonding layer,

wherein the second substrate is used as an N electrode.

43. The method of manufacturing of claim 42, wherein the epitaxial structure further comprises: a buffer layer, an AlN layer, and an AlN/AlGaN superlattice layer, the buffer layer being located on the first substrate, the buffer layer, the AlN layer, and the AlN/AlGaN superlattice layer being stacked in this order along a direction from the second surface of the epitaxial structure toward the first surface,

the manufacturing method further includes:

removing the first substrate and the buffer layer;

etching the residual epitaxial structure, the hole compensation layer of the P-type semiconductor layer, the metal layer and the reflector layer to form a groove exposing part of the metal barrier layer, wherein the groove is positioned on the edge of the second substrate; and

and forming a P electrode connected with the metal barrier layer in the groove.

44. The method of manufacturing of claim 43, further comprising roughening exposed surfaces of the epitaxial structure, the hole compensation layer of the P-type semiconductor layer, the metal layer, and the mirror layer prior to forming the P-electrode.

45. The method of manufacturing of claim 43, further comprising forming a passivation layer covering a surface and sidewalls of the epitaxial structure, the hole compensation layer of the P-type semiconductor layer, the metal layer, and sidewalls of the mirror layer.

46. The method of manufacturing of claim 34, the epitaxial structure further comprising a lattice matching stack between the first substrate and the N-type semiconductor layer, the method of manufacturing further comprising:

forming a first bonding layer on the metal barrier layer;

forming a second bonding layer on a second substrate, wherein the second substrate is used as a P electrode;

bonding the first bonding layer with the second bonding layer;

removing the first substrate and the lattice matching stack; and

and forming an N electrode on the N-type semiconductor layer.

47. The manufacturing method according to claim 46, further comprising, before forming the N electrode:

etching the N-type semiconductor layer, the multiple quantum well layer, the P-type semiconductor layer, the hole compensation layer of the P-type semiconductor layer, the metal layer and the reflector layer to form a groove, wherein the groove is positioned on the edge of the second substrate, and the bottom surface of the groove is the metal barrier layer; and

forming a passivation layer on the surface of the N-type semiconductor layer and the side wall and the bottom surface of the groove,

wherein the N electrode passes through the passivation layer.

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a deep ultraviolet LED chip and a manufacturing method thereof.

Background

In a deep-ultraviolet LED (Light-Emitting Diode), in order to obtain a good ohmic contact effect and a higher hole concentration for a P-type semiconductor layer, a P-GaN layer needs to be grown on the P-type semiconductor layer, however, the P-GaN layer absorbs a large amount of deep ultraviolet Light, and the Light emission amount of the deep-ultraviolet LED chip is seriously affected. Although the absorption of deep ultraviolet light can be reduced by thinning the p-GaN layer, the hole concentration is also significantly reduced.

Therefore, there is a need for an improved deep ultraviolet LED chip and a manufacturing method thereof, and it is desirable to reduce absorption of deep ultraviolet light by an internal structure of the deep ultraviolet LED chip while ensuring that a P-type semiconductor layer obtains a higher hole concentration.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a deep ultraviolet LED chip and a manufacturing method thereof, wherein a hole compensation layer of a P-type semiconductor layer is used to ensure that the P-type semiconductor layer obtains a higher hole concentration, and at the same time, the absorption of the internal structure of the deep ultraviolet LED chip to deep ultraviolet light is reduced.

According to an aspect of an embodiment of the present invention, there is provided a deep ultraviolet LED chip including:

an epitaxial structure having first and second opposing surfaces, the epitaxial structure including a P-type semiconductor layer, an N-type semiconductor layer, and a multi-quantum well layer sandwiched by the P-type semiconductor layer and the N-type semiconductor layer, the P-type semiconductor layer exposed at the first surface of the epitaxial structure; and the hole compensation layer of the P-type semiconductor layer is positioned on the first surface of the epitaxial structure.

Optionally, the material of the P-type semiconductor layer is one of P-type doped AlGaN and BAlN.

Optionally, the hole compensation layers of the P-type semiconductor layer are arranged at intervals.

Optionally, the hole compensation layer of the P-type semiconductor layer includes a plurality of P-type silicon nanolayers arranged at intervals.

Optionally, each of the silicon nanolayers is composed of silicon nanoparticles having a size between tens of nanometers and hundreds of nanometers.

Optionally, the plurality of silicon nanolayers are distributed in a uniform array or in a non-uniform array.

Optionally, the semiconductor device further comprises a metal layer covering the P-type semiconductor layer and the plurality of silicon nano layers, wherein ohmic contact is formed between the metal layer and the P-type semiconductor layer.

Optionally, the metal layer is composed of metal nanowires.

Optionally, the metal nanowire comprises a Cu nanowire and a cladding layer wrapping the Cu nanowire, wherein a material of the cladding layer comprises high work function metal Ni or Pt.

Optionally, the metal layer further comprises a mirror layer, and the mirror layer covers the metal layer.

Optionally, the mirror layer comprises: one of an Al mirror, an Rh mirror and an Mg mirror.

Optionally, the reflective mirror further comprises a metal barrier layer covering the reflective mirror layer.

Optionally, the material of the metal barrier layer comprises TiW or TiPt or TiNi.

Optionally, the method further comprises: a substrate in contact with a second surface of the epitaxial structure; at least one through hole extending from the metal barrier layer to the N-type semiconductor layer and exposing the N-type semiconductor layer; at least one conductive part located in the corresponding through hole and contacting the exposed N-type semiconductor layer, wherein each conductive part is respectively separated from the P-type semiconductor layer, the multiple quantum well layer, the hole compensation layer of the P-type semiconductor layer, the metal layer, the reflector layer and the metal barrier layer; the insulating layer is positioned on the metal barrier layer and filled in each through hole, and the insulating layer is provided with an N conductive channel exposing the surface of the conductive part and a P conductive channel exposing the surface of the metal barrier layer; the N electrode is positioned on the insulating layer, and part of the N electrode penetrates through the N conductive channel to be connected with the conductive part; and the P electrode is positioned on the insulating layer, part of the P electrode penetrates through the P conductive channel to be connected with the metal barrier layer, and the N electrode is separated from the P electrode.

Optionally, the semiconductor device further includes at least one groove located at an edge of the substrate and extending from the metal barrier layer to the N-type semiconductor layer, and the insulating layer further covers a sidewall of the groove and the N-type semiconductor layer.

Optionally, the epitaxial structure further comprises a buffer layer, an AlN/AlGaN superlattice layer on the substrate, wherein the buffer layer, the AlN/AlGaN superlattice layer, the N-type semiconductor layer, the multiple quantum well layer, and the P-type semiconductor layer are sequentially stacked in a direction from the second surface to the first surface of the epitaxial structure.

Optionally, the method further comprises: at least one through hole extending from the metal barrier layer to the N-type semiconductor layer and exposing the N-type semiconductor layer; at least one conductive part located in the corresponding through hole and contacting the N-type semiconductor layer, wherein each conductive part is respectively separated from the P-type semiconductor layer, the multi-quantum well layer, the hole compensation layer of the P-type semiconductor layer, the metal layer, the reflector layer and the metal barrier layer; the insulating layer covers the metal barrier layer and is filled in each through hole, and the insulating layer is provided with an N conductive channel exposing the surface of the conductive part; the first bonding layer covers the insulating layer and penetrates through the N conductive channel to be connected with the conductive part; the second bonding layer is positioned on the substrate and connected with the first bonding layer, and the substrate is used as an N electrode; at least one groove is positioned at the edge of the substrate and extends from the second surface of the epitaxial structure to the metal barrier layer; and the P electrode is positioned in the groove and is connected with the metal barrier layer.

Optionally, the epitaxial structure further comprises an AlN layer, an AlN/AlGaN superlattice layer, wherein the AlN layer, the AlN/AlGaN superlattice layer, the N-type semiconductor layer, the multiple quantum well layer, and the P-type semiconductor layer are sequentially stacked in a direction from the second surface to the first surface of the epitaxial structure.

Optionally, the epitaxial structure further comprises a passivation layer covering the second surface of the epitaxial structure and the sidewall of the groove.

Optionally, the second surface of the epitaxial structure and the sidewall of the groove are roughened surfaces.

Optionally, the method further comprises: the first bonding layer is connected with the metal barrier layer; the second bonding layer is respectively connected with a substrate and the first bonding layer, and the substrate is used as a P electrode; a passivation layer covering the second surface of the epitaxial structure, the N-type semiconductor layer being exposed to the second surface of the epitaxial structure; and an N electrode connected to the N-type semiconductor layer through the passivation layer.

Optionally, the epitaxial structure further includes a groove located at an edge of the substrate and extending from the second surface of the epitaxial structure to the metal barrier layer, wherein the passivation layer further covers a sidewall of the groove and extends to cover the metal barrier layer.

According to another aspect of the embodiments of the present invention, there is provided a method for manufacturing a deep ultraviolet LED chip, including: forming an epitaxial structure on a first substrate, wherein the epitaxial structure is provided with a first surface and a second surface which are opposite, the second surface is connected with the first substrate, the epitaxial structure comprises a P-type semiconductor layer, an N-type semiconductor layer and a multi-quantum well layer sandwiched by the P-type semiconductor layer and the N-type semiconductor layer, and the P-type semiconductor layer is exposed on the first surface of the epitaxial structure; and forming a hole compensation layer of the P-type semiconductor layer, wherein the hole compensation layer of the P-type semiconductor layer is positioned on the first surface of the epitaxial structure.

Optionally, the material of the P-type semiconductor layer is one of P-type doped AlGaN or BAlN material.

Optionally, the step of forming the hole compensation layer of the P-type semiconductor layer includes: forming a mask of a porous structure on the P-type semiconductor layer; forming a P-type silicon nano layer in each hole of the mask by adopting a sputtering method; and removing the mask.

Optionally, the characteristic size of the holes of the mask ranges from 50 to 200 microns.

Optionally, the silicon nanolayer within each pore is composed of silicon nanoparticles having a size between tens of nanometers and hundreds of nanometers.

Optionally, the plurality of apertures in the mask are one of uniformly distributed in an array, non-uniformly distributed in an array.

Optionally, the process of forming the porous structure mask comprises: step projection lithography, nanoimprint masks, or high temperature annealing of metals to form random nanoarray masks.

Optionally, the method further comprises forming a metal layer covering the P-type semiconductor layer and the plurality of silicon nano-layers, wherein the metal layer is in ohmic contact with the P-type semiconductor layer.

Optionally, the step of forming the metal layer includes: coating the Cu nanowire wrapped by the wrapping layer on the P-type semiconductor layer by adopting a spin coating process so as to cover the P-type semiconductor layer and the silicon nano layers; and forming ohmic contact between the metal layer and the P-type semiconductor layer by adopting an annealing process, wherein the material of the cladding layer comprises metal Ni or Pt with high work function.

Optionally, forming a mirror layer covering the metal layer is further included.

Optionally, the mirror layer comprises: one of an Al mirror, an Rh mirror and an Mg mirror.

Optionally, forming a metal barrier layer overlying the mirror layer is also included.

Optionally, the material of the metal barrier layer comprises TiW or TiPt or TiNi.

Optionally, before forming the metal layer, the method further includes: forming at least one via in the epitaxial structure, each via extending from a first surface of the epitaxial structure onto the N-type semiconductor layer; and forming a conductive part in each of the through holes, each of the conductive parts being in contact with the exposed N-type semiconductor layer, wherein, after the metal barrier layer is formed, an opening of each of the through holes extends to the metal barrier layer, and each of the conductive parts is spaced apart from the P-type semiconductor layer, the multiple quantum well layer, the hole compensation layer of the P-type semiconductor layer, the metal layer, the mirror layer, and the metal barrier layer.

Optionally, after forming the metal barrier layer, the opening of each via extends to the metal barrier layer, and the manufacturing method further includes: and forming an insulating layer on the metal barrier layer, wherein part of the insulating layer is filled in each through hole and covers the conductive part.

Optionally, the method further comprises: forming a P conductive via and an N conductive via through the insulating layer, the P conductive via exposing a portion of the metal barrier layer, the N conductive via exposing the conductive portion; and forming a P electrode and an N electrode on the insulating layer, wherein the P electrode is connected with the metal barrier layer through the P conductive channel, the N electrode is connected with the conductive part through the N conductive channel, and the N electrode is separated from the P electrode.

Optionally, the method further includes forming a groove at an edge of the epitaxial structure, a bottom surface of the groove is the N-type semiconductor layer, and the through hole and the groove are formed in the same etching step.

Optionally, the epitaxial structure further comprises a buffer layer, an AlN layer, and an AlN/AlGaN superlattice layer on the first substrate, wherein the buffer layer, the AlN/AlGaN superlattice layer, the N-type semiconductor layer, the multiple quantum well layer, and the P-type semiconductor layer are sequentially stacked in a direction from the second surface of the epitaxial structure toward the first surface.

Optionally, the method further comprises: forming an N conductive via through the insulating layer, the N conductive via exposing the conductive portion; and forming a first bonding layer on the insulating layer, wherein part of the first bonding layer is filled in the N conductive channel and is connected with the conductive part.

Optionally, the method further comprises: forming a second bonding layer on a second substrate; and bonding the first bonding layer and the second bonding layer, wherein the second substrate is used as an N electrode.

Optionally, the epitaxial structure further includes: the manufacturing method comprises a buffer layer, an AlN layer and an AlN/AlGaN superlattice layer, wherein the buffer layer is positioned on the first substrate, and the buffer layer, the AlN layer and the AlN/AlGaN superlattice layer are sequentially stacked along the direction from the second surface to the first surface of the epitaxial structure, and the manufacturing method further comprises the following steps: removing the first substrate and the buffer layer; etching the residual epitaxial structure, the hole compensation layer of the P-type semiconductor layer, the metal layer and the reflector layer to form a groove exposing part of the metal barrier layer, wherein the groove is positioned on the edge of the second substrate; and forming a P electrode connected with the metal barrier layer in the groove.

Optionally, before forming the P electrode, roughening exposed surfaces of the epitaxial structure, the hole compensation layer of the P-type semiconductor layer, the metal layer, and the mirror layer is further included.

Optionally, the method further comprises forming a passivation layer covering the surface and the side wall of the epitaxial structure, the hole compensation layer of the P-type semiconductor layer, the metal layer and the side wall of the mirror layer.

Optionally, the epitaxial structure further comprises a lattice matching stack between the first substrate and the N-type semiconductor layer, and the manufacturing method further comprises: forming a first bonding layer on the metal barrier layer; forming a second bonding layer on a second substrate, wherein the second substrate is used as a P electrode; bonding the first bonding layer with the second bonding layer; removing the first substrate and the lattice matching stack; and forming an N electrode on the N-type semiconductor layer.

Optionally, before forming the N electrode, the manufacturing method further includes: etching the N-type semiconductor layer, the multiple quantum well layer, the P-type semiconductor layer, the hole compensation layer of the P-type semiconductor layer, the metal layer and the reflector layer to form a groove, wherein the groove is positioned on the edge of the second substrate, and the bottom surface of the groove is the metal barrier layer; and forming a passivation layer on the surface of the N-type semiconductor layer and the side wall and the bottom surface of the groove, wherein the N electrode penetrates through the passivation layer.

According to the deep ultraviolet LED chip and the manufacturing method thereof provided by the embodiment of the invention, the P-type semiconductor layer is subjected to hole compensation by replacing a P-GaN layer with a plurality of P-type silicon nano layers arranged at intervals in the hole compensation layer of the P-type semiconductor layer, so that the internal quantum efficiency of the deep ultraviolet LED chip is improved; because the silicon nano particles of the silicon nano layer are provided with spaced gaps, the hole compensation layer of the P-type semiconductor layer is ensured to compensate the P-type semiconductor layer to obtain higher hole concentration, more holes and electrons are compounded in the quantum well layer, the internal quantum efficiency is improved, meanwhile, the deep ultraviolet light can also be emitted/incident through the gaps between the silicon nano particles, and the purpose of reducing the absorption of the deep ultraviolet light is realized.

The Cu nanowires are wrapped by the metal coating layer with the high work function, so that the contact barrier between the metal layer and the P-type semiconductor layer is reduced, the metal-semiconductor contact resistivity is improved, the effect of reducing the voltage of the deep ultraviolet LED chip is realized, and the electro-optic conversion efficiency of the deep ultraviolet LED chip is improved; and the metal nanowires in the metal layer have high transmittance, and deep ultraviolet light can efficiently transmit.

One of an Al mirror, an Rh mirror and an Mg mirror is used as a reflector layer of the deep ultraviolet light, and under the action of the reflector layer, the reflector layer is matched with a metal layer with high transmittance to enable the ultraviolet light to be reflected again, so that the whole light-emitting efficiency of the deep ultraviolet LED chip is increased. Meanwhile, the reflector layer is made of metal, so that the reflector layer can also realize the function of current expansion.

Through setting up through-hole and groove structure, increased the area of epitaxial structure lateral wall to the light extraction efficiency of horizontal direction has been increased.

Therefore, the deep ultraviolet LED chip provided by the embodiment of the invention ensures that the P-type semiconductor layer obtains higher hole concentration and better ohmic contact effect, reduces the absorption of the internal structure of the deep ultraviolet LED chip to the deep ultraviolet light, increases the internal quantum efficiency and the electro-optic conversion efficiency of the deep ultraviolet LED chip, and finally enhances the performance of the deep ultraviolet LED chip.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present application and are not limiting on the present application.

Fig. 1 to 8 are structural views showing a method of manufacturing a deep ultraviolet LED chip according to a first embodiment of the present invention at some stages.

Fig. 9 to 21 are structural views showing a method of manufacturing a deep ultraviolet LED chip according to a second embodiment of the present invention at some stages.

Fig. 22 to 28 are structural views showing a method of manufacturing a deep ultraviolet LED chip according to a third embodiment of the present invention at some stages.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expressions "directly on … …" or "on … … and adjacent thereto" will be used herein.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

In the related art, the quantum efficiency of the deep ultraviolet LED chip is low due to the following reasons: firstly, the epitaxial quality of the AlGaN material is not ideal enough, and the defect density is high, so that the internal quantum efficiency is low; secondly, a layer of P-GaN needs to be grown on the P-type semiconductor layer in order to obtain a better ohmic contact effect and hole concentration, and the P-GaN has serious absorption to deep ultraviolet light; thirdly, as the Al component in the quantum well is increased, the light emitting area of the deep ultraviolet LED chip is mainly in a TM mode (parallel to the light emitting surface), and the light emitting area in the horizontal direction is small, so that the TM light is difficult to enter an escape cone of the light emitting surface for emergence, the TM light extraction efficiency is low, and the improvement of the performance of the deep ultraviolet LED chip is seriously restricted by the problems.

In order to solve the problems of insufficient hole supply and severe absorption of deep ultraviolet light by p-GaN, various device structure design schemes are developed in the related technology at present, and the technical schemes comprise a p-AlGaN transparent contact layer, a dielectric regulation and control tunneling junction, an electric field memory, a superlattice electron blocking layer structure, a component gradual change electron blocking layer structure, a regulation and control interface polarization effect, different Al component quantum barriers and the like to reduce the strong absorption of a top layer material to the deep ultraviolet light and improve the hole activation energy and the hole injection efficiency. However, the above method has the following problems: firstly, the work function of the high-Al component P-type AlGaN material is higher, and metals with high work function such as Pt and Ni are needed to reduce the metal-semiconductor contact barrier, but the reflectivity of the metals to deep ultraviolet light is lower, the transmissivity is also lower, and a metal contact layer with high light transmission or high reflection cannot be obtained; secondly, adjusting the epitaxial structure to reduce the hole activation energy and improve the hole concentration requires strict simulation calculation and a large amount of verification to obtain a better result, but the complicated epitaxial design scheme inevitably brings more technical problems to be solved; thirdly, the high body resistance of the high Al component AlGaN material can cause the working voltage of the light emitting diode to be significantly increased, which is not favorable for obtaining ideal electro-optic conversion efficiency; finally, the complicated epitaxial layer design scheme also brings different degrees of influence on the polarization effect in the quantum well, unknown influence is caused on the recombination of electrons and holes, and the generated electron-hole wave function space separation inevitably causes the reduction of the quantum efficiency in the deep ultraviolet LED chip.

In order to solve the above problems, the present invention provides an improved deep ultraviolet LED chip and a method for manufacturing the same, in which a plurality of spaced silicon nanolayers are used to perform hole compensation on a P-type semiconductor layer, so that the deep ultraviolet light absorption by the internal structure of the deep ultraviolet LED chip is reduced while the P-type semiconductor layer is ensured to obtain a higher hole concentration. The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1 to 8 are structural views showing a method of manufacturing a deep ultraviolet LED chip according to a first embodiment of the present invention at some stages.

As shown in fig. 1, an epitaxial structure 110 is formed on a first substrate 101. The epitaxial structure 110 has a first surface 101a and a second surface 101b opposite to each other, and the second surface 101b is connected to the first substrate 101. The epitaxial structure 110 includes a P-type semiconductor layer 116, an N-type semiconductor layer 114, and a multi-quantum well layer 115 sandwiched by the P-type semiconductor layer 116 and the N-type semiconductor layer 114, wherein the P-type semiconductor layer 116 is exposed on the first surface 101a of the epitaxial structure 110.

In some preferred embodiments, to better match the lattice between the N-type semiconductor layer 114 and the first substrate 101, the epitaxial structure 110 further includes a lattice matching stack between the N-type semiconductor layer 114 and the first substrate 101. Specifically, the first substrate 101 is a sapphire substrate, and the epitaxial structure 110 includes a buffer layer 111, an AlN layer 112, an AlN/AlGaN superlattice layer 113, an N-type semiconductor layer 114, a multi-quantum well layer 115, and a P-type semiconductor layer 116 stacked in this order along the direction from the second surface 101b to the first surface 101a of the epitaxial structure, where the buffer layer 111 is made of AlN, the AlN layer 112 is thicker than the buffer layer 111, and the buffer layer 111, the AlN layer 112, and the AlN/AlGaN superlattice layer 113 are stacked as a lattice matching layer.

In the present embodiment, the thickness of the epitaxial structure 110 ranges from 5 to 10 μm, and the growth method of each layer in the epitaxial structure 110 may be metal chemical vapor deposition, laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy. The layers of epitaxial structure 110 may be polycrystalline or single crystal structures. The sapphire substrate includes but is not limited to one of a mirror or a micro/nano patterned sapphire substrate, which is preferably a mirror sapphire. The multiple quantum well layer 114 in the epitaxial structure 110 includes one or more reciprocating continuous progressive LED chip epitaxial structures formed by material systems such as AlGaN/AlInGaN, and the like, and the preferred scheme is an AlGaN structure containing different Al components.

In the present embodiment, the material of the P-type semiconductor layer 116 is P-type doped gallium aluminum nitride (AlGaN) or aluminum boron nitride (BAlN). The material of the N-type semiconductor layer 114 is N-type doped AlGaN.

One skilled in the art may also make other arrangements of the thickness of the epitaxial structure 110, and the materials of the layers, as desired. Of course, the first substrate 101 is not limited to a sapphire substrate, and may be a GaN substrate, an AlN substrate, or Ga₂O₃Any one of a substrate, a SiC substrate, a Si substrate, a ZnO single crystal substrate, and a high temperature resistant metal substrate with a pre-deposited AlN film.

Further, at least one via 102 and a recess 103 are formed in the epitaxial structure 110, as shown in fig. 2 a.

In this step, a plurality of through holes 102 uniformly distributed in an array and a groove 103 located at the edge of the first substrate 101 are simultaneously formed on the epitaxial structure 110, for example, by using photolithography and dry etching techniques. The plurality of through holes 102 and the grooves 103 extend from the first surface 101a of the epitaxial structure to the N-type semiconductor layer 114. The through holes 102 and the grooves 103 increase the area of the side wall, and are beneficial to extracting more deep ultraviolet light in the horizontal direction.

In some other embodiments, the sidewalls of the through hole 102 and the groove 103 may also be roughened as shown in fig. 2b, so as to further improve the extraction efficiency of the deep ultraviolet light in the horizontal direction.

The number of through holes 102 can be set as desired by those skilled in the art.

Further, conductive portions 120 are formed in the respective through holes 102, as shown in fig. 3.

In this step, conductive portions 120 connected to the N-type semiconductor layer 114 are formed in the through-holes 102, for example, using photolithography and physical vapor deposition techniques, and the conductive portions 120 are separated from the P-type semiconductor layer 116 and the multiple quantum well layer 115, respectively. The conductive portion 120 is then annealed to form a good ohmic contact between the conductive portion 120 and the N-type semiconductor layer 114.

In the present embodiment, the conductive portion 120 includes one or a combination of V, Ti, Cr, Al, Ni, Au, Pt metal layers along the direction from the second surface 101b to the first surface 101a of the epitaxial structure 110, and the total thickness of the conductive portion 120 is 500 nm. Annealing at N₂The annealing was carried out under an atmosphere with a process temperature of 900 c and the annealing process lasted for 1 minute.

Further, a hole compensation layer 130 of a P-type semiconductor layer is formed on the first surface 101a of the epitaxial structure, as shown in fig. 4.

In this step, for example, a porous mask is formed on the P-type semiconductor layer 116, each hole exposes a part of the P-type semiconductor layer 116, then a corresponding silicon nano-layer is formed in each hole of the mask by a sputtering method, each silicon nano-layer is in contact with the P-type semiconductor layer 116, each silicon nano-layer is P-type doped, then the porous mask and the silicon nano-layers on the mask are removed, and the hole compensation layer 130 of the formed P-type semiconductor layer is a plurality of silicon nano-layers arranged at intervals. Wherein the silicon nanolayer is composed of silicon nanoparticles, and the size of the silicon nanoparticles is between tens of nanometers and hundreds of nanometers.

In the embodiment, the characteristic size range of the holes of the mask is 50-200 microns, and the holes in the mask are distributed according to one of a uniform array distribution and a non-uniform array distribution. The uniform array distribution can ensure that the hole compensation effect of each region on the P-type semiconductor layer 116 is uniform; the use of an unevenly distributed array allows for the creation of a compensated difference in hole concentration in different areas.

The process of forming the porous structure mask includes: step projection lithography, nanoimprint masks, or metal high temperature annealing to form random nanoarray masks.

Further, a metal layer 140 covering the P-type semiconductor layer 116 and the hole compensation layer 130 of the P-type semiconductor layer is formed, as shown in fig. 5.

In this step, a Cu nanowire surrounded by a cladding layer is coated on the P-type semiconductor layer 116 to cover the P-type semiconductor layer 116 and the hole compensation layer 130 of the P-type semiconductor layer, for example, using a spin coating process, wherein a region of the via hole 102 corresponding to the groove 103 is protected and not covered by the metal layer 140, or in this step, openings of the via hole 102 and the groove 103 extend to the metal layer 140. Then, a high temperature annealing process is used to tightly bond the hole compensation layer 130 of the P-type semiconductor layer and the P-type semiconductor layer 116 and to form a good ohmic contact between the metal layer 140 and the P-type semiconductor layer 116. Wherein, the coating layer is made of metal with high work function, and the total diameter of the coating layer and the wrapped Cu nanowire is about 150 nanometers.

In the embodiment, when the material of the P-type semiconductor layer 116 is P-type doped AlGaN, the material of the cladding layer is Ni or Pt, where the work function of Ni is 5.04eV and the work function of Pt is 5.93eV, so as to reduce the contact barrier between the metal layer 140 and the P-type semiconductor layer 116, improve the metal-semiconductor contact resistivity, and reduce the deep ultraviolet LED chip voltage. Moreover, the metal layer 140 formed by the metal nanowires (with a duty ratio of 90%) has a high transmittance to deep ultraviolet light, which can reach 70% -90%, so that the deep ultraviolet light can efficiently penetrate through the metal layer 140.

However, other arrangements of the material of the metal layer 140 may be performed by those skilled in the art, as needed, for example, when the P-type semiconductor layer 116 is made of other transparent materials, the metal nanowires in the metal layer 140 and the cladding material wrapped thereon are also changed accordingly. Or, considering the material of the P-type semiconductor layer 116, the contact barrier, the light transmittance of the metal layer 140, the cost, and other factors, the metal layer 140 made of metal nanowires can be replaced by a common metal layer.

Further, a mirror layer 150 is formed to cover the metal layer 140, as shown in fig. 5.

In this step, a mirror layer 150 is formed on the metal layer 140, for example, by photolithography and physical vapor deposition, wherein the region of the through hole 102 corresponding to the groove 103 is protected and not covered by the mirror layer 150, or in this step, the openings of the through hole 102 and the groove 103 extend to the mirror layer 150.

In the present embodiment, the mirror layer 150 has a high reflectivity to deep ultraviolet light, and the thickness thereof is 200 nm. In some specific embodiments, the mirror layer 150 includes one of an Al mirror, an Rh mirror, and an Mg mirror. The thickness of the mirror layer 150 is 200 nm.

Further, a metal barrier layer 160 is formed to cover the mirror layer 150, as shown in fig. 5.

In this step, a metal barrier layer 160 is formed on the mirror layer 150, for example, by using photolithography and a physical vapor deposition process, wherein the region of the via hole 102 corresponding to the recess 103 is protected and not covered by the metal barrier layer 160, or in this step, the openings of the via hole 102 and the recess 103 extend to the metal barrier layer 160.

In the present embodiment, the metal barrier layer 160 is a metal material and has a thickness of 500 nm. In some embodiments, the material of the metal barrier layer 160 is TiW or TiPt or TiNi. The metal barrier layer 160 functions to prevent the mirror layer 150 from being oxidized and to prevent diffusion between metals.

Further, an insulating layer 104 is formed on the metal barrier layer 160, as shown in fig. 6.

In this step, an insulating layer 104 covering the semiconductor structure is formed, for example, by using an atomic layer deposition process, and a portion of the insulating layer 104 is located on the metal barrier layer 160 and partially filled in the via hole 102 and the groove 103, wherein the insulating layer 104 filled in the via hole 102 covers the conductive portion 120.

In the present embodiment, the insulating layer 104 is deposited to a thickness of 1000nm, the material comprising SiN_xA medium.

Further, P conductive vias 106 and N conductive vias 105 are formed through the insulating layer 104, as shown in fig. 7.

In this step, for example, photolithography and dry etching processes are used to form the P conductive channel 106 and the N conductive channel 105, wherein the P conductive channel 106 exposes a portion of the surface of the metal barrier layer 160, and the N conductive channel 105 exposes the surface of each conductive portion 120.

Further, P electrodes 172 and N electrodes 171 are formed on the insulating layer 104, respectively, as shown in fig. 8.

In the present embodiment, the P electrode 172 is connected to the metal barrier 160 through the P conductive channel 106, and the N electrode 171 is connected to each conductive portion 120 through the N conductive channel 105.

In some specific embodiments, the N-electrode 171 and the P-electrode 172 each include a Ti adhesion layer and a binary alloy layer of Au and Sn stacked in sequence along the direction from the second surface 102b to the first surface 102a of the epitaxial structure. Wherein, the thickness of the Ti adhesion layer is 200nm, and the thicknesses of the Au and Sn binary alloy layers are 600nm and 200nm respectively.

According to the manufacturing method of the first embodiment of the present invention, the formed deep ultraviolet LED chip is in an inverted through hole structure, and the detailed structure of the deep ultraviolet LED chip of the first embodiment is described with reference to fig. 1 to 8, which is not described herein again.

Fig. 9 to 21 are structural views showing a method of manufacturing a deep ultraviolet LED chip according to a second embodiment of the present invention at some stages.

As shown in fig. 9, an epitaxial structure 210 is formed on a first substrate 201. The epitaxial structure 210 has a first surface 201a and a second surface 201b opposite to each other, and the second surface 201b is in contact with the first substrate 201. The epitaxial structure 210 includes a P-type semiconductor layer 216, an N-type semiconductor layer 214, and a multi-quantum well layer 215 sandwiched by the P-type semiconductor layer 216 and the N-type semiconductor layer 214, wherein the P-type semiconductor layer 216 is exposed to the first surface 201a of the epitaxial structure 210.

In some preferred embodiments, to better match the lattice between the N-type semiconductor layer 214 and the first substrate 201, the epitaxial structure 210 further includes a lattice matching stack between the N-type semiconductor layer 214 and the first substrate 201. Specifically, the first substrate 201 is a sapphire substrate, and the epitaxial structure 210 includes a buffer layer 211, an AlN layer 212, an AlN/AlGaN superlattice layer 213, an N-type semiconductor layer 214, a multi-quantum well layer 215, and a P-type semiconductor layer 216, which are stacked in sequence along the second surface 201b of the epitaxial structure toward the first surface 201a, wherein the buffer layer 211 is made of AlN, the AlN layer 212 is thicker than the buffer layer 211, and the buffer layer 211, the AlN layer 212, and the AlN/AlGaN superlattice layer 213 serve as a lattice matching stack.

In the present embodiment, the thickness of the epitaxial structure 210 ranges from 5 microns to 10 microns, and the growth method of each layer in the epitaxial structure 210 may be metal chemical vapor deposition, laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy. The layers of the epitaxial structure 210 may be polycrystalline or single crystal structures. The sapphire substrate includes but is not limited to one of a mirror or a micro/nano patterned sapphire substrate, the preferred solution of which is nano patterned sapphire. The multiple quantum well layer 214 in the epitaxial structure 210 includes one or more reciprocating continuous progressive LED chip epitaxial structures formed by material systems such as AlGaN/AlInGaN, and the like, and the preferred scheme is an AlGaN structure containing different Al components.

In the present embodiment, the material of the P-type semiconductor layer 216 is P-type doped gallium aluminum nitride (AlGaN) or aluminum boron nitride (BAlN). The material of the N-type semiconductor layer 214 is N-type doped AlGaN.

The thickness of the epitaxial structure 210, and the materials of the layers, may be otherwise configured as desired by those skilled in the art. Of course, the first substrate 201 is not limited to a sapphire substrate, and may be a GaN substrate, an AlN substrate, or Ga₂O₃Any one of a substrate, a SiC substrate, a Si substrate, a ZnO single crystal substrate, and a high temperature resistant metal substrate with a pre-deposited AlN film.

Further, at least one via 202 is formed in the epitaxial structure 210, as shown in fig. 10.

In this step, a plurality of vias 202 are simultaneously formed in a uniform array distribution on the epitaxial structure 210, for example, using photolithography and dry etching techniques. The plurality of through holes 202 extend from the first surface 201a of the epitaxial structure to the N-type semiconductor layer 214. The through holes 202 increase the area of the side wall, and are beneficial to extracting more deep ultraviolet light in the horizontal direction.

The number of through holes 202 can be set as desired by those skilled in the art.

Further, a conductive portion 220 is formed in each through hole 202, as shown in fig. 11.

In this step, conductive portions 220 connected to the N-type semiconductor layer 214 are formed in the through-holes 202, for example, using photolithography and physical vapor deposition techniques, the conductive portions 220 being separated from the P-type semiconductor layer 216 and the multiple quantum well layer 215, respectively. The conductive portion 220 is then annealed to form a good ohmic contact between the conductive portion 220 and the N-type semiconductor layer 214.

In the present embodiment, the conductive portion 220 includes one or a combination of V, Ti, Cr, Al, Ni, Au, Pt metal layers along the direction from the second surface 201b to the first surface 201a of the epitaxial structure 210, and the total thickness of the conductive portion 220 is 600 nm. Annealing at N₂The annealing was carried out under an atmosphere with a process temperature of 1000 c and the annealing process lasted for 30 seconds.

Further, a hole compensation layer 230 of a P-type semiconductor layer is formed on the first surface 201a of the epitaxial structure, as shown in fig. 12.

In this step, for example, a porous mask is formed on the P-type semiconductor layer 216, each hole exposes a part of the P-type semiconductor layer 216, then a corresponding silicon nano-layer is formed in each hole of the mask by sputtering, each silicon nano-layer is in contact with the P-type semiconductor layer 216, each silicon nano-layer is doped P-type, then the porous mask and the silicon nano-layers on the mask are removed, and the hole compensation layer 230 of the formed P-type semiconductor layer is a plurality of silicon nano-layers arranged at intervals. Wherein the silicon nanolayer is composed of silicon nanoparticles, and the size of the silicon nanoparticles is between tens of nanometers and hundreds of nanometers.

In the embodiment, the characteristic size range of the holes of the mask is 50-200 microns, and the holes in the mask are distributed according to one of a uniform array distribution and a non-uniform array distribution. The uniform array distribution can ensure that the hole compensation effect of each region on the P-type semiconductor layer 216 is uniform; the use of an unevenly distributed array allows for the creation of a compensated difference in hole concentration in different areas.

The process of forming the porous structure mask includes: step projection lithography, nanoimprint masks, or metal high temperature annealing to form random nanoarray masks.

Further, a metal layer 240 covering the P-type semiconductor layer 216 and the hole compensation layer 230 of the P-type semiconductor layer is formed, as shown in fig. 13.

In this step, a Cu nanowire surrounded by a cladding layer is coated on the P-type semiconductor layer 216 to cover the P-type semiconductor layer 216 and the hole compensation layer 230 of the P-type semiconductor layer, for example, by a spin coating process, wherein a region corresponding to the through hole 202 is protected and not covered by the metal layer 240, or in this step, an opening of the through hole 202 extends to the metal layer 240. The hole compensation layer 230 of the P-type semiconductor layer is then tightly bonded to the P-type semiconductor layer 216 by a high temperature annealing process and a good ohmic contact is formed between the metal layer 240 and the P-type semiconductor layer 216. Wherein the material of the coating layer comprises a high work function metal, and the total diameter of the coating layer and the wrapped Cu nanowire is about 50 nanometers.

In this embodiment, when the P-type semiconductor layer 216 is made of P-type doped AlGaN, the cladding layer is made of Ni or Pt, so that the contact barrier between the metal layer 240 and the P-type semiconductor layer 216 is reduced, and the metal-semiconductor contact resistivity is improved, thereby achieving the purpose of reducing the voltage of the deep ultraviolet LED chip. Moreover, the metal layer 240 formed by the metal nanowires (with a duty ratio of 90%) has high transmittance to deep ultraviolet light, which can reach 70% -90%, so that the deep ultraviolet light can efficiently penetrate through the metal layer 240.

However, other arrangements of the material of the metal layer 240 may be performed by those skilled in the art, as needed, for example, when the P-type semiconductor layer 216 is made of other transparent materials, the metal nanowires in the metal layer 240 and the cladding material wrapped thereon are also changed accordingly. Or, considering the material of the P-type semiconductor layer 216, the contact barrier, the light transmittance of the metal layer 240, the cost, and other factors, the metal layer 240 made of the metal nanowire can be replaced by a common metal layer.

Further, a mirror layer 250 is formed to cover the metal layer 240, as shown in fig. 13.

In this step, a mirror layer 250 is formed on the metal layer 240, for example, by using photolithography and a physical vapor deposition process, wherein the region corresponding to the through hole 202 is protected and not covered by the mirror layer 250, or in this step, the opening of the through hole 202 extends to the mirror layer 250.

In the present embodiment, the mirror layer 250 has a high reflectivity to deep ultraviolet light, and the thickness thereof is 200 nm. In some specific embodiments, the mirror layer 250 includes one of an Al mirror, an Rh mirror, and an Mg mirror. The thickness of the mirror layer 250 is 120 nm.

Further, a metal barrier layer 260 is formed to cover the mirror layer 250, as shown in fig. 13.

In this step, a metal barrier layer 260 is formed on the mirror layer 250, for example, by using photolithography and a physical vapor deposition process, wherein a region corresponding to the via 202 is protected and not covered by the metal barrier layer 260, or in this step, an opening of the via 202 extends to the metal barrier layer 260.

In the present embodiment, the metal barrier layer 260 is a metal material and has a thickness of 800 nm. In some embodiments, the material of the metal barrier layer 260 is TiW or TiPt or TiNi. The metal barrier layer 260 functions to prevent the mirror layer 250 from being oxidized and to prevent diffusion between metals.

Further, an insulating layer 204 is formed on the metal barrier layer 260, as shown in fig. 14.

In this step, an insulating layer 204 covering the semiconductor structure is formed, for example, by using an atomic layer deposition process, and a portion of the insulating layer 204 is located on the metal barrier layer 260 and partially filled in the via hole 202, wherein the insulating layer 204 filled in the via hole 202 covers the conductive portion 220.

In the present embodiment, the insulating layer 204 is deposited to a thickness of 300nm and the material comprises AlN dielectric.

Further, an N conductive via 205 is formed through the insulating layer 204, as shown in fig. 14.

In this step, the N conductive vias 205 are formed, for example, using photolithography and dry etching processes, wherein the N conductive vias 205 expose the surface of each conductive portion 220.

Further, a first bonding layer 206 is formed on the insulating layer 204, as shown in fig. 15.

In this embodiment, the first bonding layer 206 is connected to each conductive portion 220 via an N conductive via 205.

In some specific embodiments, the first bonding layer 206 includes a Ti adhesion layer and a Ni, Sn binary alloy layer stacked in sequence along the direction from the second surface 201b of the epitaxial structure to the first surface 201 a. Wherein, the thickness of the Ti adhesion layer is 100nm, and the thicknesses of the Ni and Sn binary alloy layers are 600nm and 200nm respectively.

Further, a second bonding layer 302 is formed on the second substrate 301, as shown in fig. 16, and then the first bonding layer 206 is bonded to the second bonding layer 302, as shown in fig. 17.

In this embodiment, the second substrate 301 is a silicon substrate. The second bonding layer 302 includes a Ni, Sn binary alloy, and Ti adhesion layer sequentially stacked in a direction from the second surface 201b toward the first surface 201a of the epitaxial structure 210.

In the bonding step, the first bonding layer 206 is bonded to the second bonding layer 302 using a NiSn liquid phase transient bonding process at 260 ℃.

Further, the first substrate 201 and the buffer layer 211 are removed, as shown in fig. 18.

In this step, for example, the buffer layer 211 and the first substrate 201 are peeled and decomposed using an ultraviolet laser having a wavelength of 193nm and a small spot of 50 μm, and then, Al and Ga metals formed by decomposition of AlN and AlGaN materials are removed by washing with dilute hydrochloric acid.

Further, the surface of the epitaxial structure 210 is roughened, as shown in fig. 19.

In this step, AlN layer 212 is treated with a heated KOH solution at 70 ℃ to form a roughened surface, and the secondary micro-nano structure is used to increase the axial deep ultraviolet light extraction.

Further, portions of the AlN layer 212, the AlN/AlGaN super lattice layer 213, the N-type semiconductor layer 214, the multiple quantum well layer 215, and the P-type semiconductor layer 216, the hole compensation layer 230 of the P-type semiconductor layer, the metal layer 240, and the mirror layer 250 are etched to form a recess 203 exposing portions of the metal barrier layer 260, as shown in fig. 20.

In this step, a groove 203 is formed using photolithography and dry etching processes, and the groove 203 corresponds to an edge of the second substrate 301 as a P electrode region and a chip runner region. Preferably, the sidewalls of the grooves 203 are further roughened.

Further, a passivation layer 207 is formed to cover the surface and sidewalls of the epitaxial structure 210, the hole compensation layer 230 of the P-type semiconductor layer, the metal layer 240, the sidewalls of the mirror layer 250, and a portion of the surface of the metal blocking layer 260, as shown in fig. 21. Wherein, the material of the passivation layer 207 includes but is not limited to SiO₂Including but not limited to 200 nm.

Further, a P-electrode 270 connected to the metal barrier layer 260 is formed in the groove 203.

In this step, a P-electrode 270 is formed on the metal barrier layer 260 in the groove 203, for example, by photolithography, wet etching, and electron beam evaporation, and the material of the P-electrode 270 is, for example, CrPtAu. Wherein the second substrate 301 acts as an N-electrode.

According to the manufacturing method of the second embodiment of the present invention, the formed deep ultraviolet LED chip is a vertical through hole structure, and the specific structure of the deep ultraviolet LED chip of the second embodiment is described with reference to fig. 9 to 21, which is not described herein again.

Fig. 22 to 28 are structural views showing a method of manufacturing a deep ultraviolet LED chip according to a third embodiment of the present invention at some stages.

As shown in fig. 22, an epitaxial structure 410 is formed on a first substrate 401. The epitaxial structure 410 has opposing first and second surfaces 401a, 401b, the second surface 401b being in contact with the first substrate 401. The epitaxial structure 410 includes a P-type semiconductor layer 416, an N-type semiconductor layer 414, and a multi-quantum well layer 415 sandwiched by the P-type semiconductor layer 416 and the N-type semiconductor layer 414, wherein the P-type semiconductor layer 416 is exposed to the first surface 401a of the epitaxial structure 410.

In some preferred embodiments, to better match the lattice between the N-type semiconductor layer 414 and the first substrate 401, the epitaxial structure 410 further includes a lattice matching stack between the N-type semiconductor layer 414 and the first substrate 401. Specifically, the first substrate 401 is a sapphire substrate, and the epitaxial structure 410 includes a buffer layer 411, an AlN layer 412, an AlN/AlGaN superlattice layer 413, an N-type semiconductor layer 414, a multi-quantum well layer 415, and a P-type semiconductor layer 416 stacked in this order along a direction from the second surface 401b of the epitaxial structure to the first surface 401a, where the buffer layer 411 is made of AlN, the AlN layer 412 is thicker than the buffer layer 411, and the buffer layer 411, the AlN layer 412, and the AlN/AlGaN superlattice layer 413 are used as a lattice matching stack.

In the present embodiment, the thickness of the epitaxial structure 410 ranges from 5 microns to 10 microns, and the growth method of each layer in the epitaxial structure 410 may be metal chemical vapor deposition, laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy. The layers of epitaxial structure 410 may be polycrystalline or single crystal structures. The sapphire substrate includes but is not limited to one of a mirror or a micro/nano patterned sapphire substrate, the preferred solution of which is nano patterned sapphire. The multiple quantum well layer 414 in the epitaxial structure 410 includes one or more reciprocating continuous progressive LED chip epitaxial structures formed by material systems such as AlGaN/AlInGaN, and the like, and the preferred scheme is an AlGaN structure containing different Al components.

In the present embodiment, the material of the P-type semiconductor layer 416 is P-type doped gallium aluminum nitride (AlGaN) or aluminum boron nitride (BAlN). The material of the N-type semiconductor layer 414 is N-type doped AlGaN.

One skilled in the art may also make other arrangements of the thickness of the epitaxial structure 410, layers of material, etc., as desired. Of course, the first substrate 401 is not limited to a sapphire substrate, and may be a GaN substrate, an AlN substrate, or Ga₂O₃Any one of a substrate, a SiC substrate, a Si substrate, a ZnO single crystal substrate, and a high temperature resistant metal substrate with a pre-deposited AlN film.

Further, a hole compensation layer 430 of a P-type semiconductor layer is formed on the first surface 401a of the epitaxial structure, as shown in fig. 23.

In this step, for example, a porous mask is formed on the P-type semiconductor layer 416, each hole exposes a part of the P-type semiconductor layer 416, then a corresponding silicon nano-layer is formed in each hole of the mask by a sputtering method, each silicon nano-layer is in contact with the P-type semiconductor layer 416, each silicon nano-layer is doped P-type, then the silicon nano-layers on the porous mask and the mask are removed, and the hole compensation layer 430 of the formed P-type semiconductor layer is a plurality of silicon nano-layers arranged at intervals. Wherein the silicon nanolayer is composed of silicon nanoparticles, and the size of the silicon nanoparticles is between tens of nanometers and hundreds of nanometers.

In the embodiment, the characteristic size range of the holes of the mask is 50-200 microns, and the holes in the mask are distributed according to one of a uniform array distribution and a non-uniform array distribution. The uniform array distribution can ensure that the hole compensation effect of each region on the P-type semiconductor layer 416 is uniform; the use of an unevenly distributed array allows for the creation of a compensated difference in hole concentration in different areas.

The process of forming the porous structure mask includes: step projection lithography, nanoimprint masks, or metal high temperature annealing to form random nanoarray masks.

Specifically, a Ni metal film is deposited on the surface of the P-type semiconductor layer 416, a self-assembled nano metal mask (porous structure mask) is formed by the Ni metal film through high-temperature annealing, then a silicon nano layer is prepared on the semiconductor structure through a sputtering method, and then the self-assembled nano metal mask and the silicon nano layer thereon are removed through hydrochloric acid. The silicon nanolayer remaining on the surface of the P-type semiconductor layer 416 serves as a hole compensation layer 430 for the P-type semiconductor layer.

Further, a metal layer 440 covering the P-type semiconductor layer 416 and the hole compensation layer 430 of the P-type semiconductor layer is formed, as shown in fig. 23.

In this step, the Cu nanowire surrounded by the clad layer is coated on the P-type semiconductor layer 416 to cover the P-type semiconductor layer 416 and the hole compensation layer 430 of the P-type semiconductor layer, for example, using a spin coating process. And then, the hole compensation layer 430 of the P-type semiconductor layer is tightly combined with the P-type semiconductor layer 416 by using a high-temperature annealing process, and a good ohmic contact is formed between the metal layer 440 and the P-type semiconductor layer 416. Wherein the material of the coating layer comprises a metal with high work function, and the total diameter of the coating layer and the wrapped Cu nanowire is about 100 nanometers.

In this embodiment, when the P-type semiconductor layer 416 is made of P-type doped AlGaN, the cladding layer is made of Ni or Pt, so that the contact barrier between the metal layer 440 and the P-type semiconductor layer 416 is reduced, and the metal-semiconductor contact resistivity is improved, thereby achieving the purpose of reducing the voltage of the deep ultraviolet LED chip. Moreover, the metal layer 440 formed by the metal nanowires (with a duty ratio of 90%) has high transmittance to deep ultraviolet light, which can reach 70% -90%, so that the deep ultraviolet light can efficiently penetrate through the metal layer 440.

However, other arrangements of the material of the metal layer 440 may be performed as required by those skilled in the art, for example, when the P-type semiconductor layer 416 is made of other transparent materials, the metal nanowires in the metal layer 440 and the cladding material wrapped thereon are also changed accordingly. Or, considering the material of the P-type semiconductor layer 416, the contact barrier, the light transmittance of the metal layer 440, the cost, and other factors, the metal layer 440 made of the metal nanowire can be replaced by a common metal layer.

Further, a mirror layer 450 is formed to cover the metal layer 440, as shown in fig. 23.

In this step, a mirror layer 450 is formed on the metal layer 440, for example, using photolithography, a physical vapor deposition process.

In the present embodiment, the reflector layer 450 has a high reflectivity to deep ultraviolet light, and a thickness of 100 nm. In some specific embodiments, the mirror layer 450 includes one of an Al mirror, an Rh mirror, and an Mg mirror. The thickness of the mirror layer 450 is 100 nm.

Further, a metal barrier layer 460 is formed to cover the mirror layer 450, as shown in fig. 23.

In this step, a metal barrier layer 460 is formed on the mirror layer 450, for example, using a photolithography, physical vapor deposition process.

In the present embodiment, the metal barrier layer 460 is a conductive material and has a thickness of 500 nm. In some embodiments, the material of the metal barrier layer 460 is TiW or TiPt or TiNi. The metal barrier layer 460 functions to prevent the mirror layer 450 from being oxidized and to prevent diffusion between metals.

Further, a first bonding layer 471 is formed on the metal barrier layer 460, as shown in fig. 23.

In some specific embodiments, the first bonding layer 471 includes a Ti adhesion layer and a Cu and Sn binary alloy layer stacked in sequence along the direction from the second surface 401b to the first surface 401a of the epitaxial structure. Wherein, the thickness of the Ti adhesion layer is 100nm, and the thicknesses of the Cu and Sn binary alloy layers are 600nm and 200nm respectively.

Further, a second bonding layer 502 is formed on the second substrate 501, as shown in fig. 24, and then the first bonding layer 471 is bonded to the second bonding layer 502, as shown in fig. 25.

In this embodiment, the second substrate 501 is a silicon substrate and has a thickness of 600 μm. In a direction from the second surface 401b to the first surface 401a of the epitaxial structure 410, the second bonding layer 502 includes Sn, a Cu binary alloy, and a Ti adhesion layer, which are sequentially stacked.

In the bonding step, the first bonding layer 471 is bonded to the second bonding layer 502 by using a CuSn liquid phase transient bonding process at 260 ℃.

Further, the first substrate 401, the buffer layer 411, the AlN layer 412, and the AlN/AlGaN superlattice layer 413 are removed, as shown in fig. 26.

In this step, for example, the buffer layer 411 and the first substrate 401 are peeled and decomposed using an ultraviolet laser having a wavelength of 266nm and a small spot of 20 μm, and then Al and Ga metals formed by decomposition of AlN and AlGaN materials are removed by washing with diluted hydrochloric acid, thereby exposing the surface of the N-type semiconductor layer 414.

Further, the surface of the epitaxial structure 410 is roughened, as shown in fig. 27.

In this step, the N-type semiconductor layer 414 is processed at 60 ℃ to form a roughened surface by using a heated KOH solution, and the axial deep ultraviolet light extraction is increased by using a secondary micro-nano structure.

Further, a portion of the N-type semiconductor layer 414, the multiple quantum well layer 415, the P-type semiconductor layer 416, the hole compensation layer 430 of the P-type semiconductor layer, the metal layer 440, and the mirror layer 450 are etched to form a groove 403 exposing a portion of the metal barrier layer 460, as shown in fig. 27.

In this step, a groove 403 is formed using photolithography and dry etching processes, and the groove 403 corresponds to an edge of the second substrate 501 as a P electrode region and a chip runner region. Preferably, the sidewalls of the groove 403 are further roughened.

Further, a passivation layer 407 covering the surface and the sidewall of the epitaxial structure 410, the hole compensation layer 430 of the P-type semiconductor layer, the metal layer 440, the sidewall of the mirror layer 450, and the surface of the metal blocking layer 460 is formed, as shown in fig. 28. The material of the passivation layer 407 includes, but is not limited to, SiO₂Including but not limited to 200 nm.

Further, an N electrode 420 is formed through the passivation layer 407 and connected to the N-type semiconductor layer 414, as shown in fig. 28.

In this step, an N electrode 420 is prepared on the N electrode 420, for example, using photolithography, wet etching, and electron beam evaporation processes, and the material of the N electrode 420 is, for example, Cr/Al/Ti/Pt/Au. Wherein the second substrate 501 acts as a P-electrode.

According to the manufacturing method of the third embodiment of the present invention, the formed deep ultraviolet LED chip is in a vertical reversed polarity structure, and the specific structure of the deep ultraviolet LED chip of the third embodiment is described with reference to fig. 22 to 28, which is not described herein again.

According to the deep ultraviolet LED chip and the manufacturing method thereof provided by the embodiment of the invention, the P-type semiconductor layer is subjected to hole compensation by replacing a P-GaN layer with a plurality of P-type silicon nano layers arranged at intervals in the hole compensation layer of the P-type semiconductor layer, so that the internal quantum efficiency of the deep ultraviolet LED chip is improved; because the silicon nano particles of the silicon nano layer are provided with spaced gaps, the hole compensation layer of the P-type semiconductor layer is ensured to compensate the P-type semiconductor layer to obtain higher hole concentration, more holes and electrons are compounded in the quantum well layer, the internal quantum efficiency is improved, meanwhile, the deep ultraviolet light can also be emitted/incident through the gaps between the silicon nano particles, and the purpose of reducing the absorption of the deep ultraviolet light is realized.

The Cu nanowires are wrapped by the metal coating layer with the high work function, so that the contact barrier between the metal layer and the P-type semiconductor layer is reduced, the metal-semiconductor contact resistivity is improved, the effect of reducing the voltage of the deep ultraviolet LED chip is realized, and the electro-optic conversion efficiency of the deep ultraviolet LED chip is improved; and the metal nanowires in the metal layer have high transmittance, and deep ultraviolet light can efficiently transmit.

One of an Al mirror, an Rh mirror and an Mg mirror is used as a reflector layer of the deep ultraviolet light, and under the action of the reflector layer, the reflector layer is matched with a metal layer with high transmittance to enable the ultraviolet light to be reflected again, so that the whole light-emitting efficiency of the deep ultraviolet LED chip is increased. Meanwhile, the reflector layer is made of metal, so that the reflector layer can also realize the function of current expansion.

Through setting up through-hole and groove structure, increased the area of epitaxial structure lateral wall to the light extraction efficiency of horizontal direction has been increased.

Therefore, the deep ultraviolet LED chip provided by the embodiment of the invention ensures that the P-type semiconductor layer obtains higher hole concentration and better ohmic contact effect, reduces the absorption of the internal structure of the deep ultraviolet LED chip to the deep ultraviolet light, increases the internal quantum efficiency and the electro-optic conversion efficiency of the deep ultraviolet LED chip, and finally enhances the performance of the deep ultraviolet LED chip.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.