阅读说明：本技术 行解码电路及sonos结构的eeprom (Row decoding circuit and EEPROM with SONOS structure ) 是由 刘芳芳 于 2021-09-29 设计创作，主要内容包括：本发明提供一种行解码电路,包括：多组行解码单元,各组所述行解码单元包括：第一、第二、第三和第四预解码子单元、电平移位子单元以及第一、第二、第三和第四电压传输子单元,利用所述预解码子单元接收地址信号并给后级电路提供字线控制信号,以及利用所述电压传输子单元给后级电路提供SONOS线信号。本发明还提供一种SONOS结构的EEPROM。本申请在各组所述行解码单元中,4行预解码子单元和4行电压传输子单元共用1行电平移位子单元,可以减少所述电平移位子单元的数量,从而减少行解码电路的面积占芯片整体面积的比例。(The present invention provides a row decoding circuit, comprising: a plurality of sets of row decoding units, each set of the row decoding units comprising: the first, second, third and fourth pre-decoding subunits, the level shifting subunit and the first, second, third and fourth voltage transmission subunits are utilized to receive address signals and provide word line control signals for a rear-stage circuit, and the voltage transmission subunits are utilized to provide SONOS line signals for the rear-stage circuit. The invention also provides an EEPROM with the SONOS structure. In each group of the line decoding units, 4 lines of pre-decoding subunits and 4 lines of voltage transmission subunits share 1 line of level shifting subunits, so that the number of the level shifting subunits can be reduced, and the proportion of the area of a line decoding circuit to the whole area of a chip is reduced.)

1. A row decoding circuit, comprising: a plurality of sets of row decoding units, wherein each set of row decoding units comprises: a first, second, third and fourth pre-decoding subunit, a level shifting subunit and a first, second, third and fourth voltage transmitting subunit;

each pre-decoding subunit receives an address signal, outputs a first control signal and a second control signal to the level shifting subunit, and outputs a word line control signal to a post-stage circuit, wherein the first control signal and the second control signal are opposite to each other;

the level shifting subunit receives the first control signal and the second control signal output by the first to fourth pre-decoding subunits, and correspondingly outputs a third control signal and a fourth control signal to the first to fourth voltage transmission subunits;

and each voltage transmission subunit receives the third control signal and the fourth control signal and outputs an SONOS line signal to a rear-stage circuit.

2. The row decoding circuit of claim 1, wherein the first through fourth pre-decoding subunits each comprise: a NAND gate circuit, a NOT gate circuit and an AND gate circuit;

the first input end of the NAND gate circuit, the second input end of the NAND gate circuit and the first input end of the AND gate circuit receive the address signal, the output end of the NAND gate circuit is connected to the input end of the NOT gate circuit and outputs the first control signal, the output end of the NOT gate circuit is connected to the second input end of the AND gate circuit and outputs the second control signal, and the output end of the AND gate circuit outputs the word line control signal to a rear-stage circuit.

3. The row decoding circuit of claim 2, wherein the level shifting subunit comprises: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube;

the first PMOS tube is connected with the first NMOS tube in series, the series node of the first PMOS tube and the first NMOS tube is connected with the grid electrode of the second PMOS tube and the voltage transmission subunit so as to output the third control signal to the second PMOS tube and the voltage transmission subunit, the source electrode of the first PMOS tube is connected with a high level, and the source electrode of the first NMOS tube is grounded;

the second PMOS tube is connected with the second NMOS tube in series, the series node of the second PMOS tube and the second NMOS tube is connected with the grid electrode of the first PMOS tube and the voltage transmission subunit so as to output the fourth control signal to the first PMOS tube and the voltage transmission subunit, the drain electrode of the second PMOS tube is connected with a high level, and the drain electrode of the second NMOS tube is grounded.

4. The row decoding circuit of claim 3, wherein the output of the NAND gate of the pre-decoding subunit is further connected to the gate of the first NMOS transistor of the level shifting subunit to provide the first control signal to the level shifting subunit;

the output end of the NOT circuit of the pre-decoding subunit is further connected to the gate of the second NMOS transistor of the level shifting subunit to provide the second control signal for the level shifting subunit.

5. The row decoding circuit of claim 3, wherein the first through fourth voltage transmission subunits each comprise: the power supply comprises a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube, a first power supply and a second power supply;

the grid electrode of the third NMOS tube and the grid electrode of the fourth PMOS tube receive the third control signal, and the grid electrode of the third PMOS tube and the grid electrode of the fourth NMOS tube receive the fourth control signal;

the third PMOS tube and the third NMOS tube are reversely connected in parallel; the fourth PMOS tube and the fourth NMOS tube are reversely connected in parallel, a parallel node at one end of the third PMOS tube and one end of the third NMOS tube is connected with the first power supply, and a parallel node at one end of the fourth PMOS tube and one end of the fourth NMOS tube is connected with the second power supply; and the parallel node at the other ends of the third PMOS tube and the third NMOS tube is connected with the parallel node at the other ends of the fourth PMOS tube and the fourth NMOS tube and outputs the SONOS line signal to a rear-stage circuit together.

6. The row decoding circuit of claim 5, wherein during an erase operation, the first power supply provides 0V and the second power supply provides a first positive voltage;

during a programming operation, the first power supply provides a first positive voltage and the second power supply provides a second positive voltage.

7. The row decoding circuit of claim 5, wherein, during an erase operation, when the word line control signal outputted from the first, second, third or fourth pre-decoding sub-unit to the post-stage circuit is a logic high level based on the address signal to select the word line of the post-stage circuit, the corresponding first, second, third or fourth voltage transmitting sub-unit outputs the voltage provided by the first power supply to the post-stage circuit;

during programming operation, when the word line control signal output by the first, second, third or fourth pre-decoding subunit to the post-stage circuit is logic high level based on the address signal so as to select the word line of the post-stage circuit, the corresponding first, second, third or fourth voltage transmission subunit outputs the voltage provided by the first power supply to the post-stage circuit.

8. An SONOS-structured EEPROM comprising: the memory device of any one of claims 1-7, wherein the column decode circuit provides bit line control signals and source line control signals to the memory array; the row decode circuit provides a word line control signal and a SONOS line signal to the memory array.

Technical Field

The application relates to the technical field of memories, in particular to a row decoding circuit and an EEPROM with an SONOS structure.

Background

At present, modern electronic equipment and embedded structures are rapidly developed and widely applied, and the demand of high-integration-level circuit chips is increasingly increased, so that a series of requirements for limiting the area of the integrated circuit chips are promoted. Therefore, the area of the EEPROM (Electrically Erasable Programmable Read Only Memory) product with the SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, also called Silicon-Oxide-Nitride-Oxide-Silicon) structure also puts higher demands on the product area.

In the SONOS-structured EEPROM, a selected word line requires a high positive voltage in a program operation, and a selected word line requires a high negative voltage in an erase operation. The row decoding circuit generally includes a plurality of sets of row decoding units, each set of row decoding units including: and in each group of the 4 rows of the decoding units, the 4 rows of the decoding units correspondingly output 4 word line control signals to a rear-stage storage array, and the 4 rows of the voltage transmission units correspondingly output 4 SONOS line signals to the rear-stage storage array. That is, for the conventional design, each row of the row decoding units needs a corresponding level shifting unit (level shifting unit) for each row of the voltage transmission units (predecoding units). Then each group of row decoding units requires 4 level shifting units; the larger the product capacity is, the more row decoding units are needed, the more corresponding level shifting units are, the larger the chip area is occupied, the miniaturization is not facilitated, and the cost is not reduced.

Therefore, how to further reduce the area of the EEPROM with the SONOS structure and reduce the cost thereof has become one of the problems to be solved by those skilled in the art.

Disclosure of Invention

The application provides a line decoding circuit and an EEPROM with an SONOS structure, which can solve the problem that the area of the line decoding circuit is too large.

In one aspect, an embodiment of the present application provides a row decoding circuit, including: a plurality of sets of row decoding units, wherein each set of row decoding units comprises: a first, second, third and fourth pre-decoding subunit, a level shifting subunit and a first, second, third and fourth voltage transmitting subunit;

each pre-decoding subunit receives an address signal, outputs a first control signal and a second control signal to the level shifting subunit, and outputs a word line control signal to a post-stage circuit, wherein the first control signal and the second control signal are opposite to each other;

the level shifting subunit receives the first control signal and the second control signal output by the first to fourth pre-decoding subunits, and correspondingly outputs a third control signal and a fourth control signal to the first to fourth voltage transmission subunits;

and each voltage transmission subunit receives the third control signal and the fourth control signal and outputs an SONOS line signal to a rear-stage circuit.

Optionally, in the row decoding circuit, the first to fourth pre-decoding subunits each include: a NAND gate circuit, a NOT gate circuit and an AND gate circuit;

the first input end of the NAND gate circuit, the second input end of the NAND gate circuit and the first input end of the AND gate circuit receive the address signal, the output end of the NAND gate circuit is connected to the input end of the NOT gate circuit and outputs the first control signal, the output end of the NOT gate circuit is connected to the second input end of the AND gate circuit and outputs the second control signal, and the output end of the AND gate circuit outputs the word line control signal to a rear-stage circuit.

Optionally, in the row decoding circuit, the level shifting subunit includes: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube;

the first PMOS tube is connected with the first NMOS tube in series, the series node of the first PMOS tube and the first NMOS tube is connected with the grid electrode of the second PMOS tube and the voltage transmission subunit so as to output the third control signal to the second PMOS tube and the voltage transmission subunit, the source electrode of the first PMOS tube is connected with a high level, and the source electrode of the first NMOS tube is grounded;

the second PMOS tube is connected with the second NMOS tube in series, the series node of the second PMOS tube and the second NMOS tube is connected with the grid electrode of the first PMOS tube and the voltage transmission subunit so as to output the fourth control signal to the first PMOS tube and the voltage transmission subunit, the drain electrode of the second PMOS tube is connected with a high level, and the drain electrode of the second NMOS tube is grounded.

Optionally, in the row decoding circuit, an output end of the nand gate circuit of the pre-decoding subunit is further connected to a gate of the first NMOS transistor of the level shifting subunit, so as to provide the first control signal to the level shifting subunit;

the output end of the NOT circuit of the pre-decoding subunit is further connected to the gate of the second NMOS transistor of the level shifting subunit to provide the second control signal for the level shifting subunit.

Optionally, in the row decoding circuit, the first to fourth voltage transmission subunits each include: the power supply comprises a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube, a first power supply and a second power supply;

the grid electrode of the third NMOS tube and the grid electrode of the fourth PMOS tube receive the third control signal, and the grid electrode of the third PMOS tube and the grid electrode of the fourth NMOS tube receive the fourth control signal;

the third PMOS tube and the third NMOS tube are reversely connected in parallel; the fourth PMOS tube and the fourth NMOS tube are reversely connected in parallel, a parallel node at one end of the third PMOS tube and one end of the third NMOS tube is connected with the first power supply, and a parallel node at one end of the fourth PMOS tube and one end of the fourth NMOS tube is connected with the second power supply; and the parallel node at the other ends of the third PMOS tube and the third NMOS tube is connected with the parallel node at the other ends of the fourth PMOS tube and the fourth NMOS tube and outputs the SONOS line signal to a rear-stage circuit together.

Optionally, in the row decoding circuit, during an erase operation, the first power supply provides 0V, and the second power supply provides a first positive voltage;

during a programming operation, the first power supply provides a first positive voltage and the second power supply provides a second positive voltage.

Optionally, in the row decoding circuit, when, during an erase operation, based on the address signal, the word line control signal output by the first, second, third, or fourth pre-decoding subunit to the subsequent stage circuit is a logic high level to select a word line of the subsequent stage circuit, the corresponding first, second, third, or fourth voltage transmission subunit outputs a voltage provided by the first power supply to the subsequent stage circuit;

during programming operation, when the word line control signal output by the first, second, third or fourth pre-decoding subunit to the post-stage circuit is logic high level based on the address signal so as to select the word line of the post-stage circuit, the corresponding first, second, third or fourth voltage transmission subunit outputs the voltage provided by the first power supply to the post-stage circuit.

On the other hand, an embodiment of the present application further provides an EEPROM with a SONOS structure, including: the memory comprises a memory array, a column decoding circuit and the row decoding circuit, wherein the column decoding circuit provides a bit line control signal and a source line control signal for the memory array; the row decode circuit provides a word line control signal and a SONOS line signal to the memory array.

The technical scheme at least comprises the following advantages:

in each group of the line decoding units, 4 lines of pre-decoding subunits and 4 lines of voltage transmission subunits share the middle 1 line of level shifting subunits, so that the number of the level shifting subunits is reduced, the proportion of the area of a line decoding circuit to the whole area of a chip is reduced, the area of the chip is effectively saved, the size of a memory is reduced, and the cost is reduced.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a circuit schematic of a row decode unit of an embodiment of the present invention;

FIG. 2 is a circuit schematic of a pre-decoding subunit of an embodiment of the present invention;

FIG. 3 is a circuit diagram of a level shifting sub-unit according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a voltage transmitting subunit according to an embodiment of the present invention.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

In one aspect, an embodiment of the present invention provides a row decoding circuit, please refer to fig. 1, where fig. 1 is a schematic circuit diagram of a row decoding unit according to an embodiment of the present invention, and the row decoding circuit includes: a plurality of groups of row decoding units 100, wherein each group of row decoding units 100 comprises: a first pre-decoding subunit 10, a second pre-decoding subunit 10, a third pre-decoding subunit 10 and a fourth pre-decoding subunit 10, a level shifting subunit 20 and a first voltage transmission subunit 30, a second voltage transmission subunit 30, a third voltage transmission subunit 30 and a fourth voltage transmission subunit 30.

Each memory cell in the memory array of a SONOS-structured EEPROM typically includes: the memory device comprises a SONOS memory transistor and a selection transistor, wherein the SONOS memory transistor is used for storing data, and the selection transistor is used for completing selection on data addresses.

In this embodiment, each pre-decoding subunit 10 receives an address signal ABC, and outputs a first control signal wllb and a second control signal wll to the level shifting subunit 20, and outputs a word line control signal Wl to the selection transistor of each memory cell of the post-stage circuit, where the first control signal wllb and the second control signal wll are opposite to each other. The level shifting sub-unit 20 receives the first control signal wllb and the second control signal wll output by the first to fourth pre-decoding sub-units 10 and correspondingly outputs a third control signal wlh and a fourth control signal wlhb to the first to fourth voltage transmitting sub-units 30. Each of the voltage transmitting sub-units 30 receives the third control signal wlh and the fourth control signal wlhb, and outputs a SONOS line signal WLS to the SONOS memory transistor of each memory cell of the subsequent circuit (memory array).

Further, referring to fig. 2, fig. 2 is a circuit diagram of a pre-decoding subunit according to an embodiment of the present invention, where the first to fourth pre-decoding subunits 10 each include: a nand gate circuit D1, a not gate circuit S1, and an and gate circuit Y1. Wherein a first input terminal of the nand gate circuit D1, a second input terminal of the nand gate circuit D1 and a first input terminal of the and gate circuit Y1 receive the address signal ABC, an output terminal of the nand gate circuit D1 is connected to an input terminal of the not gate circuit S1 and outputs the first control signal wllb, an output terminal of the not gate circuit S1 is connected to a second input terminal of the and gate circuit Y1 and outputs the second control signal wll, and an output terminal of the and gate circuit Y1 outputs the word line control signal Wl to a subsequent stage circuit (memory array).

In this embodiment, referring to fig. 3, fig. 3 is a circuit schematic diagram of a level shifting sub-unit according to an embodiment of the present invention, where the level shifting sub-unit 20 includes: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1 and a second NMOS transistor N2. The first PMOS transistor P1 is connected in series with the first NMOS transistor N1, and the series node of the first PMOS transistor P1 and the first NMOS transistor N1 is connected to the gate of the second PMOS transistor P2, the gate of the fourth PMOS transistor P4 of the voltage transmission subunit 30, and the gate of the third NMOS transistor N3, so as to provide the third control signal wlh to the gate of the second PMOS transistor P2 and the voltage transmission subunit 30, the source of the first PMOS transistor P1 is connected to the high-level VPOS, and the source of the first NMOS transistor N1 is connected to the ground vgnd. Further, the second PMOS transistor P2 is connected in series with the second NMOS transistor N2, and a series node of the second PMOS transistor P2 and the second NMOS transistor N2 is connected to the gate of the first PMOS transistor P1, the gate of the third PMOS transistor P3 of the voltage transmission subunit 30, and the gate of the fourth NMOS transistor N4, so as to provide the fourth control signal wlhb to the gate of the first PMOS transistor P1 and the voltage transmission subunit 30, the drain of the second PMOS transistor P2 is connected to a high level, and the drain of the second NMOS transistor N2 is grounded.

Preferably, the output terminal of the nand gate circuit D1 of the pre-decoding subunit 10 is further connected to the gate of the first NMOS transistor N1 of the level shifting subunit 20, so as to provide the first control signal wllb to the gate of the first NMOS transistor N1 of the level shifting subunit 20. Further, the output terminal of the not gate circuit S1 of the pre-decoding subunit 10 is further connected to the gate terminal of the second NMOS transistor N2 of the level shifting subunit 20, so as to provide the second control signal wll to the gate terminal of the second NMOS transistor N2 of the level shifting subunit 20.

Further, referring to fig. 4, fig. 4 is a circuit schematic diagram of a voltage transmission subunit according to an embodiment of the present invention, where each of the first to fourth voltage transmission subunits 30 includes: a first power supply VDP, a second power supply GWLS, a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3, and a fourth NMOS transistor N4. Wherein the gates of the third and fourth NMOS transistors N3 and P4 receive the third control signal wlh, and the gates of the third and fourth PMOS transistors P3 and N4 receive the fourth control signal wlhb.

In the first to fourth voltage transmitting sub-units 30, the third PMOS transistor P3 and the third NMOS transistor N3 are connected in parallel to form a transmission gate circuit. Further, the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected in parallel to form a transmission gate circuit. A parallel node between the third PMOS transistor P3 and one end of the third NMOS transistor N3 is connected to the first power supply VDP, and a parallel node between the fourth PMOS transistor P4 and one end of the fourth NMOS transistor N4 is connected to the second power supply GWLS; the parallel node at the other end of the third PMOS tube P3 and the other end of the third NMOS tube N3 is connected with the parallel node at the other end of the fourth PMOS tube P4 and the other end of the fourth NMOS tube N4, so that the connecting node position of the two outputs the SONOS line signal WLS to a post-stage circuit. In each group of the row decoding units, the 4 rows of pre-decoding subunits 10 and the 4 rows of voltage transmission subunits 30 share the middle 1 row of level shifting subunits 20, so that the number of the level shifting subunits 20 is reduced, namely, a certain number of transistors are reduced, the proportion of the area of a row decoding circuit to the whole area of a chip is reduced, the area of the chip is effectively saved, the size of a memory is reduced, and the cost is reduced.

The input and output signals, power distribution and corresponding control relationship of the routine decoding unit implemented by the invention are shown in the table I. Preferably, the first power supply VDP supplies 0V (or low level) and the second power supply GWLS supplies a first positive voltage (or high level) at the time of the erase operation. Further, in the program operation, the first power supply VDP supplies a first positive voltage (or high level), and the second power supply GWLS supplies a second positive voltage (e.g., 1V).

Watch 1

In this embodiment, as shown in table one, when the erase operation is performed and the address signal ABC is selected, the address signal is "111", each pre-decoding subunit 10 outputs the word line control signal Wl to the subsequent circuit (memory array), and at this time, the word line control signal Wl is logic high level "1", so as to select the word line of a certain row corresponding to the subsequent circuit (memory array). Each pre-decoding subunit 10 outputs the first control signal wllb and the second control signal wll to the level shifting subunit 20, and at this time, the first control signal wllb is at a logic low level "0" and the second control signal wll is at a logic high level "1", so that the first PMOS transistor P1 and the second NMOS transistor N2 of the level shifting subunit 20 are turned on. The level shift subunit 20 outputs the third control signal wlh and the fourth control signal wlhb to the voltage transmission subunit 30, at this time, the third control signal wlh is a logic high level "1", the fourth control signal wlhb is a logic low level "0", the corresponding third PMOS transistor P3 and third NMOS transistor N3 of the voltage transmission subunit 30 are turned on, and finally outputs the SONOS line signal WLS to the subsequent-stage memory array, the SONOS line signal WLS is a voltage provided by the first power supply VDP, at this time, the first power supply provides 0V (or low level), and then the memory cell of a specific row and a specific column in the subsequent-stage circuit (memory array) is selected according to the column decoding circuit to erase the stored data therein. Further, when the erase operation is performed and the memory cell is unselected, according to the address signal ABC, the address signal is "101", each pre-decoding subunit 10 outputs the word line control signal Wl to the subsequent circuit (memory array), and at this time, the word line control signal Wl is logic low level "0", so that the unselected subsequent circuit (memory array) corresponds to the word line of the memory cell in a certain row.

In this embodiment, as shown in table one, when a program operation is performed and selected, according to the address signal ABC, the address signal is "111", and each pre-decoding subunit 10 outputs the word line control signal Wl to a subsequent circuit (memory array), where the word line control signal Wl is at a logic high level "1", so as to select a word line of a certain row corresponding to the subsequent circuit (memory array). Each pre-decoding subunit 10 outputs the first control signal wllb and the second control signal wll to the level shifting subunit 20, and at this time, the first control signal wllb is at a logic low level "0" and the second control signal wll is at a logic high level "1", so that the first PMOS transistor P1 and the second NMOS transistor N2 of the level shifting subunit 20 are turned on. The level shift subunit 20 outputs the third control signal wlh and the fourth control signal wlhb to the voltage transmission subunit 30, at this time, the third control signal wlh is logic high level "1", the fourth control signal wlhb is logic low level "0", the corresponding third PMOS transistor P3 and third NMOS transistor N3 of the voltage transmission subunit 30 are turned on, and finally outputs the SONOS line signal WLS to the subsequent memory array, the SONOS line signal WLS is a voltage provided by the first power supply VDP, at this time, the first power supply provides a first positive voltage VPOS (or high level). Then, the memory cell of a specific row and a specific column in the next-stage circuit (memory array) is selected according to the column decoding circuit to program the memory cell. Further, when the programming operation is executed and the memory cell is unselected, according to the address signal ABC, the address signal is "101", each pre-decoding subunit 10 outputs the word line control signal Wl to the subsequent circuit (memory array), and at this time, the word line control signal Wl is logic low level "0", so that the unselected subsequent circuit (memory array) corresponds to the word line of the memory cell in a certain row.

Based on the same inventive concept, an embodiment of the present application further provides an EEPROM with a SONOS structure, including: the memory comprises a memory array, a column decoding circuit and a row decoding circuit, wherein the column decoding circuit provides a bit line control signal and a source line control signal for the memory array according to an input address signal; the row decoding circuit provides a word line control signal and a SONOS line signal to the memory array according to an input address signal.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.