阅读说明：本技术 陶瓷电子部件及其制造方法 (Ceramic electronic component and method for manufacturing same ) 是由 中村智彰 田原干夫 下田贞纪 于 2020-11-17 设计创作，主要内容包括：本申请提供一种陶瓷电子部件,其包括：层叠芯片,其具有大体上长方体形状,并且包括交替地层叠的电介质层和内部电极层,内部电极层交替地露出于层叠芯片的彼此面对的两个端面；以及一对外部电极,其分别形成在两个端面上,以便与露出于各自端面的内部电极层连接,每一个外部电极延伸到层叠芯片的至少一个侧面,其中在层叠芯片中,在将内部电极层与外部电极连接的连接部附近在内部电极层周围存在包含Zn和Ni的氧化物。(The present application provides a ceramic electronic component, comprising: a laminated chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately laminated, the internal electrode layers being alternately exposed to both end faces of the laminated chip that face each other; and a pair of external electrodes formed on both end faces so as to be connected to the internal electrode layers exposed at the respective end faces, each external electrode extending to at least one side face of the laminated chip, wherein in the laminated chip, an oxide containing Zn and Ni is present around the internal electrode layers in the vicinity of a connection portion connecting the internal electrode layers and the external electrodes.)

1. A ceramic electronic component comprising:

a laminated chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers alternately laminated, the internal electrode layers being alternately exposed to both end faces of the laminated chip facing each other; and

a pair of external electrodes formed on the two end surfaces, respectively, so as to be connected to the internal electrode layers exposed at the respective end surfaces, each external electrode extending to at least one side surface of the laminated chip,

wherein in the laminated chip, an oxide including Zn and Ni is present around the internal electrode layers in the vicinity of a connection portion connecting the internal electrode layers with the external electrodes.

2. The ceramic electronic component according to claim 1, wherein:

the external electrodes each include a base conductive layer and a plating layer thereon, and

in the internal electrode layers, a diffusion length of a main component of the base conductive layer measured from the end face inward along the internal electrode layers is 5 μm or less.

3. The ceramic electronic component according to claim 1 or 2, wherein an average thickness of the internal electrode layers is 0.5 μm or less.

4. A method of manufacturing a ceramic electronic component, comprising the steps of:

alternately stacking green sheets for ceramic dielectric layers and a first conductive paste for internal electrode layers so as to be alternately exposed to both end faces facing each other to form a ceramic laminate having a substantially rectangular parallelepiped shape, wherein the first conductive paste is mainly composed of Ni;

firing the ceramic laminate to form a laminated chip;

performing heat treatment on the laminated chip;

disposing a second conductive paste on each of both end faces of the laminated chip such that the second conductive paste is in contact with the internal electrode layer exposed to the corresponding end face, wherein the second conductive paste includes a metal powder and a glass component including 20 to 30 wt% of ZnO; and

baking the second conductive paste to form an oxide including Zn and Ni around each of the internal electrode layers in the vicinity of a connection portion between the internal electrode layers and the second conductive paste.

5. A method of manufacturing a ceramic electronic component, comprising the steps of:

alternately stacking green sheets for ceramic dielectric layers and a first conductive paste for internal electrode layers so as to be alternately exposed to both end faces facing each other to form a ceramic laminate having a substantially rectangular parallelepiped shape, wherein the first conductive paste is mainly composed of Ni;

firing the ceramic laminate to form a laminated chip;

disposing a second conductive paste on each of both end faces of the laminated chip such that the second conductive paste is in contact with the internal electrode layer exposed to the corresponding end face, wherein the second conductive paste includes a metal powder and a glass component including 20 to 30 wt% of ZnO; and

baking the second conductive paste while making the oxygen concentration in the temperature rise region 10ppm or more to form an oxide including Zn and Ni around each of the internal electrode layers in the vicinity of the connection portion between the internal electrode layers and the second conductive paste.

6. A method of manufacturing a ceramic electronic component, comprising the steps of:

alternately stacking green sheets for ceramic dielectric layers and a first conductive paste for internal electrode layers so as to be alternately exposed to both end faces facing each other to form a ceramic laminate having a substantially rectangular parallelepiped shape, wherein the first conductive paste is mainly composed of Ni;

firing the ceramic laminate to form a laminated chip;

applying a glass paste containing 20-30 wt% of ZnO to each of both end faces of the laminated chip;

baking the glass paste to form an oxide including Zn and Ni around each of the internal electrode layers adjacent to the two end faces;

disposing a second conductive paste on each of both end faces of the laminated chip so that the second conductive paste is in contact with an internal electrode layer exposed to the respective end face, wherein the second conductive paste contains a metal powder and a glass component; and

baking the second conductive paste.

Technical Field

Certain aspects of the present disclosure relate to ceramic electronic components and methods of making the same.

Background

In order to achieve a small size and a large capacitance of the laminated ceramic capacitor, thinning of the internal electrode layers and the dielectric layers has been promoted to increase the number of the laminated internal electrode layers and the dielectric layers, and thinning of the upper and lower cover layers has been promoted.

When the number of stacked internal electrode layers and dielectric layers is increased and the thickness of the cover layer is reduced, cracks may occur in the area where the cover layer, the side edges, and the end edges overlap when the external electrodes are baked. The side edges are regions from each of both side faces of the laminated chip to the internal electrode layers, and the end edges are regions where the internal electrode layers connected to the same external electrode face each other without interposing the internal electrode layer connected to another external electrode therebetween.

In order to suppress the occurrence of cracking, as disclosed in, for example, japanese patent application laid-open No. 2011-135079, the length (diffusion length) of a region where the metal component of the external electrode diffuses in the internal electrode layer is controlled.

Disclosure of Invention

When the baking temperature of the external electrode is lowered, the diffusion length of the metal component of the external electrode is reduced. However, the reduction in baking temperature may cause the reaction between the internal electrode layers and the external electrodes to not proceed sufficiently, and deteriorate the contact between the internal electrode layers and the external electrodes in combination with the reduction in thickness of the internal electrode layers (0.5 μm or less).

The invention provides a ceramic electronic component and a method for manufacturing the same, which can suppress the occurrence of cracks and improve the contact between internal electrode layers and external electrodes.

According to a first aspect of the embodiments, there is provided a ceramic electronic component including: a laminated chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately laminated, the internal electrode layers being alternately exposed to both end faces of the laminated chip that face each other; and a pair of external electrodes formed on both end faces so as to be connected to the internal electrode layers exposed at the respective end faces, each external electrode extending to at least one side face of the laminated chip, wherein in the laminated chip, an oxide containing Zn and Ni is present around the internal electrode layers in the vicinity of a connection portion connecting the internal electrode layers and the external electrodes.

According to a second aspect of the embodiments, there is provided a method of manufacturing a ceramic electronic component, including the steps of: alternately stacking green sheets for ceramic dielectric layers and a first conductive paste for internal electrode layers, the first conductive paste for internal electrode layers being alternately exposed at both end faces facing each other to form a ceramic stacked body having a substantially rectangular parallelepiped shape, wherein the first conductive paste is mainly composed of Ni; firing the ceramic laminate to form a laminated chip; performing heat treatment on the laminated chip; disposing a second conductive paste on each of both end faces of the laminated chip such that the second conductive paste is in contact with the internal electrode layer exposed to the corresponding end face, wherein the second conductive paste includes a metal powder and a glass component including 20 to 30 wt% of ZnO; and baking the second conductive paste to form an oxide containing Zn and Ni around each of the internal electrode layers in the vicinity of the connection portion between the internal electrode layers and the second conductive paste.

According to a third aspect of the embodiments, there is provided a method of manufacturing a ceramic electronic component, including the steps of: alternately stacking green sheets for ceramic dielectric layers and a first conductive paste for internal electrode layers, the first conductive paste for internal electrode layers being alternately exposed at both end faces facing each other to form a ceramic stacked body having a substantially rectangular parallelepiped shape, wherein the first conductive paste is mainly composed of Ni; firing the ceramic laminate to form a laminated chip; disposing a second conductive paste on each of both end faces of the laminated chip such that the second conductive paste is in contact with the internal electrode layer exposed to the corresponding end face, wherein the second conductive paste includes a metal powder and a glass component including 20 to 30 wt% of ZnO; and baking the second conductive paste while making the oxygen concentration in the temperature rise region 10ppm or more to form an oxide containing Zn and Ni around each internal electrode layer in the vicinity of the connection portion between the internal electrode layer and the second conductive paste.

According to a fourth aspect of the embodiment, there is provided a method of manufacturing a ceramic electronic component, including the steps of: alternately stacking green sheets for ceramic dielectric layers and a first conductive paste for internal electrode layers, the first conductive paste for internal electrode layers being alternately exposed at both end faces facing each other to form a ceramic stacked body having a substantially rectangular parallelepiped shape, wherein the first conductive paste is mainly composed of Ni; firing the ceramic laminate to form a laminated chip; applying a glass paste containing 20-30 wt% of ZnO to each of both end faces of the laminated chip; baking the glass paste to form an oxide containing Zn and Ni around each of the internal electrode layers adjacent to both end faces; disposing a second conductive paste on each of both end faces of the laminated chip such that the second conductive paste is in contact with the internal electrode layer exposed to the corresponding end face, wherein the second conductive paste contains a metal powder and a glass component; and baking the second conductive paste.

Drawings

Fig. 1 is a partially sectional perspective view of a laminated ceramic capacitor according to an embodiment;

fig. 2A is a partial sectional view taken along line a-a in fig. 1, fig. 2B is a partial sectional view taken along line B-B in fig. 1, and fig. 2C is an enlarged view of an area surrounded by a dotted line in fig. 2A;

FIG. 3 is a partial cross-sectional view taken along line A-A in FIG. 1;

fig. 4A and 4B are diagrams for describing the occurrence of cracking;

FIG. 5 is a flowchart of a method of manufacturing a laminated ceramic capacitor;

fig. 6A shows the relationship between the baking temperature and the diffusion length of Cu, and fig. 6B shows the relationship between the diffusion length of Cu and the incidence of cracking;

fig. 7 is a flowchart of a method of manufacturing a laminated ceramic capacitor according to a first modification of the embodiment; and is

Fig. 8 is a flowchart of a method of manufacturing a laminated ceramic capacitor according to a second modification of the embodiment.

Detailed Description

Hereinafter, a description will be given of embodiments with reference to the accompanying drawings.

[ embodiment ]

First, the laminated ceramic capacitor will be described. Fig. 1 is a partially sectional perspective view of a laminated ceramic capacitor 100 according to an embodiment. As shown in fig. 1, the laminated ceramic capacitor 100 includes: a laminated chip 10 having a rectangular parallelepiped shape; and external electrodes 20a and 20b respectively provided on both end faces of the laminated chip 10 facing each other. Four surfaces other than the two end surfaces of the laminated chip 10 are referred to as side surfaces. The external electrodes 20a and 20b extend to four sides. However, the external electrodes 20a and 20b are spaced apart from each other on four sides.

The laminated chip 10 has a structure designed to have dielectric layers 11 and internal electrode layers 12 alternately laminated. The dielectric layer 11 contains a ceramic material serving as a dielectric material. The edges of the internal electrode layers 12 are alternately exposed at a first end face of the laminated chip 10 and a second end face of the laminated chip 10 different from the first end face. The external electrode 20a is provided on the first end face. The external electrode 20b is disposed on the second end face. Therefore, the internal electrode layers 12 are alternately electrically connected to the external electrodes 20a and the external electrodes 20 b. In the laminated chip 10, the cover layers 13 are formed on two side surfaces corresponding to the upper surface and the lower surface in the direction in which the dielectric layers 11 and the internal electrode layers 12 are laminated (hereinafter referred to as the lamination direction) among the four side surfaces. The cover layer 13 consists essentially of a ceramic material. For example, the main component of the cover layer 13 is the same as that of the dielectric layer 11.

For example, the laminated ceramic capacitor 100 may have a length of 0.25mm, a width of 0.125mm, and a height of 0.125 mm. The laminated ceramic capacitor 100 may have a length of 0.4mm, a width of 0.2mm, and a height of 0.2 mm. The laminated ceramic capacitor 100 may have a length of 0.6mm, a width of 0.3mm, and a height of 0.3 mm. The laminated ceramic capacitor 100 may have a length of 1.0mm, a width of 0.5mm, and a height of 0.5 mm. The laminated ceramic capacitor 100 may have a length of 3.2mm, a width of 1.6mm, and a height of 1.6 mm. The laminated ceramic capacitor 100 may have a length of 4.5mm, a width of 3.2mm, and a height of 2.5 mm.

The dielectric layer 11 is mainly composed of a material having the general formula ABO₃The perovskite-structured ceramic material composition is shown. The perovskite structure comprises an ABO having a non-stoichiometric composition_3-α. Examples of such ceramic materials include, but are not limited to, barium titanate (BaTiO)₃) Calcium zirconate (CaZrO)₃) Calcium titanate (CaTiO)₃) Strontium titanate (SrTiO)₃) Heyu toolBa having perovskite structure_1-x-yCa_xSr_yTi_{1- z}Zr_zO₃(x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1). The average thickness of the dielectric layer 11 is, for example, 1 μm or less.

The internal electrode layers 12 are mainly composed of nickel (Ni). The average thickness of the internal electrode layers 12 is, for example, 1 μm or less.

Fig. 2A is a partial sectional view taken along line a-a in fig. 1, fig. 2B is a partial sectional view taken along line B-B in fig. 1, and fig. 2C is an enlarged view of an area surrounded by a dotted line in fig. 2A. As shown in fig. 2A, in at least a part of a region where the internal electrode layers 12 connected to the same external electrode face each other without interposing therebetween the internal electrode layer 12 connected to another external electrode, an oxide 40 containing zinc (Zn) and Ni is present in the vicinity of the upper surface and the lower surface of each of the internal electrode layers 12. In addition, as shown in fig. 2B, in at least a part of a region where the internal electrode layers 12 connected to the same external electrode face each other without interposing therebetween the internal electrode layer 12 connected to another external electrode, an oxide 40 is present in the vicinity of the side face of each of the internal electrode layers 12. That is, the oxide 40 containing Zn and Ni exists around the internal electrode layer 12 in the vicinity of the connection portions between the external electrodes 20a, 20b and the internal electrode layer 12. Due to the presence of the oxide 40, adhesion between the internal electrode layers 12 and the dielectric layers 11 is improved, and penetration of water or the like is suppressed. Therefore, the reliability of moisture resistance of the laminated ceramic capacitor 100 is improved. The presence of Zn and Ni around the inner electrode layers 12 in the vicinity of the connection portions between the outer electrodes 20a, 20b and the inner electrode layers 12 can be confirmed by elemental mapping of energy dispersive X-ray spectroscopy (EDX). The Zn and Ni can be confirmed as oxides using a Scanning Electron Microscope (SEM) or a metallographic microscope.

In addition, the internal electrode layer 12 has a region 12a (hereinafter referred to as a diffusion region of Cu) where a main component (copper (Cu) in this embodiment) of the base conductive layer 21 of the external electrodes 20a, 20b diffuses. The region 12a extends from the connection between the external electrodes 20a, 20b and the internal electrode layers 12 toward the internal electrode layers 12. The length L of the diffusion region 12a in the direction in which the two end faces of the stacked chip 10 face each other (i.e., the diffusion length) is 5 μm or less. The length L of the diffusion region 12a of Cu can be measured according to a Cu map photograph of EDX. In the Cu map photograph of the cross section presented in fig. 2C, the distance from the external electrode to the position farthest from the external electrode among the positions where Cu is observed is defined as the length L of the diffusion region 12a of Cu. For example, the length L of the diffusion region 12a of Cu is measured for each of five internal electrodes at different positions in the lamination direction of one product, and the average of the lengths L in the five internal electrodes may be determined as the length L of the diffusion region 12a of Cu.

Fig. 3 is a sectional view of the external electrode 20b, and is a partial sectional view taken along line a-a in fig. 1. In fig. 3, hatching for indicating the cross section is omitted. The ceramic material is mainly exposed to the surface of the laminated chip 10. Therefore, it is difficult to form a plating layer without a base layer on the surface of the laminated chip 10. Therefore, as shown in fig. 3, the external electrode 20b has a structure in which a plating layer is formed on the base conductive layer 21, the base conductive layer 21 being formed on the surface of the laminated chip 10. The plating layers include a first plating layer 22 that is in contact with the base conductive layer 21 and covers the base conductive layer 21, and a second plating layer 23 that is in contact with the first plating layer 22 and covers the first plating layer 22. A base plating layer may be interposed between the base conductive layer 21 and the first plating layer 22. The base conductive layer 21 is mainly composed of a metal such as Cu, Ni, aluminum (Al), Zn, silver (Ag), gold (Au), palladium (Pd), or platinum (Pt), or an alloy of two or more of them (for example, an alloy of Cu and Ni), and contains a glass component for densifying the base conductive layer 21 and a ceramic such as a common material for controlling the sinterability of the base conductive layer 21. The glass component is an oxide of barium (Ba), strontium (Sr), calcium (Ca), Zn, Al, silicon (Si), or boron (B). The common material is a ceramic component mainly composed of the same material as the main component of the dielectric layer 11. The plating layer is mainly composed of a metal such as Cu, Ni, Al, Zn, or tin (Sn), or an alloy of two or more of them. The first plating layer 22 is, for example, a Ni plating layer, and the second plating layer 23 is, for example, a Sn plating layer.

The laminated ceramic capacitor 100 according to the present embodiment includes a laminated chip 10 and a pair of external electrodes 20a and 20b, the pair of external electrodes 20a and 20b being formed from both end faces of the laminated chip 10 facing each other to at least one side face of the laminated chip 10. The laminated chip 10 has a substantially rectangular parallelepiped shape, and includes dielectric layers 11 mainly composed of ceramic and internal electrode layers 12 mainly composed of Ni alternately laminated. The stacked internal electrode layers 12 are formed so as to be alternately exposed at both end surfaces. Around the internal electrode layer 12, an oxide 40 containing Zn and Ni exists in the vicinity of the connection portion between the internal electrode layer 12 and the external electrodes 20a, 20 b. Since the oxide 40 containing Zn and Ni is formed around the internal electrode layers 12, adhesion between the internal electrode layers 12 and the dielectric layers 11 is improved, and thus permeation of water is suppressed. Therefore, the reliability of moisture resistance of the laminated ceramic capacitor 100 is improved.

In the internal electrode layers 12, as the length of the diffusion region 12a in which Cu as the main component of the base conductive layer 21 diffuses in the direction in which both end faces face each other increases, the discontinuous portions (discontinuous portions) of Ni as the main component of the internal electrode layers 12 are filled with the diffused Cu. Therefore, the continuity of the internal electrode layers 12 is improved. However, as the length of the diffusion region 12a in the direction in which the both end faces face each other increases, the volume expansion of the internal electrode layer 12 increases. Thus, cracking is more likely to occur. Therefore, in the internal electrode layer 12, the length of the diffusion region 12a in which Cu as a main component of the base conductive layer 21 diffuses in the facing direction of both end faces is preferably 5 μm or less, more preferably 3 μm or less.

By reducing the average thickness of the internal electrode layers 12 and increasing the number of internal electrode layers 12 laminated, the capacitance of the laminated ceramic capacitor 100 can be increased. In addition, by reducing the average thickness of the internal electrode layers 12 without changing the number of the internal electrode layers 12 to be laminated, the size of the laminated ceramic capacitor 100 can be reduced. Therefore, the average thickness of the internal electrode layers 12 is preferably 0.5 μm or less, and more preferably 0.3 μm or less.

In the manufacturing process of the laminated ceramic capacitor 100, when the external electrodes 20a and 20B are baked, as shown in fig. 4A and 4B, a crack 30 may occur in a portion where the cover layer 13, the side edge 16, and the end edge 15 overlap. It is considered that this is because the internal electrode layers 12 react with the external electrodes 20a and 20B during baking, and Cu as a metal component of the external electrodes 20a and 20B diffuses to the internal electrode layers 12, and the internal electrode layers 12 expand, resulting in outward stress in the side edges 16 and the end edges 15, as indicated by arrows in fig. 4A and 4B. Fig. 4A corresponds to a section taken along line a-a in fig. 1, and fig. 4B corresponds to a section taken along line B-B in fig. 1. As shown in fig. 4A, the end edge 15 is a region where the internal electrode layers 12 connected to the external electrode 20a face each other without interposing therebetween the internal electrode layers 12 connected to the external electrode 20b, and a region where the internal electrode layers 12 connected to the external electrode 20b face each other without interposing therebetween the internal electrode layers 12 connected to the external electrode 20 a. The side edges 16 are regions from both sides of the laminated chip 10 to the internal electrode layers 12, as shown in fig. 4B.

A description will now be given of a method of manufacturing the laminated ceramic capacitor 100, which can suppress the occurrence of cracks due to diffusion of metal components of the external electrodes 20a and 20b during baking of the external electrodes 20a and 20b and improve the contact between the internal electrode layer 12 and the external electrodes 20a and 20 b. Fig. 5 is a diagram illustrating a method of manufacturing the laminated ceramic capacitor 100.

[ Process for producing raw Material powder (S1) ]

The additive compound is added to the powder of the ceramic material, which is a main component of the dielectric layer 11, according to the purpose. The additive compound may be an oxide of magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr) or rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium (Yb)), or an oxide of cobalt (Co), Ni, lithium (Li), B, sodium (Na), potassium (K) and Si, or glass. For example, a compound comprising an additive compound is added to a ceramic material powder and calcined. Next, the resulting ceramic material particles are wet mixed with the additive compound, dried and crushed. Thereby, a ceramic material powder is prepared.

[ laminating step (S2) ]

Next, a binder such as a polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained ceramic material powder, and wet mixing is performed. Using the slurry thus obtained, a dielectric green sheet in a stripe shape having a thickness of 1.0 μm or less is coated on a substrate by, for example, a die coater method or a doctor blade method, and then dried.

Then, a conductive paste for the internal electrode layers is printed by using screen printing or gravure printing, thereby providing a pattern of the internal electrode layers 12 on the surface of the dielectric green sheet. The conductive paste for the internal electrode layers contains powder of Ni as a main component metal of the internal electrode layers 12, a binder, a solvent, and additives as needed. The binder and the solvent are preferably different from those of the above-described ceramic slurry. As the co-material, a ceramic material as a main component of the dielectric layer 11 may be dispersed in the conductive paste for the internal electrode layer.

Then, the dielectric green sheets on which the internal electrode layer patterns are printed are punched out into a predetermined size, and a predetermined number (for example, 200 to 500) of the punched-out dielectric green sheets are stacked while peeling off the base material so that the internal electrode layers 12 and the dielectric layers 11 alternate with each other, and the end edges of the internal electrode layers 12 are alternately exposed to both end surfaces in the longitudinal direction of the dielectric layers so as to be alternately led out to a pair of external electrodes of different polarities. The cover sheet to be the cover layer 13 is pressed on top of and below the laminated green sheet. The obtained molded body was cut into a predetermined size (for example, 1.0 mm. times.0.5 mm). Through the above process, a ceramic laminate having a substantially rectangular parallelepiped shape is obtained.

[ firing Process (S3) ]

At a firing temperature of about 1100 ℃ to 1400 ℃, in a furnace containing, for example, about 1.0 vol.% H₂The obtained ceramic laminate is fired in a reducing atmosphere for about 2 hours. Through this process, the laminated chip 10 is obtained in which the fired dielectric layers 11 and the fired internal electrode layers 12 are alternately laminated, and the cover layers 13 are formed as the outermost layers of the laminated chip 10 in the lamination direction. In order to suppress deterioration of temperature characteristics due to excessive firing, the firing temperature is preferably 1100 ℃ to 1200 ℃.

[ reoxidation step (S4) ]

Can be in the temperature range of 600 ℃ to 1000 ℃ in N₂The obtained fired body was subjected to a re-oxidation step in an atmosphere.

[ Heat treatment Process (S5) ]

Then, the laminated chip 10 is heat-treated at a temperature of 600 to 700 ℃ in an air atmosphere. This process partially oxidizes the end faces of the internal electrode layers 12 exposed at both end faces of the laminated chip 10. That is, an oxide of Ni, which is a main component of the internal electrode layers 12, is formed on the end faces of the internal electrode layers 12.

[ Process for Forming external electrode (S6) ]

Then, a conductive paste for the base conductive layer is applied to each of the two end faces of the stacked chip 10 after the heat treatment process, at which the internal electrode layer pattern is exposed. The conductive paste for the base conductive layer contains a powder of a main component metal (Cu in this embodiment) of the base conductive layer 21, a glass component, a binder, a solvent, and other auxiliaries as needed. The binder and the solvent may be the same as those of the above-described ceramic paste. The glass component contains 20 to 30 wt% of ZnO when the total weight of the glass component is defined as 100 wt%. In addition, the glass component comprises one or more compounds selected from B₂O₃And SiO₂The network of (a) forms an oxide. The glass component may comprise one or more elements selected from Al₂O₃、CuO、Li₂O、Na₂O、K₂O、MgO、CaO、BaO、ZrO₂And TiO₂The network modified oxide of (1).

The reason why the ratio of ZnO is 20 to 30 wt% is that Zn easily reacts with an oxide of Ni formed on the end face of the internal electrode layer 12 by heat treatment, and an oxide containing Zn and Ni is formed around the internal electrode layer 12 during baking of the underlying conductive layer 21 described later. Forming oxides containing Zn and Ni around the internal electrode layers 12 allows the glass component of the conductive paste for the base conductive layer to be blended with the internal electrode layers 12. Thereby, the Ni particles of the internal electrode layers 12 and the Cu particles of the base electrode layers 21 wet each other, and thereby, the internal electrode layers 12 and the base conductive layers 21 easily react with each other. Therefore, the contact between the internal electrode layers 12 and the external electrodes 20a and the contact between the internal electrode layers 12 and the external electrodes 20b are improved.

Then, the laminated chip 10 applied with the conductive paste for the base conductive layer is baked in a nitrogen atmosphere at a temperature of about 770 ℃ or less. Through this process, the base conductive layer 21 is baked, and a semi-finished product of the laminated ceramic capacitor 100 is obtained. Here, the reason why the baking temperature of the base conductive layer 21 is preferably about 770 ℃ or less will be described.

Fig. 6A shows the relationship between the baking temperature of the base conductive layer 21 and the length L (diffusion length) of the diffusion region 12a of Cu formed in the internal electrode layer 12. The baking temperature is the highest temperature during baking. As shown in fig. 6A, as the baking temperature becomes higher, the diffusion length of Cu becomes longer. Fig. 6B shows the relationship between the length L (diffusion length) of the diffusion region 12a of Cu and the crack occurrence rate of the products 1 to 3 of the laminated ceramic capacitors having different sizes. As shown in fig. 6B, when the diffusion length was 5 μm or less, the crack occurrence rate was 0% in all the products. Therefore, the temperature at which the diffusion length is 5 μm or less (about 770 ℃ or less) is preferably set to the baking temperature of the base conductive layer 21.

Then, a first plating layer 22 is formed on the base conductive layer 21 of the semi-finished product by electroplating. Further, the second plating layer 23 is formed on the first plating layer 22 by electroplating.

In the manufacturing method of the present embodiment, the laminated chip 10 is heat-treated at a temperature of 600 to 700 ℃ in an air atmosphere to partially oxidize the end faces of the internal electrode layers 12 exposed at both end faces of the laminated chip 10. In addition, the conductive paste for the conductive layer of the base is mainly composed of Cu and contains a glass component. The glass component contains 20 to 30 wt% of ZnO when the total weight of the glass component is defined as 100 wt%. Therefore, during baking of the external electrodes 20a and 20b (specifically, the base conductive layer 21), the oxide 40 containing Zn and Ni is formed around the internal electrode layer 12 in the vicinity of the connection portion between the internal electrode layer 12 and the external electrodes 20a and 20 b. This makes it easy for the glass component of the conductive paste for the base conductive layer to blend with the internal electrode layers 12, thereby wetting the Ni particles of the internal electrode layers 12 and the Cu particles of the external electrodes 20a, 20b (base conductive layer 21) with each other. Therefore, the internal electrode layer 12 and the external electrodes 20a and 20b easily react with each other. Therefore, even when the length of the diffusion region 12a of Cu is reduced, that is, even when the baking temperature of the external electrodes 20a and 20b is lowered, the contact between the internal electrode layer 12 and the external electrodes 20a and 20b is improved. In addition, forming the oxide 40 containing Zn and Ni around the internal electrode layers 12 improves adhesion between the internal electrode layers 12 and the dielectric layers 11. Therefore, the penetration of water is suppressed, and therefore, the moisture resistance reliability of the laminated ceramic capacitor 100 is improved.

[ first modification ]

Next, a method of manufacturing the laminated ceramic capacitor 100 according to the first modification of the embodiment will be described. Fig. 7 is a flowchart of a method of manufacturing the laminated ceramic capacitor 100 according to the first modification. Here, only the steps different from the manufacturing method of the laminated ceramic capacitor 100 shown in fig. 5 will be described, and the description of the other steps will be omitted.

[ Process for Forming external electrode (S6') ]

In the first modification, heat treatment in an air atmosphere is not performed before forming the external electrode. In the first modification, after firing or reoxidation, a conductive paste for a base conductive layer is applied to both end faces of the laminated chip 10 where the internal electrode layer patterns are exposed. The conductive paste for the base conductive layer contains a powder of Cu as a main component metal of the base conductive layer 21, a glass component, a binder, a solvent, and other additives as needed. The binder and the solvent may be the same as those of the above-described ceramic paste. The glass component contains 20 to 30 wt% of ZnO when the total weight of the glass component is defined as 100 wt%.

Then, the laminated chip 10 applied with the conductive paste for the base conductive layer is baked in a nitrogen atmosphere at a temperature of about 770 ℃ or less. During baking, the oxygen concentration in the heating region is set to 10ppm or more. This causes the oxide 40 containing Zn and Ni to be formed around the internal electrode layer 12 in the vicinity of the connection portion between the internal electrode layer 12 and the external electrodes 20a, 20 b.

In the manufacturing method of the first modification, a conductive paste for a base conductive layer mainly composed of Cu and containing a glass component (which contains 20 to 30 wt% of ZnO) is applied to both end faces of the laminated chip 10 where the internal electrode layer patterns are exposed. Then, the laminated chip 10 applied with the conductive paste for the base conductive layer is baked in a nitrogen atmosphere at a temperature of about 770 ℃ or less. During baking, the oxygen concentration in the heating region is set to 10ppm or more. This allows the oxide 40 containing Zn and Ni to be formed around the internal electrode layer 12 in the vicinity of the connection between the internal electrode layer 12 and the external electrodes 20a, 20b, thereby allowing the glass component of the conductive paste for the underlying conductive layer to be easily blended with the internal electrode layer 12. Therefore, the Ni particles of the internal electrode layer 12 and the Cu particles of the external electrodes 20a, 20b (base conductive layer 21) wet each other, and this makes the internal electrode layer 12 and the external electrodes 20a, 20b easily react with each other. Therefore, even when the length of the diffusion region 12a of Cu is reduced, that is, even when the baking temperature of the external electrodes 20a, 20b is lowered, the contact between the internal electrode layer 12 and the external electrodes 20a, 20b is improved. In addition, forming the oxide 40 containing Zn and Ni around the internal electrode layers 12 improves adhesion between the internal electrode layers 12 and the dielectric layers 11. Therefore, the penetration of water is suppressed, and therefore, the moisture resistance reliability of the laminated ceramic capacitor 100 is improved.

[ second modification ]

Next, a method of manufacturing the laminated ceramic capacitor 100 according to the second modification will be described. Fig. 8 is a flowchart of a manufacturing method of the laminated ceramic capacitor 100 according to the second modification. Only the steps different from the manufacturing method of the laminated ceramic capacitor 100 shown in fig. 5 will be described, and the description of the other steps will be omitted.

[ Process for applying glass paste (S7) ]

As shown in fig. 8, before the external electrode forming process, a glass paste containing a glass component is applied in a thin layer to each of both end faces (end faces on which the external electrodes 20a and 20b are to be formed) of the laminated chip 10. Through this process, the glass paste is applied to the end faces of the internal electrode layers 12. Herein, the glass component includes 20 to 30% by weight of ZnO, when the total weight of the glass component is defined as 100% by weight.

[ baking Process (S8) ]

Then, the glass paste is baked at a temperature of 600 to 700 ℃. Through this process, the oxide 40 containing Zn and Ni is formed around the internal electrode layer 12 in the vicinity of the connection portion between the internal electrode layer 12 and the external electrodes 20a, 20 b.

[ Process for Forming external electrode (S6) ]

The conductive paste for the base conductive layer is applied to each of both end faces of the laminated chip 10 on which the glass paste is baked. The conductive paste for the base conductive layer contains a powder of Cu as a main component metal of the base conductive layer 21, a glass component, a binder, a solvent, and other additives as needed. The binder and the solvent may be the same as those of the above-described ceramic paste. In the second modification, there is no particular limitation on the ratio of ZnO contained in the glass component of the conductive paste for the base conductive layer. Then, the laminated chip 10 applied with the conductive paste for the base conductive layer is baked in a nitrogen atmosphere at a temperature of about 770 ℃ or less. Through this process, the base conductive layer 21 is baked, and a semi-finished product of the laminated ceramic capacitor 100 is obtained. Then, a first plating layer 22 is formed on the base conductive layer 21 of the semi-finished product by electroplating. Further, the second plating layer 23 is formed on the first plating layer 22 by electroplating.

In the manufacturing method of the second modification, before the external electrodes 20a and 20b are formed, a glass paste containing a glass component (which contains 20 to 30 wt% of ZnO) is applied to the end faces of the internal electrode layers 12, and then baked. Therefore, as compared with the manufacturing method shown in fig. 5, the oxide made of Ni and Zn is formed uniformly around the internal electrode layer 12. Therefore, the contact between the internal electrode layer 12 and the external electrodes 20a, 20b can be improved.

In the above-described embodiments and modifications, the laminated ceramic capacitor is described as an example of the ceramic electronic component, but this is not intended to suggest any limitation. For example, the ceramic electronic component may be other electronic components such as a varistor and a thermistor.

[ examples ]

The laminated ceramic capacitor of the embodiment was manufactured, and the characteristics were examined.

[ example 1]

In example 1, barium titanate was used as a main component ceramic of the dielectric layer 11. The additive compound is added to the barium titanate powder. The obtained barium titanate powder was thoroughly wet-mixed and pulverized in a ball mill. Thus, a dielectric material is obtained. An organic binder and a solvent are added to the dielectric material, and a dielectric green sheet is produced by a doctor blade method. The organic binder is polyvinyl butyral (PVB) resin or the like. The solvent is ethanol, toluene, etc. If necessary, a plasticizer or the like is added. Then, a conductive paste for the internal electrode layer was prepared. The conductive paste for the internal electrode layers contains a powder of the metal Ni, which is the main component of the internal electrode layers 12, a binder, a solvent, and other additives as needed. A conductive paste for the internal electrode layers was screen-printed on the dielectric sheet. Five hundred sheets of dielectric sheets each printed with a conductive paste for internal electrode layers thereon were stacked, and cover sheets were stacked on top of and below the dielectric sheets. Thereafter, a ceramic laminate is obtained by heating and pressing, and is cut into a predetermined shape. In N₂After the binder is removed from the obtained ceramic laminate in an atmosphere, the obtained ceramic laminate is fired to obtain the laminated chip 10. The laminated chip 10 has a length of 1.6mm, a width of 0.8mm, and a height of 0.8 mm.

The resulting laminated chip 10 is subjected to heat treatment at a temperature of 600 to 700 ℃ in an air atmosphere.

After the heat treatment, a conductive paste for a base conductive layer containing a Cu filler, a glass component, a binder, and a solvent is applied to the laminated chip 10, and then dried. The ratio of the weight of ZnO with respect to the total weight of the glass component was 23 wt%. Thereafter, the conductive paste for the base conductive layer was baked at 760 ℃ for 10 minutes in a nitrogen atmosphere. The oxygen concentration in the temperature rising region during baking of the conductive paste for the conductive layer of the substrate is made lower than 1 ppm.

Thereafter, a Ni plating layer is formed as a first plating layer 22 on the base conductive layer 21 by electroplating, and a Sn plating layer is formed as a second plating layer 23 on the first plating layer 22 by electroplating. 400 samples of example 1 were made.

[ example 2]

In example 2, the stacked chip 10 after firing was not heat-treated in an air atmosphere. Therefore, in example 2, the conductive paste for the base conductive layer is applied to the stacked chip 10 after firing, and then dried. In example 2, the oxygen concentration in the temperature rising region during baking of the conductive paste for the base conductive layer was made 10 ppm. Other conditions were the same as in example 1. 400 samples of example 2 were made.

The composition of the glass component and the oxygen concentration in the heating region during baking of the conductive paste for the conductive layer of the substrate are presented in table 1.

[ Table 1]

In comparative example 1, in the glass component contained in the conductive paste for the base conductive layer, the ratio of the weight of ZnO with respect to the total weight of the glass component was 11 wt%, and the laminated chip 10 after firing was not subjected to heat treatment in an air atmosphere. Other conditions were the same as in example 1. In comparative example 2, in the glass component contained in the conductive paste for the base conductive layer, the ratio of the weight of ZnO with respect to the total weight of the glass component was 11 wt%, and other conditions were the same as in example 1. In comparative example 3, in the glass component contained in the conductive paste for the base conductive layer, the ratio of the weight of ZnO with respect to the total weight of the glass component was 11 wt%, and other conditions were the same as in example 2. For each of comparative examples 1-3, 400 samples were made.

For examples 1 and 2 and comparative examples 1 to 3, the length of the diffusion region 12a of Cu was measured. In addition, the formation of oxides made of Zn and Ni and the incidence of capacitance reduction were examined. Furthermore, a moisture resistance reliability test was performed. For the capacitance reduction, the number of samples whose capacitance became less than 80% of the desired capacitance was examined. In the moisture resistance reliability test, a withstand voltage test of 10V was performed for 400 hours under conditions of a temperature of 85 ℃ and a relative humidity of 85%, and the number of abnormal samples in which the insulation resistance value became 1M Ω or less was examined. The results are presented in table 2.

In any of examples 1 and 2 and comparative examples 1 to 3, the length of the Cu diffusion region 12a was 5 μm or less. In example 1 and example 2, formation of an oxide containing Zn and Ni was observed. However, in comparative examples 1 to 3, formation of an oxide containing Zn and Ni was not observed.

In comparative examples 1 to 3, a decrease in capacitance occurred. This is considered to be because, in comparative examples 1 to 3, since oxides including Zn and Ni are not formed, the reaction between the internal electrode layer 12 and the external electrodes 20a, 20b does not proceed sufficiently, and the contact between the internal electrode layer 12 and the external electrodes 20a and 20b is deteriorated. On the other hand, in embodiment 1 and embodiment 2, the occurrence of the decrease in capacitance was reduced to 0/400. This is considered to be because, since the oxide containing Zn and Ni is formed, the internal electrode layer 12 and the external electrodes 20a, 20b easily react with each other, and the contact between the internal electrode layer 12 and the external electrodes 20a and 20b is improved even if the baking temperature is low.

For each of comparative example 1 and comparative example 2, the number of abnormal samples in the moisture resistance reliability test was two. On the other hand, in example 1 and example 2, the number of abnormal samples was zero. It is considered that this is because in examples 1 and 2, since the oxides containing Zn and Ni were formed around the internal electrode layers 12, the adhesion between the internal electrode layers 12 and the dielectric layers 11 was improved, and thus the permeation of water was suppressed.

[ Table 2]

[ example 3]

The laminated chip 10 fired without forming the external electrodes was prepared. The laminated chip 10 has a length of 1.6mm, a width of 0.8mm, and a height of 0.8 mm.

A glass paste containing a glass component containing 23 wt% of ZnO is applied in a thin layer to the end face of the laminated chip 10, and then baked at a temperature of 600 to 700 ℃.

A conductive paste for a base conductive layer containing a Cu filler, a glass component, a binder, and a solvent is applied to the end face of the laminated chip 10, and then dried. The ratio of the weight of ZnO in the conductive paste for the conductive layer of the substrate to the total weight of the glass component was 11 wt%.

Thereafter, the conductive paste for the conductive layer of the substrate was fired at 760 ℃ for 10 minutes in a nitrogen atmosphere. The composition of the glass component and the oxygen concentration in the heating region during baking of the conductive paste for the conductive layer of the substrate are presented in table 3.

[ Table 3]

Thereafter, a first plating layer 22 is formed on the base conductive layer 21 by electroplating, and then a second plating layer 23 is formed on the first plating layer 22 by electroplating. 400 samples of example 3 were made.

In comparative example 4, no glass paste was applied. Other conditions were the same as in example 3. 400 samples of comparative example 4 were produced.

For each of example 3 and comparative example 4, the formation of oxides made of Zn and Ni and the incidence of capacitance reduction were examined. Furthermore, a moisture resistance reliability test was performed.

The results are presented in table 4. In example 3, formation of an oxide including Zn and Ni was observed, but in comparative example 4, formation of an oxide including Zn and Ni was not observed. In comparative example 4, a decrease in capacitance occurred. It is considered that this is because, in comparative example 4, since the oxide containing Zn and Ni is not formed, the reaction between the internal electrode layer 12 and the external electrodes 20a, 20b does not sufficiently proceed, and thus the contact between the internal electrode layer 12 and the external electrodes 20a and 20b deteriorates. On the other hand, in embodiment 3, the occurrence of the decrease in capacitance is reduced to 0/400. It is considered that this is because, since the oxide containing Zn and Ni is formed, the internal electrode layer 12 and the external electrodes 20a and 20b easily react with each other, and the contact between the internal electrode layer 12 and the external electrodes 20a and 20b is improved even if the baking temperature is low.

In comparative example 4, the number of abnormal samples in the moisture resistance reliability test was two. On the other hand, in example 3, the number of abnormal samples was zero. It is considered that this is because in example 3, since the oxide containing Zn and Ni is formed around the internal electrode layers 12, the adhesion between the internal electrode layers 12 and the dielectric layers 11 is improved, and thereby the penetration of water is suppressed.

[ Table 4]

	Example 3	Comparative example 4
			Forming an oxide containing Zn and Ni	Observe that	Not observed
Capacitance reduction	0/400	3/400
			Moisture resistance reliability test	0/400	2/400

Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.