Guiding uncertainty-awareness policy optimization: combining model-free and model-based strategies for efficient sample learning

文档序号：573840 发布日期：2021-05-21 浏览：3次中文

阅读说明：本技术 引导不确定性-意识策略优化：结合无模型和基于模型的策略用于有效采样学习 (Guiding uncertainty-awareness policy optimization: combining model-free and model-based strategies for efficient sample learning ) 是由 J·特伦布莱 D·福克斯 M·李 C·弗洛伦萨 N·D·拉特里夫 A·加尔格 F·T·拉于 2020-11-20 设计创作，主要内容包括：本申请涉及引导不确定性-意识策略优化：结合无模型和基于模型的策略用于有效采样学习的技术。使用基于模型和无模型的控制方法的结合来控制机器人。在一些示例中,基于模型的方法使用机器人周围环境的物理模型来引导机器人。使用诸如相机的感知系统来定向物理模型。感知系统的特征可以用于确定模型的不确定性。至少部分地基于该不确定性,系统从基于模型的方法过渡到无模型的方法中,在一些实施例中,直接从感知系统提供的信息被用于指导机器人而不依赖于物理模型。(The present application relates to guiding uncertainty-aware policy optimization: techniques for efficient sample learning that combine modeless and model-based strategies. The robot is controlled using a combination of model-based and model-free control methods. In some examples, the model-based approach uses a physical model of the robot's surroundings to guide the robot. The physical model is oriented using a perception system such as a camera. The characteristics of the perception system can be used to determine the uncertainty of the model. Based at least in part on this uncertainty, the system transitions from a model-based approach to a model-free approach, and in some embodiments, information provided directly from the perception system is used to guide the robot without relying on a physical model.)

1. A computer-implemented method, comprising:

moving the robot into an area controlled using a first method of the physical model based at least in part on information from the first perception system;

determining an uncertainty of the information produced by the first perception system;

determining that the robot is in the area based at least in part on the uncertainty;

as a result of determining that the robot is in the area, the robot is moved to perform a task under control of a second method that uses information generated by a second perception system.

2. The method of claim 1, wherein the second method is independent of the physical model.

3. The method of claim 2, wherein the second method is a model-less method.

4. The method of claim 1, wherein the first method is a model-based method.

5. The method of claim 1, wherein:

the first perception system is a stationary camera; and

the second perception system is a camera mounted on the robot.

6. The method of claim 1, further comprising determining the region based at least in part on the uncertainty of the information.

7. The method of claim 1, further comprising:

determining that the robot is outside the area; and

as a result of determining that the robot is outside the area, moving the robot into the area using the first method.

8. The method of claim 1, wherein the uncertainty is a non-parametric distribution of a plurality of poses of the region and an associated weight for each pose.

9. The method of claim 1, wherein the uncertainty is a parameter distribution.

10. The method of claim 1, wherein the region is a sub-region of a region in which the second method is available to compete for tasks.

11. The method of claim 1, wherein the second method is performed using an auto-encoder trained to complete a task given input from the second perceptual system.

12. A computer system, comprising:

one or more processors; and

computer-readable memory storing executable instructions that, as a result of execution by one or more processors, cause the computer system to:

moving the robot to an area using a model of the environment of the robot, the model oriented using image data from the first camera;

determining an uncertainty of the model using uncertainty information associated with the first camera;

determining that the robot is in the region based at least in part on an uncertainty of the model; and

as a result of determining that the robot is in the area, performing a task using the robot under control of a machine learning system trained using image data from a second camera.

13. The computer system of claim 12, wherein the second camera is a wrist camera on a robot.

14. The computer system of claim 12, wherein the computer system uses results of the task to update the uncertainty of the model as a result of completing the task.

15. The computer system of claim 14, wherein the result of the task indicates a pose of the model.

16. The computer system of claim 12, wherein the model is oriented by processing at least the image data from the first camera using a depth object pose estimator.

17. The computer system of claim 12, wherein the first camera and the second camera are different cameras.

18. The computer system of claim 12, wherein the image data from the first camera is used to generate a plurality of possible gestures consistent with the image data from the first camera.

19. The computer system of claim 12, wherein the robot is moved to the area using a model-based controller that uses a target attractor defined by a motion strategy of the robot.

20. A computer-readable medium storing executable instructions that, as a result of being executed on one or more processors of a computer system, cause the computer system to at least:

moving the robot into the area under control of a model-based approach using a physical model, the physical model being oriented using information from a first perception system;

Determining an uncertainty of information produced by the first perception system;

determining, based at least in part on the uncertainty, that the robot is within the area having an edge; and

as a result of determining that the robot is in the area, the robot is instructed to perform a task under control of a second method based on information generated by a second perception system.

21. The computer-readable medium of claim 20, wherein:

the first perception system is a stationary camera; and

the second perception system is a camera that moves with the robot.

22. The computer-readable medium of claim 20, wherein the size of the region is determined based at least in part on an uncertainty of information produced by the first perception system.

23. The computer-readable medium of claim 20, wherein the uncertainty of the information produced by the first perception system is determined as a distribution of a plurality of poses of the region.

24. The computer-readable medium of claim 20, wherein the executable instructions further cause the computer system to:

determining that the robot is outside the area; and

As a result of determining that the robot is outside the area, moving the robot into the area using the model-based method.

25. The computer-readable medium of claim 20, wherein the second method is a model-free method implemented using a machine learning model trained with input from the second perception system.

26. The computer-readable medium of claim 25, wherein the input comprises a simulated image generated by a simulation of the task.

27. The computer-readable medium of claim 20, wherein the task is controlling an autonomous vehicle.

28. A processor, comprising: one or more Arithmetic Logic Units (ALUs) to perform tasks by at least:

moving the robot to an area using a model of the environment of the robot, the model oriented using image data from the first camera;

determining an uncertainty of the model using uncertainty information associated with the first camera;

determining that the robot is in the region based at least in part on an uncertainty of the model; and

As a result of determining that the robot is in the area, performing a task using the robot under control of a machine learning system trained using image data from a second camera.

29. The processor of claim 28, wherein the second camera provides a hand view of an object to be manipulated by the robot.

30. The processor of claim 28, wherein the computer system uses results of the tasks to reduce uncertainty of the model.

31. The processor of claim 28, wherein information collected as a result of completing the task is used to obtain an improved pose for the model.

32. The processor of claim 28, wherein the first camera and the second camera are different cameras.

33. The processor of claim 28, wherein image data from the first camera is used to generate a plurality of possible poses consistent with the image data from the first camera.

Technical Field

At least one embodiment relates to training a robot to perform a task. For example, at least one embodiment relates to training a robot using models and artificial intelligence in accordance with various novel techniques described herein.

Background

Training a robot to accurately perform a task can consume a significant amount of memory, time, or computing resources. Sometimes, this may result in training requiring an extremely large amount of training data, which may be unavailable or cost prohibitive for some tasks. In some examples, training may cause the system to be too fragile or unstable to reliably converge on a solution to the task. Therefore, finding a more efficient and effective training method is an important issue.

Drawings

FIG. 1 illustrates a process of directing a robot to complete a task using a combination of model-based and model-free methods, in accordance with at least one embodiment;

fig. 2 illustrates an overview of a perception module for a model-based robotic control system in accordance with at least one embodiment.

FIG. 3 illustrates an overview of a perception module for a modeless robotic control system in accordance with at least one embodiment;

FIG. 4 illustrates an example of a training image for a robot control system in accordance with at least one embodiment;

FIG. 5 illustrates an example of test results for various robot control methods in accordance with at least one embodiment;

FIG. 6 illustrates a table of test results for performing a task in accordance with at least one embodiment;

FIG. 7 illustrates a process that, as executed by a computer system, causes the computer system to direct a robot to perform a task using a combination of model-based methods and model-free methods, in accordance with at least one embodiment;

FIG. 8A illustrates inference and/or training logic in accordance with at least one embodiment;

FIG. 8B inference and/or training logic in accordance with at least one embodiment;

FIG. 9 illustrates the deployment and training of a neural network in accordance with at least one embodiment;

FIG. 10 illustrates an example data center system in accordance with at least one embodiment;

FIG. 11A illustrates an example of an autonomous vehicle in accordance with at least one embodiment;

FIG. 11B illustrates an example of camera positions and field of view of the autonomous vehicle of FIG. 11A in accordance with at least one embodiment;

FIG. 11C is a block diagram illustrating an example system architecture of the autonomous vehicle of FIG. 11A in accordance with at least one embodiment;

FIG. 11D is a diagram illustrating the system of FIG. 11A for communication between a cloud-based server and an autonomous vehicle in accordance with at least one embodiment;

FIG. 12 is a block diagram illustrating a computer system in accordance with at least one embodiment;

FIG. 13 is a block diagram illustrating a computer system in accordance with at least one embodiment;

FIG. 14 illustrates a computer system in accordance with at least one embodiment;

FIG. 15 illustrates a computer system in accordance with at least one embodiment;

FIG. 16A illustrates a computer system in accordance with at least one embodiment;

FIG. 16B illustrates a computer system in accordance with at least one embodiment;

FIG. 16C illustrates a computer system in accordance with at least one embodiment;

FIG. 16D illustrates a computer system in accordance with at least one embodiment;

16E and 16F illustrate a shared programming model in accordance with at least one embodiment;

FIG. 17 illustrates an example integrated circuit and associated graphics processor in accordance with at least one embodiment;

18A-18B illustrate an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

19A-19B illustrate additional exemplary graphics processor logic, in accordance with at least one embodiment;

FIG. 20 illustrates a computer system in accordance with at least one embodiment;

FIG. 21A illustrates a parallel processor in accordance with at least one embodiment;

FIG. 21B illustrates a partition unit in accordance with at least one embodiment;

FIG. 21C illustrates a processing cluster in accordance with at least one embodiment;

FIG. 21D illustrates a graphics multiprocessor in accordance with at least one embodiment;

FIG. 22 illustrates a multi-graphics processing unit (CPU) system in accordance with at least one embodiment;

FIG. 23 illustrates a graphics processor in accordance with at least one embodiment;

FIG. 24 is a block diagram illustrating a processor microarchitecture for a processor in accordance with at least one embodiment;

FIG. 25 illustrates a deep learning application processor in accordance with at least one embodiment;

FIG. 26 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

FIG. 27 shows at least a portion of a graphics processor in accordance with one or more embodiments;

FIG. 28 illustrates at least a portion of a graphics processor in accordance with one or more embodiments;

FIG. 29 shows at least a portion of a graphics processor in accordance with one or more embodiments;

FIG. 30 illustrates a block diagram of a graphics processing engine 3710 of a graphics processor, according to at least one embodiment;

FIG. 31 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment;

32A and 32B illustrate thread execution logic including an array of processing elements of a graphics processor core in accordance with at least one embodiment;

FIG. 33 illustrates a parallel processing unit ("PPU") according to at least one embodiment;

FIG. 34 illustrates a general purpose processing cluster ("GPC") according to at least one embodiment;

FIG. 35 illustrates a memory partitioning unit of a parallel processing unit ("PPU") in accordance with at least one embodiment; and

FIG. 36 illustrates a streaming multiprocessor in accordance with at least one embodiment;

FIG. 37 is an example data flow diagram for a high level computing pipeline in accordance with at least one embodiment;

FIG. 38 is a system diagram of an example system for training, tuning, instantiating and deploying a machine learning model in a high-level computing pipeline, according to at least one embodiment;

FIG. 39 includes an exemplary illustration of a high-level computing pipeline for processing imaging data in accordance with at least one embodiment;

FIG. 40A includes an example data flow diagram of a virtual instrument supporting an ultrasound device in accordance with at least one embodiment;

FIG. 40B includes an example data flow diagram of a virtual instrument supporting a CT scanner in accordance with at least one embodiment;

FIG. 41A illustrates a data flow diagram of a process for training a machine learning model in accordance with at least one embodiment; and

FIG. 41B is an example illustration of a client-server architecture for enhancing annotation tools with pre-trained annotation models, in accordance with at least one embodiment.

Detailed Description

In at least one embodiment, the techniques described herein demonstrate a robot control algorithm that combines the advantages of a model-based approach ("MBM") with the advantages of a model-free approach ("MFM"). In at least one embodiment, the MBM is utilized to provide efficient movement in a free space environment. For example, in at least one embodiment, MBMs are used to operate robots in spaces that are susceptible to avoiding collisions with the environment or humans. In at least one embodiment, MBM is used in conjunction with MFM, which increases the ability to learn from the environment using loosely defined targets. In at least one embodiment, a perception system that can predict pose uncertainty is used to help the system fuse the MBM and MFM.

Techniques such as deep reinforcement learning ("RL") allow robots to learn and take actions from raw sensory data. For example, the RL method can be successfully applied to contact-rich operational tasks such as insertion, pushing, and grabbing of objects. However, in some cases, the RL method is inefficient in sampling and requires multiple training interactions with the environment to be applied in the real world. To alleviate this limitation, various embodiments may carefully tune the rewards of dense shapes, which often requires a clear understanding of the world conditions (e.g., target locations). On the other hand, given a refined model and the current state of the world, many algorithms can be planned, designed, or searched for strategies for completing the task. This Model (MB) based strategy can be used for many manipulation tasks such as pin insertion, grasping and reaching. However, in some examples, the MB strategy may suffer from model bias and state estimation errors, and often achieves lower asymptotic performance.

At least one embodiment described herein combines sample efficiency from model-based strategies and overcomes errors in dynamic and perceptual models with a reinforcement learning strategy that closes the cycle of raw sensory data. At least one embodiment takes advantage of the efficiency of model-based approaches to moving in free space where collisions and contact with the environment and humans are unlikely. At least one embodiment uses the functionality of the RL method to learn from the agent's interaction with the environment and loosely defined objectives. To switch between MBM and RL, various examples introduce a perception system that can predict pose uncertainty to help the system fuse both strategies. In at least one embodiment, the task is initialized with an MB strategy in which the task moves the robot to within the uncertainty range of the object of interest, e.g., in a cassette in which the pins are inserted. In at least one embodiment, when the system reaches the uncertainty region, it switches to the RL strategy to complete the task. In learning, we use the information of the RL to reduce the uncertainty of the perception system. At least one embodiment effectively uses uncertainty to mix MB policy and RL policy to accomplish complex tasks, which can be very challenging when using both methods separately.

In various embodiments, the robotic approach relies on a refined model of the environment, a detailed description of how to perform the task, and a robust perception system to track the current state. In some other embodiments, a reinforcement learning ("RL") method operates directly from sentence-origin sensory input using reward signals to describe tasks. In one embodiment, a system is developed to achieve a universal approach that can overcome the imprecision of elements in traditional pipelines while requiring minimal interaction with the environment. In at least one embodiment, this is accomplished by using uncertainty estimates to divide the space into regions where a given model-based strategy is reliable and regions where defects exist or where definition is ambiguous. In at least one embodiment, in these hard regions, the local modeless strategy is learned directly from raw sensory input. In one embodiment, these "hard regions" may also be referred to as "uncertain regions" because the models used in the model-based approach may be uncertain. In at least one embodiment, the system allows for faster construction of robotic systems from simple and inexpensive components and from only a high-level description of tasks. In at least one embodiment, an algorithm known as "guided uncertainty-aware strategic optimization" ("GUAPO") is used in real-world robots to perform the close-fitting nail insertion task.

In at least one embodiment, the task is initialized with an MBM, wherein the method moves the robot within the uncertainty range of the object of interest (e.g., a box into which the nail is to be inserted). In at least one embodiment, after reaching a defined area proximate to the target, the system switches the control method to the MFM to complete the task. In at least one embodiment, information from MFM task completion is utilized in learning to reduce the uncertainty of the perception system. In at least one embodiment, the system mixes MBMs and MFMs to accomplish complex tasks that require environmental interaction. In various examples, switching between MBMs and MFMs may be known through RL or optimization.

In at least one embodiment, a simple and efficient way to express the pose uncertainty of a keypoint-based pose estimator is utilized. In at least one embodiment, the expansion enhances the peak estimation algorithm by fitting a 2d gaussian around each found peak. In at least one embodiment, the PnP algorithm runs on n sets of keypoints, where each set of keypoints is constructed by sampling from all 2d gaussian samples. In at least one embodiment, this provides n possible poses of the object consistent with the detection algorithm, which are considered equally likely in some examples described herein.

In at least one embodiment, the perception module is used to detect and track the state of the world. In some cases, a simple failure to perceive in such an environment may be catastrophic for the robot, as its motion generator may rely on it. Furthermore, in some cases, classical motion generators are inflexible and inflexible in accomplishing tasks. This may result in failure to adapt to changing conditions. For example, a robot controlled by a classical motion generator may only pick up objects in a certain way and will not recover if the grabbing fails. In at least one embodiment, these problems can make robotic systems based on such control algorithms unstable and difficult to expand into new areas. To extend the scope of robotics, more robust, adaptive, and flexible systems may be deployed as described herein.

In at least one embodiment, the robotic system utilizes the capabilities of a robot expert to model its environment. The MBM can be used to move within the robot space, such as path following. In various embodiments, using MBMs can be difficult when the robot must interact with its environment (e.g., grasp an object, place an object, insert an object, etc.) due to limitations or inaccuracies in the model. Physical systems in the real world can be complex and random. In a robot simulator, modeling appropriate parameters describing the real robot behavior can be a difficult task. In various embodiments, utilizing MBM in common tasks may be both difficult and complex. Furthermore, MBM typically relies on an imperfect sensing system. Potential errors mixed with various complex physical systems can be difficult to manage. In addition, MBM can be time consuming and expensive because it can be limited by the expertise and ingenuity of the robotics experts.

In various embodiments, MFMs have the ability to adapt and directly process raw sensory input that may not be subject to estimation errors. In at least one embodiment, the strength of the MFM stems from its ability to dictate what reward functions to do by defining tasks at a higher level, rather than by a set of explicit control actions that describe how the task should perform. In at least one embodiment, the MFM does not require specific physical modeling because it is implicitly learned from interactions with the environment, which allows the method to be deployed in different environments. In at least one embodiment, MFM methods have various limitations, including random interaction with the environment can be complex for human users and for various materials, and MFM sometimes does not have sampling efficiency. In some examples, introducing MFMs into new environments is difficult and complex.

In at least one embodiment, the system implements an algorithm that combines advantages from both MBM and MFM. In at least one embodiment, the efficiency of MBMs moving in a free space environment (e.g., a space that is easy to avoid collisions with the environment or humans) is leveraged to the MFM's ability to learn loosely defined targets from its environment. In at least one embodiment, a perceptual system predicts pose uncertainty to help the system fuse the MBM and MFM.

Model-based methods are control methods that rely on a physical model of the surrounding environment in order to control the robot. The physical model (sometimes simply referred to as a model) provides the positions and poses of various objects in the robot environment, and in some examples, the pose of the robot itself. For example, the physical model may be a solid object model of the robot and its nearby objects. Such methods plan motion based on physical models, which in various examples include object avoidance and object manipulation. Such systems typically use a perception system, such as a camera or depth camera, to locate objects and determine the orientation and position or pose of the model. When controlled by model-based methods, the performance of the robot is often limited by the accuracy of the model and the accuracy of the perception system. An alternative to model-based methods are model-free methods, such as reinforcement learning. A model-less approach is a control approach that operates independent of a physical model of the environment. In various examples, such systems may operate directly from sensor data without the use of a model. For example, a model-less approach may use image data from a handheld camera and manipulate objects based on future motion on the image rather than an explicit physical model. However, modeless systems can be very time consuming and difficult to train, especially for complex tasks.

FIG. 1 illustrates a process of directing a robot to complete a task using a combination of model-based and model-free methods, in accordance with at least one embodiment. FIG. 1 shows an example 100 of a real world setup for nail insertion. In at least one embodiment, the robot 102 attempts to complete the task of inserting the nail into the hole 104. In at least one embodiment, a first perception system 106 (e.g., a camera) gives an approximate location of the object of interest, and a model-based method 110 drives the system within an uncertainty region 112. Upon entering the uncertainty region 112, the model cannot be trusted and the modeless strategy 114 is learned directly from the raw sensory input of the second perception system 108 which gives enough information to complete the task 116. In various examples, the perception system may be a camera, an infrared camera, a RADAR, a LIDAR, a depth camera, or a 2D or 3D imaging system.

FIG. 1 depicts an overview of a system in accordance with various embodiments, wherein a task 116 may be initialized with MBM, wherein it may cause a robot to move the robot within a range of uncertainty of an object of interest, e.g., a box in which a nail is inserted. In at least one embodiment, the MFM can then be utilized to complete the task. In at least one embodiment, information from MFM task completion is utilized in learning to reduce the uncertainty of the perception system. In at least one embodiment, the system utilizes MBMs and MFMs to accomplish complex tasks that require environmental interaction. In various embodiments, the system outperforms the MFM or MBM classic methods for different complex tasks such as nail insertion. In at least one embodiment, the system is for expressing pose uncertainty for a keypoint-based pose estimator. In at least one embodiment, the system is a valid sample for a learning method on a real-world robot.

At least one embodiment described herein addresses the problem of learning to perform an unknown a priori operation in a region where there may only be an estimated location without an accurate model. In at least one embodiment, the problem may be formulated as a Markov solution (Markov) decision process ("MDP") where the strategy is learned byTo maximize a particular awardThe practice strategies PiTo be a probability distribution over any given state S e S, action a e A. In thatIn at least one embodiment, a first assumption used within the system is expressed as having a transition function P The transition function indicates the probability of crossing over to the next state when a particular action is applied to the current state. In at least one embodiment, the transitions are assumed to be in state space onlyIs available in the subspace. This can be used in various robotic systems where the way a robot moves in open space can be determined, but there is no reliable, accurate model for general contact and interaction with the robot's surroundings. In at least one embodiment, the partial model is capable of planning and performing traversal S_openThe various methods of trajectory of (2) are combined, but completion requires S _hard＝S\S_openThe task of action remains difficult and complex.

In various embodiments, tasks that may be addressed include achieving a particular state or configuration through interaction with the environment, such as a pin insertion, switch tie-off, or grip. In various embodiments, these tasks are represented by a binary reward function r (S) 1[ S e S ∈ S_g]Defining the binary reward function to indicate successful attainment of the target setSuch rewards may be very sparse and thus random actions may require a large number of samples to be discovered. Furthermore, in many examples, S may not be assumed_hardBut only its noise estimate. In at least one embodiment, the system utilizes various imperfect perception systems and dynamics to efficiently learn to solve a complete task through interaction with the environment.

In at least one embodiment, the tasks are performed using a model-free method ("MFM"). In some embodiments, running MFMs is inefficient and fragile because it may be necessary to learn how to control the robot everywhere, and if the target location changes, the task may look different. In at least one embodiment, a partial model with a model-based approach ("MBM") is utilized that determines the uncertainty in the sensing and actuation system that directs the agent to the relevant region, thereby reducing the region in which the MFM strategy may need to be optimized, making it more invariant to the absolute target position. Various embodiments of the algorithm are referred to herein as guided uncertainty-aware policy optimization ("GUAPO").

In at least one embodiment, the GUAPO includes a method for generating S based on a perceptual system uncertainty estimate_hardSuper set of S ^ S_hardThe method of (1). In at least one embodiment, the set is used to divide the space into regions that use MBM and regions that train MFM. In at least one embodiment, the determination is at S ^ S_hardThe externally used MBM brings the robot into the collection. In at least one embodiment, an MFM is defined and learning is made more efficient by localizing its inputs.

In many examples, coarse perception systems may be faster to set up because they may require simpler hardware (such as RGB cameras) and may be used inventively without excessive adjustment and calibration effort. If such a system is used to directly locate S_hardThen a perception error may mislead to indicate that a region belongs to S_openThis may result in an attempt to apply MBM and may not learn how to recover from it. In various embodiments, a perception system is utilized that also gives an estimate of uncertainty. In at least one embodiment, uncertainty is represented by a nonparametric distribution using various methods, where regionsN possible gestures and their associated weightsInterpreting these weights as being Can belong to S_hardIs represented as:

in at least one embodiment, the perception system provides a distribution of parameters, and the probabilities can be computed by integration, or such that the set S ^ S_hard＝{s：p(s∈S_hard) ε may be the S set by the user for the appropriate set of εs_hardIs approximated by way of a superset of (c). In at least one embodiment, a more accurate sensing system enables S ^ S_hardIs converted into S_hardFurther reducing the area where modeless methods are needed. α (S) may be defined as α (S) ═ 1[ S ∈ S ^ S_hard]And the overall strategy employed may be:

π(a|s)＝(1-α(s))*π_MB(a|s)+α(s)*π_MF(a|s)

wherein pi_MB(a | s) and π_MF(as) may be a model-based strategy and a model-free strategy, respectively. Thus, in at least one embodiment, switching between the two strategies is utilized based at least in part on uncertainty estimates. For example, when the robot is determined to be in S ^ based on the uncertainty of the perception module_hardWithin range, the system may transition from MBM to MFM. In various examples, this will result in a determination that the robot is located S ^ S_hardWithin a sub-region of (a). The sub-region is completely surrounded at S ^ S_hardA total volume of less than S ^ S_hard。

In at least one embodiment, S ^ S_hardIs an area where it is known that there is some reward for completing a task, not how. In at least one embodiment, it is assumed that outside of this region, the environmental model is well known, and therefore a model-based approach may be used. Thus, in at least one embodiment, at S ^ S _hardIn addition, the model-based approach may take the robot back into it. In at least one embodiment, the system derives a probability distribution from the perception system, at S_hardA particular point (e.g., its centroid) is selected as the most likely location and set as the target of the model-based approach. In at least one embodiment, this can ensure that the robot is facing S ^ whenever it is outside it_hardAnd (4) advancing.

In at least one embodiment, the formula is expanded to account for multiple rewards. For example, if there is an obstacle to be avoided and its location is uncertain, then S ^ S_hardCan be described asWhereinAndthen, in at least one embodiment, the MBM avoiding the obstacle can be utilized to reach the area where the target is located, while avoiding the area where the obstacle may exist.

In at least one embodiment, once π_MBBringing the system into S ^_hardIn (3), then control is handed over to π represented in the strategy_MF. In at least one embodiment, the switch definition can be made bi-directional, so if π_MFAdopt to shift it out of S ^ S_hardBeyond exploratory action, the MBM may act again to import the state through the funnel to the region of interest. As noted above, in at least one embodiment, this provides a framework for safe learning against obstacles that may be avoided. In at least one embodiment, there may be several advantages in more restricted areas where the MFM needs to learn how to take action: first, exploration may become easier; and secondly, the policy may be local. In at least one embodiment, for example, only images are fed to π _MFWhere the image is from a wrist mounted camera and its current speed, as shown in figure 3.

In at least one embodiment, having no global information like that provided by the perception system in FIG. 2, makes the MFM policy at S ^ S_hardThe promotion effect at each position is better. In at least one embodiment, an out-of-policy MFM algorithm is utilized so that all observed transitions can be added to the replay buffer, whether they come from π_MBOr is pi_MF。

In at least one embodiment, the framework uses any newly acquired experience to reduce S ^ S_hardSo that successive extrapolations can use model-based methods over a larger region of the state space. For example, in the task of the staple, once the reward of fully inserting the staple is received, the position of the opening can be immediately known and the S ^ S can be updated_hard＝S_hardNow only no model is needed for the actual insertion, instead of always finding the opening.

In at least one embodiment, a GUAPO algorithm was developed for nail insertion tasks that closely fit the 7 degree-of-freedom torque controlled robot Franka Panda, although in various embodiments any robot may be used. In at least one embodiment, a state estimation module is utilized and uncertainty estimates are obtained to locate S ^ S. In at least one embodiment, a model-based strategy is utilized to avoid obstacles while at S _openMedium navigation and also with the structured RL algorithm and modeless strategy.

In at least one embodiment, a depth object pose estimator ("DOPE") is used as the perception system. In at least one embodiment, DOPE uses a simple neural network architecture that can be trained quickly through synthetic data and domain randomization.

FIG. 4 illustrates an example of a training image for a robot control system in accordance with at least one embodiment. FIG. 4 depicts an image generated using a large number of domain randomizations for training the perception system. In some examples, the model of the object that DOPE needs to detect may not be very detailed, consisting primarily of shapes. In at least one embodiment, depth sensing is not utilized to supplement the RGB information. In at least one embodiment, the algorithm first uses local peaks on the map to find object cuboid keypoints. In one embodiment, DOPE may run a view n-point (PnP) algorithm to find the final object pose in the camera frame, taking advantage of the physical dimensions of the cuboid, the camera intrinsic properties, and the keypoint locations. In the example shown in fig. 4, the training image illustrates a hole box with various occlusions or backgrounds.

Fig. 2 illustrates an overview of a perception module for a model-based robotic control system in accordance with at least one embodiment. In at least one embodiment, FIG. 2 illustrates DOPE perception and uncertainty to estimate S_hard. In at least one embodiment, the image 202 obtained from the camera is provided to the DOPE perception system 204, the DOPE perception system 204 providing an estimate of the location of the object in the robotic environment.

In at least one embodiment, the DOPE perception system is extended to obtain an uncertainty estimate of the pose of the object. In at least one embodiment, the expansion enhances the peak estimation algorithm by fitting a 2D gaussian around each found peak, as depicted by the black profile 206 in fig. 2. In at least one embodiment, the PnP algorithm runs on n sets of keypoints, where each set of keypoints is constructed by sampling from a 2D gaussian. In at least one embodiment, this provides n possible gestures 208, 210, and 212 of the object consistent with the detection algorithm, as shown in FIG. 2. In at least one embodiment, they may be considered to have equal possibilities.

In some examples, a region of interest S around an object for which an operation needs to be performed may be assumed _hard214 are accessed. In one embodiment of the peg insertion task, this is a rectangle centered on the opening of the hole. In at least one embodiment, for each of the n postural samples given by the extended DOPE perception algorithm, its associated open pore location may be calculatedAs shown in fig. 2. In at least one embodiment, the points are then fitted by a 3D gaussian with diagonal covariance, represented in blue in the same figure. In at least one embodiment, the mean valueIs used as S ^ S_hardAnd a certain state S belongs to S_hardBy passing S along an axis_hardIs overestimated by moving the position by one standard deviation.

In at least one embodiment, a complete setup is depicted in fig. 1, where a DOPE camera (640 x 480 x 3RGB images) is mounted on top of the workspace and an example image is provided.

In at least one embodiment, as a model-based controller, the robot is moved to a desired end effector position using a target attractor defined by Riemann motion strategy ("RMP"). In at least one embodiment, the RMP is at a desired end effector position in cartesian spaceIn at least one embodiment, the target is set to S ^ S _hardThe centroid corresponding to aperture μ ^_holeIs provided. In at least one embodiment, a rough model of the object can be used to train a perception module that can provide the location estimate and its uncertainty. In at least one embodiment, the RMP also uses a model of the robot. In at least one embodiment, these two features can contribute to a "model-based" component of the system. In at least one embodiment, the GUAPO algorithm does not require that these models be extremely accurate. In at least one embodiment, a barrier type RMP may be defined if it is desired to avoid obstacles reaching S ^.

In various embodiments, the strategy sends end effector position commands at 20 Hz. In at least one embodiment, the RMP calculates the desired joint position q at 1000Hz_d. In at least one embodiment, the interface of the RMP may be used as a modeless motion space, assuming that the impedance end effector control is a motion space that may improve sample efficiency for RL policy learning.

Fig. 3 illustrates an overview of a perception module for a modeless robotic control system in accordance with at least one embodiment. In at least one embodiment, a variant autoencoder for model-less systems is used to accomplish the task. In at least one embodiment, the RGB image 302 and the speed 304 are provided to autoencoders 306 and 308.

In at least one embodiment, a model-free off-policy RL algorithm is utilized, such as Soft Actor criticic. In at least one embodiment, the modeless strategy works directly from the raw sensory input. In at least one embodiment, this consists of joint speed and images from a wrist mounted camera on the robot (e.g., 64 x 3 RGB images from the romatel zeiss) (see fig. 1). As shown in fig. 3, in at least one embodiment, the input may be fed to a beta variable automatic encoder ("VAE") which gives a low-dimensional potential spatial representation of the state. In at least one embodiment, the parameters of the VAE are trained in advance on the data set collected offline. In at least one embodiment, the portion that can be learned by the RL algorithm is the 2-layer multilevel perceptions ("MLPs") 314 and 316, which take as input the 64-dimensional potential representation 310 given by the VAE and produce the 3-D positional displacement Δ x of the robotic end effector. In at least one embodiment, the robot action 312 is provided to an auto-encoder, which estimates the next velocity 318 and reconstructs the image 320.

In at least one embodiment, on a graphics processing unit such as a Titan XP GPU, the VAE is trained with at least 160,000 data points for 12 epochs. In at least one embodiment, DOPE was trained on four P100 GPUs for 8 hours, although any processing unit may be utilized in various embodiments. In at least one embodiment, 60 trains of GUAPO, SAC and Residual are performed, 1000 steps each, and in some examples, approximately 90 minutes.

In at least one embodiment, for GUAPO, sparse rewards when a strategy completes a task (inserts nails) are utilized. In at least one embodiment, a policy gets-1 everywhere and gets 0 when it completes a task. In at least one embodiment, for SAC and residual, the negative L2 norm is utilized for the target position μ ^_holeWhen it reaches S ^ S_hardThe reward is 0 when it completes the taskThen prize 1.

In various examples, the performance of the GUAPO algorithm may be measured. In one example of performance evaluation, three overall baselines are used. First, it is a baseline that does not involve any learning. In at least one embodiment, those can be represented as static "model-based" methods that do not utilize any real-world interactions to update their policies. Thus, such embodiments may not recover from the failure, and they may be represented in the various figures as horizontal dashed lines. The second type of baseline is a similar model-free algorithm used in one or more embodiments of the GUAPO method, but does not utilize a model-based strategy to reduce its workspace. Here, in the example, a Soft-Actor criticic ("SAC") is used for comparison with GUAPO. Finally, residual learning techniques may be compared, and these approaches may also attempt to combine model-based approaches with model-free approaches.

In the baseline category based on static models, the performance of the script method can be considered. In at least one embodiment, the most direct approach is likely to be to reach S ^ using the same attractor-based control as used in the GUAPO approach directly_hardAnd then execute the task using the completed scripted policy. In at least one embodiment, this may be hard coding the straight descent of the nail during the nail insertion task. In at least one embodiment, this approach is very sensitive to errors in the sensing system, as even a few millimeters of error can result in a nail not being inserted properly. In at least one embodiment, to provide an increased opportunity to insert a staple and thus complete a task, a random action may be added to the downward motion. In at least one embodiment, this is illustrated by the curve MB-RA-DOPE-EST (model-based strategy with stochastic motion using DOPE target estimation) as depicted in FIG. 5.

Fig. 5 illustrates an example of test results for various robot control methods in accordance with at least one embodiment. The first graph 502 shows the number of training iterations for task completion and task success, and the second graph 504 shows the number of steps required for task completion and training iterations. FIG. 5 shows the task results comparing GUAPO to the other five baselines: (1) model-based strategies with perfect target estimation (MBPERF-EST), (2) model-based strategies with stochastic action of perfect target estimation (MB-RA-PERF-EST), (3) model-based strategies with stochastic action using DOPE target estimation (MB-RA-DOPE-EST), (4) model-free Soft Actor Critical (SAC) and (5) residual strategies. In this example, 60 trains were performed on the GUAPO, SAC and residual. In at least one embodiment, GUAPO is capable of 100% nail insertion after 60 episodes (approximately 90 minutes of training time) and reduces the number of steps required for nail insertion. In at least one embodiment, when DOPE is used, model-based algorithms ("MBs") fail the task due to errors in the perception system, and SAC and Residual take only 60 times to complete the task.

To provide a prophetic and demonstrate that this scripted approach may work under ideal state estimation, the performance of the strategy under ideal state estimation with MB-PERF-EST (model-based strategy with ideal target estimation) and MB-RA-PERF-EST (model-based strategy with ideal target estimation with stochastic action) may be considered. The MB-PERF-EST may drill a hole and then push down without taking random action. In some examples, the random action does not unduly degrade the overall performance achieved by the same script action, but without any additional random actions. As shown in FIG. 6, in some examples, MB-RA-DOPE-EST may perform better than MB-DOPE-EST when there is a perceptual error. FIG. 6 illustrates a table of test results for performing a task in accordance with at least one embodiment.

In at least one embodiment, model-based methods are compared, such as SACs without various model-based components. In some examples, the SAC may not be able to implement any insertions. In some examples, this is due to a very low data mechanism. In some examples, the RL may require several orders of magnitude of additional data.

In at least one embodiment, residual learning may also be considered. In at least one embodiment, the method applies a random action on top of a given policy. In some examples, this is a scripted policy. In various embodiments, residual learning results in various errors. In at least one embodiment, a common failure condition is to apply a large disturbance too far from the aperture opening and thus end up on the side of the cassette where the aperture is located and then push against the side of the cassette instead. In at least one embodiment, the system turns on the model-free portion only when it is already near the region of interest, thereby avoiding such a fault condition.

In one embodiment, the results are shown in fig. 5 and 6. In at least one embodiment, a model-based strategy with perfect perception estimation ("MB-PERF-EST") may outperform GUAPO because the strategy knows exactly where the wells of the box are and can use handwriting to complete the task. However, in at least one embodiment, when DOPE is used as the sensing system, which may have about 2.5 to 3.5cm of noise and error, the performance of MB-DOPE-EST and MB-RA-DOPE-EST drops sharply. In at least one embodiment, MB-RA-DOPE-EST performs 26.6% better than MB-DOPE-EST because random motion cancels out perceptual errors. In at least one embodiment, neither the residual nor the SAC is able to complete the task within the training time frame. However, in at least one embodiment, after 60 training periods, the residual can reach S ^ 100% with_hardAnd SAC still cannot reach the area.

In at least one embodiment of robotic manipulation, there are various paradigms for performing tasks, such as model-based paradigms and model-free paradigms. In at least one embodiment, the first category of methods may rely on an accurate description of the task, such as an accurate CAD model of all objects and various perception systems. In some examples, it may be used with various search algorithms, such as an exercise plan. In at least one embodiment, the method is limited by the implementation, and if the sensing system has some noise, both may be constrained to unrecoverable failure.

In at least one embodiment, the modeless approach does not require a detailed description, but rather accesses interactions with the environment and rewards that may indicate success. In at least one embodiment, such binary rewards may be easy to describe, but they may make the RL method sampling very inefficient and may take advantage of the extreme shape of the reward that requires considerable adjustment and precision of the sensing system. In at least one embodiment, the use of automatic curriculum generation or demonstration may be utilized, and may require a significant amount of interaction with the environment. Furthermore, in various embodiments, these methods may need to be retrained if the position of objects in the scene changes or there are new interferers in the background. In at least one embodiment, the developed system is sample-efficient even with only sparse success rewards, and is robust to these variations due to model-based components.

In at least one embodiment, object pose estimation is utilized in various robotics and computer vision applications. In at least one embodiment, keypoints that are regressed onto the object or onto a cuboid that surrounds the object are utilized. In at least one embodiment, keypoints are first detected by a neural network, and then PnP is used to predict the pose of the object. In at least one embodiment, uncertainty is exploited by using a random sample consensus voting algorithm to find areas where keypoints can be detected. In at least one embodiment, this allows for the utilization of probability PnP, where different keypoints are weighted according to their spatial distribution. In at least one embodiment, the vector voting graph can be regressed to locations where the keypoints can then be found using line intersections. In some embodiments, the pose uncertainty is not considered in the final prediction.

In one embodiment, a GUAPO algorithm is developed that combines the generalization capability of model-based approaches with the adaptability of model-free approaches. In at least one embodiment, it may enable a task to be loosely defined by providing only a coarse model of the object and a coarse description of the regions where certain operations need to be performed. In at least one embodiment, the model-based system may utilize advanced information and an inexpensive state estimation system to create a funnel around the area of interest. In at least one embodiment, uncertainty estimates provided by the perception system can be utilized to automatically switch between model-based strategies and model-free strategies that can be learned from sparse rewards, which can overcome errors in the estimation of the model and model-based portions. In at least one embodiment, learning is achieved in the real world of the close-fitting peg insertion task.

FIG. 7 illustrates a process, in accordance with at least one embodiment, which, as a result of being performed by a computer system, such as those shown and described in FIGS. 8-41 below, and the associated description, causes the computer system to direct a robot to perform a task using a combination of model-based and model-free methods, as described above. In at least one embodiment, the process begins at block 702, where a computer system obtains information from a first perception system. The sensing system may be a camera, depth camera, LIDAR, RADAR or other sensing system that provides position or location information, such as listed below. In at least one embodiment, the perception system is a stationary camera that observes the robot and the surrounding environment. In at least one embodiment, at block 704, the information is processed using a pose estimator, such as DOPE, to generate a physical model of the robot's surroundings, as described above. In at least one embodiment, the physical model is a 2-D or 3-D model of the object, surface, around the robot. In at least one embodiment, the physical model includes pose and position information for the object, and in some embodiments, the robot itself. The robot may be an articulated robot, an autonomous vehicle, a pick-and-place machine, or other machine controlled by a computer system. In at least one embodiment, the uncertainty is determined 706 based on information provided by the first perception system, as described above. In at least one embodiment, the uncertainty is a distribution of possible object and/or robot poses. In at least one embodiment, the uncertainty is based on the camera resolution and the error of the first perception system.

In at least one embodiment, at block 708, the computer system implements a model-based method using a physical model, such as the MBM described above, to move the robot to a region of space, which in some examples is determined according to uncertainty. In at least one embodiment, the spatial region is a region where the computer system determines that the model is no longer accurate enough to allow the robot to complete the task. In at least one embodiment, at decision block 710, the computer system determines whether the robot is in the area based on the uncertainty. For example, using the uncertainty, the system may determine that the likelihood of the robot being within the area is greater than a threshold or percentage. If the robot is not in the area, execution returns to block 702, but if the robot is determined to be within the required deterministic area, execution proceeds to block 712.

In at least one embodiment, at block 712, the computer system obtains information from the second perception system. In at least one embodiment, the second perception system is a built-in camera mounted on the robot manipulator or a camera mounted on the wrist of the robot. In at least one embodiment, at block 714, the computer system provides information from the second perception system to a model-less method that generates control instructions for the robot from the information without relying on the physical model. In at least one embodiment, at block 716, the robot is moved using control instructions generated using a model-free method. In at least one embodiment, at decision block 718, the computer system determines whether the executing task is completed by a modeless method. If not, execution returns to block 712. In at least one embodiment, if the task is complete, execution proceeds to block 720 and the process ends. In various examples, the task may be to insert a nail into a hole as described above, or to perform an operation of an autonomous vehicle as described below.

Inference and training logic

FIG. 8A illustrates inference and/or training logic 815 for performing inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B.

In at least one embodiment, inference and/or training logic 815 can include, but is not limited to, code and/or data store 801 for storing forward and/or output weights and/or input/output data, and/or other parameters to configure neurons or layers of a neural network that are trained and/or used for inference in one or more embodiments. In at least one embodiment, the training logic 815 may include or be coupled to code and/or data memory 801 to store graphics code or other software to control timing and/or sequencing, where weights and/or other parameter information will be loaded to configure logic including integer and/or floating point units (collectively Arithmetic Logic Units (ALUs)). In at least one embodiment, code, such as graphical code, loads weights or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the data store 801 stores weight parameters and/or input/output data for each layer of a neural network that is trained or used in connection with one or more embodiments during forward propagation of input/output data and/or weight parameters during reasoning and/or training using aspects of one or more embodiments. In at least one embodiment, any portion of the code and/or data storage 801 may be included with other on-chip or off-chip data storage (including the processor's L1, L2, or L3 cache, or system memory).

In at least one embodiment, any portion of the code and/or data storage 801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and/or data store 801 can be a cache memory, a dynamic random access memory ("DRAM"), a static random access memory ("SRAM"), a non-volatile memory (e.g., flash memory), or other storage device. In at least one embodiment, the code and/or data store 801 is a choice of whether internal or external to the processor, including, for example, DRAM, SRAM, flash, or by other types of memory, depending on the storage available on-chip, the latency requirements for performing the training and/or reasoning functions, the bulk size of the data used in reasoning and/or training the neural network, or some combination of these factors.

In at least one embodiment, inference and/or training logic 815 may include, but is not limited to, code and/or data store 805 to store backward and/or output weights and/or input/output data corresponding to a neural network or layers of a neural network trained and/or used for inference in aspects of one or more embodiments. In at least one embodiment, code and/or data store 805 stores weight parameters and/or input/output data for each layer of a neural network that is trained with or used in connection with one or more embodiments during backward propagation of input/output data and/or weight parameters during training and/or reasoning using aspects of one or more embodiments. In at least one embodiment, the training logic 815 may include or be coupled to code and/or data memory 805 to store graphics code or other software to control the timing and/or order in which weights and/or other parameter information is loaded to configure logic including integer and/or floating point units (collectively Arithmetic Logic Units (ALUs)).

In at least one embodiment, code, such as graphical code, loads weights or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and/or data storage 805 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and/or data storage 805 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and/or data store 805 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, code and/or data store 805 is a choice of whether internal or external to the processor, e.g., made up of DRAM, SRAM, flash memory, or other memory types, depending on the on-chip available storage, the latency requirements for performing the training and/or reasoning functions, the bulk size of the data used in reasoning and/or training the neural network, or some combination of these factors.

In at least one embodiment, code and/or data store 801 and code and/or data store 805 can be separate storage structures. In at least one embodiment, code and/or data store 801 and code and/or data store 805 can be the same storage structure. In at least one embodiment, code and/or data store 801 and code and/or data store 805 can be partially combined and partially separated. In at least one embodiment, any portion of the code and/or data storage 801 and 805 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory.

In at least one embodiment, the inference and/or training logic 815 may include, but is not limited to, one or more arithmetic logic units ("ALUs") 810 including integer and/or floating point units to perform logical and/or arithmetic operations based at least in part on or instructed by training and/or inference code (e.g., graphics code), the results of which may result in activation of input/output and/or weight parameter data functions (e.g., output values from layers or neurons within a neural network) stored in the activation store 820 as stored in the code and/or data store 801 and/or the code and/or data store 805. In at least one embodiment, the activations stored in the activation store 820 are generated according to linear algebra and/or matrix-based mathematics performed by the ALU 810 in response to executing instructions or other code, where the weight values and/or data stores 801 stored in the code and/or data store 805 are used as operands along with other values (e.g., bias values, gradient information, momentum values or other parameters or hyper-parameters), any or all of which may be stored in the code and/or data store 805 or the code and/or data store 801 or other on-chip or off-chip memory.

In at least one embodiment, one or more ALUs 810 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 810 may be external to the processor or other hardware logic device or circuit in which they are used (e.g., a coprocessor). In at least one embodiment, ALU810 may be included within an execution unit of a processor, or otherwise included in a set of ALUs accessible to the execution unit of a processor, which may be within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and/or data store 801, code and/or data store 805, and activation store 820 may be in a shared common processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 820 may be included with other on-chip or off-chip data stores, including the L1, L2, or L3 caches of processors or system memory. Further, inference and/or training code may be stored with other code accessible to a processor or other hardware logic or circuitry, and may be extracted and/or processed using the extraction, decoding, scheduling, execution, retirement, and/or other logic circuitry of the processor.

In at least one embodiment, activation store 820 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, activation storage 820 may be wholly or partially within or outside one or more processors or other logic circuits. In at least one embodiment, activation store 820 is a choice of internal or external to the processor, for example, or is comprised of DRAM, SRAM, flash memory, or some other type of storage, depending on the on-chip available storage, the latency requirements for performing the training and/or reasoning functions, the bulk size of the data used in reasoning and/or training the neural network, or some combination of these factors.

In at least one embodiment, inference and/or training logic 815 illustrated in FIG. 8A may be integrated with an application specific integrated circuit ("ASIC") (e.g., from Google)Processing unit from Graphcore^TMAn Inference Processing Unit (IPU) orFrom Intel corporation(e.g., a "Lake Crest") processor). In at least one embodiment, the inference and/or training logic 815 illustrated in fig. 8A may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware, such as a field programmable gate array ("FPGA").

Fig. 8B illustrates various inference and/or training logic 815 in accordance with at least one embodiment. In at least one embodiment, the inference and/or training logic 815 can include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, the inference and/or training logic 815 illustrated in FIG. 8B may be associated with an Application Specific Integrated Circuit (ASIC) (e.g., of Google)Processing unit, Graphcore^TMOr from Intel corporation(e.g., a "Lake Crest") processor). In at least one embodiment, the inference and/or training logic 815 illustrated in fig. 8B may be used in conjunction with Central Processing Unit (CPU) hardware, Graphics Processing Unit (GPU) hardware, or other hardware, such as a Field Programmable Gate Array (FPGA). In at least one embodiment, inference and/or training logic 815 includes, but is not limited to, code and/or data store 801 and code and/or data store 805, which may be used to store code (e.g., graphical code) weight values and/or other information, including bias values, gradient information, momentum values, and/or other parameter or hyper-parameter information. In at least one embodiment shown in FIG. 8B, each of data store 801 and data store 805 is associated with a dedicated computing resource (e.g., computing hardware 802 and computing hardware 806), respectively. In at least one embodiment Each of the computing hardware 802 and the computing hardware 806 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) only on information stored in the data store 801 and the code and/or data store 805, respectively, the results of which are stored in the activation store 820.

In at least one embodiment, each of the code and/or data stores 801 and 805 and the corresponding computing hardware 802 and 806, respectively, correspond to a different layer of the neural network, thereby providing for the generation of an activation of one "store/compute pair 801/802" from the code and/or data store 801 and computing hardware 802 as an input to the next "store/compute pair 805/806" of the code and/or data store 805 and computing hardware 806 to mirror the conceptual organization of the neural network. In at least one embodiment, each storage/compute pair 801/802 and 805/806 may correspond to more than one neural network layer. In at least one embodiment, additional storage/computation pairs (not shown) may be included in the inference and/or training logic 815 after or in parallel with the storage computation pairs 801/802 and 805/806.

Neural network training and deployment

FIG. 9 illustrates training and deployment of a deep neural network in accordance with at least one embodiment. In at least one embodiment, the untrained neural network 906 is trained using the training data set 902. In at least one embodiment, the training frame 904 is a PyTorch frame, while in other embodiments, the training frame 904 is Tensorflow, Boost, Caffe, Microsoft Cognitive Toolkit/CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frame. In at least one embodiment, the training framework 904 trains the untrained neural network 906 and enables it to be trained using the processing resources described herein to generate a trained neural network 908. In at least one embodiment, the weights may be selected randomly or by using a deep belief network. In at least one embodiment, the training may be performed in a supervised, partially supervised or unsupervised manner.

In at least one embodiment, the untrained neural network 906 is trained using supervised learning, wherein the training data set 902 includes inputs paired with expected outputs of the inputs, or wherein the training data set 902 includes inputs having known outputs, and the outputs of the neural network are manually ranked. In at least one embodiment, the untrained neural network 906 is trained in a supervised manner to process inputs from the training data set 902 and compare the resulting outputs to a set of expected or expected outputs. In at least one embodiment, the error is then propagated back through the untrained neural network 906. In at least one embodiment, the training framework 904 adjusts the weights that control the untrained neural network 906. In at least one embodiment, the training framework 904 includes tools for monitoring the condition that the untrained neural network 906 is converging towards a model, such as the trained neural network 908, which is adapted to generate a correct answer, such as a result 914, based on known input data, such as new data 912. In at least one embodiment, the training framework 904 iteratively trains the untrained neural network 906 while adjusting the weights to refine the output of the untrained neural network 906 using a loss function and an adjustment algorithm (e.g., a random gradient descent). In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 achieves a desired accuracy. In at least one embodiment, the recurrent neural network 908 can then be deployed to implement any number of machine learning operations.

In at least one embodiment, the untrained neural network 906 is trained using unsupervised learning, wherein the untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training data set 902 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 906 can learn the groupings within the training data set 902 and can determine how the individual inputs relate to the untrained data set 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map, operations useful for reducing the dimensionality of the new data set 912 can be performed in the trained neural network 908. In at least one embodiment, unsupervised training may also be used to perform anomaly detection, which allows data points in the new data set 912 to be identified that deviate from the normal pattern of the new data set 912.

In at least one embodiment, semi-supervised learning may be used, which is a technique in which the training data set 902 includes a mixture of labeled data and unlabeled data. In at least one embodiment, the training framework 904 can be used to perform incremental learning, such as learning techniques through transitions. In at least one embodiment, incremental learning enables the trained neural network 908 to adapt to the new data set 912 without forgetting the knowledge injected into the trained neural network 908 during initial training.

Data center

FIG. 10 illustrates an example data center 1000 in which at least one embodiment can be used. In at least one embodiment, the data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

In at least one embodiment, as shown in fig. 10, the data center infrastructure layer 1010 can include a resource coordinator 1012, grouped computing resources 1014, and node computing resources ("node c.r.") 1016(1) -1016(N), where "N" represents a positive integer) which is a different integer "N" than used in other images. In at least one embodiment, nodes c.r.1016(1) -1016(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, Field Programmable Gate Arrays (FPGAs), graphics processors, etc.), memory storage devices 1018(1) -1018(N) (e.g., dynamic read only memory, solid state memory, or disk drives), network input/output ("NW I/O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the nodes c.r.1016(1) -1016(N) may be a server having one or more of the computing resources described above.

In at least one embodiment, the grouped computing resources 1014 may comprise individual groups of nodes c.r. housed in one or more racks (not shown), or individual groups of many racks housed in data centers of various geographic locations (also not shown). In at least one embodiment, the individual groupings of node c.r. within the grouped computing resources 1014 may include computing, network, memory, or storage resources that may be configured or allocated as a group to support one or more workloads. In at least one embodiment, several nodes c.r. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks can also include any number of any combination of power modules, cooling modules, and network switches.

In at least one embodiment, the resource coordinator 1012 may be configured to or otherwise have control of one or more nodes c.r.1016(1) -1016(N) and/or grouped computing resources 1014 in a water-tight manner. In at least one embodiment, the resource coordinator 1012 may include a software design infrastructure ("SDI") management entity for the data center 1000. In at least one embodiment, the resource orchestrator may comprise hardware, software, or some combination thereof.

In at least one embodiment, as shown in FIG. 10, framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, framework layer 1020 can include a framework for supporting software 1032 of software layer 1030 and/or one or more applications 1042 of application layer 1040. In at least one embodiment, the software 1032 or application 1042 may comprise a Web-based service software or application, respectively, such as Services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be, but is not limited to, a free and open source software network application framework, such as an Apache Spark TM (hereinafter "Spark") that may utilize the distributed file system 1028 for large scale extended data processing (e.g., "big data"). In at least one embodiment, job scheduler 1032 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 1000. In at least one embodiment, configuration manager 1024 may be capable of configuring different layers (e.g., software layer 1030 and framework layer 1020 including Spark) and distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, resource manager 1026 is capable of managing cluster or group computing resources mapped to or allocated to support distributed file system 1028 and job scheduler 1022. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 1014 at the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1026 may coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least a portion of the distributed file system 1028 of the nodes c.r.1016(1) -1016(N), the grouping computing resources 1014, and/or the framework layer 1020. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web searching software, email virus scanning software, database software, and streaming video content software.

In at least one embodiment, the applications 1042 included in the application layer 1040 can include one or more types of applications used by at least a portion of the nodes c.r.1016(1) -1016(N), the grouped computing resources 1714, and/or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, the one or more types of applications can include, but are not limited to, any number of genomic applications, cognitive computing and machine learning applications, including training or reasoning software, machine learning framework software (e.g., PyTorch, tensrflow, Caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

In at least one embodiment, any of configuration manager 1024, resource manager 1026, and resource coordinator 1012 may implement any number and type of self-modifying actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying action may mitigate a data center operator of the data center 1000 from making configuration decisions that may not be good and may avoid underutilization and/or poorly performing portions of the data center.

In at least one embodiment, data center 1000 may include tools, services, software, or other resources to train or use one or more machine learning models to predict or infer information in accordance with one or more embodiments described herein. For example, in at least one embodiment, the machine learning model may be trained by computing weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 1000. In at least one embodiment, using the weight parameters calculated through one or more training techniques described herein, the information can be inferred or predicted using the trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1000.

In at least one embodiment, the data center may use a CPU, Application Specific Integrated Circuit (ASIC), GPU, FPGA, or other hardware to perform training and/or reasoning using the above resources. Further, one or more of the software and/or hardware resources described above may be configured as a service to allow a user to train or perform information reasoning, such as image recognition, voice recognition, or other artificial intelligence services.

In at least one embodiment, a computer system as described above may be used to create a robotic control system that implements model-based and model-free control. For example, a computer system as described above may include a memory storing executable instructions that, as a result of execution by a processor of the computer system, cause the computer system to implement a model-based and model-free control system as described herein.

Autonomous vehicle

FIG. 11A illustrates an example of an autonomous vehicle 1100 in accordance with at least one embodiment. In at least one embodiment, autonomous vehicle 1100 (alternatively referred to herein as "vehicle 1100") may be, but is not limited to, a passenger vehicle, such as an automobile, a truck, a bus, and/or another type of vehicle that may house one or more passengers. In at least one embodiment, vehicle 1100 may be a semi-tractor-trailer for hauling cargo. In at least one embodiment, the vehicle 1100 may be an aircraft, a robotic vehicle, or other type of vehicle.

The automated Driving of automobiles may be described in Terms of Automation levels defined by the national highway traffic safety administration ("NHTSA") and the society of automotive engineers ("SAE") "Terms relating to Driving Automation Systems for Road Motor Vehicles (e.g., standard numbers J3016-201806 published On 6/15 th 2018, standard numbers J3016-201609 published On 30 th 2016, and previous and future versions of this standard) under the united states department of transportation. In one or more embodiments, the vehicle 1100 may be capable of functioning according to one or more of level 1 through level 5 of the autonomous driving level. For example, in at least one embodiment, the vehicle 1100 may be capable of conditional automation (level 3), highly automated (level 4), and/or fully automated (level 5), depending on the embodiment.

In at least one embodiment, the vehicle 1100 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1100 may include, but is not limited to, a propulsion system 1150 such as an internal combustion engine, a hybrid power plant, an all-electric engine, and/or another type of propulsion system. In at least one embodiment, propulsion system 1150 may be connected to a driveline of vehicle 1100, which may include, but is not limited to, a transmission to enable propulsion of vehicle 1100. In at least one embodiment, the propulsion system 1150 may be controlled in response to receiving signals from the throttle/accelerator 1152.

In at least one embodiment, steering system 1154 (which can include, but is not limited to, a steering wheel) is used to steer vehicle 1100 (e.g., along a desired path or route) when propulsion system 1150 is operating (e.g., while the vehicle is traveling). In at least one embodiment, the steering system 1154 can receive signals from a steering actuator 1156. In at least one embodiment, the steering wheel may be optional for fully automated (level 5) functionality. In at least one embodiment, the brake sensor system 1146 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1148 and/or brake sensors.

In at least one embodiment, the controller 1136 may include, but is not limited to, one or more systems on a chip ("SoC") (not shown in fig. 11A) and/or a graphics processing unit ("GPU") to provide signals (e.g., representative of commands) to one or more components and/or systems of the vehicle 1100. For example, in at least one embodiment, the controller 1136 may send signals to operate vehicle brakes via a brake actuator 1148, a steering system 1154 via a steering actuator 1156, and/or a propulsion system 1150 via a throttle/accelerator 1152. In at least one embodiment, the controller 1136 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representative of the commands) to implement autopilot and/or assist a driver in driving the vehicle 1100. In at least one embodiment, the controllers 1136 may include a first controller for an autopilot function, a second controller for a functional safety function, a third controller for an artificial intelligence function (e.g., computer vision), a fourth controller for an infotainment function, a fifth controller for redundancy in case of emergency, and/or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and/or any combination thereof.

In at least one embodiment, the controller 1136 provides signals for controlling one or more components and/or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from sensors, sensor types such as, but not limited to, global navigation satellite system ("GNSS") sensors 1158 (e.g., global positioning system sensors), RADAR sensors 1160, ultrasonic sensors 1162, LIDAR sensors 1164, Inertial Measurement Unit (IMU) sensors 1166 (e.g., accelerometers, gyroscopes, magnetic compasses, magnetometers, etc.), microphones 1196, stereo cameras 1168, wide-angle cameras 1170 (e.g., fisheye cameras), infrared cameras 1172, surround cameras 1174 (e.g., 360 degree cameras), remote cameras (not shown in fig. 11A), mid-range cameras (not shown in fig. 11A), speed sensors 1144 (e.g., for measuring the speed of the vehicle 1100), vibration sensors 1142, steering sensors 1140, brake sensors (e.g., as part of a brake sensor system 1146), and/or other sensor types.

In at least one embodiment, one or more controllers 1136 can receive input (e.g., represented by input data) from a dashboard 1132 of vehicle 1100 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1134, voice annunciators, speakers, and/or other components of vehicle 1100. In at least one embodiment, the output may include information such as vehicle speed, time, map data (e.g., a high-definition map (not shown in FIG. 11A), location data (e.g., the location of the vehicle 1100, e.g., on a map), directions, the location of other vehicles (e.g., occupancy gratings), information about objects, and the status of objects as perceived by the controller 1136, etc. for example, in at least one embodiment, the HMI display 1134 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and/or information about driving operations that the vehicle has, is, or will make (e.g., is now changing lanes, is exiting 34B exit in two miles, etc.).

In at least one embodiment, the vehicle 1100 further includes a network interface 1124, which may communicate over one or more networks using a wireless antenna 1126 and/or a modem. For example, in at least one embodiment, network interface 1124 may be capable of communicating over long term evolution ("LTE"), wideband code division multiple access ("WCDMA"), universal mobile telecommunications system ("UMTS"), global system for mobile communications ("GSM"), IMT-CDMA multi-carrier ("CDMA 2000") networks, and/or the like. In at least one embodiment, the wireless antenna 1126 may also enable communication between objects (e.g., vehicles, mobile devices) in an environment using a local area network (e.g., Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and/or a Low Power Wide Area Network (LPWAN) (e.g., LoRaWAN, SigFox, etc.).

In at least one embodiment, the techniques described herein may be used to control an autonomous vehicle. For example, a model-based control algorithm may be used to position the vehicle for parking, while a model-free RL network may be used to park the vehicle.

Fig. 11B illustrates an example of camera positions and field of view of the autonomous vehicle 1100 of fig. 11A in accordance with at least one embodiment. In at least one embodiment, the cameras and respective fields of view are one example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and/or alternative cameras may be included and/or may be located at different locations on vehicle 1100.

In at least one embodiment, the type of camera used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and/or systems of the vehicle 1100. In at least one embodiment, one or more cameras may operate at automotive safety integrity level ("ASIL") B and/or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red transparent ("RCCC") color filter array, a red transparent blue ("RCCB") color filter array, a red blue green transparent ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer (Bayer) sensor ("RGGB") color filter array, a monochrome sensor color filter array, and/or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an RCCC, RCCB, and/or RBGC color filter array, may be used in an effort to improve light sensitivity.

In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlamp control. In at least one embodiment, one or more cameras (e.g., all cameras) can record and provide image data (e.g., video) simultaneously.

In at least one embodiment, one or more cameras can be installed in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, to cut out stray light and reflections from within the vehicle 1100 (e.g., reflections of the dashboard reflect off of the windshield mirrors), which can interfere with the image data capture capabilities of the cameras. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D print custom made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, the camera may be integrated into a rear view mirror. In at least one embodiment, for a side-looking camera, the camera may also be integrated into four posts at each corner of the cabin.

In at least one embodiment, a camera having a field of view that includes a portion of the environment in front of the vehicle 1100 (e.g., a forward-facing camera) can be used to look around and, with the aid of one or more controllers 1136 and/or control socs, help identify forward paths and obstacles, thereby providing information critical to generating an occupancy grid and/or determining a preferred vehicle path. In at least one embodiment, the forward facing camera may be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward facing camera may also be used for ADAS functions and systems including, but not limited to, lane departure warning ("LDW"), automatic cruise control ("ACC"), and/or other functions (e.g., traffic sign recognition).

In at least one embodiment, various cameras may be used in a forward configuration, including, for example, a monocular camera platform including a CMOS ("complementary metal oxide semiconductor") color imager. In at least one embodiment, a wide angle camera 1170 can be used to perceive objects entering from the periphery (e.g., pedestrians, road crossings, or bicycles). Although only one wide-angle camera 1170 is shown in fig. 11B, in other embodiments, there may be any number (including zero) of wide-angle cameras 1170 on the vehicle 1100. In at least one embodiment, any number of remote cameras 1198 (e.g., remote stereo camera pairs) may be used for depth-based object detection, particularly for objects that have not yet trained a neural network. In at least one embodiment, remote cameras 1198 may also be used for object detection and classification and basic object tracking.

In at least one embodiment, any number of stereo cameras 1168 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 1168 may include an integrated control unit that includes a scalable processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a single on-chip integrated controller area network ("CAN") or ethernet interface. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1100, including distance estimates for all points in the image. In at least one embodiment, the one or more stereo cameras 1168 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one left and right, respectively) and one image processing chip, which may measure the distance from the vehicle 1100 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1168 may be used in addition to those described herein.

In at least one embodiment, a camera having a field of view that includes a portion of the environment to the side of the vehicle 1100 (e.g., a side view camera) may be used for surround viewing, providing information for creating and updating an occupancy grid, and generating side impact warnings. For example, in at least one embodiment, surround cameras 1174 (e.g., four surround cameras as shown in fig. 11B) may be positioned on the vehicle 1100. In at least one embodiment, the surround cameras 1174 may include, but are not limited to, any number and combination of wide angle cameras, fisheye lenses, 360 degree cameras, and/or similar cameras. For example, in at least one embodiment, four fisheye lens cameras may be located at the front, back, and sides of the vehicle 1100. In at least one embodiment, the vehicle 1100 can use three surround cameras 1174 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth, looking-around camera.

In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1100 (e.g., a rear view camera) may be used for parking assistance, looking around, rear collision warning, and creating and updating occupancy rasters. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as forward facing cameras (e.g., remote camera 1198 and/or mid-range camera 1176, stereo camera 1168, infrared camera 1172, etc.), as described herein.

Inference and/or training logic 815 is operable to perform inference and/or training operations related to one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, inference and/or training logic 815 can be employed in the system of fig. 11B to infer or predict operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein.

In at least one embodiment, a robotic control system as described herein may be used to navigate an autonomous vehicle. For example, a model-based control system may use a map and GPS signals to navigate a car, while a control without a model is used to provide a lane keeping function while driving.

Fig. 11C illustrates a block diagram of an example system architecture of the autonomous vehicle 1100 of fig. 11A, in accordance with at least one embodiment. In at least one embodiment, each of the components, features, and systems of vehicle 1100 in fig. 11C are shown connected via a bus 1102. In at least one embodiment, bus 1102 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, the CAN bus CAN be a network internal to the vehicle 1100 for assisting in controlling various features and functions of the vehicle 1100, such as brake actuation, acceleration, braking, steering, wipers, and the like. In one embodiment, bus 1102 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). In at least one embodiment, the bus 1102 may be read to find steering wheel angle, ground speed, number of revolutions per minute ("RPM") of the engine, button position, and/or other vehicle status indicators. In at least one embodiment, bus 1102 may be an ASIL B compliant CAN bus.

In at least one embodiment, FlexRay and/or Ethernet (Ethernet) may be used in addition to or from CAN. In at least one embodiment, there may be any number of buses forming bus 1102, which may include, but is not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and/or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1102 can be used to perform different functions, and/or can be used for redundancy. For example, the first bus 1102 may be used for collision avoidance functionality and the second bus 1102 may be used for actuation control. In at least one embodiment, each of buses 1102 may communicate with any component of vehicle 1100, and two or more of buses 1102 may communicate with the respective components. In at least one embodiment, each of any number of system-on-a-chip ("SoC") 1104 (e.g., SoC1104(a) and SoC1104(B)), each of the controllers 1136 and/or each computer within the vehicle may have access to the same input data (e.g., input from sensors of the vehicle 1100), and may be connected to a common bus, such as a CAN bus.

In at least one embodiment, the vehicle 1100 may include one or more controllers 1136, such as those described herein with respect to fig. 11A. The controller 1136 may be used for a variety of functions. In at least one embodiment, the controller 1136 can be coupled to any of a variety of other components and systems of the vehicle 1100, and can be used to control the vehicle 1100, artificial intelligence of the vehicle 1100, infotainment of the vehicle 1100, and/or other functions.

In at least one embodiment, the vehicle 1100 can include any number of socs 1104. SoC in at least one embodiment, each of 1104 may include, but is not limited to, a central processing unit ("CPU") 1106, a graphics processing unit ("GPU") 1108, a processor 1110, a cache 1112, an accelerator 1114, a data store 1116, and/or other components and features not shown. In at least one embodiment, the SoC 1104 can be used to control the vehicle 1100 in a variety of platforms and systems. For example, in at least one embodiment, SoC 1104 may be combined in a system (e.g., a system of vehicle 1100) with a high definition ("HD") map 1122, which high definition map 1122 may obtain map refreshes and/or updates from one or more servers (not shown in fig. 11C) via network interface 1124.

In at least one embodiment, the CPU 1106 may comprise a CPU cluster or CPU complex (alternatively referred to herein as "CCPLEX"). In at least one embodiment, CPU 1106 may include multiple cores and/or level two ("L2") caches. For example, in at least one embodiment, CPU 1106 may include eight cores in a multi-processor configuration coupled to each other. In at least one embodiment, the CPU 1106 may include four dual core clusters, with each cluster having a dedicated L2 cache (e.g., a 2 megabyte MB L2 cache). In at least one embodiment, the CPUs 1106 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of CPUs 1106 may be active at any given time.

In at least one embodiment, one or more CPUs 1106 can implement power management functions including, but not limited to, one or more of the following features: when the system is idle, each hardware module can be automatically subjected to clock gating so as to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution wait for interrupt ("WFI")/event wait ("WFE") instructions; each core can be independently powered; when all cores are clock-gated or power-gated, each cluster of cores may be independently clock-gated; and/or each cluster of cores may be power gated independently when all cores are power gated. In at least one embodiment, CPU 1106 may further implement enhanced algorithms for managing power states, wherein allowed power states and expected wake times are specified, and hardware/microcode determines which optimal power state to input for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state input sequence in software, where work is shared to microcode.

In at least one embodiment, GPU 1108 may comprise an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, GPU 1108 may be programmable and may be efficient for parallel workloads. In at least one embodiment, GPU 1108 may use an enhanced tensor instruction set. In at least one embodiment, GPU 1108 may include one or more streaming microprocessors, where each streaming microprocessor may include a level one ("L1") cache (e.g., an L1 cache having a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having a storage capacity of 512 KB). In at least one embodiment, GPU 1108 may include at least eight streaming microprocessors. In at least one embodiment, GPU 1108 may use a computing Application Programming Interface (API). In at least one embodiment, GPU 1108 may use one or more parallel computing platforms and/or programming models (e.g., CUDA model of NVIDIA).

In at least one embodiment, one or more GPUs 1108 may be power consumption optimized for best performance in automotive and embedded use cases. For example, in one embodiment, GPU 1108 may be fabricated on a fin field effect transistor ("FinFET") circuit. In at least one embodiment, each streaming microprocessor may contain multiple mixed-precision processing cores divided into multiple blocks. For example, but not limiting of, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 COREs, 8 FP64 COREs, 16 INT32 COREs, two mixed precision NVIDIA TENSOR CORE for deep learning matrix arithmetic, level zero ("L0") instruction cache, thread bundle scheduler, dispatch unit, and/or 64KB register file. In at least one embodiment, a streaming microprocessor may include independent parallel integer and floating point data paths to provide efficient execution of the workload of mixed compute and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

In at least one embodiment, one or more GPUs 1108 may include a high bandwidth memory ("HBM") and/or 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB/sec in some examples. In at least one embodiment, a synchronous graphics random access memory ("SGRAM"), such as a graphics double data rate type five-synchronous random access memory ("GDDR 5"), may be used in addition to or in place of HBM memory.

In at least one embodiment, GPU 1108 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow GPU 1108 to directly access CPU 1106 page tables. In at least one embodiment, the address translation request may be sent to CPU 1106 when a CPU memory management unit ("MMU") in GPU 1108 experiences a miss. In response, in at least one embodiment, two of CPUs 1106 can look up the virtual-to-physical mapping of addresses in their page tables and communicate the translation back to GPU 1108. In at least one embodiment, unified memory technology may allow a single unified virtual address space for both CPU 1106 and GPU 1108 memory, thereby simplifying programming of GPU 1108 and porting applications to GPU 1108.

In at least one embodiment, GPU1108 may include any number of access counters that may track the frequency of accesses by GPU1108 to the memory of other processors. In at least one embodiment, the access counters may help to ensure that memory pages are moved into the physical memory of the processor that most frequently accesses the pages, thereby increasing the efficiency of the memory range shared between processors.

In at least one embodiment, one or more socs 1104 can include any number of caches 1112, including those described herein. For example, in at least one embodiment, the cache 1112 may include a three-level ("L3") cache available to the CPU1106 and the GPU1108 (e.g., connecting the two CPUs 1106 and the GPU 1108). In at least one embodiment, cache 1112 may include a write-back cache that may track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB or more, depending on the embodiment, although smaller cache sizes may be used.

In at least one embodiment, the one or more socs 1104 can include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC 1104 may include a hardware acceleration cluster, which may include optimized hardware accelerators and/or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable hardware acceleration clusters to accelerate neural networks and other computations. In at least one embodiment, hardware accelerated clusters may be used to supplement GPU1108 and offload some tasks of GPU1108 (e.g., free up more cycles of GPU1108 to perform other tasks). In at least one embodiment, the accelerator 1114 can be used for target workloads that are stable enough to withstand acceleration checks (e.g., perceptions, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.). In at least one embodiment, the CNNs may include region-based or region-convolutional neural networks ("RCNNs") and fast RCNNs (e.g., as used for object detection), or other types of CNNs.

In at least one embodiment, the accelerator 1114 (e.g., a hardware acceleration cluster) can include a deep learning accelerator ("DLA"). In at least one embodiment, the DLA may include, but is not limited to, one or more Tensor processing units ("TPU"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. In at least one embodiment, the TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, the DLA can be further optimized for a particular set of neural network types and floating point operations and reasoning. In at least one embodiment, the design of a DLA may provide higher per millimeter performance than a typical general purpose GPU, and often significantly exceed the performance of a CPU. In at least one embodiment, the TPU may perform several functions, including single instance convolution functions and post-processor functions that support, for example, INT8, INT16, and FP16 data types for features and weights. In at least one embodiment, the DLA may quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: CNN for object recognition and detection using data from camera sensors; CNN for distance estimation using data from camera sensors; CNN for emergency vehicle detection and identification and detection using data from the microphone; a CNN for face recognition and car owner recognition using data from the camera sensor; and/or CNN for security and/or security related events.

In at least one embodiment, the DLA may perform any function of GPU 1108, and through the use of an inference accelerator, for example, a designer may target either the DLA or GPU 1108 for any function. For example, in at least one embodiment, the designer may focus CNN processing and floating point operations on the DLA and leave other functionality to GPU 1108 and/or accelerator 1114.

In at least one embodiment, the accelerator 1114 may comprise a programmable visual accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1138, autonomous driving, augmented reality ("AR") applications, and/or virtual reality ("VR") applications. In at least one embodiment, PVA can be balanced between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and/or any number of vector processors.

In at least one embodiment, the RISC core may interact with an image sensor (e.g., of any of the cameras described herein), an image signal processor, and the like. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and/or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and/or tightly coupled RAM.

In at least one embodiment, DMA may enable components of the PVA to access system memory independently of CPU 1106. In at least one embodiment, the DMA may support any number of features for providing optimization to the PVA, including, but not limited to, support for multidimensional addressing and/or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block stepping, vertical block stepping, and/or depth stepping.

In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, DMA engines (e.g., two DMA engines), and/or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the primary processing engine for the PVA, and may include a vector processing unit ("VPU"), an instruction cache, and/or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU can include a digital signal processor, such as a single instruction multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

In at least one embodiment, each vector processor may include an instruction cache and may be coupled to a dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA can be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA can execute a common computer vision algorithm, except on different areas of the image. In at least one embodiment, the vector processor included in a particular PVA may perform different computer vision algorithms on the same image simultaneously, or even on sequential or partial images. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA, among others. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance overall system security.

In at least one embodiment, the accelerator 1114 can include an on-chip computer vision network and static random access memory ("SRAM") to provide the accelerator 1114 with high bandwidth, low latency SRAM. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks, which may be accessed by both PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone network that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and DLA to memory (e.g., using APB).

In at least one embodiment, the computer-on-chip visual network may include an interface that determines that both the PVA and DLA provide ready and valid signals prior to transmitting any control signals/addresses/data. In at least one embodiment, the interface may provide a separate phase and separate channel for sending control signals/addresses/data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may conform to the international organization for standardization ("ISO") 26262 or international electrotechnical commission ("IEC") 61508 standards, although other standards and protocols may be used.

In at least one embodiment, one or more socs 1104 can include a real-time line-of-sight tracking hardware accelerator. In at least one embodiment, a real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of objects (e.g., within a world model), to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and/or analysis, for simulations of SONAR systems, for general wave propagation simulations, comparison with LIDAR data for localization and/or other functions, and/or for other uses.

In at least one embodiment, the accelerator 1114 has a wide range of uses for autonomous driving. In at least one embodiment, PVA may be used in key processing stages in ADAS and autonomous cars. In at least one embodiment, the capabilities of the PVA at low power consumption and low latency are well matched to the domain of the algorithm that requires predictable processing. In other words, PVA performs well in semi-intensive or intensive conventional computing, even on small data sets that may require predictable runtime with low latency and low power consumption. In at least one embodiment, such as vehicle 1100, PVAs can be designed to run classical computer vision algorithms because they are efficient in object detection and integer mathematical operations.

For example, in accordance with at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching based algorithm may be used in some examples, although this is not meant to be limiting. In at least one embodiment, the application for level 3-5 autopilot uses dynamic estimation/stereo matching on the fly (e.g., recovery of structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, the PVA can perform computer stereo vision functions on input from two monocular cameras.

In at least one embodiment, PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process the raw RADAR data (e.g., using a 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

In at least one embodiment, the DLA may be used to run any type of network to enhance control and driving safety, including for example, but not limited to, a neural network that outputs a confidence for each object detection. In at least one embodiment, the confidence level may be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to the other detections. In at least one embodiment, the confidence level enables the system to make further decisions as to which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system may set a threshold for the confidence level, and only detect exceeding the threshold are considered true positive detections. In one embodiment using an automatic emergency braking ("AEB") system, a false positive detection would result in the vehicle automatically performing emergency braking, which is clearly undesirable. In at least one embodiment, the detection of high confidence may be considered a trigger for the AEB. In at least one embodiment, the DLA may run a neural network for regressing confidence values. In at least one embodiment, the neural network may have as its inputs at least some subset of the parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of IMU sensors 1166 related to vehicle 1100 direction, distance, 3D position estimates of objects obtained from the neural network and/or other sensors (e.g., LIDAR sensor 1164 or RADAR sensor 1160), and so forth.

In at least one embodiment, one or more socs 1104 can include a data memory 1116 (e.g., a memory). In at least one embodiment, data storage 1116 may be an on-chip memory of SoC 1104, which may store a neural network to be executed on GPU 1108 and/or a DLA. In at least one embodiment, the data store 1116 may have a capacity large enough to store multiple instances of a neural network for redundancy and security. In at least one embodiment, data store 1116 may include an L2 or L3 cache.

In at least one embodiment, one or more socs 1104 can include any number of processors 1110 (e.g., embedded processors). In at least one embodiment, processor 1110 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the SoC 1104 boot sequence and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low power state transitions, SoC 1104 thermal and temperature sensor management, and/or SoC 1104 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 1104 may use the ring oscillator to detect the temperature of the CPU 1106, GPU 1108, and/or accelerator 1114. In at least one embodiment, if it is determined that the temperature exceeds the threshold, the boot and power management processor can enter a temperature fault routine and place the SoC 1104 in a lower power consumption state and/or place the vehicle 1100 in a safe parking pattern for the driver (e.g., to safely park the vehicle 1100).

In at least one embodiment, the one or more processors 1110 may further include a set of embedded processors that may serve as an audio processing engine, which may be an audio subsystem capable of providing hardware with full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I/O interfaces. In at least one embodiment, the audio processing engine is a special purpose processor core having a digital signal processor with a special purpose RAM.

In at least one embodiment, the processor 1110 may further include an always-on processor engine that may provide the necessary hardware features to support low power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, processor cores, tightly coupled RAM, support peripherals (e.g., timers and interrupt controllers), various I/O controller peripherals, and routing logic.

In at least one embodiment, processor 1110 may further include a security cluster engine including, but not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, support peripherals (e.g., timers, interrupt controllers, etc.), and/or routing logic. In the secure mode, in at least one embodiment, two or more cores may operate in lockstep mode and may act as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, processor 1110 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor 1110 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

In at least one embodiment, processor 1110 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by the video playback application to generate the final video to generate the final image for the player window. In at least one embodiment, the video image synthesizer can perform lens distortion correction on the wide angle camera 1170, the surround cameras 1174, and/or the in-cabin surveillance camera sensors. In at least one embodiment, the in-cabin surveillance camera sensor is preferably monitored by a neural network running on another instance of the SoC 1104, the neural network configured to recognize cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular services and make phone calls, indicate email, change the destination of the vehicle, activate or change the infotainment systems and settings of the vehicle, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in the autonomous mode, and are otherwise disabled.

In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, temporal noise reduction performed by a video image compositor may use information from a previous image to reduce noise in a current image.

In at least one embodiment, the video image compositor may be further configured to perform stereo correction on the input stereo lens frames. In at least one embodiment, the video image compositor may also be used for user interface compositing when using an operating system desktop, and GPU 1108 is not required to continuously render new surfaces. In at least one embodiment, a video image compositor may be used to offload GPU 1108 to improve performance and responsiveness when GPU 1108 is powered and actively rendering 3D.

In at least one embodiment, one or more of socs 1104 may further include a mobile industrial processor interface ("MIPI") camera serial interface for receiving video and input from a camera, a high speed interface, and/or a video input block that may be used for camera and related pixel input functions. In at least one embodiment, one or more of socs 1104 can further include an input/output controller that can be controlled by software and can be used to receive I/O signals that are not submitted to a particular role.

In at least one embodiment, one or more of socs 1104 can further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio coder/decoders ("codecs"), power management, and/or other devices. In at least one embodiment, SoC 1104 CAN be used to process data from cameras, sensors (e.g., LIDAR sensor 1164, RADAR sensor 1160, etc., which CAN be connected through an ethernet network) (e.g., connected through a gigabit multimedia serial link and an ethernet network), data from bus 1102 (e.g., speed of vehicle 1100, steering wheel position, etc.), data from GNSS sensor 1158 (e.g., connected through an ethernet or CAN bus), and so forth. In at least one embodiment, one or more socs 1104 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines, and may be used to free CPU 1106 from conventional data management tasks.

In at least one embodiment, SoC 1104 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, providing a comprehensive functional security architecture that leverages and efficiently uses computer vision and ADAS technology to achieve diversity and redundancy, providing a platform that can provide a flexible, reliable driving software stack and deep learning tools. In at least one embodiment, the SoC 1104 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, the accelerator 1114, when combined with the CPU 1106, GPU 1108, and data memory 1116, can provide a fast, efficient platform for a class 3-5 autonomous vehicle.

In at least one embodiment, the computer vision algorithms may be executed on a CPU, which may be configured using a high-level programming language (e.g., C programming language) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU is generally unable to meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs are not capable of executing complex object detection algorithms in real time that are used in onboard ADAS applications and in real class 3-5 autonomous vehicles.

The embodiments described herein allow multiple neural networks to be executed simultaneously and/or sequentially, and allow the results to be combined together to achieve a level 3-5 autopilot function. For example, in at least one embodiment, CNNs executed on DLAs or discrete GPUs (e.g., GPU 1120) may include text and word recognition, allowing reading and understanding of traffic signs, including signs where the neural network has not been trained specifically. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing a semantic understanding of the symbols and passing the semantic understanding to a path planning module running on the CPU Complex.

In at least one embodiment, multiple neural networks may be run simultaneously for 3, 4, or 5 levels of drive. For example, in at least one embodiment, the message "alert: the flashing lights indicate warning signs of icing conditions (discharge light indication conditions), which, together with the connected lights, can be interpreted independently or collectively by a plurality of neural networks. In at least one embodiment, the warning sign itself may be recognized as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "flashing light indication icing conditions" may be interpreted by a second deployed neural network, which informs the vehicle's path planning software (preferably executing on CPU Complex): when a flashing light is detected, an icing condition exists. In at least one embodiment, the flashing lights may be identified by operating the third deployed neural network over a plurality of frames, notifying the path planning software of the vehicle of the presence (or absence) of the flashing lights. In at least one embodiment, all three neural networks may be running simultaneously, e.g., within a DLA and/or on GPU 1108.

In at least one embodiment, the CNN for facial recognition and vehicle owner recognition may use data from the camera sensor to identify the presence of an authorized driver and/or owner of the vehicle 1100. In at least one embodiment, a normally open sensor processor engine may be used to unlock the vehicle when the owner approaches the driver door and turns on the lights, and may be used to disable the vehicle when the owner leaves the vehicle in a safe mode. In this manner, the SoC 1104 provides safeguards against theft and/or hijacking.

In at least one embodiment, the CNN used for emergency vehicle detection and identification may use data from the microphone 1196 to detect and identify an emergency vehicle alarm. In at least one embodiment, the SoC 1104 uses CNNs to classify environmental and urban sounds, as well as to classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approach speed of the emergency vehicle (e.g., by using the doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by GNSS sensors 1158. In at least one embodiment, while operating in europe, the CNN will seek to detect european alarms, while in north america, the CNN will seek to identify only north american alarms. In at least one embodiment, once an emergency vehicle is detected, the control program may be used with the assistance of the ultrasonic sensors 1162 to execute emergency vehicle safety routines, slow the vehicle down, drive the vehicle to the curb, park, and/or idle the vehicle until the emergency vehicle passes.

In at least one embodiment, the vehicle 1100 can include a CPU 1118 (e.g., a discrete CPU or dCPU) that can be coupled to the SoC 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the CPU 1118 may include an X86 processor, for example, the CPU 1118 may be configured to perform any of a variety of functions, including, for example, the result of potential arbitration inconsistencies between ADAS sensors and the SoC 1104, and/or monitoring the status and health of the controller 1136 and/or information system on a chip ("information SoC") 1130.

In at least one embodiment, vehicle 1100 can include GPU 1120 (e.g., a discrete GPU or a dGPU), which can be coupled to SoC 1104 via a high-speed interconnect (e.g., NVLINK channel of NVIDIA). In at least one embodiment, GPU 1120 may provide additional artificial intelligence functionality, such as by executing redundant and/or different neural networks, and may be used to train and/or update the neural networks based at least in part on input from sensors (e.g., sensor data) of vehicle 1100.

In at least one embodiment, the vehicle 1100 may further include a network interface 1124, which may include, but is not limited to, a wireless antenna 1126 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a bluetooth antenna, etc.). In at least one embodiment, the network interface 1124 can be used to wirelessly connect over the internet with cloud services (e.g., servers and/or other network devices), other vehicles, and/or computing devices (e.g., passenger's client devices). In at least one embodiment, a direct link can be established between the vehicle 1100 and another vehicle and/or an indirect link can be established (e.g., over a network and the internet) for communicating with other vehicles. In at least one embodiment, a direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide information to vehicle 1100 about vehicles in the vicinity of vehicle 1100 (e.g., vehicles in front of, to the side of, and/or behind vehicle 1100). In at least one embodiment, the aforementioned functionality may be part of a cooperative adaptive cruise control function of vehicle 1100.

In at least one embodiment, network interface 1124 may include a SoC that provides modulation and demodulation functions and enables controller 1136 to communicate over a wireless network. In at least one embodiment, network interface 1124 can include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, the frequency conversion may be performed in any technically feasible manner. For example, the frequency conversion may be performed by a well-known process and/or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and/or other wireless protocols.

In at least one embodiment, the vehicle 1100 may further include a data store 1128, which may include, but is not limited to, off-chip (e.g., off-chip SoC 1104) memory. In at least one embodiment, the data memory 1128 can include, but is not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and/or other components and/or devices that can store at least one bit of data.

In at least one embodiment, the vehicle 1100 may further include GNSS sensors 1158 (e.g., GPS and/or assisted GPS sensors) to assist with mapping, perception, occupancy raster generation, and/or path planning functions. In at least one embodiment, any number of GNSS sensors 1158 may be used, including for example and without limitation GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

In at least one embodiment, the vehicle 1100 may further include one or more RADAR sensors 1160. In at least one embodiment, the RADAR sensor 1160 can be used by the vehicle 1100 for remote vehicle detection, even in dark and/or severe weather conditions. In at least one embodiment, the RADAR function security level may be ASIL B. In at least one embodiment, the RADAR sensor 1160 CAN use the CAN and/or the bus 1102 (e.g., to transmit data generated by the RADAR sensor 1160) for control and access to object tracking data, and in some examples, CAN access the ethernet to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limiting of, the RADAR sensor 1160 may be suitable for anterior, posterior, and lateral RADAR use. In at least one embodiment, the one or more RADAR sensors 1160 are pulsed doppler RADAR sensors.

In at least one embodiment, the RADAR sensor 1160 may include different configurations, such as a long range with a narrow field of view, a short range with a wide cause, short range side coverage, and the like. In at least one embodiment, the remote RADAR may be used for adaptive cruise control functions. In at least one embodiment, the remote RADAR system may provide a wide field of view achieved by two or more independent scans (e.g., in the range of 250 m). In at least one embodiment, RADAR sensors 1160 may help distinguish between static objects and moving objects and may be used by ADAS system 1138 for emergency braking assistance and forward collision warning. In at least one embodiment, the sensors 1160 included in the remote RADAR system may include, but are not limited to, a single-base multi-mode RADAR having multiple (e.g., six or more) stationary RADAR antennas and a high-speed CAN and FlexRay interface. In at least one embodiment, having six antennas, four antennas in the center, can create a focused beam pattern designed to record the surroundings of the vehicle 1100 at higher speeds with minimal traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view so that a vehicle entering or leaving the lane of the vehicle 1100 can be quickly detected.

In at least one embodiment, the mid-range RADAR system may include a range of up to 160m (anterior) or 80m (posterior), and a field of view of up to 42 degrees (anterior) or 150 degrees (posterior), as examples. In at least one embodiment, the short-range RADAR system can include, but is not limited to, any number of RADAR sensors 1160 designed to be mounted at both ends of the rear bumper. When mounted at both ends of a rear bumper, in at least one embodiment, the RADAR sensor system can generate two beams that constantly monitor the rear of the vehicle and the blind spots in the vicinity. In at least one embodiment, the short range RADAR system may be used in the ADAS system 1138 for blind spot detection and/or lane change assistance.

In at least one embodiment, the vehicle 1100 may further include one or more ultrasonic sensors 1162. In at least one embodiment, ultrasonic sensors 1162, which may be positioned at front, rear, and/or side locations of vehicle 1100, may be used for parking assistance and/or to create and update occupancy gratings. In at least one embodiment, a wide variety of ultrasonic sensors 1162 can be used, and different ultrasonic sensors 1162 can be used for different detection ranges (e.g., 2.5m, 4 m). In at least one embodiment, the ultrasonic sensors 1162 may operate at the functional safety level of ASIL B.

In at least one embodiment, the vehicle 1100 may include one or more LIDAR sensors 1164. In at least one embodiment, the LIDAR sensor 1164 may be used for object and pedestrian detection, emergency braking, collision avoidance, and/or other functions. In at least one embodiment, the LIDAR sensor 1164 may operate at a functional security level ASIL B. In at least one embodiment, the vehicle 1100 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1164 (e.g., providing data to a gigabit ethernet switch) that can use an ethernet channel.

In at least one embodiment, the LIDAR sensor 1164 may be capable of providing a list of objects and their distances for a 360 degree field of view. In at least one embodiment, a commercially available LIDAR sensor 1164 may have an advertising range of approximately 100m, have an accuracy of 2cm-3cm, and support an Ethernet connection of 100Mbps, for example. In at least one embodiment, one or more non-protruding LIDAR sensors 1164 can be used. In such embodiments, the LIDAR sensor 1164 may be comprised of small devices embedded in the front, back, sides, and/or corners of the vehicle 1100. In at least one embodiment, the LIDAR sensor 1164, in such an embodiment, may provide up to 120 degrees of horizontal view and 35 degrees of vertical view, even for low reflectivity objects, and have a range of 200 m. In at least one embodiment, the forward LIDAR sensor 1164 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, the 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around the vehicle 1100. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse travel time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1100 to the object. In at least one embodiment, a flash LIDAR may allow each laser flash to be utilized to generate a highly accurate and distortion-free image of the surrounding environment. In at least one embodiment, four flashing LIDAR sensors may be deployed, one on each side of the vehicle 1100. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, a flashing LIDAR device may use 5 nanoseconds of class I (eye safe) laser pulses per frame and may capture reflected laser light in the form of a 3D ranging point cloud and co-registered intensity data.

In at least one embodiment, the vehicle may also include IMU sensors 1166. In at least one embodiment, the IMU sensor 1166 may be located in the rear axle center of the vehicle 1100, in at least one embodiment. In at least one embodiment, IMU sensors 1166 may include, for example and without limitation, accelerometers, magnetometers, gyroscopes, magnetic compasses, and/or other sensor types. In at least one embodiment, for example in a six-axis application, IMU sensors 1166 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, IMU sensors 1166 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

In at least one embodiment, the IMU sensors 1166 may be implemented as a miniature high-performance GPS assisted inertial navigation system ("GPS/INS") incorporating micro-electromechanical systems ("MEMS") inertial sensors, high-sensitivity GPS receivers, and advanced kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, IMU sensor 1166 may enable vehicle 1100 to estimate heading without input from a magnetic sensor by directly observing and correlating changes in speed from the GPS to IMU sensor 1166. In at least one embodiment, IMU sensors 1166 and GNSS sensors 1158 may be combined in a single integrated unit.

In at least one embodiment, the vehicle 1100 may include a microphone 1196 placed in and/or around the vehicle 1100. In at least one embodiment, microphone 1196 may additionally be used for emergency vehicle detection and identification.

In at least one embodiment, the vehicle 1100 may further include any number of camera types, including a stereo camera 1168, a wide-angle camera 1170, an infrared camera 1172, a surround camera 1174, a remote camera 1198, a mid-range camera 1176, and/or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire periphery of the vehicle 1100. In at least one embodiment, the type of camera used depends on the vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1100. In at least one embodiment, the number of cameras may vary from embodiment to embodiment. For example, in at least one embodiment, the vehicle 1100 may include six cameras, seven cameras, ten cameras, twelve cameras, or other number of cameras. In at least one embodiment, the camera may support, by way of example and not limitation, gigabit multimedia serial link ("GMSL") and/or gigabit ethernet. In at least one embodiment, each camera is described in more detail herein before with reference to fig. 11A and 11B.

In at least one embodiment, the vehicle 1100 may further include a vibration sensor 1142. In at least one embodiment, the vibration sensor 1142 may measure vibrations of a component (e.g., a shaft) of the vehicle 1100. For example, in at least one embodiment, a change in vibration may indicate a change in road surface. In at least one embodiment, when two or more vibration sensors 1142 are used, the difference between the vibrations may be used to determine friction or slip of the road surface (e.g., when there is a vibration difference between the powered drive shaft and the free rotating shaft).

In at least one embodiment, vehicle 1100 may include an ADAS system 1138. In some examples, ADAS system 1138 may include, but is not limited to, a SoC. In at least one embodiment, ADAS system 1138 may include, but is not limited to, any number and combination of autonomous/adaptive/auto cruise control ("ACC") systems, coordinated adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and/or other systems, features, and/or functions.

In at least one embodiment, the ACC system may use the RADAR sensor 1160, the LIDAR sensor 1164, and/or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and/or a transverse ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle in close proximity to the vehicle 1100 and automatically adjusts the speed of the vehicle 1100 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance maintenance and advises the vehicle 1100 to change lanes when needed. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via a wireless link or indirectly via a network connection (e.g., via the internet) via network interface 1124 and/or wireless antenna 1126. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communications provide information about the immediately preceding vehicle (e.g., the vehicle immediately preceding and in the same lane as vehicle 1100), while I2V communications provide information about more forward traffic. In at least one embodiment, the CACC system may include one or both of I2V and V2V information sources. In at least one embodiment, the CACC system may be more reliable given the information of vehicles ahead of vehicle 1100, and have the potential to improve smoothness of traffic flow and reduce road congestion.

In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward facing camera and/or RADAR sensor 1160 coupled to a dedicated processor, DSP, FPGA and/or ASIC that is electrically coupled to driver feedback, such as a display, speaker and/or vibration assembly. In at least one embodiment, the FCW system may provide a warning, for example in the form of an audible, visual warning, vibration, and/or rapid braking pulse.

In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and may automatically apply the brakes if the driver takes no corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a forward facing camera and/or RADAR sensor 1160 coupled to a dedicated processor, DSP, FPGA and/or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system will typically first alert the driver to take corrective action to avoid the collision, and if that driver does not take corrective action, the AEB system may automatically apply brakes in an attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and/or imminent-collision braking.

In at least one embodiment, the LDW system provides a visual, audible, and/or tactile warning, such as a steering wheel or seat vibration, to alert the driver when the vehicle 1100 crosses a lane marker. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, for example, by activating a turn signal light. In at least one embodiment, the LDW system may use a front facing camera coupled to a special purpose processor, DSP, FPGA and/or ASIC that is electrically coupled to components such as a display, speakers and/or vibration. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1100 begins to leave the lane, the LKA system provides steering inputs or braking to correct the vehicle 1100.

In at least one embodiment, the BSW system detects and warns the driver of the vehicle in the blind zone of the car. In at least one embodiment, the BSW system may provide a visual, audible, and/or tactile alert to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system may provide additional warnings when the driver is using the turn signal. In at least one embodiment, the BSW system can use rear facing camera and/or RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA and/or ASIC that are electrically coupled to driver feedback, such as a display, speaker and/or vibration assembly.

In at least one embodiment, the RCTW system may provide a visual, audible, and/or tactile notification when an object is detected outside of the rear camera range while the vehicle 1100 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear facing RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and/or ASIC that are electrically coupled to provide driver feedback, such as a display, speaker, and/or vibration assembly.

In at least one embodiment, conventional ADAS systems may be prone to false positive results, which may be annoying and distracting to the driver, but are generally not catastrophic, as they may alert the driver and allow the driver to decide whether a safety condition actually exists and take corresponding action. In at least one embodiment, in the event of a conflict in results, the vehicle 1100 itself decides whether to listen to the results of the primary or secondary computer (e.g., the first controller or the second controller). For example, in at least one embodiment, the ADAS system 1138 may be a backup and/or auxiliary computer that provides sensory information to the backup computer rationality module. In at least one embodiment, the standby computer rationality monitor can run redundant various software on the hardware components to detect faults in the sensing and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1138 may be provided to a monitoring MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervising MCU decides how to coordinate the conflicts to ensure safe operation.

In at least one embodiment, the host computer may be configured to provide a confidence score to the supervising MCU to indicate the confidence of the host computer on the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervising MCU may follow the direction of the primary computer regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, where the confidence score does not satisfy the threshold, and where the primary and secondary computers indicate different results (e.g., conflicts), the supervising MCU may arbitrate between the computers to determine the appropriate results.

In at least one embodiment, the supervising MCU may be configured to run a neural network that is trained and configured to determine a condition for the auxiliary computer to provide a false alarm based at least in part on an output from the main computer and an output from the auxiliary computer. In at least one embodiment, the neural network in the supervising MCU may learn when the output of the helper computer can be trusted, and when it cannot. For example, in at least one embodiment, when the helper computer is a RADAR-based FCW system, the neural network in the supervising MCU can learn when the FCW system identifies metal objects that are not actually dangerous, such as a drain grid or manhole cover that would trigger an alarm. In at least one embodiment, when the helper computer is a camera-based LDW system, the neural network in the supervising MCU can learn to override the LDW when a cyclist or pedestrian is present and indeed lane departure is the safest operation. In at least one embodiment, the supervising MCU may comprise at least one of a DLA or a GPU adapted to run a neural network with associated memory. In at least one embodiment, the supervising MCU may include and/or be included as a component of the SoC 1104.

In at least one embodiment, the ADAS system 1138 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the helper computer may use classical computer vision rules (if-then), and supervising the presence of the neural network in the MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the varied implementation and intentional non-uniformity makes the overall system more fault tolerant, especially with respect to faults caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in the software running on the main computer, and non-identical software code running on the auxiliary computer provides consistent overall results, the supervising MCU may more confidently assume that the overall results are correct, and the bug in the software or hardware on the main computer does not result in a significant error.

In at least one embodiment, the output of the ADAS system 1138 may be input into the perception module of the host computer and/or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1138 indicates a forward collision warning due to an object directly in front, the perception block may use this information in identifying the object. In at least one embodiment, as described herein, the helper computer may have its own neural network that is trained to reduce the risk of false positives.

In at least one embodiment, the vehicle 1100 may further include an infotainment SoC1130 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as a SoC, in at least one embodiment, infotainment system 1130 may not be a SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, infotainment SoC1130 may include, but is not limited to, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistants, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephony (e.g., hands-free talk), network connectivity (e.g., LTE, WiFi, etc.), and/or information services (e.g., navigation systems, post-parking assistance, radio data systems, vehicle-related information such as fuel level, total coverage distance, brake fuel level, door open/close, air filter information, etc.) to vehicle 1100. For example, infotainment SoC1130 can include a radio, disk player, navigation system, video player, USB and bluetooth connections, automobiles, in-vehicle entertainment systems, WiFi, steering wheel audio controls, hands-free voice controls, heads-up display ("HUD"), HMI display 1134, telematics devices, control panels (e.g., for controlling and/or interacting with various components, features, and/or systems), and/or other components. In at least one embodiment, the infotainment SoC1130 may further be used to provide information (e.g., visual and/or audible) to a user of the vehicle, such as information from the ADAS system 1138, automated driving information (such as planned vehicle maneuvers), trajectories, ambient environment information (e.g., intersection information, vehicle information, road information, etc.), and/or other information.

In at least one embodiment, infotainment SoC 1130 may include any number and type of GPU functionality. In at least one embodiment, infotainment SoC 1130 may communicate with other devices, systems, and/or components of vehicle 1100 via bus 1102. In at least one embodiment, the infotainment SoC 1130 may be coupled to a monitoring MCU such that the GPU of the infotainment system may perform some autopilot functions in the event of a failure of the master controller 1136 (e.g., the primary and/or backup computer of the vehicle 1100). In at least one embodiment, the infotainment SoC 1130 may place the vehicle 1100 into a driver-to-safety stop mode, as described herein.

In at least one embodiment, vehicle 1100 may further include an instrument panel 1132 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the dashboard 1132 may include, but is not limited to, controllers and/or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1132 may include, but is not limited to, any number and combination of a set of instruments such as, for example, a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, seatbelt warning light, parking brake warning light, engine fault light, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, and the like. In some examples, information may be displayed and/or shared between infotainment SoC 1130 and dashboard 1132. In at least one embodiment, dashboard 1132 may be included as part of infotainment SoC 1130 or vice versa.

Fig. 11D is a diagram of a system 1176 to communicate between a cloud-based server and the autonomous vehicle 1100 of fig. 11A, in accordance with at least one embodiment. In at least one embodiment, the system 1176 can include, but is not limited to, a server 1178, a network 1190, and any number and type of vehicles, including vehicle 1100. In at least one embodiment, server 1178 can include, but is not limited to, a plurality of GPUs 1184(a) -1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(a) -1182(D) (collectively referred to herein as PCIe switches 1182), and/or CPUs 1180(a) -1180(B) (collectively referred to herein as CPUs 1180), GPU 1184, CPU 1180, and PCIe switch 1182 can be interconnected with high-speed connection lines, such as, but not limited to, NVLink interface 1188 and/or PCIe connection 1186 developed by NVIDIA. In at least one embodiment, GPU 1184 is connected via NVLink and/or NVSwitchSoC, and GPU 1184 and PCIe switch 1182 are connected via a PCIe interconnect. In at least one embodiment, although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are shown, this is not intended to be limiting. In at least one embodiment, each of the servers 1178 can include, but is not limited to, any number of GPUs 1184, CPUs 1180, and/or PCIe switches 1182 in any combination. For example, in at least one embodiment, the servers 1178 can each include eight, sixteen, thirty-two, and/or more GPUs 1184.

In at least one embodiment, the server 1178 may receive image data representing images showing unexpected or changing road conditions, such as recently started road works, from the vehicle over the network 1190. In at least one embodiment, the server 1178 may transmit the neural network 1192, the updated neural network 1192, and/or the map information 1194, including but not limited to information about traffic and road conditions, through the network 1190 and to the vehicle. In at least one embodiment, the updates to the map information 1194 may include, but are not limited to, updates to the HD map 1122 such as information regarding a construction site, potholes, sidewalks, floods, and/or other obstacles. In at least one embodiment, the neural network 1192, and/or the map information 1194 may be generated by new training and/or experience represented in data received from any number of vehicles in the environment, and/or based at least on training performed at the data center (e.g., using the server 1178 and/or other servers).

In at least one embodiment, the server 1178 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle, and/or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the relevant neural network benefits from supervised learning) and/or subjected to other pre-processing. In at least one embodiment, no amount of training data is labeled and/or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle over network 1190, and/or the machine learning model can be used by server 1178 to remotely monitor the vehicle.

In at least one embodiment, the server 1178 can receive data from the vehicle and apply the data to the latest real-time neural network for real-time intelligent reasoning. In at least one embodiment, the server 1178 can include a deep learning supercomputer and/or a dedicated AI computer powered by the GPU 1184, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, the server 1178 may comprise a deep learning infrastructure of a data center powered using a CPU.

In at least one embodiment, the deep learning infrastructure of the server 1178 may be capable of rapid, real-time reasoning, and this capability may be used to assess and verify the health of the processors, software, and/or related hardware in the vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure can receive periodic updates from the vehicle 1100, such as a sequence of images and/or objects (e.g., via computer vision and/or other machine learning object classification techniques) in which the vehicle 1100 is positioned. In at least one embodiment, the deep learning infrastructure can run its own neural network to identify objects and compare them to those identified by the vehicle 1100, and if the results do not match and the deep learning infrastructure concludes that the AI in the vehicle 1100 is malfunctioning, the server 1178 can send a signal to the vehicle 1100 to instruct the fail-safe computer of the vehicle 1100 to take control, notify the passengers, and complete the safe parking maneuver.

In at least one embodiment, server 1178 may include a GPU 1184 and one or more programmable inference accelerators (e.g., TensorRT 3 of NVIDIA). In at least one embodiment, a combination of GPU-driven servers and inference acceleration may enable real-time responses. In at least one embodiment, servers driven by CPUs, FPGAs, and other processors can be used for reasoning, for example, where performance is less critical. In at least one embodiment, inference and/or training logic 815 is used to implement one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B.

Computer system

FIG. 12 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system on a chip (SOC), or some combination thereof, formed with a processor that may include execution units to execute instructions, according to at least one embodiment. In at least one embodiment, in accordance with the present disclosure, such as the embodiments described herein, the computer system 1200 may include, but is not limited to, a component, such as the processor 1202, whose execution unit includes logic to execute an algorithm for process data. In at least one embodiment, computer system 1200 can include a processor, such as that available from Intel Corporation of Santa Clara, CalifProcessor family, Xeon^TM、XScale^TMAnd/or StrongARM^TM，Core^TMOrNervana^TMA microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1200 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash, although other operating systems (e.g., UNIX and Linux), embedded software, and/or graphical user interfaces may also be used.

Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular telephones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions in accordance with at least one embodiment.

In at least one embodiment, the computer system 1200 may include, but is not limited to, a processor 1202, the processor 1202 may include, but is not limited to, one or more execution units 1208 to perform machine learning model training and/or reasoning in accordance with the techniques described herein. In at least one embodiment, computer system 1200 is a single-processor desktop or server system, but in another embodiment, computer system 1200 may be a multi-processor system. In at least one embodiment, the processor 1202 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1202 may be coupled to a processor bus 1210, which processor bus 1210 may transmit data signals between the processor 1202 and other components in the computer system 1200.

In at least one embodiment, the processor 1202 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1204. In at least one embodiment, the processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to the processor 1202. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and needs. In at least one embodiment, register file 1206 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and instruction pointer registers.

In at least one embodiment, an execution unit 1208, including but not limited to logic to perform integer and floating point operations, is also located in the processor 1202. In at least one embodiment, the processor 1202 may also include microcode ("ucode") read only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, execution unit 1208 may include logic to process packed instruction set 1209. In at least one embodiment, the encapsulated data in the general purpose processor 1202 may be used to perform operations used by many multimedia applications by including the encapsulated instruction set 1209 in the general purpose processor's instruction set and the associated circuitry to execute the instructions. In one or more embodiments, many multimedia applications may be accelerated and more efficiently executed by performing operations on encapsulated data using the full width of the processor's data bus, which may not require transferring smaller units of data over the processor's data bus to perform one or more operations of one data element at a time.

In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuitry. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, the memory 1220 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, the memory 1220 may store instructions 1219 and/or data 1221 represented by data signals that may be executed by the processor 1202.

In at least one embodiment, a system logic chip may be coupled to the processor bus 1210 and the memory 1220. In at least one embodiment, the system logic chips may include, but are not limited to, a memory controller hub ("MCH") 1216 and the processor 1202 may communicate with the MCH 1216 via a processor bus 1210. In at least one embodiment, the MCH 1216 may provide a high bandwidth memory path 1218 to memory 1220 for instruction and data storage, and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1216 may initiate data signals between the processor 1202, the memory 1220, and other components in the computer system 1200, and bridge the data signals between the processor bus 1210, the memory 1220, and the system I/O1222. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1216 may be coupled to memory 1220 through a high bandwidth memory path 1218 and the Graphics/video card 1212 may be coupled to the MCH 1216 through an Accelerated Graphics Port (AGP) interconnect 1214.

In at least one embodiment, the computer system 1200 may couple the MCH 1216 to an I/O controller hub ("ICH") 1230 using the system I/O1222 as a proprietary hub interface bus. In at least one embodiment, the ICH 1230 may provide direct connectivity to certain I/O devices through a local I/O bus. In at least one embodiment, the local I/O bus can include, but is not limited to, a high speed I/O bus for connecting peripheral devices to the memory 1220, chipset, and processor 1202. Examples may include, but are not limited to, an audio controller 1229, a firmware hub ("flash BIOS") 1228, a wireless transceiver 1226, data storage 1224, a legacy I/O controller 1223 and keyboard interface containing user input, a serial expansion port 1227 (e.g., Universal Serial Bus (USB)), and a network controller 1234. Data storage 1224 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

In at least one embodiment, fig. 12 shows a system including interconnected hardware devices or "chips," while in other embodiments, fig. 12 may show an exemplary SoC. In at least one embodiment, the devices shown in the figures may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using a compute express link (CXL) interconnect.

Inference and/or training logic 815 is operable to perform inference and/or training operations related to one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, inference and/or training logic 815 may be used in system diagram 12 to infer or predict operations based, at least in part, on weight parameters computed using neural network training operations, neural network functions, and/or architecture or neural network use cases as described herein.

In at least one embodiment, a computer system as described above may be used to create a robotic control system that implements model-based and model-free control. For example, a computer system as described above may include a memory storing executable instructions that, as a result of being executed by a processor of the computer system, cause the computer system to implement a model-based and model-free control system as described herein.

Fig. 13 is a block diagram illustrating an electronic device 1300 for utilizing a processor 1310 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1300 may be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

In at least one embodiment, the electronic device 1300 may include, but is not limited to, a processor 1310 communicatively coupled to any suitable number or variety of components, peripherals, modules, or devices. In at least one embodiment, processor 1310 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a Low Pin Count (LPC) bus, a serial peripheral interface ("SPI"), a high definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver/transmitter ("UART") bus. In at least one embodiment, fig. 13 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, fig. 13 may illustrate an exemplary SoC. In at least one embodiment, the devices shown in fig. 13 are interconnected with a dedicated interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of fig. 13 are interconnected using a compute quicklink (CXL) interconnect.

In at least one embodiment, fig. 13 may include a display 1324, a touchscreen 1325, a touchpad 1330, a near field communication unit ("NFC") 1345, a sensor hub 1340, a thermal sensor 1346, an Express chipset ("EC") 1335, a trusted platform module ("TPM") 1338, a BIOS/firmware/Flash memory ("BIOS, FW Flash") 1322, a DSP 1360, a drive 1320 (e.g., a solid state disk) ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN") 1350, a bluetooth unit 1352, a wireless wide area network unit ("WWAN") 1356, a Global Positioning System (GPS) unit 1355, a camera such as a USB3.0 camera ("USB 3.0 camera") 1354, and/or a double data rate ("LPDDR") storage unit ("LPDDR 3") 1315, such as implemented in the LPDDR3 standard. These components may each be implemented in any suitable manner.

In at least one embodiment, other components may be communicatively coupled to the processor 1310 via the components described herein. In at least one embodiment, an accelerometer 1341, an ambient light sensor ("ALS") 1342, a compass 1343, and a gyroscope 1344 are communicatively coupled to the sensor hub 1340. In at least one embodiment, thermal sensor 1339, fan 1337, keyboard 1336, and touchpad 1330 may be communicatively coupled to EC 1335. In at least one embodiment, a speaker 1363, headphones 1364, and a microphone ("mic") 1365 can be communicatively coupled to an audio unit ("audio codec and class D amplifier") 1362, which in turn can be communicatively coupled to the DSP 1360. In at least one embodiment, the audio unit 1362 can include, for example, but not limited to, an audio coder/decoder ("codec") and a class D amplifier. In at least one embodiment, a SIM card ("SIM") 1357 may be communicatively coupled to the WWAN unit 1356. In at least one embodiment, components such as WLAN unit 1350 and bluetooth unit 1352, as well as WWAN unit 1356, may be implemented in Next Generation Form Factor (NGFF).

In at least one embodiment, a computer system as described above may be used to create a robotic control system that implements model-based and model-free control. For example, a computer system as described above may include a memory storing executable instructions that, as a result of being executed by a processor of the computer system, cause the computer system to implement a model-based and model-free control system as described herein.

FIG. 14 illustrates a computer system 1400 in accordance with at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement the various processes and methods described throughout this disclosure.

In at least one embodiment, computer system 1400 includes, but is not limited to, at least one central processing unit ("CPU") 1402, the central processing unit 1402 being connected to a communication bus 1410 implemented using any suitable protocol, such as PCI ("peripheral component interconnect"), peripheral component interconnect express ("PCI-express"), AGP ("accelerated graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1400 includes, but is not limited to, a main memory 1404 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in the main memory 1404, which can take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1422 provides an interface to other computing devices and networks, for receiving data from and transmitting data to other systems with computer system 1400.

In at least one embodiment, computer system 1400 includes, but is not limited to, an input device 1408, a parallel processing system 1412, and a display device 1406, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light emitting diode ("LED") display, a plasma display, or other suitable display technology in at least one embodiment. In at least one embodiment, user input is received from an input device 1408 such as a keyboard, mouse, touchpad, microphone, or the like. In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

In at least one embodiment, a computer system as described above may be used to create a robotic control system that implements model-based and model-free control. For example, a computer system as described above may include a memory storing executable instructions that, as a result of being executed by a processor of the computer system, cause the computer system to implement a model-based and model-free control system as described herein. .

FIG. 15 illustrates a computer system 1500 in accordance with at least one embodiment. In at least one embodiment, computer system 1500 includes, but is not limited to, a computer 1510 and a USB stick 1520. In at least one embodiment, the computer 1510 can include, but is not limited to, any number and type of processors (not shown) and a memory (not shown). In at least one embodiment, computer 1510 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

In at least one embodiment, the USB stick 1520 includes, but is not limited to, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, processing unit 1530 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1530 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1530 includes an application specific integrated circuit ("ASIC") optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, processing unit 1530 is a tensor processing unit ("TPC") that is optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1530 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning reasoning operations.

In at least one embodiment, USB interface 1540 may be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1540 is a USB 3.0Type-C receptacle for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0Type-A connector. In at least one embodiment, USB interface logic 1550 may include any number and type of logic that enables processing unit 1530 to interface with a device (e.g., computer 1510) via USB connector 1540.

Fig. 16A illustrates an example architecture in which a plurality of GPUs 1610(1) - (1613 (N) are communicatively coupled to a plurality of multicore processors 1605(1) - (1606 (M)) via high-speed links 1640(1) - (N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, high-speed link 1640(1) -1640(N) supports a communication throughput of 4GB/s, 30GB/s, 80GB/s or higher. In at least one embodiment, various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In each figure, "N" and "M" represent positive integers, the values of which may vary from figure to figure.

Additionally, in one embodiment, two or more of GPUs 1610-1613 are interconnected by high-speed links 1629(1) -1629(2), which may be implemented using the same or different protocols/links as those used for high-speed links 1640(1) -1640 (N). Similarly, two or more multicore processors 1605 may be connected by a high speed link 1628, which may be a Symmetric Multiprocessor (SMP) bus running at 20GB/s, 30GB/s, 120GB/s, or higher. Alternatively, all communications between the various system components shown in fig. 16A may be accomplished using similar protocols/links (e.g., over a common interconnect fabric).

In one embodiment, each multicore processor 1605 is communicatively coupled to processor memory 1601(1) -1601(M) via memory interconnects 1626(1) -1626(M), respectively, and each GPU 1610(1) -1610(M) is communicatively coupled to GPU memory 1620(1) -1620(N) through GPU memory interconnects 1650(1) -1650(N), respectively. In at least one embodiment, memory interconnects 1626 and 1650 may utilize similar or different memory access technologies. By way of example and not limitation, processor memories 1601(1) -1601(M) and GPU memory 1620 may be volatile memories such as Dynamic Random Access Memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and/or may be non-volatile memories (e.g., 3D XPoint or Nano-Ram). In at least one embodiment, some portions of the processor memory 1601 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

As described herein, although various multi-core processors 1605 and GPUs 1610 may be physically coupled to particular memories 1601, 1620, respectively, and/or a unified memory architecture may be implemented with a virtual system address space (also referred to as an "effective address" space) distributed among the various physical memories. For example, when M-2 and N-4, the processor memories 1601(1) -1601(M) may each include 64GB of system memory address space, and the GPU memories 1620(1) -1620(N) may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example). Other values for N and M are also possible.

Fig. 16B shows additional details for the interconnection between the multi-core processor 1607 and the graphics acceleration module 1646, according to an example embodiment. In at least one embodiment, the graphics acceleration module 1646 may include one or more GPU chips integrated on a line card coupled to the processor 1607 by a high-speed link 1640. In at least one embodiment, graphics acceleration module 1646 may optionally be integrated with processor 1607 on the same package or chip.

In at least one embodiment, the illustrated processor 1607 includes a plurality of cores 1660A-1660D, each having a translation look-aside buffer 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, the cores 1660A-1660D may include various other components for executing instructions and processing data not shown. In at least one embodiment, the caches 1662A-1662D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1656 may be included in the caches 1662A-1662D and shared by a set of cores 1660A-1660D. For example, one embodiment of processor 1607 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1607 and the graphics acceleration module 1646 are coupled to the system memory 1614, and the system memory 1614 may comprise the processor memory 1601-1602 of FIG. 16A.

In at least one embodiment, the coherency of data and instructions stored in the various caches 1662A-1662D, 1656 and system memory 1614 is maintained via inter-core communications over a coherency bus 1664. For example, each cache may have associated with it cache coherency logic/circuitry that communicates on coherency bus 1664 in response to a detected read or write to a particular cache line. In at least one embodiment, a cache snoop protocol is implemented on coherency bus 1664 to snoop cache accesses.

In at least one embodiment, proxy circuitry 1625 communicatively couples graphics acceleration module 1646 to coherency bus 1664, allowing graphics acceleration module 1646 to participate in a cache coherency protocol as a peer of cores 1660A-1660D. In particular, in at least one embodiment, interface 1635 provides a connection to proxy circuit 1625 over high-speed link 1640, and interface 1637 connects graphics acceleration module 1646 to link 1640.

In at least one embodiment, accelerator integrated circuit 1636 represents multiple graphics processing engines 1631, 1632, N of graphics acceleration module 1646, providing cache management, memory access, context management, and interrupt management services. In at least one embodiment, the graphics processing engines 1631, 1632, N, may each include a separate Graphics Processing Unit (GPU). In at least one embodiment, graphics processing engines 1631(1) -1631(N) may optionally include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and dual-rail engines. In at least one embodiment, graphics acceleration module 1646 may be a GPU with multiple graphics processing engines 1631(1) -1631(N) or graphics processing engines 1631(1) -1631(N) may be separate GPUs integrated on a common package, line card, or chip.

In at least one embodiment, the accelerator integrated circuit 1636 includes a Memory Management Unit (MMU)1639 to perform various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation) and memory access protocols for accessing the system memory 1614. In at least one embodiment, MMU 1639 may also include a Translation Lookaside Buffer (TLB) (not shown) for translating virtual/effective addresses to physical/real addresses. In at least one embodiment, the cache 1638 may store commands and data for efficient access by the graphics processing engines 1631(1) -1631 (N). In one embodiment, data stored in cache 1638 and graphics memory 1633(1) -1633(M) may be kept coherent with core caches 1662A-1662D, 1656 and system memory 1614 using a fetch unit 1644. As described above, this may be accomplished via proxy circuitry 1625 (e.g., sending updates to the cache 1638 related to modification/access of cache lines on the processor caches 1662A-1662D, 1656 and receiving updates from the cache 1638) on behalf of the cache 1638 and the memories 1633(1) -1633 (M).

In at least one embodiment, a set of registers 1645 store context data for threads executed by graphics processing engines 1631(1) -1631(N), and context management circuitry 1648 manages thread contexts. For example, the context management circuit 1648 may perform save and restore operations to save and restore the context of the respective threads during a context switch (e.g., where a first thread is saved and a second thread is stored such that the second thread may be executed by the graphics processing engine). For example, on a context switch, the context management circuit 1648 may store the current register value to a specified region in memory (e.g., identified by a context pointer). Then, when the context is returned, it can restore the register values. In at least one embodiment, the interrupt management circuit 1647 receives and processes interrupts received from system devices.

In one implementation, the MMU 1639 translates virtual/effective addresses from the graphics processing engine 1631 to real/physical addresses in the system memory 1614. In at least one embodiment, accelerator integrated circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and/or other accelerator devices. In at least one embodiment, the graphics accelerator module 1646 may be dedicated to a single application executing on the processor 2307 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of graphics processing engine 1631(1) -1631(N) are shared with multiple applications or Virtual Machines (VMs). In at least one embodiment, resources may be subdivided into "slices," which are assigned to different VMs and/or applications, based on processing requirements and priorities associated with the VMs and/or applications.

In at least one embodiment, accelerator integrated circuit 1636 serves as a bridge for the system of graphics acceleration module 1646 and provides address translation and system memory caching services. Additionally, in at least one embodiment, accelerator integrated circuit 1636 may provide a virtualization facility for a host processor to manage virtualization, interrupt and memory management of graphics processing engines 1631(1) -1631 (N).

In at least one embodiment, because the hardware resources of graphics processing engine 1631(1) -1631(N) are explicitly mapped to the real address space seen by host processor 1607, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1636 is the physical separation of graphics processing engines 1631(1) -1631(N) such that they appear as separate units in the system.

In at least one embodiment, one or more graphics memories 1633(1) -1633(M) are coupled to each of the graphics processing engines 1631(1) -1631(N), respectively, and N ═ M. In at least one embodiment, graphics memories 1633(1) -1633(M) store instructions and data processed by each graphics processing engine 1631(1) -1631 (N). In at least one embodiment, graphics memories 1633(1) -1633(M) may be volatile memories, such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR6), or HBMs, and/or may be non-volatile memories (e.g., 3D XPoint or Nano-Ram).

In one embodiment, to reduce data traffic on high-speed link 1640, biasing techniques are used to ensure that the data stored in graphics memory 1633(1) -1633(M) will be the data that is most frequently used by graphics processing engines 1631(1) -1631(N) and 30 and that cores 2360A-2360D preferably do not use (at least are infrequently used). Similarly, in at least one embodiment, the biasing mechanism attempts to maintain data required by the cores (preferably not the graphics processing engines 1631(1) -1631(N)) in the caches 1662A-1662D, 1656 of the cores and system memory 1614.

Fig. 16C illustrates another exemplary embodiment in which an acceleration integrated circuit 1636 is integrated within the processor 1607. In this embodiment, graphics processing engines 1631(1) -1631(N) communicate directly with accelerator integrated circuit 1636 over high-speed link 1640 via interface 1637 and interface 1635 (again, any form of bus or interface protocol may be utilized). In at least one embodiment, the accelerator integrated circuit 1636 may perform the same operations as described with respect to FIG. 16B, but may have higher throughput in view of its close proximity to the coherency bus 1664 and the caches 1662A-1662D, 1656. One embodiment supports different programming models, including a dedicated-processing programming model (no graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by accelerator integrated circuit 1636 and a programming model controlled by graphics acceleration module 1646.

In at least one embodiment, graphics processing engines 1631(1) -1631(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may focus other application requests to the graphics processing engines 1631(1) -1631(N), thereby providing virtualization within a VM/partition.

In at least one embodiment, graphics processing engines 1631(1) -1631(N) may be shared by multiple VM/application partitions. In at least one embodiment, the sharing model may use a hypervisor to virtualize the graphics processing engines 1631(1) -1631(N) to allow access for each operating system. In at least one embodiment, the operating system owns the graphics processing engines 1631(1) -1631(N) for a single partitioned system without a hypervisor. In at least one embodiment, the operating system may virtualize the graphics processing engines 1631(1) -1631(N) to provide access to each process or application.

In at least one embodiment, the graphics acceleration module 1646 or the separate graphics processing engine 1631(1) -1631(N) uses the process handle to select a processing element. In one embodiment, the processing elements are stored in system memory 1614 and may be addressed using effective to real address translation techniques described herein. In at least one embodiment, the do-handle may be an implementation-specific value provided to the host process (i.e., invoking system software to add a processing element to a processing element linked list) when its context is registered with graphics processing engine 1631(1) -1631 (N). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the linked list.

Fig. 16D illustrates an exemplary accelerator integrated chip 1690. In at least one embodiment, as used herein, a "slice" comprises a designated portion of the processing resources of the acceleration integrated circuit 1636. An application effective address space 1682 within system memory 1614 stores processing elements 1683. In at least one embodiment, processing element 1683 stores in response to a GPU call 1681 of an application 1680 executing on processor 1607. In at least one embodiment, processing elements 1683 include a processing state of a corresponding application 1680. Work Descriptor (WD)1684 included in processing element 1683 may be a single job requested by an application or may include a pointer to a job queue. In at least one embodiment, WD 1684 is a pointer to a queue of job requests in application address space 1682.

In at least one embodiment, graphics acceleration module 1646 and/or individual graphics processing engines 1631(1) -1631(N) may be shared by all or a portion of the processes in the system. In at least one embodiment, an infrastructure for setting process state and sending WD 1684 to graphics acceleration module 1646 to begin work in a virtualized environment may be included.

In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, a single process owns the graphics acceleration module 1646 or the single graphics processing engine 1631 in this model. In at least one embodiment, since graphics acceleration module 1646 is owned by a single process, when graphics acceleration module 1646 is allocated, the hypervisor initializes accelerator integrated circuits 1636 for the owned partitions and the operating system initializes accelerator integrated circuits 1636 for the owned processes.

In at least one embodiment, in operation, the WD fetch unit 1691 in the accelerator integrated slice 1690 fetches the next WD 1684 including an indication of work to be done by one or more graphics processing engines of the graphics acceleration module 1646. In at least one embodiment, data from WD 1684 may be stored in registers 1645 and used by MMU 1639, interrupt management circuitry 1647, and/or context management circuitry 1648, as shown. For example, one embodiment of MMU 1639 includes fragment/page roaming circuitry for accessing fragment/page tables 1686 within OS virtual address space 1685. In at least one embodiment, the interrupt management circuit 1647 may process interrupt events 1692 received from graphics acceleration. In at least one embodiment, effective addresses 1693 generated by the graphics processing engines 1631(1) -1631(N) are translated to real addresses by the MMU 1639 when performing graphics operations.

In one embodiment, the same register set 1645 is replicated for each graphics processing engine 1631(1) -1631(N) and/or graphics acceleration module 1646 and may be initialized by a hypervisor or operating system. In at least one embodiment, each of these duplicate registers may be included in the accelerator chip 1690. Exemplary registers that may be initialized by the hypervisor are shown in Table 1.

TABLE 1 hypervisor initialized registers

Register #	Description of the invention
		1	Chip control register
2	Real Address (RA) plan progress area pointer
		3	Authorization mask override register
4	Interrupt vector table input offset
		5	Interrupt vectorMeter entry restriction
6	Status register
		7	Logical partition ID
8	Real Address (RA) hypervisor accelerator utilization record alignment
		9	Memory description register

Exemplary registers initialized by the operating system are shown in Table 2

TABLE 2 registers for operating System initialization

In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and/or graphics processing engines 1631(1) -1631 (N). In at least one embodiment, it contains all the information needed for the graphics processing engine 1631(1) -1631(N) to perform work, or it may be a pointer to a memory location where the application has established a command queue for work to be completed.

FIG. 16E illustrates additional details of one exemplary embodiment of a sharing model. This embodiment includes a hypervisor real address space 1698 in which a list 1699 of processing elements is stored. In at least one embodiment, the hypervisor real address space 1698 is accessible by the hypervisor 1696, and the hypervisor 1696 virtualizes the graphics acceleration module engine for the operating system 1695.

In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1646. In at least one embodiment, there are two programming models that share graphics acceleration module 1646 by multiple processes and partitions (i.e., time slice sharing and graphics orientation sharing).

In at least one embodiment, in this model, the hypervisor 1696 owns the graphics acceleration module 1646, and its functionality is available to all operating systems 1695. In at least one embodiment, in order for graphics acceleration module 1646 to support hypervisor 1696 for virtualization, graphics acceleration module 1646 may comply with certain requirements, such as: 1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), otherwise the graphics acceleration module 1646 must provide a context save and restore mechanism. 2) The graphics acceleration module 1646 ensures that job requests of the application are completed within a specified time, including any translation errors, or the graphics acceleration module 1646 provides the ability to preempt job processing. 3) When operating in the targeted sharing programming model, the graphics acceleration module 1646 must ensure fairness between processes.

In at least one embodiment, the application 1680 is required to make an operating system 1695 system call having a graphics acceleration module 1646 type, a Work Descriptor (WD), a permission mask register (AMR) value, and a context save/restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes a target acceleration function for a system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module 1646 and may be in the form of: the graphics acceleration module 1646 commands, effective address pointers to user-defined structures, effective address pointers to command queues, or any other data structure to describe the work to be done by the graphics acceleration module 1646.

In at least one embodiment, the AMR value is an AMR state to be used for the current process. In at least one embodiment, the value passed to the operating system is similar to the application setting AMR. In at least one embodiment, if the acceleration integrated circuit 1636 and graphics acceleration module 1646 implementations do not support a User Authorization Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1696 can optionally apply the current Authorization Mask Override Register (AMOR) value before placing AMR in the processing element 1683. In at least one embodiment, CSRP is one of registers 1645 that contains the effective address of a region in application address space 1682 for graphics acceleration module 1646 to save and restore context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or preempt jobs. In at least one embodiment, the context save/restore area may be a fixed system memory.

Upon receiving the system call, operating system 1695 can verify that application 1680 is registered and authorized to use graphics acceleration module 1646. In at least one embodiment, the operating system 1695 then calls the hypervisor 1696 using the information shown in Table 3.

Table 3-OS call information call manager

Parameter #	Description of the invention
		1	Work Descriptor (WD)
2	Authorization Mask Register (AMR) value (possibly masked)
		3	Effective Address (EA) context save/restore area pointer (CSRP)
4	Process ID (PID) and optional Thread ID (TID)
		5	Virtual Address (VA) Accelerator Utilization Record Pointer (AURP)
6	Virtual address (SSTP) to store segment table pointer
		7	Logic Interruption Service Number (LISN)

In at least one embodiment, upon receiving the hypervisor call, the hypervisor 1696 verifies that the operating system 1695 is registered and authorized to use the graphics acceleration module 1646. In at least one embodiment, the hypervisor 1696 then places the processing element 1683 in a corresponding graphics acceleration module 1646 type of processing element linked list. In at least one embodiment, the processing element may contain the information shown in Table 4.

TABLE 4 processing element information

Element #	Description of the invention
		1	Work Descriptor (WD)
2	Authorization Mask Register (AMR) value (possibly masked)
		3	Effective Address (EA) context save/restore area pointer (CSRP)
4	Process ID (PID) and optional Thread ID (TID)
		5	Virtual Address (VA) Accelerator Utilization Record Pointer (AURP)
6	Virtual address (SSTP) to store segment table pointer
		7	Logic Interruption Service Number (LISN)
8	Interrupt vector table, derived from hypervisor call parameters
		9	Status Register (SR) value
10	Logical Partition ID (LPID)
		11	Real Address (RA) virtual machine hypervisor accelerator utilization record pointer
12	Memory descriptor register (SDR)

In at least one embodiment, the hypervisor initializes a plurality of accelerator integrated chip 1690 registers 1645.

As shown in FIG. 16F, in at least one embodiment, a unified memory is used that is addressable by a common virtual memory address space for accessing physical processor memory 1601(1) -1601(N) and GPU memory 1620(1) -1620 (N). In this implementation, operations performed on GPUs 1610(1) - (1610 (N) utilize the same virtual/effective memory address space to access processor memory 1601(1) - (1601 (N), and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual/effective address space is allocated to processor memory 1601(1), a second portion is allocated to second processor memory 1601(N), a third portion is allocated to GPU memory 1601(1), and so on. In at least one embodiment, the entire virtual/effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1601 and GPU memory 1620, allowing any processor or GPU to access any physical memory having virtual addresses mapped to that memory.

In one embodiment, the bias/coherency management circuits 1694A-1694E within one or more of the MMUs 1639A-1639E ensure cache coherency between one or more host processors (e.g., 1605) and the caches of the GPU 1610 and implement a biasing technique that indicates the physical memory in which certain types of data should be stored. Although multiple instances of bias/coherency management circuits 1694A-1694E are shown in fig. 16, the bias/coherency circuits may be implemented within the MMU of one or more host processors 1605 and/or within accelerator integrated circuit 1636.

One embodiment allows GPU memory 1620 to be mapped as part of system memory and accessed using Shared Virtual Memory (SVM) techniques, but does not suffer from the performance drawbacks associated with full system cache coherency. In at least one embodiment, the ability to access GPU memory 1620 as system memory without the heavy cache coherency overhead provides a beneficial operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor F05 software to set operands and access results of computations without the overhead of traditional I/O DMA data copies. In at least one embodiment, such conventional copies involve driver calls, interrupts, and memory mapped I/o (mmio) accesses that are inefficient relative to simple memory accesses. In at least one embodiment, the ability to access GPU memory 1620 without cache coherency overhead is critical to the execution time of offloaded computations. In at least one embodiment, for example, where there is a large amount of streaming write memory traffic, the cache coherency overhead can significantly reduce the effective write bandwidth seen by the GPU 1610. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computations may play a role in determining the efficiency of GPU offloading.

In at least one embodiment, the selection of GPU offsets and host processor offsets is driven by an offset tracker data structure. In at least one embodiment, for example, an offset table may be used, which may be a page granularity structure (i.e., controlled at the granularity of memory pages), each memory page attached to the GPU including 1 or 2 bits. In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU memories 1620, with or without a bias cache in GPU 1610 (e.g., to cache frequently/recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

In at least one embodiment, the bias table entry associated with each access to memory 1620 attached to the GPU is accessed prior to actually accessing the GPU memory, resulting in the following operations. In at least one embodiment, local requests from GPUs 1610 (whose pages are found in GPU offsets) are forwarded directly to respective GPU memories 1620. In at least one embodiment, local requests from GPUs that find their pages in host bias are forwarded to processor 1605 (e.g., over a high-speed link, as described above). In at least one embodiment, a find requested page request in host processor bias from processor 1605 completes a request similar to an ordinary memory read. Optionally, a request for GPU-biased pages may be forwarded to GPU 1610. In at least one embodiment, the GPU may convert the page to a host processor bias if the GPU is not currently using the page. In at least one embodiment, the bias state of a page may be changed by a software-based mechanism, by a hardware-assisted software-based mechanism, or in limited cases, purely by a hardware-based mechanism.

In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn invokes the GPU's device driver, which in turn sends a message (or queued command descriptor) to the GPU to direct it to change the bias state and, for some transitions, perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for the transition from host processor 1605 bias to GPU bias, but not for the opposite transition.

In one embodiment, cache coherency is maintained by temporarily disabling the host processor 1605 from caching GPU-biased pages. In at least one embodiment, to access these pages, the processor 1605 may request the GPU 1610 for access, which may or may not be immediately authorized. In at least one embodiment, to reduce communication between processor 1605 and GPU 1610, it is beneficial to ensure that GPU-biased pages are pages required by the GPU rather than pages required by host processor 1605, and vice versa.

Hardware architecture 815 is used to implement one or more embodiments. Details regarding hardware architecture (x)815 are provided herein in connection with fig. 8A and/or 8B.

Fig. 17 illustrates an exemplary integrated circuit and associated graphics processor, which may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to the illustration, other logic and circuitry may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores.

Fig. 17 is a block diagram illustrating an exemplary system on a chip integrated circuit 1700 that can be fabricated using one or more IP cores in accordance with at least one embodiment. In at least one embodiment, the integrated circuit 1700 includes one or more application processors 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and/or a video processor 1720, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1700 includes peripheral or bus logic including USB controller 1725, UART controller 1730, SPI/SDIO controller 1735, and I²2S/I²A 2C controller 1740. In at least one embodiment, integrated circuit 1700 may include a display device 1745 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1750 and a Mobile Industrial Processor Interface (MIPI) display interface 1755. In at least one embodiment, storage may be provided 1760 by a flash subsystem, including flash memory and a flash controller. In at least one embodiment, a memory interface may be provided for accessing SDRAM or SRAM memory devices via the memory controller 1765. In at least one embodiment, some integrated circuits also include an embedded security engine 1770.

In at least one embodiment, the processor or GPU described herein may be used to create a robot control system that implements model-based and model-free control. For example, a processor or GPU as described above may be used to execute executable instructions that cause the processor to implement the model-based and model-free control systems described herein.

Fig. 18A-18B illustrate an example integrated circuit and associated graphics processor that may be fabricated using one or more IP cores, in accordance with various embodiments described herein. Other logic and circuitry may be included in at least one embodiment, in addition to that illustrated, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores.

18A-18B are block diagrams illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Fig. 18A illustrates a further exemplary graphics processor 1810 of a system on a chip integrated circuit, which may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 18B illustrates an exemplary graphics processor 1840 of a system-on-chip integrated circuit, which can be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, graphics processor 1810 of FIG. 18A is a low power graphics processor core. In at least one embodiment, the graphics processor 1840 of FIG. 18B is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1810, 1840 may be a variation of graphics processor 1710 of fig. 17.

In at least one embodiment, graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D through 1815N-1, and 1815N). In at least one embodiment, graphics processor 1810 may execute different shader programs via separate logic such that vertex processor 1805 is optimized to perform operations for vertex shader programs while one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations or pixel shader programs for fragments. In at least one embodiment, vertex processor 1805 performs a vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, one or more fragment processors 1815A-1815N use the primitives and vertex data generated by vertex processor 1805 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1815A-1815N are optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

In at least one embodiment, graphics processor 1810 additionally includes one or more Memory Management Units (MMUs) 1820A-1820B, caches 1818A-1818B, and circuit interconnects 1830A-1830B. In at least one embodiment, one or more MMUs 1820A-1820B provide virtual to physical address mapping for graphics processor 1810, including for vertex processor 1805 and/or fragment processors 1815A-1815N, which may reference vertex or image/texture data stored in memory in addition to vertex or image/texture data stored in one or more caches 1818A-1818B. In at least one embodiment, one or more of MMUs 1820A-1820B may be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1705, image processors 1715, and/or video processors 1720 of fig. 17, such that each processor 1705 and 1720 may participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable graphics processor 1810 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

In at least one embodiment, the graphics processor 1840 includes one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F, through 1855N-1 and 1855N) that provide a unified shader core architecture in which a single core or type or core may execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, the plurality of shader cores may vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tiling operations for tile-based rendering, where rendering operations for a scene are subdivided in image space, e.g., to optimize internal cache usage with local spatial coherence within the scene.

19A-19B illustrate additional exemplary graphics processor logic, according to embodiments described herein. In at least one embodiment, FIG. 19A illustrates a graphics core 1900 that may be included within the graphics processor 1710 of FIG. 17, which in at least one embodiment may be the unified shader cores 1855A-1855N in FIG. 18B. FIG. 19B illustrates a highly parallel general purpose graphics processing unit 1930 suitable for deployment on a multi-chip module in at least one embodiment.

In at least one embodiment, graphics core 1900 includes a shared instruction cache 1902, a texture unit 1918, and a cache/shared memory 1920, which are common to the execution resources within graphics core 1900. In at least one embodiment, graphics core 1900 may include multiple slices 1901A-1901N or partitions for each core, and a graphics processor may include multiple instances of graphics core 1900. The slices 1901A-1901N may include support logic including local instruction caches 1904A-1904N, thread schedulers 1906A-1906N, thread dispatchers 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, slices 1901A-1901N may include a set of additional functional units (AFUs 1912A-1912N), floating point units (FPUs 1914A-1914N), integer arithmetic logic units (ALUs 1916 and 1916N), address calculation units (ACUs 1913A-1913N), double precision floating point units (DPFPUs 1915A-1915N), and matrix processing units (MPUs 1917A-1917N).

In at least one embodiment, the FPUs 1914A-1914N may perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1915A-1915N may perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1916A-1916N may perform variable precision integer operations with 8-bit, 16-bit, and 32-bit precision, and may be configured for mixed precision operations. In at least one embodiment, the MPUs 1917A-1917N may also be configured for mixed precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1917A-1917N may perform various matrix operations to accelerate the machine learning application framework, including generic matrix-to-matrix multiplication (GEMM) to enable support for acceleration. In at least one embodiment, AFUs 1912A-1912N can perform additional logical operations not supported by floating point units or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

FIG. 19B illustrates a general purpose processing unit (GPGPU)1930 that can be configured to enable highly parallel computing operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, the GPGPU 1930 can be directly linked to other instances of the GPGPU 1930 to create a multi-GPU cluster to increase the training speed of the deep neural network. In at least one embodiment, GPGPU 1930 includes a host interface 1932 to enable connectivity to a host processor. In at least one embodiment, host interface 1932 is a PCI Express interface. In at least one embodiment, host interface 1932 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1930 receives commands from a host processor and dispatches the execution threads associated with those commands to a set of compute clusters 1936A-1936H using a global scheduler 1934. In at least one embodiment, the compute clusters 1936A-1936H share a cache memory 1938. In at least one embodiment, the cache memory 1938 can serve as a high level cache of cache memory within the compute clusters 1936A-1936H.

In at least one embodiment, GPGPU 1930 includes memories 1944A-1944B coupled to compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B. In at least one embodiment, memories 1944A-1944B may comprise various types of memory devices, including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory.

In at least one embodiment, compute clusters 1936A-1936H each include a set of graphics cores, such as graphics core 1900 of fig. 19A, which may include various types of integer and floating point logic units that may perform compute operations with a range of precision including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating point units in each compute cluster 1936A-1936H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

In at least one embodiment, multiple instances of GPGPU 1930 may be configured to operate as a compute cluster. In at least one embodiment, the communication used by the compute clusters 1936A-1936H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate through host interface 1932. In at least one embodiment, GPGPU 1930 includes an I/O hub 1939 that couples GPGPU 1930 with a GPU link 1940, which enables direct connections to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled with a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 1930 are located in separate data processing systems and communicate via a network device accessible via the host interface 1932. In at least one embodiment, GPU link 1940 may be configured to enable connection to a host processor in addition to, or in place of, host interface 1932.

In at least one embodiment, GPGPU1930 may be configured to train a neural network. In at least one embodiment, a GPGPU1930 can be used within the inference platform. In at least one embodiment in which the inference is made using GPGPU1930, the GPGPU may include fewer compute clusters 1936A-1936H relative to when training a neural network using the GPGPU. In at least one embodiment, the memory technology associated with memories 1944A-1944B may differ between inference and training configurations, with higher bandwidth memory technologies dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU1930 can support inference specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot-product instructions that can be used during the inference operations of the deployed neural network.

FIG. 20 is a block diagram illustrating a computing system 2000 in accordance with at least one embodiment. In at least one embodiment, the computing system 2000 includes a processing subsystem 2001 having one or more processors 2002 and a system memory 2004 that communicate via an interconnection path, which may include a memory hub 2005. In at least one embodiment, the memory hub 2005 may be a separate component within a chipset component or may be integrated within the one or more processors 2002. In at least one embodiment, the memory hub 2005 is coupled with an I/O subsystem 2011 via a communication link 2006. In at least one embodiment, the I/O subsystem 2011 includes an I/O hub 2007, which may enable the computing system 2000 to receive input from one or more input devices 2008. In at least one embodiment, the I/O hub 2007 may enable a display controller, which may be included in the one or more processors 2002, to provide output to the one or more display devices 2010A. In at least one embodiment, the one or more display devices 2010A coupled with the I/O hub 2007 may include local, internal, or embedded display devices.

In at least one embodiment, the processing subsystem 2001 includes one or more parallel processors 2012 coupled to the memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 may be one of many standards-based communication link technologies or protocols, such as but not limited to PCI express, or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, the one or more parallel processors 2012 form a compute-centric parallel or vector processing system that may include a large number of processing cores and/or processing clusters, such as integrated multi-core (MIC) processors. In at least one embodiment, the one or more parallel processors 2012 form a graphics processing subsystem that can output pixels to one of one or more display devices 2010A coupled via an I/O hub 2007. In at least one embodiment, one or more of the parallel processors 2012 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2010B.

In at least one embodiment, a system storage unit 2014 may connect to the I/O hub 2007 to provide a storage mechanism for the computing system 2000. In at least one embodiment, the I/O switch 2016 may be used to provide an interface mechanism to enable connection between the I/O hub 2007 and other components, such as a network adapter 2018 and/or a wireless network adapter 2019, which may be integrated into a platform, as well as various other devices that may be added via one or more additional devices 2020. In at least one embodiment, the network adapter 2018 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2019 may include one or more of Wi-Fi, bluetooth, Near Field Communication (NFC), or other network devices including one or more radios.

In at least one embodiment, computing system 2000 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I/O hub 2007. In at least one embodiment, the communication paths interconnecting the various components in FIG. 20 may be implemented using any suitable protocol, such as a PCI (peripheral component interconnect) -based protocol (e.g., PCI-express), or other bus or point-to-point communication interfaces and/or protocols (e.g., NV-Link high-speed interconnect or interconnect protocol).

In at least one embodiment, one or more of the parallel processors 2012 includes circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a Graphics Processing Unit (GPU). In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for general purpose processing. In at least one embodiment, components of computing system 2000 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more of parallel processor 2012, memory hub 2005, processor 2002, and I/O hub 2007 may be integrated into a system on a chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 2000 may be integrated into a single package to form a System In Package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2000 may be integrated into a multi-chip module (MCM) that may be interconnected with other multi-chip modules into a modular computing system.

Processor with a memory having a plurality of memory cells

FIG. 21A illustrates a parallel processor 2100, according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as a programmable processor, an Application Specific Integrated Circuit (ASIC), or a Field Programmable Gate Array (FPGA). In at least one embodiment, the illustrated parallel processor 2100 is a variation of one or more of the parallel processors 2012 illustrated in FIG. 20 in accordance with the illustrative embodiments.

In at least one embodiment, parallel processor 2100 includes a parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes an I/O unit 2104 that enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, the I/O unit 2104 can be directly connected to other devices. In at least one embodiment, the I/O unit 2104 interfaces with other devices using a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between the memory hub 2105 and the I/O unit 2104 forms a communication link 2113. In at least one embodiment, the I/O unit 2104 interfaces with a host interface 2106 and a memory crossbar 2116, where the host interface 2106 receives commands for performing processing operations and the memory crossbar 2116 receives commands for performing memory operations.

In at least one embodiment, when the host interface 2106 receives the command buffers via the I/O unit 2104, the host interface 2106 can direct work operations to execute those commands to the front end 2108. In at least one embodiment, the front end 2108 is coupled with a scheduler 2110 that the scheduler 2110 is configured to assign commands or other work items to clusters that process the cluster array 2112. In at least one embodiment, scheduler 2110 ensures that processing cluster array 2112 is properly configured and in a valid state before tasks are assigned to processing cluster array 2112. In at least one embodiment, scheduler 2110 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2110 may be configured to perform complex scheduling and work allocation operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2112. In at least one embodiment, the host software may attest to the workload for scheduling on the processing cluster array 2112 through one of a plurality of graphics processing paths. In at least one embodiment, the workload may then be automatically allocated on the processing array 2112 by scheduler 2110 logic within the microcontroller including the scheduler 2110.

In at least one embodiment, processing cluster array 2112 may include up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B through cluster 2114N), where "N" represents a positive integer (where a different integer "N" may be used in different figures). In at least one embodiment, each cluster 2114A-2114N of the processing cluster array 2112 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2110 may assign jobs to clusters 2114A-2114N of processing cluster array 2112 using various scheduling and/or job assignment algorithms, which may vary depending on the workload generated by each program or computing type. In at least one embodiment, scheduling may be handled dynamically by scheduler 2110 or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N of the processing cluster array 2112 may be allocated for processing different types of programs or for performing different types of computations.

In at least one embodiment, processing cluster array 2112 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2112 is configured to perform general purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2112 may include logic to perform processing tasks including filtering of video and/or audio data, performing modeling operations, including physical operations, and performing data transformations.

In at least one embodiment, processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2112 may include additional logic to support the performance of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2112 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2102 may transfer data from system memory for processing via the I/O unit 2104. In at least one embodiment, during processing, the transferred data may be stored to on-chip memory (e.g., parallel processor memory 2122) and then written back to system memory during processing.

In at least one embodiment, when the parallel processing unit 2102 is configured to perform graphics processing, the scheduler 2110 may be configured to divide the processing workload into approximately equal sized tasks to better allocate graphics processing operations to the multiple clusters 2114A-2114N of the processing cluster array 2112. In at least one embodiment, portions of processing cluster array 2112 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2114A-2114N may be stored in a buffer to allow the intermediate data to be transmitted between the clusters 2114A-2114N for further processing.

In at least one embodiment, the processing cluster array 2112 may receive processing tasks to be executed via a scheduler 2110, which scheduler 2110 receives commands defining the processing tasks from the front end 2108. In at least one embodiment, a processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and/or pixel data, as well as state parameters and commands that define how the data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 2110 may be configured to obtain an index corresponding to the task or may receive the index from front end 2108. In at least one embodiment, the front end 2108 can be configured to ensure that the processing cluster array 2112 is configured to a valid state prior to initiating a workload specified by an incoming command buffer (e.g., batch buffer, push buffer, etc.).

In at least one embodiment, each of the one or more instances of the parallel processing unit 2102 may be coupled with a parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 may be accessed via memory crossbar 2116, which memory crossbar 2116 may receive memory requests from processing cluster array 2112 and I/O unit 2104. In at least one embodiment, memory crossbar 2116 may access parallel processor memory 2122 via memory interface 2118. In at least one embodiment, memory interface 2118 may include a plurality of partition units (e.g., partition unit 2120A, partition unit 2120B, to partition unit 2120N), which may each be coupled to a portion (e.g., a memory unit) of parallel processor memory 2122. In at least one embodiment, the plurality of partition units 2120A-2120N is configured to equal the number of memory units such that a first partition unit 2120A has a corresponding first memory unit 2124A, a second partition unit 2120B has a corresponding memory unit 2124B, and an nth partition unit 2120N has a corresponding nth memory unit 2124N. In at least one embodiment, the number of partition units 2120A-2120N may not equal the number of storage units.

In at least one embodiment, memory units 2124A-2124N may comprise various types of memory devices, including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory. In at least one embodiment, memory units 2124A-2124N may also include 3D stacked memory, including but not limited to High Bandwidth Memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps, may be stored across the memory units 2124A-2124N, allowing the partition units 2120A-2120N to write portions of each render target in parallel to efficiently use the available bandwidth of the parallel processor memory 2122. In at least one embodiment, local instances of the parallel processor memory 2122 may be eliminated to facilitate a unified memory design that utilizes system memory in combination with local cache memory.

In at least one embodiment, any of the clusters 2114A-2114N of the processing cluster array 2112 can process data to be written to any of the memory cells 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 may be configured to transmit the output of each cluster 2114A-2114N to any partition unit 2120A-2120N or another cluster 2114A-2114N, and the clusters 2114A-2114N may perform other processing operations on the output. In at least one embodiment, each cluster 2114A-2114N may communicate with a memory interface 2118 through a memory crossbar 2116 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 2116 has a connection to memory interface 2118 to communicate with I/O unit 2104, and to a local instance of parallel processor memory 2122, to allow processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory not local to parallel processing unit 2102. In at least one embodiment, the memory crossbar 2116 may use virtual channels to separate traffic flows between the clusters 2114A-2114N and the partition units 2120A-2120N.

In at least one embodiment, multiple instances of the parallel processing unit 2102 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2102 may be configured to operate with each other even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and/or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2102 may include a higher precision floating point unit relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2102 or parallel processor 2100 may be implemented in various configurations and form factors, including but not limited to a desktop, laptop or handheld personal computer, server, workstation, gaming console, and/or embedded system.

FIG. 21B is a block diagram of a partition unit 2120 in accordance with at least one embodiment. In at least one embodiment, partition unit 2120 is an example of one of partition units 2120A-2120N of FIG. 21A. In at least one embodiment, partition unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and a raster operations unit ("ROP") 2126. In at least one embodiment, L2 cache 2121 is a read/write cache configured to perform load and store operations received from memory crossbar 2116 and ROP 2126. In at least one embodiment, the L2 cache 2121 outputs read misses and urgent writeback requests to the frame buffer interface 2125 for processing. In at least one embodiment, updates may also be sent to a frame buffer for processing via a frame buffer interface 2125. In at least one embodiment, the frame buffer interface 2125 interacts with one of the memory units in the parallel processor memory, such as memory units 2124A-2124N of FIG. 21 (e.g., within parallel processor memory 2122).

In at least one embodiment, ROP2126 is a processing unit that performs raster operations, such as stencil, z-test, blending, and the like. In at least one embodiment, ROP2126 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP2126 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a plurality of compression algorithms. In at least one embodiment, the type of compression performed by ROP2126 may vary based on statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per tile basis.

In at least one embodiment, ROP2126 is included within each processing cluster (e.g., clusters 2114A-2114N of FIG. 21) rather than within partition unit 2120. In at least one embodiment, read and write requests for pixel data are transmitted through memory crossbar 2116 instead of pixel fragment data. In at least one embodiment, the processed graphics data may be displayed on a display device (such as one of the one or more display devices 2010 of fig. 20), routed for further processing by processor 2702, or routed for further processing by one of the processing entities within parallel processor 2100 of fig. 21A.

FIG. 21C is a block diagram of a processing cluster 2114 within a parallel processing unit in accordance with at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 2114A-2114N of FIG. 21. In at least one embodiment, one or more of the one or more processing clusters 2114 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multi-threading (SIMT) techniques are used to support parallel execution of a large number of generally simultaneous threads, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

In at least one embodiment, the operation of the processing clusters 2114 may be controlled by a pipeline manager 2132 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 2132 receives instructions from scheduler 2110 of FIG. 21, and manages execution of those instructions by graphics multiprocessor 2134 and/or texture unit 2136. In at least one embodiment, graphics multiprocessor 2134 is an illustrative example of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within processing cluster 2114. In at least one embodiment, one or more instances of graphics multiprocessor 2134 may be included within processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 may process data, and the data crossbar 2140 may be used to distribute the processed data to one of a number of possible purposes (including other shader units). In at least one embodiment, the pipeline manager 2132 may facilitate the allocation of processing data by specifying a destination for the processing data to be allocated for the data crossbar 2140.

In at least one embodiment, each graphics multiprocessor 2134 within processing cluster 2114 can include the same set of function execution logic (e.g., arithmetic logic unit, load storage unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, wherein a new instruction may be issued before a previous instruction completes. In at least one embodiment, the function execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, shifting, and computation of various algebraic functions. In at least one embodiment, different operations may be performed by the same functional unit hardware, and any combination of functional units may be present.

In at least one embodiment, instructions passed to the processing cluster 2114 constitute a thread. In at least one embodiment, the set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, groups of threads execute a common program on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within graphics multiprocessor 2134. In at least one embodiment, the thread group may include fewer threads than a plurality of processing engines within graphics multiprocessor 2134. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during a cycle in which the thread group is being processed. In at least one embodiment, the thread group may also include more threads than multiple processing engines within graphics multiprocessor 2134. In at least one embodiment, processing may be performed in consecutive clock cycles when the thread group includes more threads than the processing engines within graphics multiprocessor 2134. In at least one embodiment, multiple thread groups may be executing simultaneously on graphics multiprocessor 2134.

In at least one embodiment, graphics multiprocessor 2134 includes an internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2134 may relinquish internal caching and use cache memory within the processing cluster 2114 (e.g., the L1 cache 2148). In at least one embodiment, each graphics multiprocessor 2134 may also access an L2 cache within partition units (e.g., partition units 2120A-2120N of FIG. 21) that are shared among all processing clusters 2114 and that may be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2134 may also access an off-chip global memory, which may include one or more of a local parallel processor memory and/or a system memory. In at least one embodiment, any memory external to the parallel processing unit 2102 may be used as global memory. In at least one embodiment, the processing cluster 2114 includes multiple instances of the graphics multiprocessor 2134 and shares common instructions and data that may be stored in the L1 cache 2148.

In at least one embodiment, each processing cluster 2114 may include a memory management unit ("MMU") 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2845 may reside within memory interface 2818 of fig. 28. In at least one embodiment, the MMU 2845 includes a set of Page Table Entries (PTEs) that are used to map virtual addresses to physical addresses of a tile and, optionally, to cache memory lines. In at least one embodiment, the MMU 2145 may include an address Translation Lookaside Buffer (TLB) or a cache that may reside within the graphics multiprocessor 2134 or L1 cache or processing cluster 2114. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

In at least one embodiment, processing cluster 2114 may be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations, e.g., determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2134, and fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2134 outputs processed tasks to data crossbar 2140 to provide the processed tasks to another processing cluster 2114 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2116. In at least one embodiment, preROP 2142 (a pre-raster operations unit) is configured to receive data from graphics multiprocessor 2134, direct the data to ROP units, which may be located with partition units described herein (e.g., partition units 2120A-2120N of FIG. 21). In at least one embodiment, the PreROP 2142 unit may perform optimizations for color mixing, organize pixel color data, and perform address translation.

Fig. 21D illustrates a graphics multiprocessor 2134 in accordance with at least one embodiment. In at least one embodiment, graphics multiprocessor 2134 is coupled with a pipeline manager 2132 of processing cluster 2114. In at least one embodiment, graphics multiprocessor 2134 has an execution pipeline that includes, but is not limited to, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, register files 2158, one or more General Purpose Graphics Processing Unit (GPGPU) cores 2162, and one or more load/store units 2166. In at least one embodiment, GPGPU core 2162 and load/store unit 2166 are coupled with cache memory 2172 and shared memory 2170 by a memory and cache interconnect 2168.

In at least one embodiment, instruction cache 2152 receives a stream of instructions to be executed from pipeline manager 2132. In at least one embodiment, instructions are cached in instruction cache 2152 and dispatched for execution by instruction unit 2154. In one embodiment, instruction unit 2154 may dispatch instructions as thread groups (e.g., thread bundles), each assigned to a different execution unit within GPGPU core 2162. In at least one embodiment, an instruction may access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2156 may be used to translate addresses in the unified address space into different memory addresses that may be accessed by the load/store unit 2166.

In at least one embodiment, register file 2158 provides a set of registers for the functional units of graphics multiprocessor 2134. In at least one embodiment, register file 2158 provides temporary storage for operands connected to the datapath of the functional units of graphics multiprocessor 2134 (e.g., GPGPU core 2162, load/store unit 2166). In at least one embodiment, register file 2158 is divided among each functional unit such that a dedicated portion of register file 2158 is allocated for each functional unit. In at least one embodiment, the register file 2158 is divided among the different thread bundles that the graphics multiprocessor 2134 is executing.

In at least one embodiment, the GPGPU cores 2162 may each include a Floating Point Unit (FPU) and/or an integer Arithmetic Logic Unit (ALU) for executing instructions of the graphics multiprocessor 2134. In at least one embodiment, GPGPU core 2162 may be similar in architecture or may differ in architecture. In at least one embodiment, the first portion of the GPGPU core 2162 includes single-precision FPUs and integer ALUs, while the second portion of the GPGPU core includes double-precision FPUs. In at least one embodiment, the FPU may implement the IEEE 754-. In at least one embodiment, graphics multiprocessor 2134 can additionally include one or more fixed-function or special-function units to perform specific functions, such as copy rectangle or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special function logic.

In at least one embodiment, GPGPU core 2162 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, GPGPU core 2162 may physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for a GPGPU core may be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel by a single SIMD8 logic unit.

In at least one embodiment, memory and cache interconnect 2168 is an interconnect network that connects each functional unit of graphics multiprocessor 2134 to register file 2158 and shared memory 2170. In at least one embodiment, memory and cache interconnect 2168 is a crossbar interconnect that allows load/store unit 2166 to perform load and store operations between shared memory 2170 and register file 2158. In at least one embodiment, the register file 2158 may operate at the same frequency as the GPGPU core 2162, so that the latency of data transfer between the GPGPU core 2162 and the register file 2158 is very low. In at least one embodiment, shared memory 2170 may be used to enable communication between threads executing on functional units within graphics multiprocessor 2134. In at least one embodiment, cache memory 2172 may function as, for example, a data cache to cache texture data communicated between functional units and texture unit 2136. In at least one embodiment, shared memory 2170 may also be used as a cache for program management. In at least one embodiment, threads executing on GPGPU core 2162 may programmatically store data in shared memory in addition to automatically cached data stored in cache memory 2172.

In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host/processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various General Purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor/core via a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on a package or chip and communicatively coupled to the core through an internal processor bus/interconnect (internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPUs are connected, the processor cores may allocate work to the GPUs in the form of a sequence of commands/instructions contained in a work descriptor. In at least one embodiment, the GPU then uses special-purpose circuitry/logic to efficiently process these commands/instructions.

Fig. 22 illustrates a multi-GPU computing system 2200 in accordance with at least one embodiment. In at least one embodiment, the multi-GPU computing system 2200 can include a processor 2202 coupled to a plurality of general purpose graphics processing units (GPGPGPUs) 2206A-D via a host interface switch 2204. In at least one embodiment, the host interface switch 2204 is a PCI express switching device that couples the processor 2202 to a PCI express (express) bus through which the processor 2202 may communicate with the GPGPGPUs 2206A-D. In at least one embodiment, the GPGPGPGPUs 2206A-D can be interconnected via a set of high speed point-to-point GPU links 2216. In at least one embodiment, a GPU-to-GPU link 2216 connects to each GPGPU2206A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU link 2216 enables direct communication between each GPGPU2206A-D without communicating through the host interface bus 2204 to which the processor 2202 is connected. In at least one embodiment, where GPU-to-GPU traffic is directed to P2P GPU link 2216, host interface bus 2204 remains available for system memory access or communication with other instances of multi-GPU computing system 2200, e.g., via one or more network devices. While in at least one embodiment, the GPGPGPUs 2206A-D are connected to the processor 2202 via the host interface switch 2204, in at least one embodiment, the processor 2202 includes direct support for the P2P GPU link 2216 and may be connected directly to the GPGPGPUs 2206A-D.

Fig. 23 is a block diagram of a graphics processor 2300, according to at least one embodiment. In at least one embodiment, graphics processor 2300 includes a ring interconnect 2302, pipeline front end 2304, media engine 2337, and graphics cores 2380A-2380N. In at least one embodiment, ring interconnect 2302 couples graphics processor 2300 to other processing units, including other graphics processors or one or more general purpose processor cores. In at least one embodiment, graphics processor 2300 is one of many processors integrated within a multi-core processing system.

In at least one embodiment, graphics processor 2300 receives batches of commands via ring interconnect 2302. In at least one embodiment, the input commands are interpreted by a command streamer 2303 in the pipeline front end 2304. In at least one embodiment, graphics processor 2300 includes extensible execution logic to perform 3D geometry processing and media processing via graphics cores 2380A-2380N. In at least one embodiment, for 3D geometry processing commands, command streamer 2303 provides the commands to geometry pipeline 2336. In at least one embodiment, for at least some media processing commands, the command streamer 2303 provides the commands to a video front end 2334, which is coupled with a media engine 2337. In at least one embodiment, the media engines 2337 include a Video Quality Engine (VQE)2323 for video and image post-processing, and a multi-format encode/decode (MFX)2333 engine for providing hardware accelerated media data encoding and decoding. In at least one embodiment, geometry pipeline 2336 and media engine 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380A.

In at least one embodiment, graphics processor 2300 includes scalable thread execution resources that play an important role in modular cores 2380A-2380N (sometimes referred to as core slices), each modular core having a plurality of sub-cores 2350A-550N, 2360A-2360N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2300 may have any number of graphics cores 2380A through 2380N. In at least one embodiment, graphics processor 2300 includes graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, graphics processor 2300 is a low power processor with a single sub-core (e.g., 2350A). In at least one embodiment, graphics processor 2300 includes a plurality of graphics cores 2380A-2380N, each graphics core including a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. In at least one embodiment, each of the first sub-cores 2350A-2350N includes at least a first set of execution units 2352A-2352N and media/texture samplers 2354A-2354N. In at least one embodiment, each of second sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each sub-core 2350A-2350N, 2360A-2360N shares a set of shared resources 2370A-2370N. In at least one embodiment, the shared resources include a shared cache and pixel operation logic.

Fig. 24 is a block diagram illustrating a microarchitecture for a processor 2400, which processor 2400 may include logic circuitry to execute instructions, in accordance with at least one embodiment. In at least one embodiment, the processor 2400 can execute instructions including x86 instructions, ARM instructions, application specific instructions for an Application Specific Integrated Circuit (ASIC), and the like. In at least one embodiment, processor 2400 may include registers for storing packed data, such as a 64-bit wide MMX in a microprocessor enabled with MMX technology by Intel corporation of Santa Clara, Calif ^TMA register. In at least one embodiment, MMX registers available in integer and floating point form may be run with packed data elements that accompany single instruction multiple data ("SIMD") and streaming SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or higher version (commonly referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, processor 2400 can execute instructions to accelerate machine learning or deep learning algorithms, training, or reasoning.

In at least one embodiment, processor 2400 includes an in-order front end ("front end") 2401 to fetch instructions to be executed and prepare the instructions for later use in a processor pipeline. In at least one embodiment, front end 2401 may include several units. In at least one embodiment, the instruction prefetcher 2426 retrieves instructions from memory and provides the instructions to the instruction decoder 2428, which in turn decodes or interprets the instructions by the instruction decoder 2428. For example, in at least one embodiment, the instruction decoder 2428 decodes a received instruction into one or more operations that the machine can perform, so-called "microinstructions" or "micro-operations" (also referred to as "micro-operations" or "micro-instructions"). In at least one embodiment, the instruction decoder 2428 parses an instruction into an opcode and corresponding data and control fields that may be used by a micro-architecture to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 2430 may assemble decoded microinstructions into program ordered sequences or traces in the microinstruction queue 2434 for execution. In at least one embodiment, when the trace cache 2430 encounters a complex instruction, the microcode ROM 2432 provides the microinstructions needed to complete the operation.

In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions may require several micro-operations to complete the entire operation. In at least one embodiment, if more than four microinstructions are needed to complete an instruction, the instruction decoder 2428 may access the microcode ROM 2432 to execute the instruction. In at least one embodiment, instructions may be decoded into a small number of microinstructions for processing at the instruction decoder 2428. In at least one embodiment, if multiple microinstructions are needed to complete an operation, the instructions may be stored in microcode ROM 2432. In at least one embodiment, the trace cache 2430 references a entry point programmable logic array ("PLA") to determine the correct micro-instruction pointer for reading a micro-code sequence from the micro-code ROM 2432 to complete one or more instructions in accordance with at least one embodiment. In at least one embodiment, the front end 2401 of the machine may resume fetching micro-operations from the trace cache 2430 after the microcode ROM 2432 completes ordering the micro-operations for the instruction.

In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 2403 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the stream of instructions to optimize performance as instructions descend down the pipeline and are scheduled to execute. In at least one embodiment, the out-of-order execution engine 2403 includes, but is not limited to, a dispatcher/register renamer 2440, a memory micro-instruction queue 2442, an integer/floating-point micro-instruction queue 2444, a memory scheduler 2446, a fast scheduler 2402, a slow/general floating-point scheduler ("slow/general FP scheduler") 2404, and a simple floating-point scheduler ("simple FP scheduler") 2406. In at least one embodiment, the fast scheduler 2402, the slow/general floating point scheduler 2404, and the simple floating point scheduler 2406 are also collectively referred to as "microinstruction schedulers 2402, 2404, 2406". In at least one embodiment, allocator/register renamer 2440 allocates machine buffers and resources required for sequential execution of each microinstruction. In at least one embodiment, allocator/register renamer 2440 renames logical registers to entries in a register file. In at least one embodiment, the allocator/register renamer 2440 also allocates an entry for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 2442 for memory operations and an integer/floating point microinstruction queue 2444 for non-memory operations, ahead of the memory scheduler 2446 and the microinstruction schedulers 2402, 2404, 2406. In at least one embodiment, the microinstruction schedulers 2402, 2404, 2406 determine when microinstructions are ready to be executed based on the readiness of their dependent input register operand sources and the availability of execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2402 may schedule on each half of the main clock cycle, while the slow/general floating point scheduler 2404 and the simple floating point scheduler 2406 may schedule once per main processor clock cycle. In at least one embodiment, the microinstruction scheduler 2402, 2404, 2406 arbitrates between the scheduling ports to schedule the microinstructions for execution.

In at least one embodiment, execution block b11 includes, but is not limited to, an integer register file/bypass network 2408, a floating point register file/bypass network ("FP register file/bypass network") 2410, address generation units ("AGU") 2412 and 2414, fast arithmetic logic units ("fast ALU") 2416 and 2418, slow arithmetic logic units ("slow ALU") 2420, a floating point ALU ("FP") 2422, and a floating point move unit ("FP move") 2424. In at least one embodiment, the integer register file/branch network 2408 and the floating point register file/bypass network 2410 are also referred to herein as "register files 2408, 2410". In at least one embodiment, AGUs 2412 and 2414, fast ALUs 2416 and 2418, slow ALU 2420, floating point ALU 2422, and floating point move unit 2424 are also referred to herein as "execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424". In at least one embodiment, execution block b11 may include, but is not limited to, any number (including zeros) and type of register files, bypass networks, address generation units, and execution units (in any combination).

In at least one embodiment, the register networks 2408, 2410 may be disposed between the microinstruction schedulers 2402, 2404, 2406 and the execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424. In at least one embodiment, integer register file/branch network 2408 performs integer operations. In at least one embodiment, the floating point register file/tributary network 2410 performs floating point operations. In at least one embodiment, each of the register networks 2408, 2410 may include, but is not limited to, a bypass network that may bypass or forward just completed results that have not been written to the register file to a new dependent object. In at least one embodiment, the register networks 2408, 2410 may communicate data with each other. In at least one embodiment, integer register file/branch network 2408 may include, but is not limited to, two separate register files, one register file for the lower order 32-bit data and a second register file for the upper order 32-bit data. In at least one embodiment, the floating point register file/branch network 2410 may include, but is not limited to, 128 bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits in width.

In at least one embodiment, the execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424 may execute instructions. In at least one embodiment, the register networks 2408, 2410 store integer and floating point data operand values that the microinstructions need to execute. In at least one embodiment, processor 2400 may include, but is not limited to, any number and combination of execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424, and the like. In at least one embodiment, the floating-point ALU 2422 and floating-point move unit 2424 may perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating-point ALU 2422 may include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform divide, square root, and remainder micro-operations. In at least one embodiment, instructions involving floating point values may be processed with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2416, 2418. In at least one embodiment, the fast ALUS 2416, 2418 may perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations enter the slow ALU 2420 because the slow ALU 2420 may include, but is not limited to, integer execution hardware for long latency type operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load/store operations may be performed by the AGUS 2412, 2414. In at least one embodiment, the fast ALU 2416, the fast ALU 2418, and the slow ALU 2420 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, and so on. In at least one embodiment, the floating-point ALU 2422 and floating-point move unit 2424 may be implemented to support a range of operands having bits of various widths, such as 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

In at least one embodiment, the microinstruction scheduler 2402, 2404, 2406 schedules dependent operations before the parent load completes execution. In at least one embodiment, the processor 2400 may also include logic to handle memory misses because microinstructions may be speculatively scheduled and executed in the processor 2400. In at least one embodiment, if a data load in the data cache misses, there may be dependent operations running in the pipeline that cause the scheduler to temporarily miss the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations may need to be replayed and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture a sequence of instructions for a text string comparison operation.

In at least one embodiment, the term "register" may refer to an on-board processor storage location that may be used as part of an instruction to identify operands. In at least one embodiment, the registers may be those that can be used from outside the processor (from the programmer's perspective). In at least one embodiment, the registers may not be limited to a particular type of circuitry. Rather, in at least one embodiment, the registers may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within a processor using a number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, and so forth. In at least one embodiment, the integer register stores 32 bits of integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

Inference and/or training logic 815 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, part or all of the inference and/or training logic 815 may be incorporated into the execution block 2411 as well as other memories or registers, shown or not shown. For example, in at least one embodiment, the training and/or reasoning techniques described herein may use one or more ALUs shown in execution block 2411. Further, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of execution block 2411 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

Fig. 25 illustrates a deep learning application processor 2500 in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2500 uses instructions that, if executed by the deep learning application processor 2500, cause the deep learning application processor 2500 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, deep learning application processor 2500 is an Application Specific Integrated Circuit (ASIC). In at least one embodiment, application processor 2500 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions or both. In at least one embodiment, deep learning application processor 2500 includes, but is not limited to, processing clusters 2510(1) -2510(12), inter-chip links ("ICLs") 2520(1) -2520(12), inter-chip controllers ("ICCs") 2530(1) -2530(2), second generation high bandwidth memories ("HBM 2") 2540(1) -2540(4), memory controllers ("Mem ctrl") 2542(1) -2542(4), high bandwidth memory physical layers ("HBM PHY") 2544(1) -2544(4), management controller central processing unit ("management controller CPU") 2550, serial peripheral interfaces, internal integrated circuits, and general purpose input/output blocks ("SPI, I2C, HBM 2560), peripheral component interconnect express controllers and direct memory access blocks (" PCIe controllers and DMA ") 2570, And sixteen channel peripheral component interconnect Express port ("PCI Express x 16") 2580.

In at least one embodiment, the processing cluster 2510 can perform deep learning operations, including inference or prediction operations based on weight parameters computed by one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2510 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2500 may include any number and type of processing clusters 2500. In at least one embodiment, the inter-chip link 2520 is bidirectional. In at least one embodiment, inter-chip link 2520 and inter-chip controller 2530 enable the plurality of deep learning application processors 2500 to exchange information, including activation information resulting from execution of one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2500 may include any number (including zero) and type of ICLs 2520 and ICC 2530.

In at least one embodiment, HBM 22540 provides a total of 32GB of memory. In at least one embodiment, HBM 22540 (i) is associated with both memory controller 2542(i) and HBM PHY2544 (i). In at least one embodiment, any number of HBMs 22540 may provide any type and amount of high bandwidth memory and may be associated with any number (including zero) and type of memory controllers 2542 and HBM PHYs 2544. In at least one embodiment, SPI, I2C, GPIO 2560, PCIe controller and DMA 2570 and/or PCIe2580 may be replaced with any number and type of blocks, implementing any number and type of communication standards in any technically feasible manner.

Inference and/or training logic 815 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2500. In at least one embodiment, the deep learning application processor 2500 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2500. In at least one embodiment, processor 2500 may be used to perform one or more neural network use cases described herein.

Fig. 26 is a block diagram of a neuromorphic processor 2600 in accordance with at least one embodiment. In at least one embodiment, the neuromorphic processor 2600 may receive one or more inputs from a source external to the neuromorphic processor 2600. In at least one embodiment, these inputs can be transmitted to one or more neurons 2602 within the neuromorphic processor 2600. In at least one embodiment, the neuron 2602 and its components can be implemented using circuitry or logic that includes one or more Arithmetic Logic Units (ALUs). In at least one embodiment, the neuromorphic processor 2600 may include, but is not limited to, examples of thousands of neurons 2602, but any suitable number of neurons 2602 may be used. In at least one embodiment, each instance of neuron 2602 can include a neuron input 2604 and a neuron output 2606. In at least one embodiment, the neuron 2602 can generate an output that can be transmitted to an input of other instances of the neuron 2602. In at least one embodiment, neuron inputs 2604 and neuron outputs 2606 may be interconnected via synapses 2608.

In at least one embodiment, the neurons 2602 and synapses 2608 may be interconnected such that the neuromorphic processor 2600 operates to process or analyze information received by the neuromorphic processor 2600. In at least one embodiment, the neuron 2602 can send an output pulse (or "trigger" or "peak") when the input received through the neuron input 2604 exceeds a threshold. In at least one embodiment, the neuron 2602 can sum or integrate signals received at the neuron input 2604. For example, in at least one embodiment, the neuron 2602 may be implemented as a leaky integrate-and-trigger neuron, wherein if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 2602 may use a transfer function such as a sigmoid or threshold function to produce an output (or "trigger"). In at least one embodiment, a leaky integrate-and-trigger neuron can sum the signals received at neuron input 2604 to a membrane potential, and can apply an attenuation factor (or leak) to reduce the membrane potential. In at least one embodiment, a leaky integrate-trigger neuron may trigger if multiple input signals are received at neuron input 2604 that are fast enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, the neuron 2602 can be implemented using circuitry or logic that receives an input, integrates the input to a membrane potential, and attenuates the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Further, in at least one embodiment, neuron 2602 may include, but is not limited to, a comparator circuit or logic that generates an output spike at neuron output 2606 when the result of applying a transfer function to neuron input 2604 exceeds a threshold. In at least one embodiment, once the neuron 2602 triggers, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, the neuron 2602 can resume normal operation after a suitable period of time (or repair period).

In at least one embodiment, the neurons 2602 can be interconnected by synapses 2608. In at least one embodiment, the synapse 2608 may be operable to transmit a signal from an output of a first neuron 2602 to an input of a second neuron 2602. In at least one embodiment, the neuron 2602 can transmit information on more than one instance of synapse 2608. In at least one embodiment, one or more instances of neuron output 2606 can be connected to instances of neuron input 2604 in the same neuron 2602 through instances of synapse 2608. In at least one embodiment, the instance of a neuron 2602 that produces an output to be transmitted on the instance of the synapse 2608 may be referred to as a "pre-synaptic neuron," as opposed to that instance of the synapse 2608. In at least one embodiment, with respect to an instance of synapse 2608, an instance of neuron 2602 receiving an input transmitted through an instance of synapse 2608 may be referred to as a "post-synaptic neuron". In at least one embodiment, with respect to various instances of synapses 2608, because an instance of a neuron 2602 may receive input from one or more instances of synapses 2608, and may also transmit output through one or more instances of synapses 2608, a single instance of neuron 2602 may be both a "pre-synaptic neuron" and a "post-synaptic neuron".

In at least one embodiment, the neurons 2602 can be organized into one or more layers. In at least one embodiment, each instance of a neuron 2602 can have one neuron output 2606, which neuron output 2606 can fan out to one or more neuron inputs 2604 through one or more synapses 2608. In at least one embodiment, neuron outputs 2606 of neurons 2602 in the first layer 2610 can be connected to neuron inputs 2604 of neurons 2602 in the second layer 2612. In at least one embodiment, the layer 2610 may be referred to as a "feed-forward layer". In at least one embodiment, each instance of neurons 2602 in an instance of the first tier 2610 can fan out to each instance of neurons 2602 in the second tier 2612. In at least one embodiment, the first layer 2610 can be referred to as a "fully connected feed-forward layer. In at least one embodiment, each instance of neurons 2602 in each instance of the second layer 2612 fans out to less than all instances of neurons 2602 in the third layer 2614. In at least one embodiment, the second layer 2612 can be referred to as a "sparsely connected feed-forward layer. In at least one embodiment, the neurons 2602 in the second layer 2612 can fan out to neurons 2602 in a number of other layers, also including the neurons 2602 in the second layer 2612. In at least one embodiment, the second tier 2612 can be referred to as a "cyclic tier". In at least one embodiment, the neuromorphic processor 2600 may include, but is not limited to, any suitable combination of a loop layer and a feedforward layer, including, but not limited to, a sparsely connected feedforward layer and a fully connected feedforward layer.

In at least one embodiment, the neuromorphic processor 2600 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnects to connect the synapses 2608 to the neurons 2602. In at least one embodiment, the neuromorphic processor 2600 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2602 as needed, depending on the neural network topology and neuron fan-in/fan-out. For example, in at least one embodiment, synapses 2608 may be connected to neurons 2602 using an interconnect structure (such as a network on a chip) or by dedicated connections. In at least one embodiment, synaptic interconnects and components thereof may be implemented using circuitry or logic

FIG. 27 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, the system 2700 includes one or more processors 2702 and one or more graphics processors 2708, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2702 or processor cores 2707. In at least one embodiment, system 2700 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

In at least one embodiment, system 2700 can include or be incorporated into a server-based gaming platform, including a game console, such as a game and media console, a mobile game console, a handheld game console, or an online game console. In at least one embodiment, system 2700 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2700 may also include a wearable device, coupled to or integrated in a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2700 is a television or set-top box device having one or more processors 2702 and a graphical interface generated by one or more graphics processors 2708.

In at least one embodiment, the one or more processors 2702 each include one or more processor cores 2707 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2707 is configured to process a particular sequence of instructions 2709. In at least one embodiment, the instruction set 2709 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via Very Long Instruction Words (VLIW). In at least one embodiment, processor cores 2707 may each process a different sequence of instructions 2709, which sequence of instructions 2709 may include instructions that facilitate emulation of other sequences of instructions. In at least one embodiment, processor core 2707 may also include other processing devices, such as a Digital Signal Processor (DSP).

In at least one embodiment, the processor 2702 includes a cache memory 2704. In at least one embodiment, the processor 2702 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among the various components of the processor 2702. In at least one embodiment, the processor 2702 also uses an external cache (e.g., a level three (L3) cache or a Level Last Cache (LLC)) (not shown) that may be shared among the processor cores 2707 using known cache coherency techniques. In at least one embodiment, a register file 2706 is additionally included in the processor 2702, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2706 may include general purpose registers or other registers.

In at least one embodiment, the one or more processors 2702 are coupled to one or more interface buses 2710 to transmit communication signals, such as address, data, or control signals, between the processors 2702 and other components in the system 2700. In at least one embodiment, the interface bus 2710 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2710 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2702 includes an integrated memory controller 2716 and a platform controller hub 2730. In at least one embodiment, memory controller 2716 facilitates communication between memory devices and other components of system 2700, while Platform Controller Hub (PCH)2730 provides a connection to I/O devices through a local I/O bus.

In at least one embodiment, the memory device 2720 may be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with suitable capabilities to function as a process memory. In at least one embodiment, the memory device 2720 may be used as system memory for the system 2700 to store data 2722 and instructions 2721 used when the one or more processors 2702 execute an application or process. In at least one embodiment, the memory controller 2716 is also coupled to an optional external graphics processor 2712, which external graphics processor 2712 may communicate with one or more graphics processors 2708 of the processor 2702 to perform graphics and media operations. In at least one embodiment, a display device 2711 can be connected to the processor 2702. In at least one embodiment, the display device 2711 can include one or more of an internal display device, such as in a mobile electronic device or laptop computer device or portable computer, or an external display device connected through a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2711 may comprise a Head Mounted Display (HMD), such as a stereoscopic display device for Virtual Reality (VR) applications or Augmented Reality (AR) applications.

In at least one embodiment, platform controller hub 2730 enables peripheral devices to be connected to storage 2720 and processor 2702 via a high speed I/O bus. In at least one embodiment, I/O peripherals include, but are not limited to, audio controller 2746, network controller 2734, firmware interface 2728, wireless transceiver 2726, touch sensor 2725, data storage 2724 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, the data storage 2724 may be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI express). In at least one embodiment, touch sensor 2725 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2726 may be a Wi-Fi transceiver, a bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2728 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2734 may enable a network connection to a wired network. In at least one embodiment, a high performance network controller (not shown) is coupled to interface bus 2710. In at least one embodiment, audio controller 2746 is a multi-channel high definition audio controller. In at least one embodiment, system 2700 includes an optional legacy I/O controller 2740 for coupling legacy (e.g., personal System 2(PS/2)) devices to the system. In at least one embodiment, the platform controller hub 2730 may also be connected to one or more Universal Serial Bus (USB) controllers 2742, the one or more Universal Serial Bus (USB) controllers 2742 being connected to input devices, such as a keyboard and mouse 2743 combination, a camera 2744, or other USB input devices.

In at least one embodiment, the instances of the memory controller 2716 and the platform controller hub 2730 may be integrated into a separate external graphics processor, such as external graphics processor 2712. In at least one embodiment, the platform controller hub 2730 and/or the memory controller 2716 may be external to the one or more processors 2702. For example, in at least one embodiment, the system 2700 may include an external memory controller 2716 and a platform controller hub 2730, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with the processor 2702.

Inference and/or training logic 815 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, some or all of the inference and/or training logic 815 may be incorporated into the graphics processor 2700. For example, in at least one embodiment, the training and/or reasoning techniques described herein may use one or more ALUs embodied in a 3D pipeline. Further, in at least one embodiment, the inference and/or training operations described herein may be performed using logic other than that shown in FIG. 8A or FIG. 8B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of the graphics processor 2700 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

FIG. 28 is a block diagram of a processor 2800 having one or more processor cores 2802A-2802N, an integrated memory controller 2814, and an integrated graphics processor 2808 according to at least one embodiment. In at least one embodiment, the processor 2800 may include additional cores that correspond to and include additional cores 2802N, represented by dashed boxes. In at least one embodiment, each of processor cores 2802A-2802N includes one or more internal cache units 2804A-2804N. In at least one embodiment, each processor core may also access one or more units of shared cache 2806.

In at least one embodiment, the internal cache units 2804A-2804N and the shared cache unit 2806 represent a cache memory hierarchy within the processor 2800. In at least one embodiment, the cache memory units 2804A-2804N may include at least one level of instructions and a data cache in each processor core and one or more shared mid-level cache levels, such as level 2(L2), level 3(L3), level 4(L4), or other levels of cache, with the highest level of buffering before external memory being categorized as LLC. In at least one embodiment, cache coherency logic maintains coherency between the various cache molecules 2806 and 2804A-2804N.

In at least one embodiment, processor 2800 can also include a set of one or more bus controller units 2816 and a system agent core 2810. In at least one embodiment, one or more bus controller units 2816 manage a set of peripheral buses, such as one or more PCI or PCI express buses. In at least one embodiment, system proxy core 2810 provides management functions for various processor components. In at least one embodiment, the system proxy core 2810 includes one or more integrated memory controllers 2814 to manage access to various external memory devices (not shown).

In at least one embodiment, one or more processor cores 2802A-2802N include support for simultaneous multithreading. In at least one embodiment, system proxy core 2810 includes components for coordinating and operating cores 2802A-2802N during multi-threaded processing. In at least one embodiment, system proxy core 2810 may additionally include a Power Control Unit (PCU) that includes logic and components to regulate one or more power states of processor cores 2802A-2802N and graphics processor 2808.

In at least one embodiment, processor 2800 additionally includes a graphics processor 2808 to perform graphics processing operations. In at least one embodiment, graphics processor 2808 is coupled to a shared cache unit 2806 and a system agent core 2810 that includes one or more integrated memory controllers 2814. In at least one embodiment, the system proxy core 2810 also includes a display controller 2811 for driving graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2811 may also be a stand-alone module coupled with the graphics processor 2808 via at least one interconnect, or may be integrated within the graphics processor 2808.

In at least one embodiment, a ring-based interconnect unit 2812 is used to couple the internal components of processor 2800. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other techniques. In at least one embodiment, graphics processor 2808 is coupled with a ring interconnect 2812 via an I/O link 2813.

In at least one embodiment, the I/O link 2813 represents at least one of a variety of I/O interconnects, including an on-package I/O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2818 (e.g., an eDRAM module). In at least one embodiment, each of processor cores 2802A-2802N and graphics processor 2808 use embedded memory module 2818 as a shared last level cache.

In at least one embodiment, processor cores 2802A-2802N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2802A-2802N are heterogeneous in Instruction Set Architecture (ISA), in which one or more processor cores 2802A-2802N execute a common instruction set and one or more other processor cores 2802A-28-02N execute a common instruction set or a subset of different instruction sets. In at least one embodiment, processor cores 2802A-2802N are heterogeneous in terms of micro-architecture, where one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, processor 2800 may be implemented on one or more chips or as a SoC integrated circuit.

Inference and/or training logic 815 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, part or all of the inference and/or training logic 815 may be incorporated into the graphics processor 2810. For example, in at least one embodiment, the training and/or inference techniques described herein may use one or more ALUs embodied in the 3D pipeline, graphics core 2802, shared function logic, or other logic in fig. 28. Further, in at least one embodiment, the inference and/or training operations described herein may be performed using logic other than that shown in FIG. 8A or FIG. 8B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of processor 2800 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

Fig. 29 is a block diagram of a graphics processor 2900, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores. In at least one embodiment, graphics processor 2900 communicates with registers on graphics processor 2900 via a memory mapped I/O interface with commands placed in memory. In at least one embodiment, graphics processor 2900 includes a memory interface 2914 for accessing memory. In at least one embodiment, memory interface 2914 is an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

In at least one embodiment, graphics processor 2900 also includes a display controller 2902 for driving display output data to a display device 2920. In at least one embodiment, display controller 2902 includes hardware for one or more overlay planes of display device 2920 and a composition of multi-layer video or user interface elements. In at least one embodiment, display device 2920 may be an internal or external display device. In at least one embodiment, display device 2920 is a head-mounted display device, such as a Virtual Reality (VR) display device or an Augmented Reality (AR) display device. In at least one embodiment, graphics processor 2900 includes a video codec engine 2906 to encode, decode, or transcode media into, from, or between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as h.264/MPEG-4AVC, and Society of Motion Picture Television Engineers (SMPTE)421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and motion JPEG mjpeg.

In at least one embodiment, graphics processor 2900 includes a block image transfer (BLIT) engine 2904 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in at least one embodiment, 2D graphics operations are performed using one or more components of Graphics Processing Engine (GPE) 2910. In at least one embodiment, GPE 2910 is a compute engine for performing graphics operations including three-dimensional (3D) and media operations.

In at least one embodiment, GPE 2910 includes a 3D pipeline 2912 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions acting on 3D primitive shapes (e.g., rectangles, triangles, etc.). In at least one embodiment, the 3D pipeline 2912 includes programmable and fixed functional elements that perform various tasks and/or spawn threads of execution to the 3D/media subsystem 2915. Although the 3D pipeline 2912 may be used to perform media operations, in at least one embodiment the GPE 2910 also includes a media pipeline 2916, the media pipeline 2916 being used to perform media operations such as video post-processing and image enhancement.

In at least one embodiment, the media pipeline 2916 includes fixed function or programmable logic units to perform one or more dedicated media operations, such as video decoding acceleration, video de-interlacing, and video encoding acceleration instead of or on behalf of the video codec engine 2906. In at least one embodiment, media pipeline 2916 also includes a thread spawning unit to spawn a thread to execute on 3D/media subsystem 2915. In at least one embodiment, the spawned threads perform computations of media operations on one or more graphics execution units contained in 3D/media subsystem 2915.

In at least one embodiment, 3D/media subsystem 2915 includes logic for executing threads spawned by 3D pipeline 2912 and media pipeline 2916. In at least one embodiment, the 3D pipeline 2912 and the media pipeline 2916 send thread execution requests to the 3D/media subsystem 2915, which includes thread dispatch logic for arbitrating and dispatching various requests to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D/media subsystem 2915 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 2915 also includes shared memory, including registers and addressable memory, to share data between the threads and store output data.

Inference and/or training logic 815 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, some or all of the inference and/or training logic 815 may be incorporated into the graphics processor 2900. For example, in at least one embodiment, the training and/or reasoning techniques described herein may use one or more of the ALUs contained in the 3D pipeline 2912. Further, in at least one embodiment, the reasoning and/or training operations described herein may be accomplished using logic different from that shown in FIG. 8A or FIG. 8B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of the graphics processor 2900 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

FIG. 30 is a block diagram of a graphics processing engine 3010 of a graphics processor according to at least one embodiment. In at least one embodiment, Graphics Processing Engine (GPE)3010 is a version of GPE 2910 shown in fig. 29. In at least one embodiment, media pipeline 3016 is optional and may not be explicitly included within GPE 3010. In at least one embodiment, a separate media and/or image processor is coupled to GPE 3010.

In at least one embodiment, GPE 3010 is coupled to or includes command streamer 3003, command streamer 3003 providing command streams to 3D pipeline 3012 and/or media pipeline 3016. In at least one embodiment, command streamer 3003 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. In at least one embodiment, command streamer 3003 receives commands from memory and sends commands to 3D pipeline 3612 and/or media pipeline 3616. In at least one embodiment, the commands are instructions, primitives, or micro-operations fetched from a ring buffer that stores commands for 3D pipeline 3612 and media pipeline 3616. In at least one embodiment, the ring buffer may additionally include a batch command buffer that stores batches of multiple commands. In at least one embodiment, commands for 3D pipeline 3612 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 3612 and/or image data and memory objects for media pipeline 3616. In at least one embodiment, 3D pipeline 3612 and media pipeline 3616 process commands and data by performing operations or by dispatching one or more threads of execution to graphics core array 3014. In at least one embodiment, graphics core array 3014 includes one or more graphics core blocks (e.g., graphics core 3015A, graphics core 3015B), each block containing one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources including general purpose and graphics specific execution logic for performing graphics and computing operations, and fixed function texture processing and/or machine learning and artificial intelligence acceleration logic including inference and/or training logic 815 in fig. 8A and 8B.

In at least one embodiment, 3D pipeline 3612 includes fixed functionality and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching threads of execution to graphics core array 3014. In at least one embodiment, graphics core array 3014 provides a unified execution resource block for processing shader programs. In at least one embodiment, multipurpose execution logic (e.g., execution units) within graphics cores 3015A-3015B in graphics core array 3014 includes support for various 3D API shader languages and may execute multiple simultaneous execution threads associated with multiple shaders.

In at least one embodiment, graphics core array 3014 also includes execution logic to perform media functions such as video and/or image processing. In at least one embodiment, the execution unit includes, in addition to graphics processing operations, general purpose logic that is programmable to perform parallel general purpose computing operations.

In at least one embodiment, output data generated by threads executing on graphics core array 3014 may output data to memory in Unified Return Buffer (URB) 3018. In at least one embodiment, the URB 3018 may store data for multiple threads. In at least one embodiment, the URBs 3018 may be used to send data between different threads executing on the graphics core array 3014. In at least one embodiment, the URB 3018 may additionally be used for synchronization between threads on the graphics core array 3014 and fixed function logic within the shared function logic 3020.

In at least one embodiment, graphics core array 3014 is scalable such that graphics core array 3014 includes a variable number of graphics cores, each having a variable number of execution units based on a target power and performance level of GPE 3010. In at least one embodiment, the execution resources are dynamically extensible such that the execution resources can be enabled or disabled as needed.

In at least one embodiment, graphics core array 3014 is coupled to shared function logic 3020, which shared function logic 3020 includes a plurality of resources that are shared among the graphics cores in graphics core array 3014. In at least one embodiment, the shared functions performed by shared function logic 3020 are embodied in hardware logic units that provide specialized, supplemental functions to graphics core array 3014. In at least one embodiment, shared function logic 3020 includes, but is not limited to, sampler 3021, math operator 3022, and inter-thread communication (ITC)3023 logic. In at least one embodiment, one or more caches 3025 are included in shared function logic 3020 or coupled to shared function logic 3020.

In at least one embodiment, shared functionality is used if the need for dedicated functionality is insufficient to be included in graphics core array 3014. In at least one embodiment, a single instance of the dedicated function is used in shared function logic 3020 and shared among other execution resources in graphics core array 3014. In at least one embodiment, certain shared functions in shared function logic 3020, which is widely used by graphics core array 3014, may be included in shared function logic 3016 within graphics core array 3014. In at least one embodiment, shared function logic 3016 within graphics core array 3014 may include some or all of the logic within shared function logic 3020. In at least one embodiment, all logic elements within shared function logic 3020 may be replicated within shared function logic 3016 of graphics core array 3014. In at least one embodiment, shared function logic 3020 is excluded and shared function logic 3016 is supported within graphics core array 3014.

Inference and/or training logic 815 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, some or all of the inference and/or training logic 815 may be incorporated into the graphics processor 3010. For example, in at least one embodiment, the training and/or reasoning techniques described herein may use one or more ALUs included in 3D pipeline 3612, graphics core 3015A, shared function logic 3016, graphics core 3015B, shared function logic 3020, or other logic in fig. 30. Further, in at least one embodiment, logic other than that shown in FIG. 8A or FIG. 8B may be used to accomplish the reasoning and/or training operations described herein. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of graphics processor 3010 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

Fig. 31 is a block diagram of hardware logic of a graphics processor core 3100 in accordance with at least one embodiment described herein. In at least one embodiment, the graphics processor core 3100 is included within a graphics core array. In at least one embodiment, the graphics processor core 3100 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 3100 is an example of one graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance context. In at least one embodiment, each graphics core 3100 may include a fixed function block 3130, also referred to as a sub-slice, that includes a modular block of general and fixed function logic coupled to a plurality of sub-cores 3101A-3101F.

In at least one embodiment, fixed function block 3130 includes geometry/fixed function line 3136, which geometry/fixed function line 3136 may be shared by all of the sub-cores in graphics processor 3100, for example, in lower performance and/or lower power graphics processor implementations. In at least one embodiment, the geometry/fixed function pipeline 3136 includes a 3D fixed function pipeline, a video front end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

In at least one embodiment, fixed functional block 3130 further comprises a graphics SoC interface 3137, a graphics microcontroller 3138, and a media pipeline 3139. In at least one fixed embodiment, graphics SoC interface 3137 provides an interface between graphics core 3100 and other processor cores in the on-chip integrated circuit system. In at least one embodiment, graphics microcontroller 3138 is a programmable sub-processor that may be configured to manage various functions of graphics processor 3100, including thread dispatch, scheduling, and preemption. In at least one embodiment, media pipeline 3139 includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing multimedia data including image and video data. In at least one embodiment, media pipeline 3139 enables media operations via requests to compute or sample logic within sub-cores 3101 and 3101F.

In at least one embodiment, SoC interface 3137 enables graphics core 3100 to communicate with a general-purpose application processor core (e.g., CPU) and/or other components within the SoC, including memory hierarchy elements such as a shared last level cache, system RAM, and/or embedded on-chip or packaged DRAM. In at least one embodiment, SoC interface 3137 may also enable communication with fixed-function devices (e.g., camera imaging pipelines) within the SoC, and enable use and/or implementation of global memory atoms that may be shared between graphics core 3100 and a CPU internal to the SoC. In at least one embodiment, graphics SoC interface 3137 may also implement power management control for graphics core 3100 and enable interfaces between the clock domain of graphics core 3100 and other clock domains within the SoC. In at least one embodiment, SoC interface 3137 enables receiving command buffers from the command streamer and global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to media pipeline 3139 when a media operation is to be performed, or may be distributed to geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 3136, geometry and fixed function pipeline 3114) when a graphics processing operation is to be performed.

In at least one embodiment, graphics microcontroller 3138 may be configured to perform various scheduling and management tasks on graphics core 3100. In at least one embodiment, the graphics microcontroller 3138 may perform graphics and/or compute workload scheduling on the various graphics parallel engines within the Execution Unit (EU) arrays 3102A-3102F, 3104A-3104F in the sub-cores 3101A-3101F. In at least one embodiment, host software executing on a CPU core of a SoC that includes graphics core 3100 may submit a workload of one of the multiple graphics processor doorbell that invokes a scheduling operation on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload to run next, submitting the workload to a command streamer, preempting an existing workload running on an engine, monitoring the progress of the workload, and notifying the host software when the workload completes. In at least one embodiment, graphics microcontroller 3138 may also facilitate a low-power or idle state of graphics core 3100, providing graphics core 3100 with the ability to save and restore registers across low-power state transitions within graphics core 3100 independent of the operating system and/or graphics driver software on the system.

In at least one embodiment, graphics core 3100 may have up to N more or less modular sub-cores than sub-cores 3101A-3101F shown. For each set of N sub-cores, in at least one embodiment, graphics core 3100 may also include shared function logic 3110, shared and/or cache memory 3112, geometry/fixed function pipeline 3114, and additional fixed function logic 3116 to accelerate various graphics and computing processing operations. In at least one embodiment, shared function logic 3110 may include logic elements (e.g., samplers, math and/or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 3100. In at least one embodiment, shared and/or cache memory 3112 may be the last level cache of the N sub-cores 3101A-3101F within graphics core 3100, and may also be used as a shared memory accessible by multiple sub-cores. In at least one embodiment, geometric/fixed function line 3114 may be included in place of geometric/fixed function line 3136 within fixed function block 3130, and may include the same or similar logic cells.

In at least one embodiment, graphics core 3100 includes additional fixed function logic 3116, which may include various fixed function acceleration logic for use by graphics core 3100. In at least one embodiment, the additional fixed function logic 3116 includes additional geometry pipelines for use in location-only shading. In position-only shading, there are at least two geometric pipelines, while among the full geometric and cull pipelines within geometric and fixed function pipelines 3116, 3136 are additional geometric pipelines that may be included in additional fixed function logic 3116. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline may execute different instances of the application, each instance having a separate environment. In at least one embodiment, the location-only shading may hide long culling runs of discarded triangles so that shading may be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 3116 may execute the position shader in parallel with the host application and typically generate critical results faster than the full pipeline because the culling pipeline fetches and masks the position attributes of the vertices without performing rasterization and rendering the pixels to the frame buffer. In at least one embodiment, the culling pipeline may use the generated critical results to calculate visibility information for all triangles regardless of whether the triangles were culled. In at least one embodiment, the full pipeline (which in this case may be referred to as a replay pipeline) may consume visibility information to skip culled triangles to mask only the visible triangles that are ultimately passed to the rasterization stage.

In at least one embodiment, the additional fixed function logic 3116 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementing optimizations including for machine learning training or reasoning.

In at least one embodiment, a set of execution resources is included within each graphics sub-core 3101A-3101F that may be used to perform graphics, media, and compute operations in response to requests by a graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics sub-cores 3101A-3101F include a plurality of EU arrays 3102A-3102F, 3104A-3104F, thread dispatch and inter-thread communication (TD/IC) logic 3103A-3103F, 3D (e.g., texture) samplers 3105A-3105F, media samplers 3106A-3106F, shader processors 3107A-3107F, and Shared Local Memories (SLM) 3108A-3108F. In at least one embodiment, the EU arrays 3102A-3102F, 3104A-3104F each include a plurality of execution units, which are general purpose graphics processing units capable of servicing graphics, media, or computational operations, performing floating point and integer/fixed point logical operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD/IC logic 3103A-3103F performs local thread dispatch and thread control operations for execution units within the sub-cores and facilitates communication between threads executing on the execution units of the sub-cores. In at least one embodiment, 3D samplers 3105A-3105F may read data related to textures or other 3D graphics into memory. In at least one embodiment, the 3D sampler may read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, media samplers 3106A-3106F may perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 3101A-3101F may alternatively comprise unified 3D and media samplers. In at least one embodiment, threads executing on execution units within each sub-core 3101A-3101F may utilize shared local memory 3108A-3108F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

Inference and/or training logic 815 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, some or all of the inference and/or training logic 815 may be incorporated into the graphics processor 3110. For example, in at least one embodiment, the training and/or reasoning techniques described herein may use one or more ALUs embodied in 3D pipeline 3110, graphics microcontroller 3138, geometric and fixed function pipelines 3114 and 3136, or other logic in fig. 31. Further, in at least one embodiment, the inference and/or training operations described herein may be performed using logic other than that shown in FIG. 8A or FIG. 8B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of the graphics processor 3100 to perform one or more machine learning algorithms, neural network architectures, use-cases, or training techniques described herein.

Fig. 32A-32B illustrate thread execution logic 3200 that includes an array of processing elements of a graphics processor core in accordance with at least one embodiment. FIG. 32A illustrates at least one embodiment in which thread execution logic 3200 is employed. FIG. 32B illustrates exemplary internal details of a graphics execution unit 3208, according to at least one embodiment.

As shown in fig. 32A, in at least one embodiment, the thread execution logic 3200 includes a shader processor 3202, a thread dispatcher 3204, an instruction cache 3206, a scalable execution unit array including a plurality of execution units 3207A-3207N and 3208A-3208N, a sampler 3210, a data cache 3212, and a data port 3214. In at least one embodiment, the scalable array of execution units may be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 3208A-N and 3207A-N), for example, based on computational requirements of the workload. In at least one embodiment, scalable execution units are interconnected by an interconnect fabric that links to each execution unit. In at least one embodiment, the thread execution logic 3200 includes one or more connections to memory (such as system memory or cache memory) through one or more of an instruction cache 3206, a data port 3214, a sampler 3210, and an execution unit 3207 or 3208. In at least one embodiment, each execution unit (e.g., 3208A) is an independent programmable general purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 3207 and/or 3208 is scalable to include any number of individual execution units.

In at least one embodiment, execution units 3207 and/or 3208 are primarily used to execute shader programs. In at least one embodiment, shader processor 3202 may process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 3204. In at least one embodiment, the thread dispatcher 3204 includes logic to arbitrate thread initialization celebrations from the graphics and media pipelines and to instantiate a requested thread on one or more of the execution units 3207 and/or 3208. For example, in at least one embodiment, a geometry pipeline may dispatch a vertex, tessellation, or geometry shader to thread execution logic for processing. In at least one embodiment, thread dispatcher 3204 may also process runtime thread generation requests from executing shader programs.

In at least one embodiment, execution units 3207 and/or 3208 support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs in graphics libraries (e.g., Direct 3D and OpenGL) require minimal translation to execute. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general purpose processing (e.g., compute and media shaders). In at least one embodiment, each execution unit 3207 and/or 3208 includes one or more Arithmetic Logic Units (ALUs) capable of executing multiple-issue Single Instruction Multiple Data (SIMD), and multi-threading enables an efficient execution environment despite higher latency memory accesses. In at least one embodiment, each hardware thread within each execution unit has a dedicated high bandwidth register file and associated independent thread state. In at least one embodiment, execution is multiple issues per clock to a pipeline capable of integer, single and double precision floating point operations, SIMD branch functions, logical operations, a priori operations, and other operations. In at least one embodiment, while waiting for data from one of the memory or shared functions, dependency logic within execution units 3207 and/or 3208 puts the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, the hardware resources may be dedicated to processing other threads. For example, in at least one embodiment, during a delay associated with vertex shader operations, the execution unit may perform operations on a pixel shader, a fragment shader, or another type of shader program (including a different vertex shader).

In at least one embodiment, each execution unit of execution units 3207 and/or 3208 operates on an array of data elements. In at least one embodiment, the plurality of data elements are "execution size" or number of lanes of instructions. In at least one embodiment, an execution lane is a logical unit for execution of data element access, masking, and flow control within an instruction. In at least one embodiment, the multiple channels may be independent of multiple physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In at least one embodiment, execution units 3207 and/or 3208 support both integer and floating point data types.

In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, the various data elements may be stored as packed data types in registers, and the execution unit will process the various elements based on the data size of the elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in a register, and the execution unit operates on the vector as four separate 64-bit packed data elements (four word (QW) size data elements), eight separate 32-bit packed data elements (double word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

In at least one embodiment, one or more execution units may be combined into a fused execution unit 3209A-3209N with thread control logic (3211A-3211N) common to the fused EU, such as execution unit 3207A fused with execution unit 3208A to form fused execution unit 3209A. In at least one embodiment, multiple EUs can be combined into one EU group. In at least one embodiment, each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU set can vary according to various embodiments. In at least one embodiment, each EU can execute a variety of SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD 32. In at least one embodiment, each fused graphics execution unit 3209A-3209N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 3209A includes a first EU3207A, a second EU390 3907A, and thread control logic 3211A common to the first EU3207A and the second EU 3208A. In at least one embodiment, the thread control logic 3207A controls threads executing on the fused graphics execution unit 3209A, allowing each EU within the fused execution units 3209A-3209N to execute using a common instruction pointer register.

In at least one embodiment, one or more internal instruction caches (e.g., 3206) are included in thread execution logic 3200 to cache thread instructions for execution units. In at least one embodiment, one or more data caches (e.g., 3212) are included to cache thread data during thread execution. In at least one embodiment, a sampler 3210 is included to provide texture samples for 3D operations and media samples for media operations. In at least one embodiment, the sampler 3210 includes specialized texture or media sampling functionality to process the texture or media data in a sampling process before providing the sampled data to the execution units.

During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to thread execution logic 3200 through thread spawn and dispatch logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 3202 is invoked to further compute output information and cause writing of the results to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In at least one embodiment, a pixel shader or fragment shader computes values for various vertex attributes to be interpolated on the rasterized object. In at least one embodiment, pixel processor logic within shader processor 3202 then executes pixel or fragment shader programs provided by an Application Program Interface (API). In at least one embodiment, to execute shader programs, shader processor 3202 dispatches threads to execution units (e.g., 3208A) via thread dispatcher 3204. In at least one embodiment, the shader processor 3202 uses texture sampling logic in the sampler 3210 to access texture data in a texture map stored in memory. In at least one embodiment, arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric segment, or discard one or more pixels for further processing.

In at least one embodiment, data ports 3214 provide a memory access mechanism for thread execution logic 3200 to output processed data to memory for further processing on a graphics processor output pipeline. In at least one embodiment, the data port 3214 includes or is coupled to one or more cache memories (e.g., data cache 3212) to cache data for memory access via the data port.

As shown in fig. 32B, in at least one embodiment, the graphics execution unit 3208 may include an instruction fetch unit 3237, a general register file array (GRF)3224, an architectural register file Array (ARF)3226, a thread arbiter 3222, a send unit 3230, a branch unit 3232, a set of SIMD Floating Point Units (FPUs) 3234, and, in at least one embodiment, a set of dedicated SIMD integer ALUs 3235. In at least one embodiment, GRF3224 and ARF3226 include a set of general purpose register files and architectural register files associated with each simultaneous hardware thread that may be active in the graphics execution unit 3208. In at least one embodiment, each thread architecture state is maintained in ARF3226, while data used during thread execution is stored in GRF 3224. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, may be stored in thread-specific registers in ARF 3226.

In at least one embodiment, the graphics execution unit 3208 has an architecture that is a combination of Simultaneous Multithreading (SMT) and fine-grained Interleaved Multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and a number of registers per execution unit, where execution unit resources are allocated on logic for executing multiple simultaneous threads.

In at least one embodiment, the graphics execution units 3208 may collectively issue multiple instructions, each of which may be a different instruction. In at least one embodiment, the thread arbiter 3222 of a graphics execution unit thread 3208 may dispatch instructions to one of the dispatch unit 3230, the branch unit 3242, or the SIMD FPU 3234 for execution. In at least one embodiment, each execution thread may access 128 general purpose registers in GRF 3224, where each register may store 32 bytes, which may be accessed as a SIMD 8 element vector of 32-bit data elements. In at least one embodiment, each execution unit thread may access 4KB in GRF 3224, although embodiments are not so limited and in other embodiments more or less register resources may be provided. In at least one embodiment, up to seven threads may be executed simultaneously, although the number of threads per execution unit may also vary depending on the embodiment. In at least one embodiment, where seven threads may access 4KB, GRF 3224 may store a total of 28 KB. In at least one embodiment, a flexible addressing scheme may allow registers to be addressed together to effectively create wider registers or rectangular block data structures representing strides.

In at least one embodiment, memory operations, sampler operations, and other longer latency system communications are scheduled via "send" instructions executed by messaging transmit unit 3230. In at least one embodiment, dispatching branch instructions to the dedicated branch unit 3232 facilitates SIMD divergence and eventual convergence.

In at least one embodiment, graphics execution unit 3208 includes one or more SIMD Floating Point Units (FPUs) 3234 to perform floating point operations. In at least one embodiment, the FPU 3234 also supports integer computations. In at least one embodiment, the FPU 3234 can perform up to M32-bit floating point (or integer) operations in SIMD, or up to 2M 16-bit integer or 16-bit floating point operations in SIMD. In at least one embodiment, at least one of the FPUs provides extended mathematical capabilities to support high throughput a priori mathematical functions and double precision 64-bit floating points. In at least one embodiment, there is also a set of 8-bit integer SIMD ALU 3235, and may be specifically optimized to perform operations related to machine learning calculations.

In at least one embodiment, an array of multiple instances of the graphics execution unit 3208 may be instantiated in a graphics sub-core packet (e.g., a subslice). In at least one embodiment, execution units 3208 may execute instructions across multiple execution channels. In at least one embodiment, each thread executing on graphics execution unit 3208 executes on a different channel.

Inference and/or training logic 815 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, some or all of the inference and/or training logic 1515 may be incorporated into the execution logic 3200. Further, in at least one embodiment, logic other than that shown in FIG. 8A or FIG. 8B may be used to accomplish the inference and/or training operations described herein. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALU threads of the execution logic 3200 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

FIG. 33 illustrates a parallel processing unit ("PPU") 3300 in accordance with at least one embodiment. In at least one embodiment, the PPU3300 is configured with machine-readable code that, if executed by the PPU3300, causes the PPU3300 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the PPU3300 is a multithreaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simple instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution and is an instance of a set of instructions configured to be executed by the PPU 3300. In at least one embodiment, PPU3300 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data in order to generate two-dimensional ("2D") image data for display on a display device, such as a liquid crystal display ("LCD") device. In at least one embodiment, the PPU3300 is used to perform computations, such as linear algebraic operations and machine learning operations. Fig. 33 shows an example parallel processor for illustrative purposes only, and should be construed as a non-limiting example of a processor architecture contemplated within the scope of the present disclosure, and any suitable processor may be employed in addition to and/or in place of it.

In at least one embodiment, one or more PPUs 3300 are configured to accelerate high performance computing ("HPC"), data centers, and machine learning applications. In at least one embodiment, the PPU 3300 is configured to accelerate deep learning systems and applications, including the following non-limiting examples: the system comprises an automatic driving automobile platform, deep learning, high-precision voice, images, a text recognition system, intelligent video analysis, molecular simulation, drug discovery, disease diagnosis, weather forecast, big data analysis, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimization, personalized user recommendation and the like.

In at least one embodiment, PPU 3300 includes, but is not limited to, an input/output ("I/O") unit 3306, a front end unit 3310, a scheduler unit 3312, a work assignment unit 3314, a hub 3316, a crossbar ("Xbar") 3320, one or more general purpose processing clusters ("GPCs") 3318, and one or more partition units ("memory partition units") 3322. In at least one embodiment, the PPU 3300 is connected to a host processor or other PPU 3300 by one or more high-speed GPU interconnects ("GPU interconnects") 3308. In at least one embodiment, the PPU 3300 is connected to a host processor or other peripheral device via a system bus 3302. In an embodiment, the PPU 3300 is connected to local memory that includes one or more memory devices ("memory") 3304. In at least one embodiment, memory device 3304 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and/or configurable as a high bandwidth memory ("HBM") subsystem, and multiple DRAM dies are stacked within each device.

In at least one embodiment, the high-speed GPU interconnect 3308 may refer to a line-based, multi-channel communication link that a system uses to scale, and includes one or more PPUs 3300 ("CPUs") in conjunction with one or more central processing units, supporting cache coherence between the PPUs 3300 and the CPUs, as well as CPU hosting. In at least one embodiment, the high-speed GPU interconnect 3308 transmits data and/or commands to other units of the PPU 3300, such as one or more replication engines, video encoders, video decoders, power management units, and/or other components that may not be explicitly shown in fig. 33, through the hub 3316.

In at least one embodiment, the I/O unit 3306 is configured to send and receive communications (e.g., commands, data) from a host processor (not shown in fig. 33) over the system bus 3302. In at least one embodiment, the I/O unit 3306 communicates with the host processor directly over the system bus 3302 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I/O unit 3306 may communicate with one or more other processors (e.g., one or more PPUs 3300) via a system bus 3302. In at least one embodiment, I/O unit 3306 implements a peripheral component interconnect express ("PCIe") interface for communicating over a PCIe bus. In at least one embodiment, the I/O unit 3306 implements an interface for communicating with external devices.

In at least one embodiment, the I/O unit 3306 decodes packets received via the system bus 3302. In at least one embodiment, at least some of the packets represent commands configured to cause PPU 3300 to perform various operations. In at least one embodiment, the I/O unit 3306 sends the decoded command to various other units of the PPU 3300 as specified by the command. In at least one embodiment, commands are sent to the front end unit 3310 and/or to other units of the hub 3316 or PPU 3300, such as one or more replication engines, video encoders, video decoders, power management units, and the like (not explicitly shown in fig. 33). In at least one embodiment, the I/O unit 3306 is configured to route communications between the various logical units of the PPU 3300.

In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 3300 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffers are areas in memory accessible (e.g., read/write) by both the host processor and the PPU 3300 — the host interface unit may be configured to access buffers in system memory connected to the system bus 3302 via memory requests transmitted over the system bus 3302 by the I/O unit 3306. In at least one embodiment, the host processor writes command streams to a buffer and then sends pointers indicating the start of the command streams to the PPU 3300, such that the front end unit 3310 receives pointers to and manages one or more command streams, reads commands from the command streams and forwards the commands to the various units of the PPU 3300.

In at least one embodiment, the front end unit 3310 is coupled to a scheduler unit 3312, which scheduler unit 3312 configures various GPCs 3318 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 3312 is configured to track status information related to various tasks managed by the scheduler unit 3312, where the status information may indicate which GPCs 3318 the task is assigned to, whether the task is active or inactive, priorities associated with the tasks, and so forth. In at least one embodiment, a scheduler unit 3312 manages a plurality of tasks executing on one or more GPCs 3318.

In at least one embodiment, the scheduler unit 3312 is coupled to a work allocation unit 3314, the work allocation unit 3314 being configured to dispatch tasks to execute on GPCs 3318. In at least one embodiment, the work allocation unit 3314 tracks the number of scheduled tasks received from the scheduler unit 3312 and the work allocation unit 3314 manages the pending task pool and the active task pool for each GPC 3318. In at least one embodiment, the pool of pending tasks includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 3318; the active task pool may include multiple slots (e.g., 4 slots) for tasks actively processed by the GPCs 3318, such that as one of the GPCs 3318 completes its execution, that task will be evicted from the active task pool of the GPC 3318, and another task is selected from the pending task pool and scheduled to execute on the GPC 3318. In at least one embodiment, if the active task is in an idle state on the GPC 3318, for example while waiting for a data dependency to resolve, the active task is evicted from the GPC 3318 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled to execute on the GPC 3318.

In at least one embodiment, the work distribution unit 3314 communicates with one or more GPCs 3318 via XBar 3320. In at least one embodiment, XBar 3320 is an interconnection network that couples many of the units of PPU 3300 to other units of PPU 3300 and may be configured to couple work distribution units 3314 to particular GPCs 3318. In at least one embodiment, other units of one or more PPUs 3300 may also be connected to XBar 3320 through hubs 3316.

In at least one embodiment, tasks are managed by a scheduler unit 3312 and allocated to one of the GPCs 3318 by a work allocation unit 3314. In at least one embodiment, GPCs 3318 are configured to process tasks and produce results. In at least one embodiment, results may be consumed by other tasks in a GPC 3318, routed to a different GPC 3318 through an XBar 3320, or stored in memory 3304. In at least one embodiment, the results may be written to memory 3304 by partition unit 3322, which implements a memory interface for writing data to memory 3304 or reading data from memory 3304. In at least one embodiment, the results may be transmitted to another PPU 3304 or CPU via the high-speed GPU interconnect 3308. In at least one embodiment, the PPU 3300 includes, but is not limited to, U partition units 3322, which is equal to the number of separate and distinct storage devices 3304 coupled to the PPU 3300. In at least one embodiment, partition unit 3322 is described in more detail below in conjunction with FIG. 35.

In at least one embodiment, the host processor executes a driver core that implements an Application Programming Interface (API) that enables one or more applications executing on the host processor to schedule operations to execute on the PPU 3300. In one embodiment, multiple computing applications are executed simultaneously by the PPU 3300, and the PPU 3300 provides isolation, quality of service ("QoS"), and independent address spaces for multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 3300, and the driver core outputs the tasks to one or more streams processed by the PPU 3300. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as thread bundles (warp). In at least one embodiment, a thread bundle includes multiple related threads (e.g., 32 threads) that may be executed in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads, including instructions for performing tasks and exchanging data through shared memory. In at least one embodiment, threads and cooperative threads are described in more detail in conjunction with FIG. 35.

FIG. 34 illustrates a general processing cluster ("GPC") 3400 in accordance with at least one embodiment. In at least one embodiment, the GPC 3400 is the GPC 4018 of fig. 40. In at least one embodiment, each GPC 3400 includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC 3400 includes, but is not limited to, a pipeline manager 3402, a pre-raster operations unit ("preROP") 3404, a raster engine 3408, a work distribution crossbar ("WDX") 3416, a memory management unit ("MMU") 3418, one or more data processing clusters ("DPC") 3406, and any suitable combination of components.

In at least one embodiment, the operation of GPCs 3400 is controlled by a pipeline manager 3402. In at least one embodiment, pipeline manager 3402 manages the configuration of one or more DPCs 3406 to process tasks allocated to GPCs 3400. In at least one embodiment, pipeline manager 3402 configures at least one of the one or more DPCs 3406 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC 3406 is configured to execute vertex shader programs on programmable streaming multiprocessors ("SM") 3414. In at least one embodiment, the pipeline manager 3402 is configured to route data packets received from work distribution units to appropriate logic units within the GPC 3400, and in at least one embodiment, some data packets may be routed to the preROP 3404 and/or fixed function hardware units in the raster engine 3408, while other data packets may be routed to the DPC 3406 for processing by the primitive engine 3412 or SM 3414. In at least one embodiment, pipeline manager 3402 configures at least one of DPCs 3406 to implement a neural network model and/or a compute pipeline.

In at least one embodiment, the preROP unit 3404 is configured to route data generated by the raster engine 3408 and the DPC 3406 to a raster operations ("ROP") unit in the partition unit 3322 described in more detail above in connection with fig. 33 in at least one embodiment. In at least one embodiment, preROP unit 3404 is configured to perform optimizations for color mixing, organize pixel data, perform address translations, and so on. In at least one embodiment, the raster engine 3408 includes, but is not limited to, a plurality of fixed function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 3408 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to a coarse raster engine to generate coverage information for the base primitive (e.g., x, y coverage masks for tiles); the output of the coarse raster engine will be passed to a culling engine where fragments associated with primitives that fail the z-test will be culled and passed to a clipping engine where fragments that lie outside the viewing cone are clipped. In at least one embodiment, the clipped and culled segments are passed to a fine raster engine to generate attributes for the pixel segments based on a plane equation generated by a setup engine. In at least one embodiment, the output of the raster engine 3408 includes fragments to be processed by any suitable entity (e.g., by a fragment shader implemented within the DPC 3406).

In at least one embodiment, each DPC 3406 included in the GPC 3400 includes, but is not limited to, an M-line controller ("MPC") 3410; a primitive engine 3412; one or more SM 3414; and any suitable combination thereof. In at least one embodiment, the MPC 3410 controls the operation of the DPC 3406, routing packets received from the pipeline manager 3402 to the appropriate elements in the DPC 3406. In at least one embodiment, packets associated with the vertices are routed to primitive engine 3412, primitive engine 3412 is configured to retrieve vertex attributes associated with the vertices from memory; instead, data packets associated with the shader programs may be sent to the SM 3414.

In at least one embodiment, the SM 3414 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by a plurality of threads. In at least one embodiment, the SM 3414 is multithreaded and configured to concurrently execute multiple threads (e.g., 32 threads) from a particular thread group and implements a single instruction multiple data ("SIMD") architecture in which each thread in a group of threads (e.g., a thread bundle) is configured to process different sets of data based on a common set of instructions. In at least one embodiment, all threads in a thread group execute the same instruction. In at least one embodiment, the SM 4114 implements a single instruction multiple threading ("SIMT") architecture in which each thread in a group of threads is configured to process different sets of data based on a common set of instructions, but in which the individual threads in the group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle to enable concurrency between the thread bundle and serial execution within the thread bundle as threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, so that there is equal concurrency between all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing common instructions may be converged and executed in parallel to improve efficiency. At least one embodiment of the SM 3414 is described in more detail below.

In at least one embodiment, MMU 3418 provides an interface between GPCs 3400 and a memory partition unit (e.g., partition unit 3322 of fig. 33), and MMU 3418 provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, MMU 3418 provides one or more translation lookaside buffers ("TLBs") for performing virtual address to physical address translations in memory.

FIG. 35 illustrates a memory partitioning unit 3500 of a parallel processing unit ("PPU") according to one embodiment. In at least one embodiment, memory partition unit 3500 includes, but is not limited to, a raster operations ("ROP") unit 3502; a level two ("L2") cache 3504; a memory interface 3506; and any suitable combination thereof. In at least one embodiment, memory interface 3506 is coupled to memory. In at least one embodiment, the memory interface 3506 can implement a 32, 64, 128, 1024 bit data bus, or the like, for high speed data transfer. In at least one embodiment, the PPU includes U memory interfaces 3506 (where U is a positive integer), one memory interface 3506 per pair of partition units 3500, where each pair of partition units 3500 is connected to a respective memory device. For example, in at least one embodiment, the PPU may be connected to up to Y storage devices, such as a high bandwidth memory stack or graphics double data rate, version 5, synchronous dynamic random access memory ("GDDR 5 SDRAM").

In one embodiment, memory interface 3506 implements a high bandwidth memory second generation ("HBM 2") memory interface, and Y is equal to half of U. In at least one embodiment, the HBM2 memory stack and PPU are on a physical package, saving a significant amount of power and area compared to conventional GDDR5 SDRAM systems. In one embodiment, each HBM2 stack includes four memory dies and Y ═ 4, while the HBM2 stack includes two 128-bit lanes per die, for a total of 8 lanes and a data bus width of 1024 bits. In at least one embodiment, the memory supports single error correction double error detection ("SECDED") error correction codes ("ECC") to protect data. In at least one embodiment, ECC may provide greater reliability for computing applications that are sensitive to data corruption.

In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, memory partition unit 3500 supports unified memory to provide a single unified virtual address space for CPU and PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of accesses by the PPU to memory located on other processors is tracked to ensure that pages of memory are moved to the physical memory of the PPU that more frequently access the pages. In one embodiment, the high speed GPU interconnect 3308 supports an address translation service that allows the PPU to directly access the CPU's page tables and provide full access to the CPU memory by the PPU.

In one embodiment, the replication engine transfers data between multiple PPUs or between a PPU and a CPU. In one embodiment, the copy engine may generate a page fault for an address that is not mapped into a page table, and the memory partition unit 3500 then services the page fault, maps the address into the page table, and the copy engine performs the transfer. In at least one embodiment, fixed (i.e., non-pageable) memory is operated for multiple replication engines among multiple processors, thereby substantially reducing available memory. In one embodiment, due to a hardware page fault, the address may be passed to the copy engine regardless of whether the memory page resides, and the copy process is transparent.

According to at least one embodiment, data from memory 3304 of FIG. 33, or other system memory, is fetched by memory partition unit 3500 and stored in L2 cache 3504, which L2 cache 3504 is located on-chip and shared among various GPCs. In one embodiment, each memory partition unit 3500 includes at least a portion of the L2 cache associated with the corresponding memory device. In at least one embodiment, the lower level cache is implemented in various units within the GPC. In one embodiment, each SM 3414 may implement a level one ("L1") cache, where the L1 cache is a private memory dedicated to a particular SM 3414, and data from the L2 cache 3504 is retrieved and stored in each L1 cache for processing in the functional units of the SM 3414. In one embodiment, the L2 cache 3504 is coupled to the memory interface 3506 and XBar 3320 shown in fig. 33.

In one embodiment, ROP unit 3502 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. In one embodiment, ROP unit 3502 performs depth testing with raster engine 3408, receiving the depth of sample locations associated with pixel fragments from a culling engine of raster engine 3408. In at least one embodiment, to target sample locations associated with a fragment, depth tests are performed in a depth buffer for respective depths. In at least one embodiment, if the fragment passes the depth test for the sample location, ROP unit 3502 updates the depth buffer and sends the results of the depth test to grid raster engine 3408. It will be appreciated that the number of partition units 3500 may be different from the number of GPCs, and thus, in at least one embodiment, each ROP unit 3502 may be coupled to each GPC. In at least one embodiment, ROP unit 3502 tracks packets received from different GPCs and determines to which GPC the results generated by ROP unit 3502 are routed through Xbar 2820.

Fig. 36 shows a streaming multiprocessor ("SM") 3600 according to one embodiment. In at least one embodiment, SM 3600 is the SM of fig. 36. In at least one embodiment, SM 3600 includes, but is not limited to, instruction cache 3602; one or more scheduler units 3604; a register file 3608; one or more processing cores ("cores") 3610; one or more special function units ("SFUs") 3612; one or more load/store units ("LSUs") 3614; an interconnection network 3616; a shared memory/level one ("L1") cache 3618; and any suitable combination thereof.

In at least one embodiment, the work allocation unit dispatches tasks for execution on a general purpose processing cluster ("GPC") of parallel processing units ("PPUs"), and each task is allocated to a particular data processing cluster ("DPC") within the GPC, and, if the task is associated with a shader program, to the SM 3600. In one embodiment, the scheduler unit 3604 receives tasks from the work allocation unit and manages the scheduling of instructions assigned to one or more thread blocks of the SM 3600. In at least one embodiment, the scheduler unit 3604 schedules thread blocks for execution as bundles of parallel threads, where each thread block is assigned at least one bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 3604 manages a plurality of different thread blocks, assigns thread bundles to different thread blocks, and then assigns instructions from a plurality of different cooperating groups to respective functional units (e.g., cores 3610, SFUs 3612, and LSUs 3614) at each clock cycle.

In at least one embodiment, a collaboration group may refer to a programming model for organizing groups of communication threads that allows developers to express the granularity of the threads that are communicating, thereby making the expression richer and more efficient parallel decomposition. In at least one embodiment, the collaborative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the application of the conventional programming model provides a single simple construct for synchronizing the cooperative threads: a barrier (e.g., synchrads () function) across all threads of a thread block. However, in at least one embodiment, programmers often want to define thread groups at a size smaller than the thread block granularity and synchronize within the defined groups to achieve higher performance, design flexibility, and software reuse in the form of functional interfaces on a collective scale. In at least one embodiment, the collaboration group enables a programmer to define thread groups that are explicitly located on sub-block (e.g., as small as a single thread) and multi-block granularity, and perform collective operations, such as synchronization, on the threads in the collaboration group. In at least one embodiment, the programming model supports composition of cleanup across software boundaries, so libraries and utility functions can be safely synchronized in their local context without assumptions on convergence. In at least one embodiment, the collaboration group primitives enable new collaborative parallel modes, including producer-consumer parallel, opportunistic parallel, and global synchronization across the thread block grid.

In at least one embodiment, the schedule unit 3606 is configured to send instructions to one or more functional units, and the scheduler unit 3604 includes, but is not limited to, two schedule units 3606 that enable two different instructions from a common thread bundle to be scheduled in each clock cycle. In at least one embodiment, each scheduler unit 3604 includes a single scheduler unit 3606 or additional scheduler units 3606.

In at least one embodiment, each SM 3600 includes a register file 3608 that provides a set of registers for the functional units of the SM 3600. In at least one embodiment, register file 3608 is divided among each functional unit such that each functional unit is allocated a dedicated portion of register file 3608. In at least one embodiment, the register file 3608 is divided by the different threads executed by the SM 3600, and the register file 3608 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 3600 includes a number L of processing core new cores 3610 (where L is a positive integer). In at least one embodiment, the SM 3600 includes a large number, but not limited to (e.g., 128 or more) different processing cores 3610. In at least one embodiment, each core 3610 includes, but is not limited to, full-pipeline, single-precision, double-precision, and/or mixed-precision processing units including, but not limited to, floating-point arithmetic logic units ("ALUs") and integer arithmetic logic units. In at least one embodiment, the floating point arithmetic logic unit implements the IEEE 754-. In at least one embodiment, the processing cores 3610 include, but are not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

In accordance with at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, the cores 3610 include one or more tensor cores. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and reasoning. In at least one embodiment, each tensor core operates on a 4 x 4 matrix and performs a matrix multiply and accumulate operation D ═ a x B + C, where a, B, C, and D are 4 x 4 matrices.

In at least one embodiment, the matrix multiplication inputs a and B are 16-bit floating point matrices, and the accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on 16-bit floating-point input data. In at least one embodiment, 16-bit floating-point multiplication requires 64 operations and produces a full-precision product that is then accumulated with other intermediate products for a 4 x 4 matrix using 32-bit floating-point addition. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API, such as the CUDA 9C + + API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use the tensor core from the ClJDA-C + + program. In at least one embodiment, at the CUDA level, the thread bundle level interface assumes a matrix of 16 x 16 size across all 32 threads of the thread bundle.

In at least one embodiment, each SM3600 includes, but is not limited to, M SFUs 3612 that perform a particular function (e.g., attribute evaluation, inverse square root, etc.). In at least one embodiment, SFU 3612 includes, but is not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, SFU 3612 includes, but is not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load a texture map (e.g., a 2D array of pixels) from memory and sample the texture map to produce sampled texture values for use in a shader program executed by the SM 3600. In at least one embodiment, the texture map is stored in shared memory/L1 cache 3618. In at least one embodiment, the texture unit performs texture operations, such as filtering operations using mip-maps (e.g., texture maps with varying levels of detail). In at least one embodiment, each SM3600 includes, but is not limited to, two texture units.

In at least one embodiment, each SM3600 includes, but is not limited to, N LSUs 3614, the LSUs 3614 implementing load and store operations between the shared memory/Ll cache 3618 and the register file 3608. In at least one embodiment, interconnection network 3616 connects each functional unit to register file 3608 and LSU 3614 to register file 3608 and shared memory/L1 cache 3618. In at least one embodiment, interconnection network 3616 is a crossbar configurable to connect any functional unit to any register in register file 3608 and LSU 3614 to memory locations in register file 3608 and shared memory/L1 cache 3618.

In at least one embodiment, the shared memory/Ll cache 3618 is an array of on-chip memory that, in one embodiment, allows data storage and communication between the SM 3600 and the origin engines and between threads in the SM 3600. In at least one embodiment, the shared memory/LI cache 3618 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 3600 to the partition unit. In at least one embodiment, shared memory/L1 cache 3618 is used for caching reads and writes. One or more of shared memory/L1 cache 3618, L2 cache, and memory are backing store.

In at least one embodiment, combining data caching and shared memory functions into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, this capacity is used by programs that do not use the shared memory or as a cache, e.g., if the shared memory is configured to use half the capacity, texture and load/store operations may use the remaining capacity. According to at least one embodiment, integration within shared memory/L1 cache 3618 enables shared memory/L1 cache 3618 to function as a high throughput pipeline for streaming data while providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general purpose parallel computing, a simpler configuration may be used compared to graphics processing. In at least one embodiment, fixed function graphics processing units are bypassed, thereby creating a simpler programming model. In at least one embodiment, in a general purpose parallel computing configuration, the work allocation unit allocates and distributes blocks of threads directly to the DPCs. In at least one embodiment, the threads in a block execute the same program, use a unique thread ID in the computations to ensure that each thread generates a unique result, execute the program using SM 3600 and perform the computations, use shared memory/L1 cache 3618 to communicate between threads, and LSU 3614 reads and writes global memory through shared memory/L1 cache 3618 and memory partition units. In at least one embodiment, the SM 3600 write scheduler unit 3604 may be used to initiate new work commands on the DPC when configured for general purpose parallel computing.

In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), personal digital assistant ("PDA"), digital camera, vehicle, head mounted display, handheld electronic device, or the like. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system on chip ("SoC") along with one or more other devices (e.g., an additional PPU, memory, a reduced instruction set computer ("RISC") CPU, one or more memory management units ("MMUs"), digital-to-analog converters ("DACs"), etc.).

In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to connect to a PCIe slot on the desktop computer motherboard. In at least one embodiment, the PPU may be an integrated graphics processing unit ("iGPU") included in a chipset of a motherboard.

Inference and/or training logic 815 is operable to perform inference and/or training operations related to one or more embodiments. Details regarding inference and/or training logic 815 are provided herein in connection with fig. 8A and/or 8B. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the SM 3600. In at least one embodiment, the SM 3600 is used to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or by the SM 3600. In at least one embodiment, the SM 3600 may be used to perform one or more of the neural network use cases described herein.

Embodiments are disclosed that relate to virtualized computing platforms for advanced computing, such as image inference and image processing in medical applications. Without limitation, embodiments may include radiography, Magnetic Resonance Imaging (MRI), nuclear medicine, ultrasound examination, elastography, photoacoustic imaging, tomography, echocardiography, functional near infrared spectroscopy, and magnetic particle imaging, or combinations thereof. In at least one embodiment, the virtualized computing platform and related processes described herein may additionally or alternatively be used for, but are not limited to, forensic scientific analysis, subsurface exploration and imaging (e.g., oil exploration, archaeology, etc.), terrain, oceanography, geology, osteopathies, meteorology, smart area or object tracking and monitoring, sensor data processing (e.g., RADAR, SONAR, LIDAR, etc.), and/or genomics and genetic sequencing.

Referring to fig. 37, fig. 37 is an example data flow diagram of a process 3700 for generating and deploying an image processing and reasoning pipeline in accordance with at least one embodiment. In at least one embodiment, the process 3700 can be deployed for imaging devices, processing devices, genetic sequence devices, radiation devices, and/or other devices, etc., at one or more facilities 3702 (e.g., medical facilities, hospitals, medical institutions, clinics, research or diagnostic laboratories, etc.). In at least one embodiment, process 3700 can be deployed to perform genomic analysis and inference on sequencing data. Examples of genomic analysis that may be performed using the systems and processes described herein include, but are not limited to, variant calling, mutation detection, and gene expression quantification.

In at least one embodiment, the process 3700 may be performed within the training system 3704 and/or the deployment system 3706. In at least one embodiment, the training system 3704 can be used to perform training, deployment, and implementation of machine learning models used in the deployment system 3706 (e.g., neural networks, object detection algorithms, computer vision algorithms, etc.). In at least one embodiment, the deployment system 3706 can be configured to offload processing and computing resources in a distributed computing environment to reduce infrastructure requirements on the facility 3702. In at least one embodiment, the deployment system 3706 can provide a simplified platform for selecting, customizing, and enabling virtual instruments for use with an imaging device (e.g., MRI, CT scan, X-ray, ultrasound, etc.) or ordering devices at the facility 3702. In at least one embodiment, the virtual instrument may include a software defined application for performing one or more processing operations with respect to classification of imaging data generated by an imaging device, a sequencing device, a radiation device, and/or other device types. In at least one embodiment, one or more applications in the pipeline can use or invoke services (e.g., inference, visualization, computation, AI, etc.) of the deployment system 3706 during execution of the applications.

In at least one embodiment, some applications used in the advanced processing and reasoning pipeline may use a machine learning model or other AI to perform one or more processing steps. In at least one embodiment, a machine learning model may be trained at a facility 3702 using data 3708 (e.g., imaging data) generated at the facility 3702 (and stored on one or more Picture Archiving and Communication Systems (PACS) servers at the facility 3702). Training is performed using imaging or sequencing data 3708 from another facility or facilities (e.g., different hospitals, laboratories, clinics, etc.) or a combination thereof. In at least one embodiment, the training system 3704 can be utilized to provide applications, services, and/or other resources to generate a working, deployable machine learning model for the deployment system 3706.

In at least one embodiment, the model registry 3724 can be supported by an object store, which can support versioning and object metadata. In at least one embodiment, the object store may be accessed through an Application Programming Interface (API) compatible with the cloud store (e.g., cloud 3826 of fig. 38), for example, from within the cloud platform. In at least one embodiment, the machine learning models in the model registry 3724 can be uploaded, listed, modified, or deleted by a developer or partner of the system interacting with the API. In at least one embodiment, the API can provide access to methods that allow a user with appropriate credentials to associate a model with an application so that the model can be executed as part of the execution of a containerized instance of the application

In at least one embodiment, training pipeline 3804 (fig. 38) may include the following scenarios: the facilities 3702 are training their own machine learning models, or have existing machine learning models that need to be optimized or updated. In at least one embodiment, imaging data 3708 generated by an imaging device, a sequencing device, and/or other device type can be received. In at least one embodiment, upon receiving imaging data 3708, AI auxiliary annotations 3710 may be used to help generate annotations corresponding to imaging data 3708 for use as ground truth data for a machine learning model. In at least one embodiment, the AI-assist annotations 3710 can include one or more machine learning models (e.g., Convolutional Neural Networks (CNNs)) that can be trained to generate annotations corresponding to certain types of imaging data 3708 (e.g., from certain devices) and/or certain types of anomalies in the imaging data 3708. In at least one embodiment, AI-assisted annotation 3710 can then be used directly, or can be adjusted or refined using annotation tools (e.g., by researchers, clinicians, doctors, scientists, etc.) to generate ground truth data. In at least one embodiment, in some examples, the labeled clinical data 3712 (e.g., annotations provided by clinicians, doctors, scientists, technicians, etc.) can be used as ground truth data for training the machine learning model. In at least one embodiment, the AI auxiliary annotations 3710, labeled clinical data 3712, or a combination thereof may be used as ground truth data for training the machine learning model. In at least one embodiment, the trained machine learning model may be referred to as the output model 3716 and may be used by the deployment system 3706, as described herein.

In at least one embodiment, training pipeline 3804 (fig. 38) may include the following scenarios: the facility 3702 requires a machine learning model for performing one or more processing tasks for one or more applications in the deployment system 3706, but the facility 3702 may not currently have such a machine learning model (or may not have a model optimized, efficient, or effective for this purpose). In at least one embodiment, an existing machine learning model may be selected from the model registry 3724. In at least one embodiment, the model registry 3724 can include machine learning models trained to perform a variety of different inference tasks on the imaging data. In at least one embodiment, the machine learning models in model registry 3724 can be trained on imaging data from a facility other than facility 3702 (e.g., a remotely located facility). In at least one embodiment, the machine learning model may have been trained on imaging data from one location, two locations, or any number of locations. In at least one embodiment, when imaging data is trained from a particular location, the training may be performed at that location, or at least in a manner that protects the confidentiality of the imaging data or limits imaging data transferred from backup devices (off-provisions) (e.g., compliance with HIPAA regulations, privacy regulations, etc.). In at least one embodiment, once the model is trained, or partially trained, in one location, the machine learning model can be added to the model registry 3724. In at least one embodiment, the machine learning model may then be retrained or updated at any number of other facilities, and the retrained or updated model may be used in the model registry 3724. In at least one embodiment, a machine learning model can then be selected from the model registry 3724 and referred to as the output model 3716, and can be used in the deployment system 3706 to perform one or more processing tasks for one or more applications of the deployment system.

In at least one embodiment, the training pipeline 3804 (fig. 38) may be used in a scenario that includes a facility 3702 that requires machine learning models for performing one or more processing tasks on one or more applications in the deployment system 3706, although the facility 3702 may not currently have such machine learning models (or may not have models optimized, efficient, or effective for this purpose). In at least one embodiment, the machine learning model selected from the model registry 3724 may not be fine-tuned or optimized for the imaging data 3708 generated at the facility 3702 due to population differences, genetic variations, robustness of training data used to train the machine learning model, diversity of training data anomalies, and/or other issues with the training data. In at least one embodiment, AI auxiliary annotations 3710 may be used to help generate annotations corresponding to imaging data 3708 to use as ground truth data for retraining or updating a machine learning model. In at least one embodiment, the labeled clinical data 3712 (e.g., annotations provided by clinicians, doctors, scientists, etc.) can be used as ground truth data for training the machine learning model. In at least one embodiment, retraining or updating the machine learning model may be referred to as model training 3714. In at least one embodiment, model training 3714-e.g., AI-assisted annotation 3710, labeled clinical data 3712, or a combination thereof-can be used as ground truth data to train or update the machine learning model.

In at least one embodiment, the deployment system 3706 may include software 3718, services 3720, hardware 3722, and/or other components, features, and functionality. In at least one embodiment, the deployment system 3706 can include a software "stack" such that software 3718 can be built on top of the services 3720 and can use the services 3720 to perform some or all of the processing tasks, and the services 3720 and software 3718 can be built on top of the hardware 3722 and use the hardware 3722 to perform the processing, storage, and/or other computing tasks of the deployment system 3706.

In at least one embodiment, the software 3718 can include any number of different containers, where each container can perform an instantiation of an application. In at least one embodiment, each application may perform one or more processing tasks (e.g., inference, object detection, feature detection, segmentation, image enhancement, calibration, etc.) in a high-level processing and inference pipeline. In at least one embodiment, for each type of imaging device (e.g., CT, MRI, X-ray, ultrasound examination, echocardiography, etc.), sequencing device, radiology device, genomics device, etc., there can be any number of containers that can perform data processing tasks on the imaging data 3708 generated by the device (or other data types, such as those described herein). In at least one embodiment, a high-level processing and reasoning pipeline may be defined based on a selection of different containers desired or required to process imaging data 3708, in addition to containers that receive and configure imaging images for use by each container and/or for use by facility 3702 after processing through the pipeline (e.g., converting output back to usable data types, such as digital imaging and communications in medicine (DICOM) data, Radiology Information System (RIS) data, Clinical Information System (CIS) data, Remote Procedure Call (RPC) data, data that substantially conforms to a representational state transfer (REST) interface, data that substantially conforms to a file-based interface, and/or raw data for storage and display at facility 3702). In at least one embodiment, the combination of containers within the software 3718 (e.g., component pipelines) can be referred to as virtual instruments (as described in more detail herein), and the virtual instruments can utilize the services 3720 and hardware 3722 to perform some or all of the processing tasks of the applications instantiated in the containers.

In at least one embodiment, the data processing pipeline may receive input data (e.g., imaging data 3708) in DICOM, RIS, CIS, REST-compatible, RPC, raw, and/or other formats in response to an inference request (e.g., a request from a user of the deployment system 3706, such as a clinician, doctor, radiologist, etc.). In at least one embodiment, the input data may represent one or more images, videos, and/or other data representations generated by one or more imaging devices, sequencing devices, radiology devices, genomic devices, and/or other device types. In at least one embodiment, data may be pre-processed as part of a data processing pipeline to prepare the data for processing by one or more applications. In at least one embodiment, post-processing may be performed on the output of one or more inference tasks or other processing tasks of the pipeline to prepare output data for the next application and/or to prepare output data for transmission and/or use by a user (e.g., as a response to an inference request). In at least one embodiment, the inference task may be performed by one or more machine learning models, such as trained or deployed neural networks, which may include the output model 3716 of the training system 3704.

In at least one embodiment, the tasks of the data processing pipeline may be encapsulated in one or more containers, each container representing a discrete, fully functional instantiation of an application and a virtualized computing environment capable of referencing a machine learning model. In at least one embodiment, the container or application may be published into a private (e.g., limited-access) area of the container registry (described in more detail herein), and the trained or deployed model may be stored in the model registry 3724 and associated with one or more applications. In at least one embodiment, an image of an application (e.g., a container image) can be available in a container registry, and once selected by a user from the container registry for deployment in the pipeline, the image can be used to generate a container for instantiation of the application for use by the user system.

In at least one embodiment, a developer (e.g., a software developer, a clinician, a physician, etc.) may develop, publish, and store an application (e.g., as a container) for performing image processing and/or reasoning on the provided data. In at least one embodiment, development, release, and/or storage may be performed using a Software Development Kit (SDK) associated with the system (e.g., to ensure that the developed applications and/or containers are compatible or matched with the system). In at least one embodiment, the developed application may be tested locally (e.g., at the first facility, on data from the first facility) using an SDK that may support at least some of the services 3720 as a system (e.g., system 3800 of fig. 38). In at least one embodiment, because a DICOM object may contain anywhere from one to hundreds of images or other data types, and because of the changing data, developers may be responsible for managing (e.g., setting up constructs, building pre-processing into applications, etc.) the extraction and preparation of incoming DICOM data. In at least one embodiment, once verified by the system 3800 (e.g., accuracy, security, patient privacy, etc.), the application may be used in a container registry for a user (e.g., a hospital, clinic, laboratory, healthcare provider, etc.) to perform one or more processing tasks on data at a user facility (e.g., a second facility).

In at least one embodiment, the developer may then share applications or containers over a network for access and use by users of the system (e.g., system 3800 of FIG. 38). In at least one embodiment, the completed and verified application or container can be stored in the container registry and the associated machine learning model can be stored in the model registry 3724. In at least one embodiment, a requesting entity (e.g., a user in a medical facility) (a person providing inference or image processing requests) can browse the container registry and/or the model registry 3724 for applications, containers, data sets, machine learning models, etc., select a desired combination of elements to include in the data processing pipeline, and submit imaging processing requests. In at least one embodiment, the request may include input data necessary to perform the request (and in some examples, data related to the patient), and/or may include a selection of an application and/or machine learning model to perform when processing the request. In at least one embodiment, the request may then be passed to one or more components (e.g., the cloud) of the deployment system 3706 to perform processing of the data processing pipeline. In at least one embodiment, the processing by the deployment system 3706 can include referencing selected elements (e.g., applications, containers, models, etc.) from the container registry and/or the model registry 3724. In at least one embodiment, once the results are generated by the pipeline, the results may be returned to the user for reference (e.g., for viewing in a viewing application suite executing on a local, on-premises workstation or terminal). In at least one embodiment, the radiologist may receive results from a data processing pipeline that includes any number of applications and/or containers, where the results may include anomaly detection for X-rays, CT scans, MRI, and so forth.

In at least one embodiment, to assist in processing or executing applications or containers in the pipeline, the services 3720 can be utilized. In at least one embodiment, the services 3720 can include computing services, Artificial Intelligence (AI) services, visualization services, and/or other service types. In at least one embodiment, the services 3720 can provide functionality common to one or more applications in the software 3718, and thus can abstract functionality into services that can be called or utilized by applications. In at least one embodiment, the functionality provided by the services 3720 can run dynamically and more efficiently, while also scaling well by allowing applications to process data in parallel (e.g., using the parallel computing platform 3830 (fig. 38)). In at least one embodiment, rather than requiring each application sharing the same functionality provided by the service 3720 to have a respective instance of the service 3720, the service 3720 can be shared among the various applications. In at least one embodiment, the service may include, as non-limiting examples, an inference server or engine that may be used to perform detection or segmentation tasks. In at least one embodiment, a model training service may be included that may provide machine learning model training and/or retraining capabilities. In at least one embodiment, a data enhancement service may further be included that may provide GPU accelerated data (e.g., DICOM, RIS, CIS, REST compatible, RPC, raw, etc.), extraction, resizing, scaling, and/or other enhancements. In at least one embodiment, a visualization service may be used that may add image rendering effects (e.g., ray tracing, rasterization, denoising, sharpening, etc.) to add realism to two-dimensional (2D) and/or three-dimensional (3D) models. In at least one embodiment, a virtual instrument service may be included that provides beamforming, segmentation, reasoning, imaging, and/or support for other applications within the pipeline of the virtual instrument.

In at least one embodiment, where the services 3720 include AI services (e.g., inference services), one or more machine learning models associated with an application for anomaly detection (e.g., neoplasia, growth anomaly, scarring, etc.) can be executed as part of the application's execution by invoking (e.g., calling as an API to) the inference service (e.g., inference server) to execute the machine learning models or processing thereof. In at least one embodiment, where another application includes one or more machine learning models for a split task, the application may invoke an inference service to execute the machine learning models for performing one or more processing operations associated with the split task. In at least one embodiment, software 3718 implementing the high-level processing and inference pipelines including segmentation and anomaly detection applications can be streamlined in that each application can invoke the same inference service to perform one or more inference tasks.

In at least one embodiment, the hardware 3722 can include a GPU, a CPU, a graphics card, an AI/deep learning system (e.g., an AI supercomputer, a DGX supercomputer system such as NVIDIA), a cloud platform, or a combination thereof. In at least one embodiment, different types of hardware 3722 can be used to provide efficient, specific-purpose support for software 3718 and services 3720 in the deployment system 3706. In at least one embodiment, the use of GPU processing may be implemented for local processing (e.g., at the facility 3702), in AI/deep learning systems, in cloud systems, and/or in other processing components of the deployment system 3706 to improve the efficiency, accuracy, and efficacy of image processing, image reconstruction, segmentation, MRI examination, stroke or heart attack detection (e.g., in real-time), image quality in rendering, and the like. In at least one embodiment, the facility may include an imaging device, a genomic device, a sequencing device, and/or other locally deployed device types that may utilize the GPU to generate imaging data representative of the anatomy of the subject.

In at least one embodiment, software 3718 and/or services 3720 may be optimized for deep learning, machine learning, and/or high performance computing pins for GPU processing, as non-limiting examples. In at least one embodiment, at least some of the computing environments of the deployment system 3706 and/or the training system 3704 may execute one or more supercomputers or high performance computing systems in a datacenter with GPU optimized software (e.g., a combination of hardware and software of the DGX system of NVIDIA). In at least one embodiment, the data center may comply with HIPAA regulations such that privacy with respect to patient data securely handles receiving, processing, and transmitting imaging data and/or other patient data. In at least one embodiment, hardware 3722 may include any number of GPUs that may be invoked to perform data processing in parallel, as described herein. In at least one embodiment, the cloud platform may also include GPU processing for GPU-optimized execution of deep learning tasks, machine learning tasks, or other computing tasks. In at least one embodiment, the cloud platform (e.g., NGC of NVIDIA) may be executed using software (e.g., as provided on the DGX system of NVIDIA) that is a hardware abstraction and scaling platform AI/deep learning supercomputer and/or GPU optimization. In at least one embodiment, the cloud platform may integrate an application container cluster system or orchestration system (e.g., kubbernetes) on multiple GPUs to achieve seamless scaling and load balancing.

FIG. 38 is a system diagram of an example system 3800 for generating and deploying an imaging deployment pipeline, according to at least one embodiment. In at least one embodiment, system 3800 can be utilized to implement process 3700 of fig. 37 and/or other processes, including high-level processing and inference pipelines. In at least one embodiment, the system 3800 can include a training system 3704 and a deployment system 3706. In at least one embodiment, the training system 3704 and the deployment system 3706 may be implemented using software 3718, services 3720, and/or hardware 3722.

In at least one embodiment, the system 3800 (e.g., training system 3704 and/or deployment system 3706) may be implemented in a cloud computing environment (e.g., using cloud 3826). In at least one embodiment, the system 3800 can be implemented locally for a healthcare facility, or as a combination of cloud and local computing resources. In at least one embodiment, in embodiments implementing cloud computing implementations, patient data may be separate from or not processed by one or more components of the system 3800, which would make the processing non-compliant with HIPAA and/or other data processing and privacy regulations or laws. In at least one embodiment, access to APIs in cloud 3826 can be restricted to authorized users through established security measures or protocols. In at least one embodiment, the security protocol may include a network token that may be signed by an authentication service (e.g., AuthN, AuthZ, glucecon, etc.) and may carry the appropriate authorization. In at least one embodiment, the API of the virtual instrument (described herein) or other instances of system 3800 can be limited to a set of public IPs that have been audited or authorized for interaction.

In at least one embodiment, the various components of system 3800 can communicate between each other via wire and/or wireless communication protocols using any of a variety of different network types, including but not limited to a Local Area Network (LAN) and/or a Wide Area Network (WAN). In at least one embodiment, communications between facilities and components of system 3800 (e.g., for sending inference requests, for receiving results of inference requests, etc.) can be communicated over one or more data buses, wireless data protocols (Wi-Fi), wired data protocols (e.g., ethernet), and so forth.

In at least one embodiment, the training system 3704 may execute the training pipeline 3804 similar to those described herein with respect to fig. 37. In at least one embodiment, where the deployment system 3706 is to use one or more machine learning models in the deployment pipeline 3810, the training pipeline 3804 can be used to train or retrain one or more (e.g., pre-trained) models, and/or implement one or more pre-trained models 3806 (e.g., without retraining or updating). In at least one embodiment, as a result of training pipeline 3804, an output model 3716 can be generated. In at least one embodiment, the training pipeline 3804 may include any number of processing steps, such as, but not limited to, conversion or adaptation of imaging data (or other input data) (e.g., using the DICOM adapter 3802A to convert DICOM images to be suitable for processing by a corresponding machine learning model, such as the neuroimaging information technology planning (NIfTI) format, AI-assisted annotation 3710, labels or annotations 3708 of the imaging data to generate labeled clinical data 3712, selection of a model from a registry, model training 3714, training, retraining, or updating of a model, and/or other processing steps the different training pipeline 3804 may be used for different machine learning models used by the deployment system 3706 in at least one embodiment, a training pipeline 3804 similar to the first example described with respect to fig. 37 may be used for the first machine learning model, training pipeline 3804 similar to the second example described with respect to fig. 37 may be used for the second machine learning model, and training pipeline 3804 similar to the third example described with respect to fig. 37 may be used for the third machine learning model. In at least one embodiment, any combination of tasks within the training system 3704 can be used as required by each respective machine learning model. In at least one embodiment, one or more of the machine learning models may have been trained and are ready for deployment, and thus the machine learning models may not be processed by the training system 3704, and may be implemented by the deployment system 3706.

In at least one embodiment, the output model 3716 and/or the pre-training model 3806 may include any type of machine learning model, depending on the implementation or embodiment. In at least one embodiment, but not limited to, the machine learning model used by system 3800 can include machine learning models using linear regression, logistic regression, decision trees, Support Vector Machines (SVMs), naive bayes, K-nearest neighbors (Knn), K-means clustering, random forests, dimensionality reduction algorithms, gradient boosting algorithms, neural networks (e.g., autoencoders, convolutions, recursions, perceptrons, long term/short term memory (LSTM), hopfields, Boltzmann, deep beliefs, deconvolution, generative confrontations, liquid state machines, etc.), and/or other types.

In at least one embodiment, the training pipeline 3804 can include AI-assisted annotations, as described in more detail herein with respect to at least fig. 41B. In at least one embodiment, the labeled clinical data 3712 (e.g., traditional annotations) can be generated by a number of techniques. In at least one embodiment, the tags or other annotations may be generated within a drawing program (e.g., an annotation program), a computer-aided design (CAD) program, a marking program, another type of program suitable for generating annotations or tags for ground truth, and/or in some examples, the tags or other annotations may be hand drawn. In at least one embodiment, the ground truth data may be synthetically generated (e.g., from computer models or rendering), truly generated (e.g., designed and generated from real-world data), machine automated (e.g., using feature analysis and learning to extract features from the data and then generate labels), manually annotated (e.g., a labeler or annotation expert, defining the location of labels), and/or combinations thereof. In at least one embodiment, for each instance of imaging data 3708 (or other data type used by the machine learning model), there may be corresponding ground truth data generated by training system 3704. In at least one embodiment, AI-assisted annotation can be performed as part of the deployment pipeline 3810; or in addition to or in lieu of AI-assisted annotations included in the training pipeline 3804. In at least one embodiment, the system 3800 can include a multi-tier platform that can include software layers (e.g., software 3718) of a diagnostic application (or other application type) that performs one or more medical imaging and diagnostic functions. In at least one embodiment, the system 3800 can be communicatively coupled (e.g., via an encrypted link) to a PACS server network of one or more facilities. In at least one embodiment, the system 3800 can be configured to access and reference data (e.g., via the DICOM adapter 3802 or other data type (e.g., RIS, CIS, REST-compatible, RPC, raw, etc.) adapters) from a PACS server (e.g., DICOM data, RIS data, raw data, CIS data, REST-compliant data, RPC data, raw data, etc.) to perform operations, such as training a machine learning model, deploying a machine learning model, image processing, reasoning, and/or other operations.

In at least one embodiment, the software layer may be implemented as a secure, encrypted, and/or authenticated API through which an application or container may be woken up (e.g., called) from the external environment (e.g., the facility 3702). In at least one embodiment, the applications can then call or execute one or more services 3720 to perform computing, AI, or visualization tasks associated with the respective applications, and software 3718 and/or services 3720 can utilize hardware 3722 to perform processing tasks in an efficient and effective manner.

In at least one embodiment, the deployment system 3706 can execute the deployment pipeline 3810. In at least one embodiment, the deployment pipeline 3810 may include any number of applications (and/or other data types) that may be sequentially, non-sequentially, or otherwise applied to imaging data (including AI-assisted annotation as described above) generated by an imaging device, a sequencing device, a genomic device, or the like. In at least one embodiment, as described herein, the deployment pipeline 3810 for a single device may be referred to as a virtual instrument for the device (e.g., a virtual ultrasound instrument, a virtual CT scan instrument, a virtual sequencing instrument, etc.). In at least one embodiment, there may be more than one deployment pipeline 3810 for a single device, depending on the information desired to generate the data from the device. In at least one embodiment, where an anomaly is desired to be detected from the MRI machine, there may be a first deployment pipeline 3810, and where image enhancement from the output of the MRI machine is desired, there may be a second deployment pipeline 3810.

In at least one embodiment, the applications that may be used to deploy the pipeline 3810 may include any application that may be used to perform processing tasks on imaging data or other data from a device. In at least one embodiment, the different applications may be responsible for image enhancement, segmentation, reconstruction, anomaly detection, object detection, feature detection, treatment planning, dosimetry, beam planning (or other radiation treatment procedures), and/or other analysis, image processing, or inference tasks. In at least one embodiment, the deployment system 3706 can define a construct for each application such that a user of the deployment system 3706 (e.g., a medical facility, laboratory, clinic, etc.) can understand the construct and adapt the application for implementation within their respective facility. In at least one embodiment, the application used for image reconstruction may be selected for inclusion in the deployment pipeline 3810, but the type of data generated by the imaging device may be different from the type of data used within the application. In at least one embodiment, a DICOM adapter 3802B (and/or DICOM reader) or another data type (e.g., RIS, CIS, REST-compatible, RPC, raw, etc.) adapter or reader may be used within the deployment pipeline 3810 to convert the data to a form usable by applications within the deployment system 3706. In at least one embodiment, accesses to DICOM, RIS, CIS, REST compatible, RPC, raw and/or other data type libraries may be accumulated and preprocessed, including decoding, extracting and/or performing any convolution, color correction, sharpness, gamma and/or other enhancement to the data. In at least one embodiment, DICOM, RIS, CIS, REST-compliant RPC, and/or raw data may be unordered and pre-pass may be performed to organize or categorize the collected data. In at least one embodiment, because various applications may share common image operations, in some embodiments, a data enhancement library (e.g., as one of services 3720) may be used to accelerate these operations. In at least one embodiment, to avoid bottlenecks in conventional processing methods that rely on CPU processing, the parallel computing platform 3830 may be used for GPU acceleration of these processing tasks.

In at least one embodiment, the image reconstruction application can include a processing task that includes using a machine learning model. In at least one embodiment, users may wish to use their own machine learning model, or select a machine learning model from the model registry 3724. In at least one embodiment, users can implement their own machine learning models or select machine learning models for inclusion in an application that performs a processing task. In at least one embodiment, the application may be selectable and customizable, and by defining the configuration of the application, the deployment and implementation of the application for a particular user is presented as a more seamless user experience. In at least one embodiment, by utilizing other features of the system 3800, such as the services 3720 and hardware 3722, the deployment pipeline 3810 may be more user friendly, provide easier integration, and produce more accurate, efficient, and timely results.

In at least one embodiment, the deployment system 3706 can include a user interface 3814 (e.g., a graphical user interface, a network interface, etc.) that can be used to select applications to be included in the deployment pipeline 3810, arrange applications during setup and/or deployment, modify or change applications or parameters or constructs thereof, use and interact with the deployment pipeline 3810 during setup and/or deployment, and/or otherwise interact with the deployment system 3706. For training system 3704 (not shown), user interface 3814 (or a different user interface) may be used to select models for use in deployment system 3706, to select models for training or retraining in training system 3704, and/or to otherwise interact with training system 3704.

In at least one embodiment, in addition to the application orchestration system 3828, the pipeline manager 3812 may be used to manage interactions between applications or containers of the deployment pipeline 3810 and the services 3720 and/or hardware 3722. In at least one embodiment, the pipeline manager 3812 may be configured to facilitate interactions from application to application, from application to service 3720, and/or from application or service to hardware 3722. In at least one embodiment, although illustrated as being included in software 3718, this is not meant to be limiting, and in some examples, the pipeline manager 3812 may be included in the service 3720. In at least one embodiment, application orchestration system 3828 (e.g., kubernets, DOCKER, etc.) may be included, possibly including a container orchestration system, which may group applications into multiple containers for coordination, management, expansion, and deployment as logical units. In at least one embodiment, by associating applications (e.g., rebuild applications, segmented applications, etc.) from the deployment pipeline 3810 with respective containers, each application may execute in a self-contained environment (e.g., at the kernel level) to increase speed and efficiency.

In at least one embodiment, each application and/or container (or image thereof) may be separately developed, modified, and deployed (e.g., a first user or developer may develop, modify, and deploy a first application and a second user or developer may develop, modify, and deploy a second application separate from the first user or developer), which may enable tasks that focus on and focus on a single application and/or container without being encumbered by the tasks of another application or container. In at least one embodiment, the pipeline manager 3812 and the application orchestration system 3828 may facilitate communication and collaboration between different containers or applications. In at least one embodiment, the application orchestration system 3828 and/or the pipeline manager 3812 may facilitate communication and resource sharing among and between each application or container, as long as the expected inputs and/or outputs of each container or application are known to the system (e.g., based on the configuration of the application or container). In at least one embodiment, because one or more applications or containers in the deployment pipeline 3810 may share the same services and resources, the application orchestration system 3828 may coordinate, load balance, and determine the sharing of services or resources between various applications or between containers. In at least one embodiment, a scheduler may be used to track the resource requirements of an application or container, the current or projected use of these resources, and the resource availability. Thus, in at least one embodiment, the scheduler can allocate resources to different applications in view of the needs and availability of the system, and allocate resources among and between applications. In some examples, the scheduler (and/or other components of the application orchestration system 3828) may determine resource availability and allocation based on constraints imposed on the system (e.g., user constraints), such as quality of service (QoS), urgency of demand for data output (e.g., determining whether to perform real-time processing or deferred processing), and so on.

In at least one embodiment, the services 3720 utilized by and shared by applications or containers in the deployment system 3706 may include computing services 3816, AI services 3818, visualization services 3820, and/or other service types. In at least one embodiment, an application can invoke (e.g., execute) one or more of the services 3720 to perform processing operations for the application. In at least one embodiment, applications may utilize computing service 3816 to perform supercomputing or other High Performance Computing (HPC) tasks. In at least one embodiment, parallel processing may be performed with computing services 3816 (e.g., using parallel computing platform 3830) to process data substantially simultaneously by one or more applications and/or one or more tasks of a single application. In at least one embodiment, the parallel computing platform 3830 (e.g., CUDA by NVIDIA) may implement general purpose computing on a GPU (gpgpu) (e.g., GPU 3822). In at least one embodiment, a software layer of the parallel computing platform 3830 may provide access to the virtual instruction set of the GPU and the parallel computing elements to execute the compute kernels. In at least one embodiment, parallel computing platform 3830 may include memory, and in some embodiments, memory may be shared among and among multiple containers, and/or among and among different processing tasks within a single container. In at least one embodiment, inter-process communication (IPC) calls may be generated for multiple containers and/or multiple processes within a container to use the same data from the shared memory segment of the parallel computing platform 3830 (e.g., where multiple different phases of an application or multiple applications are processing the same information). In at least one embodiment, rather than copying and moving data to different locations in memory (e.g., read/write operations), the same data in the same location in memory may be used for any number of processing tasks (e.g., at the same time, at different times, etc.). In at least one embodiment, since data is used as a result of processing to generate new data, information of the new location of the data may be stored and shared among various applications. In at least one embodiment, the location of the data and the location of the updated or modified data may be part of a definition of how the payload is understood in the container.

In at least one embodiment, AI service 3818 may be utilized to perform inference services to execute machine learning models associated with an application (e.g., tasks assigned to perform one or more processing tasks of the application). In at least one embodiment, AI services 3818 may utilize AI system 3824 to perform machine learning models (e.g., neural networks such as CNNs) for segmentation, reconstruction, object detection, feature detection, classification, and/or other inference tasks. In at least one embodiment, the application of the deployment pipeline 3810 can use one or more of the output models 3716 from the training system 3704 and/or models of other applications to reason about imaging data (e.g., DICOM data, RIS data, CIS data, REST-compatible data, RPC data, raw data, etc.). In at least one embodiment, two or more examples of reasoning using the application orchestration system 3828 (e.g., a scheduler) may be available. In at least one embodiment, the first category may include high priority/low latency paths that may implement higher service level agreements, for example, for performing reasoning on emergency requests in an emergency situation, or for providing to a radiologist during diagnosis. In at least one embodiment, the second category may include standard priority paths that may be used for requests that may not be urgent or for requests that may be analyzed at a later time. In at least one embodiment, the application coordination system 3828 can allocate resources (e.g., services 3720 and/or hardware 3722) based on priority paths for different inference tasks of the AI service 3818.

In at least one embodiment, the shared storage may be installed to an AI service 3818 within the system 3800. In at least one embodiment, the shared storage may be used as a cache (or other storage device type) and may be used to process inference requests from applications. In at least one embodiment, when a reasoning request is submitted, a set of API instances of the deployment system 3706 can receive the request and can select one or more instances (e.g., for best fit, for load balancing, etc.) to process the request. In at least one embodiment, to process the request, the request may be entered into a database, the machine learning model may be found from the model registry 3724 (if not already in cache), a verification step may ensure that the appropriate machine learning model is loaded into cache (e.g., shared store) and/or a copy of the model may be saved into cache. In at least one embodiment, a scheduler (e.g., of the pipeline manager 3812) may be used to launch the application referenced in the request if the application is not already running or there are not enough instances of the application. In at least one embodiment, the inference server can be launched if it has not already been launched to execute the model. In at least one embodiment, each model may launch any number of inference servers. In at least one embodiment, in a pull model where inference servers are clustered, the model can be cached as long as load balancing is advantageous. In at least one embodiment, the inference server can be statically loaded in the corresponding distributed server.

In at least one embodiment, inference can be performed using an inference server running in a container. In at least one embodiment, an instance of the inference server can be associated with a model (and optionally multiple versions of the model). In at least one embodiment, if an instance of the inference server does not exist when a request to perform inference on a model is received, a new instance may be loaded. In at least one embodiment, when the inference server is launched, the models can be passed to the inference server so that the same container can be used to serve different models as long as the inference server operates as a different instance.

In at least one embodiment, during application execution, inference requests for a given application can be received, and a container (e.g., an instance of a hosted inference server) can be loaded (if not already loaded), and a launcher can be invoked. In at least one embodiment, the pre-processing logic in the container may load, decode, and/or perform any additional pre-processing on the incoming data (e.g., using one or more CPUs and/or one or more GPUs). In at least one embodiment, once the data is ready for reasoning, the container can reason the data as needed. In at least one embodiment, this may include a single inference call for one image (e.g., hand X-ray) or may require that hundreds of images (e.g., chest CT) be inferred. In at least one embodiment, the application may summarize the results prior to completion, which may include, but is not limited to, single confidence scores, pixel level segmentation, voxel level segmentation, generating visualizations, or generating text to summarize the findings. In at least one embodiment, different models or applications may be assigned different priorities. For example, some models may have real-time (TAT less than one minute) priority, while other models may have lower priority (e.g., TAT less than 10 minutes). In at least one embodiment, the model execution time can be measured from the requesting authority or entity, and can include partner network traversal time and execution on the inference service.

In at least one embodiment, the request transfer between the service 3720 and the inference application can be hidden behind the Software Development Kit (SDK) and can provide robust transfer through queues. In at least one embodiment, requests via the API for a single application/tenant ID combination are placed in a queue, and the SDK will pull the request from the queue and provide the request to the application. In at least one embodiment, the name of the queue may be provided in the context from which the SDK picks the queue. In at least one embodiment, asynchronous communication through a queue may be useful because it may allow any instance of an application to pick up work when available. In at least one embodiment, the results may be transferred back through the queue to ensure that no data is lost. In at least one embodiment, the queue may also provide the ability to segment work because the highest priority work may enter the queue connected to most instances of the application, while the lowest priority work may enter the queue connected to a single instance that processes tasks in the order received. In at least one embodiment, the application may run on a GPU-accelerated instance generated in the cloud 3826, and the inference service may perform inference on the GPU.

In at least one embodiment, the visualization service 3820 may be utilized to generate visualizations to view the output of the applications and/or the deployment pipeline 3810. In at least one embodiment, visualization service 3820 may utilize GPU3822 to generate visualizations. In at least one embodiment, the visualization service 3820 may implement rendering effects, such as ray tracing, to generate higher quality visualizations. In at least one embodiment, the visualization may include, but is not limited to, 2D image rendering, 3D volume reconstruction, 2D tomographic slices, virtual reality displays, augmented reality displays, and the like. In at least one embodiment, a virtualized environment may be used to generate a virtual interactive display or environment (e.g., a virtual environment) for interaction by a system user (e.g., a doctor, nurse, radiologist, etc.). In at least one embodiment, the visualization services 3820 may include internal visualizers, movies, and/or other rendering or image processing capabilities or functions (e.g., ray tracing, rasterization, internal optics, etc.).

In at least one embodiment, hardware 3722 may include GPU3822, AI system 3824, cloud 3826, and/or any other hardware used to execute training system 3704 and/or deployment system 3706. In at least one embodiment, GPUs 3822 (e.g., TESLA and/or quaduro GPUs of NVIDIA) may include any number of GPUs that may be used to execute computing services 3816, AI services 3818, visualization services 3820, other services, and/or processing task software 3718 of any function or characteristic. For example, with respect to AI services 3818, GPU3822 may be used to perform pre-processing on imaging data (or other data types used by the machine learning model), post-processing the output of the machine learning model, and/or perform inference (e.g., execute the machine learning model). In at least one embodiment, the GPU3822 may be used by the cloud 3826, AI system 3824, and/or other components of system 3800. In at least one embodiment, the cloud 3826 may include a GPU optimization platform for deep learning tasks. In at least one embodiment, AI systems 3824 may use GPUs, and one or more AI systems 3824 may be used to perform cloud 3826 (or at least a portion of the tasks responsible for deep learning or reasoning). Also, while hardware 3722 is shown as a discrete component, this is not intended to limit the invention, and any component of hardware 3722 may be combined with or utilized by any other component of hardware 3722.

In at least one embodiment, AI system 3824 may include a special-purpose computing system (e.g., a supercomputer or HPC) configured for reasoning, deep learning, machine learning, and/or other artificial intelligence tasks. In at least one embodiment, the AI system 3824 (e.g., DGX of NVIDIA) may include GPU optimized software (e.g., a software stack) that may be executed using multiple GPUs 3822, in addition to a CPU, RAM, memory, and/or other components, features, or functions. In at least one embodiment, one or more AI systems 3824 can be implemented in the cloud 3826 (e.g., in a data center) to perform some or all of the AI-based processing tasks of system 3800.

In at least one embodiment, cloud 3826 may include a GPU-accelerated infrastructure (e.g., NGC of NVIDIA), which may provide a GPU-optimized platform for performing processing tasks of system 3800. In at least one embodiment, cloud 3826 can include an AI system 3824 for performing one or more AI-based tasks of system 3800 (e.g., as a hardware abstraction and scaling platform). In at least one embodiment, the cloud 3826 can be integrated with an application orchestration system 3828 that utilizes multiple GPUs to enable seamless scaling and load balancing between and among applications and services 3720. In at least one embodiment, the cloud 3826 can assume the task of executing at least some of the services 3720 of the system 3800, the system 3800 including a computing service 3816, an AI service 3818, and/or a visualization service 3820, as described herein. In at least one embodiment, cloud 3826 may perform small and large scale inference (e.g., perform TENSOR RT for NVIDIA), provide accelerated parallel computing APIs and platforms 3830 (e.g., CUDA for NVIDIA), execute application orchestration system 3828 (e.g., kubbernetes), provide graphics rendering APIs and platforms (e.g., for ray tracing, 2D graphics, 3D graphics, and/or other rendering techniques to produce higher quality movie effects), and/or may provide other functionality for system 3800.

In at least one embodiment, to protect patient confidentiality (e.g., where the backup device uses patient data or records), the cloud 3826 may include a registry, such as a deep learning container registry. In at least one embodiment, the registry may store containers for instantiating applications that may perform pre-processing, post-processing, or other processing tasks on patient data. In at least one embodiment, the cloud 3826 can receive data including patient data as well as sensor data in containers, perform the requested processing only on the sensor data in those containers, and then forward the resulting output and/or visualization to the appropriate participants and/or devices (e.g., locally deployed medical devices for visualization or diagnosis) without having to extract, store, or access the patient data. In at least one embodiment, confidentiality of patient data is preserved in accordance with HIPAA and/or other data regulations.

FIG. 39 includes an example illustration of a deployment pipeline 3810A for processing imaging data in accordance with at least one embodiment. In at least one embodiment, the system 3800, and in particular the deployment system 3706, can be utilized to customize, update, and/or integrate the deployment pipeline 3810A into one or more production environments. In at least one embodiment, the deployment pipeline 3810A of fig. 39 may include non-limiting examples of deployment pipelines 3810A, which may be custom-defined by a particular user (or team of users) at a facility (e.g., hospital, clinic, laboratory, research environment, etc.). In at least one embodiment, to define the deployment pipeline 3810A for the CT scanner 3902, a user may select one or more applications, for example from a container registry, that perform particular functions or tasks with respect to imaging data generated by the CT scanner 3902. In at least one embodiment, the application may be applied to the deployment pipeline 3810A as a container that may utilize the services 3720 and/or hardware 3722 of the system 3800. Further, the deployment pipeline 3810A may include additional processing tasks or applications that may be implemented to prepare data for use by the applications (e.g., the DICOM adapter 3802B and DICOM reader 3906 may be used in the deployment pipeline 3810A to prepare data for use in CT reconstruction 3908, organ segmentation 3910, etc.). In at least one embodiment, the deployment line 3810A may be customized or selected for consistent deployment, one use, or another frequency or interval. In at least one embodiment, a user may wish to have CT reconstructions 3908 and organ segmentations 3910 for several objects within a particular interval, and thus may deploy the pipeline 3810A within that time period. In at least one embodiment, the user may select, for each request from the system 3800, an application for which the user wants to perform processing on the data for the request. In at least one embodiment, the deployment pipeline 3810A can be adjusted at any interval, and this can be a seamless process due to the adaptability and scalability of the container structure within the system 3800.

In at least one embodiment, the deployment line 3810A of fig. 39 may include a CT scanner 3902 that generates imaging data of a patient or subject. In at least one embodiment, imaging data from the CT scanner 3902 can be stored on a PACS server 3904 associated with the facility housing the CT scanner 3902. In at least one embodiment, the PACS server 3904 may include software and/or hardware components (e.g., the CT scanner 3902) that may interface directly with imaging modalities at a facility. In at least one embodiment, the DICOM adapter 3802B may enable sending and receiving DICOM objects using the DICOM protocol. In at least one embodiment, the DICOM adapter 3802B may help prepare or configure DICOM data from the PACS server 3904 for use by the deployment pipeline 3810A. In at least one embodiment, once DICOM data is processed through the DICOM adapter 3802B, the pipeline manager 3812 may route the data to the deployment pipeline 3810A. In at least one embodiment, the DICOM reader 3906 may extract an image file and any associated metadata from DICOM data (e.g., raw sinogram data as shown in the visualization 3916A). In at least one embodiment, the extracted work files may be stored in a cache for faster processing by other applications in the deployment pipeline 3810A. In at least one embodiment, once the DICOM reader 3906 completes the retrieval and/or storage of the data, a completion signal may be communicated to the pipeline manager 3812. In at least one embodiment, the pipeline manager 3812 may then launch or invoke one or more other applications or containers in the deployment pipeline 3810A.

In at least one embodiment, the CT reconstruction 3908 application and/or container can be performed once the data (e.g., raw sinogram data) is available for processing by the CT reconstruction 3908 application. In at least one embodiment, the CT reconstruction 3908 can read the raw sinogram data from a cache, reconstruct an image file from the raw sinogram data (e.g., as shown in the visualization 3916B), and store the resulting image file in the cache. In at least one embodiment, upon completion of the rebuild, the pipeline manager 3812 may be signaled that the rebuild task is complete. In at least one embodiment, once the reconstruction is complete, and the reconstructed image file may be stored in a cache (or other storage device), the organ segmentation 3910 application and/or container may be triggered by the pipeline manager 3812. The organ segmentation 3910 application and/or container may read the image files from the cache, normalize or convert the image files to a format suitable for inference (e.g., convert the image files to an input resolution of a machine learning model), and then run an inference on the normalized images. In at least one embodiment, to reason about the normalized images, the organ segmentation 3910 applications and/or containers may rely on the service 3720, and the pipeline manager 3812 and/or the application orchestration system 3828 may facilitate use of the service 3720 by the organ segmentation 3910 applications and/or containers. In at least one embodiment, for example, organ segmentation 3910 applications and/or containers may utilize AI service 3818 to perform inference on the normalized images, and AI service 3818 may utilize hardware 3722 (e.g., AI system 3824) to perform AI service 3818. In at least one embodiment, the result of the inference can be a mask file (e.g., as shown in visualization 3916C) that can be stored in a cache (or other storage device).

In at least one embodiment, a signal may be generated for the pipeline manager 3812 once the application processing the DICOM data and/or data extracted from the DICOM data has completed processing. In at least one embodiment, the pipeline manager 3812 may then execute the DICOM writer 3912 to read the results from the cache (or other storage device), package the results into a DICOM format (e.g., as DICOM export 3914) for use by the user at the facility that generated the request. In at least one embodiment, the DICOM export 3914 may then be sent to the DICOM adapter 3802B to prepare the DICOM export 3914 for storage on the PACS server 3904 (e.g., for viewing by a DICOM viewer at the facility). In at least one embodiment, in response to a request for reconstruction and segmentation, visualizations 3916B and 3916C may be generated and made available to a user for diagnostic, research, and/or for other purposes.

Although illustrated as a sequential application in the deployment pipeline 3810A, in at least one embodiment, the CT reconstruction 3908 and organ segmentation 3910 applications may be processed in parallel. In at least one embodiment, where the applications do not depend on each other and data is available to each application (e.g., after data is fetched by the DICOM reader 3906), the applications may be executed at the same time, substantially at the same time, or with some overlap. In at least one embodiment, where two or more applications require similar services 3720, the scheduler of system 3800 can be used for load balancing and allocating computing or processing resources among the various applications and among the various applications. In at least one embodiment, in some embodiments, the parallel computing platform 3830 may be used to perform parallel processing on applications to reduce the runtime of the deployment pipeline 3810A to provide real-time results.

In at least one embodiment, and as illustrated with reference to fig. 40A-40B, the deployment system 3706 can be implemented as one or more virtual instruments to perform different functions, such as image processing, segmentation, enhancement, AI, visualization, and reasoning, with an imaging device (e.g., CT scanner, X-ray machine, MRI machine, etc.), a sequencing device, a genomic device, and/or other device types. In at least one embodiment, the system 3800 can allow for the creation and provision of virtual instruments that can include a software-defined deployment pipeline 3810 that can receive raw/unprocessed input data generated by one or more devices and output processed/reconstructed data. In at least one embodiment, the deployment pipeline 3810 (e.g., 3810A and 3810B) representing the virtual instrument can implement intelligence into the pipeline, for example, by utilizing machine learning models, to provide containerized reasoning support to the system. In at least one embodiment, the virtual instrument may execute any number of containers, each container including an instance of an application. In at least one embodiment, the deployment pipeline 3810 representing the virtual instrument may be static (e.g., a container and/or application may be set), for example where real-time processing is required, while in other examples, a container and/or application for the virtual instrument may be selected (e.g., on a per-request basis) from an application or pool of resources (e.g., in a container registry).

In at least one embodiment, the system 3800 can be instantiated or executed as one or more virtual instruments deployed locally at a facility in a computing system, for example, adjacent to or otherwise in communication with a radiation machine, an imaging device, and/or other device types in the facility. However, in at least one embodiment, the on-premise installation may be instantiated or performed within a computing system (e.g., a computing system integrated with the imaging device) of the device itself in a local data center (e.g., an on-premise data center) and/or in a cloud environment (e.g., cloud 3826). In at least one embodiment, the deployment system 3706, which operates as a virtual instrument, may be instantiated by a supercomputer or other HPC system in some examples. In at least one embodiment, the local deployment installation may allow for high bandwidth usage for real-time processing (e.g., over a higher throughput local communication interface, such as RF over ethernet). In at least one embodiment, real-time or near real-time processing may be particularly useful where the virtual instrument supports an ultrasound device or other imaging modality in which immediate visualization is desired or required for accurate diagnosis and analysis. In at least one embodiment, the cloud computing architecture may be able to dynamically explode to cloud computing service providers or other computing clusters when local demand exceeds local deployment capacity or capability. In at least one embodiment, the cloud architecture, when implemented, can be adapted for training a neural network or other machine learning model, as described herein with respect to the training system 3704. In at least one embodiment, with an appropriate training pipeline, a machine learning model may continually learn and improve while processing other data in its supporting devices. In at least one embodiment, the virtual instrument can be continuously improved using additional data, new data, existing machine learning models, and/or new or updated machine learning models.

In at least one embodiment, the computing system can include some or all of the hardware 3722 described herein, and the hardware 3722 can be distributed in any of a variety of ways included within a device, as and located near a device within a local data center coupled to the facility and/or in the cloud 3826. In at least one embodiment, because the deployment system 3706 and associated applications or containers are created in software (e.g., as separate containerized instances of the applications), the behavior, operation, and configuration of the virtual instruments and the output generated by the virtual instruments can be modified or customized as needed without changing or altering the original output of the devices supported by the virtual instruments.

Fig. 40A includes an example data flow diagram of a virtual instrument supporting an ultrasound device in accordance with at least one embodiment. In at least one embodiment, the deployment pipeline 3810B may utilize one or more of the services 3720 of the system 3800. In at least one embodiment, the deployment pipeline 3810B and services 3720 may utilize the hardware 3722 of the system locally or in the cloud 3826. In one embodiment, although not shown, process 4000 may be facilitated by a pipeline manager 3812, an application orchestration system 3828, and/or a parallel computing platform 3830.

In at least one embodiment, the process 4000 can include receiving imaging data from an ultrasound device 4002. In at least one embodiment, may be stored on the PACS server in DICOM format (or other formats, e.g., RIS, CIS, REST compatible, RPC, raw, etc.) and may be received by the system 3800 for selection for processing by the deployment pipeline 3810 or for customization as virtual instruments (e.g., virtual ultrasound) for the ultrasound device 4002. In at least one embodiment, imaging data can be received directly from an imaging device (e.g., ultrasound device 4002) and processed through a virtual instrument. In at least one embodiment, a transducer or other signal converter communicatively coupled between the imaging device and the virtual instrument may convert signal data generated by the imaging device into image data that may be processed by the virtual instrument. In at least one embodiment, the raw data and/or image data may be applied to the DICOM reader 3906 to extract data for use by an application or container deploying the pipeline 3810B. In at least one embodiment, the DICOM reader 3906 can utilize the data enhancement library 4014 (e.g., DALI of NVIDIA) as a service 3720 (e.g., as one of the computing services 3816) to extract, resize, rescale, and/or otherwise prepare data for use by an application or container.

In at least one embodiment, once the data is prepared, a reconstruction 4006 application and/or container can be executed to reconstruct the data from the ultrasound device 4002 into an image file. In at least one embodiment, after or concurrent with the reconstruction 4006, a detection 4008 application and/or container can be executed for anomaly detection, object detection, feature detection, and/or other detection tasks related to the data. In at least one embodiment, the image file generated during reconstruction 4006 can be used during detection 4008 to identify anomalies, objects, features, and the like. In at least one embodiment, the detection 4008 application can utilize an inference engine 4016 (e.g., as one of AI services 3818) to perform inferences on the data to generate the detection. In at least one embodiment, the detection 4008 application can execute or invoke one or more machine learning models (e.g., from the training system 3704).

In at least one embodiment, once the reconstruction 4006 and/or the detection 4008 are complete, data output from these applications and/or containers can be used to generate a visualization 4010, such as a visualization 4012 (e.g., a grayscale output) displayed on a workstation or display terminal. In at least one embodiment, visualization may allow a technician or other user to visualize the results of the deployment line 3810B relative to the ultrasound device 4002. In at least one embodiment, the visualization 4010 (e.g., one of the visualization services 3820) can be executed by utilizing the rendering component 4018 of the system 3800. In at least one embodiment, the rendering component 4018 can execute 2D, OpenGL or a ray tracing service to generate the visualization 4012.

Fig. 40B includes an example data flow diagram of a virtual instrument supporting a CT scanner in accordance with at least one embodiment. In at least one embodiment, the deployment pipeline 3810C may utilize one or more of the services 3720 of the system 3800. In at least one embodiment, the deployment pipeline 3810C and services 3720 may utilize the hardware 3722 of the system locally or in the cloud 3826. In at least one embodiment, although not shown, process 4020 may be facilitated by a pipeline manager 3812, an application orchestration system 3828, and/or a parallel computing platform 3830.

In at least one embodiment, the process 4020 may include a CT scanner 4022 generating raw data, which may be received by the DICOM reader 3906 (e.g., directly via the PACS server 3904 after processing, etc.). In at least one embodiment, the virtual CT (instantiated by the deployment pipeline 3810C) can include a first real-time pipeline for monitoring a patient (e.g., patient motion detection AI 4026) and/or for adjusting or optimizing exposure of the CT scanner 4022. (e.g., using exposure control AI 4024). In at least one embodiment, one or more applications (e.g., 4024 and 4026) may utilize a service 3720, such as an AI service 3818. In at least one embodiment, the output of the exposure control AI 4024 application (or container) and/or the patient motion detection AI 4026 application (or container) may be used as feedback to the CT scanner 4022 and/or a technician to adjust the exposure (or other settings of the CT scanner 4022) and/or to notify the patient to reduce motion.

In at least one embodiment, the deployment pipeline 3810C may comprise a non-real-time pipeline for analyzing data generated by the CT scanner 4022. In at least one embodiment, the second pipeline may include a CT reconstruction 3908 application and/or container, a coarse inspection AI 4028 application and/or container, a fine inspection AI 4032 application and/or container (e.g., where certain results are detected by the coarse inspection AI 4028), a visualization 4030 application and/or container, and a DICOM writer 3912 (and/or other data type writers, such as RIS, CIS, REST-compatible, RPC, pristine, etc.) application and/or container. In at least one embodiment, the raw data generated by the CT scanner 4022 may be passed through a pipeline (instantiated as a virtual CT instrument) of the deployment pipeline 3810C to generate results. In at least one embodiment, the results from the DICOM writer 3912 may be sent for display and/or may be stored on the PACS server 3904 for later retrieval, analysis, or display by a technician, practitioner, or other user.

Fig. 41A illustrates a data flow diagram of a process 4100 for training, retraining, or updating a machine learning model in accordance with at least one embodiment. In at least one embodiment, the process 4100 may be performed using the system 3800 of fig. 38 as a non-limiting example. In at least one embodiment, the process 4100 may utilize the services 3720 and/or hardware 3722 of the system 3800 described herein. In at least one embodiment, the improved model 4112 generated by the process 4100 can be executed by the deployment system 3706 for one or more containerized applications in the deployment pipeline 3810.

In at least one embodiment, model training 3714 can include retraining or updating the initial model 4104 (e.g., a pre-trained model) with new training data (e.g., new input data, such as the customer data set 4106 and/or new ground truth data associated with the input data). In at least one embodiment, to retrain or update the initial model 4104, the output or loss layers of the initial model 4104 can be reset or deleted and/or replaced with updated or new output or loss layers. In at least one embodiment, the initial model 4104 may have previously fine-tuned parameters (e.g., weights and/or biases) retained from previous training, so training or retraining 3714 may not take as long or as much processing as the training model starts from scratch. . In at least one embodiment, during model training 3714, by resetting or replacing the output or loss layer of the initial model 4104, parameters can be updated and readjusted for a new customer data set 4106 (e.g., image data 3708 of fig. 37) based on a loss layer in prediction with respect to the accuracy of the output calculated or generated.

In at least one embodiment, the pre-trained models 3806 may be stored in a data store or registry (e.g., model registry 3724 of FIG. 37). In at least one embodiment, the pre-training model 3806 may have been trained, at least in part, at one or more facilities other than the facility performing process 4100. In at least one embodiment, pre-trained model 3806 may have been trained using customer or patient data generated at the on-premise deployment in order to protect the patient, subject, or customer of a different facility. In at least one embodiment, the pre-trained model 3806 may be trained using the cloud 3826 and/or other hardware 3722, but confidential, privacy-protected patient data may not be communicated to, used by, or accessible to any component of the cloud 3826 (other non-native hardware). In at least one embodiment, where the pre-training model 3806 is trained using patient data from more than one facility, the pre-training model 3806 may be trained separately for each facility prior to training patient or customer data from another facility. In at least one embodiment, customer or patient data from any number of facilities may be used to train the pre-trained model 3806, for example, in a locally deployed and/or standby facility in a data center or other cloud computing infrastructure, such as where the customer or patient data has issued privacy concerns (e.g., by abandonment, for experimental use, etc.), or where the customer or patient data is contained in a public data set.

In at least one embodiment, when selecting an application for use in the deployment pipeline 3810, the user may also select a machine learning model to be used for the particular application. In at least one embodiment, the user may not have a model to use, so the user may select a pre-trained model 3806 to use with the application. In at least one embodiment, the unoptimized pre-training model 3806 is optimized to generate accurate results on the customer data set 4106 of the user facility (e.g., based on patient diversity, demographics, type of medical imaging device used, etc.). In at least one embodiment, the pre-trained models 3806 may be updated, retrained, and/or fine-tuned for the respective facility prior to deployment of the pre-trained models 3806 into the deployment pipeline 3810 for use with one or more applications. .

In at least one embodiment, the user may select pre-trained models 3806 to be updated, retrained, and/or fine-tuned, and the pre-trained models 3806 may be referred to as initial model 4104 data for the training system 3704 in the process 4100. In at least one embodiment, the customer data set 4106 (e.g., imaging data, genomic data, sequencing data, or other data types generated by devices in the facility) may be used to perform model training 3714 (which may include, but is not limited to, transfer learning) on the initial model 4104 to generate the refined model 4112. In at least one embodiment, ground truth data corresponding to the customer data set 4106 can be generated by the training system 3704. In at least one embodiment, ground truth data may be generated in a facility at least in part by a clinician, scientist, doctor, or practitioner. (e.g., clinical data 3712 as labeled in figure 37).

In at least one embodiment, AI assist annotations 3710 may be used in some examples to generate ground truth data. In at least one embodiment, the AI-assist annotation 3710 (e.g., implemented using the AI-assist annotation SDK) can utilize a machine learning model (e.g., a neural network) to generate suggested or predicted ground truth data for the client data set. In at least one embodiment, the user 4110 can use an annotation tool within a user interface (graphical user interface (GUI)) on the computing device 4108.

In at least one embodiment, the user 4110 can interact with the GUI via the computing device 4108 to edit or fine tune the annotation or to automatically annotate. In at least one embodiment, the polygon editing feature may be used to move the vertices of the polygon to more precise or fine-tuned locations.

In at least one embodiment, once the client data set 4106 has associated ground truth data, the ground truth data (e.g., from AI-assisted annotations, manual tagging, etc.) can be used during model training 3714 to generate the refining model 4112. In at least one embodiment, the customer data set 4106 may be applied to the initial model 4104 multiple times, and the ground truth data may be used to update the parameters of the initial model 4104 until an acceptable level of accuracy is reached for the refined model 4112. In at least one embodiment, once the refinement model 4112 is generated, the refinement model 4112 may be deployed within one or more deployment pipelines 3810 at a facility for performing one or more processing tasks on the medical imaging data.

In at least one embodiment, the refinement model 4112 may be uploaded to the pre-trained model 3806 in the model registry 3724 for selection by another facility. In at least one embodiment, his process may be completed at any number of facilities, such that the refined model 4112 may be further refined any number of times over the new data set to generate a more general model.

Fig. 41B is an example illustration of a client-server architecture 4132 for enhancing annotation tools with pre-trained annotation models, in accordance with at least one embodiment. In at least one embodiment, the AI-assisted annotation tool 4136 can be instantiated based on the client-server architecture 4132. In at least one embodiment, the annotation tool 4136 in the imaging application can assist the radiologist, for example, in identifying organs and abnormalities. In at least one embodiment, the imaging application may include a software tool that assists the user 4110 in identifying some extreme points on a particular organ of interest of the raw image 4134 (e.g., in a 3D MRI or CT scan), and receiving automatic annotation results of all 2D slices of the particular organ, as non-limiting examples. In at least one embodiment, the results may be stored in a data store as training data 4138 and used as, for example and without limitation, ground truth data for training. In at least one embodiment, when the computing device 4108 sends the limit points for the AI assist annotation 3710, the deep learning model can, for example, receive this data as input and return an inference result of segmenting the organ or anomaly. In at least one embodiment, a pre-instantiated annotation tool (e.g., AI-assisted annotation tool 4136B in fig. 41) can be enhanced by making API calls (e.g., API calls 4144) to a server, such as annotation assist server 4140, which can include a set of pre-trained models 4142 stored in an annotation model registry, for example. In at least one embodiment, the annotation model registry can store a pre-trained model 4142 (e.g., a machine learning model, such as a deep learning model) that is pre-trained to perform AI-assisted annotation on a particular organ or anomaly. In at least one embodiment, these models can be further updated through the use of training pipeline 3804. In at least one embodiment, the pre-installed annotation tools can be improved over time as new tagged clinical data 3712 is added.

At least one embodiment of the present disclosure may be described according to the following clauses:

1. a computer-implemented method, comprising: moving the robot into an area controlled using a first method of the physical model based at least in part on information from the first perception system; determining an uncertainty of the information produced by the first perception system; determining that the robot is in the area based at least in part on the uncertainty; as a result of determining that the robot is in the area, the robot is moved to perform a task under control of a second method using information generated by a second perception system.

2. The method of clause 1, wherein the second method is independent of the physical model.

3. The method of clause 2, wherein the second method is a modeless method.

4. The method of any of clauses 1-3, wherein the first method is a model-based method.

5. The method of any of clauses 1-4, wherein: the first perception system is a stationary camera; and the second perception system is a camera mounted on the robot.

6. The method of any of clauses 1-5, further comprising determining the region based at least in part on the uncertainty of the information.

7. The method of any of clauses 1-6, further comprising: determining that the robot is outside the area; and as a result of determining that the robot is outside the area, moving the robot into the area using the first method.

8. The method of any of clauses 1-7, wherein the uncertainty is a non-parametric distribution of a plurality of gestures of the region and an associated weight for each gesture.

9. The method of any of clauses 1-8, wherein the uncertainty is a parameter distribution.

10. The method of any of clauses 1-9, wherein the area is a sub-area of an area in which the second method is available to compete for tasks.

11. The method of any of clauses 1 to 10, wherein the second method is performed using a self-encoder trained to accomplish a given task of input from the second perceptual system.

12. A computer system, comprising: one or more processors; and a computer-readable memory storing executable instructions that, as a result of being executed by one or more processors, cause the computer system to: moving the robot to an area using a model of the robot environment, the model being located using image data from the first camera; determining an uncertainty of the model using uncertainty information associated with the first camera; determining that the robot is in the region based at least in part on an uncertainty of the model; and performing a task using the robot under control of a machine learning system trained using image data from the second camera as a result of determining that the robot is in the area.

13. The computer system of clause 12, wherein the second camera is a wrist camera on the robot.

14. The computer system of clause 12 or 13, wherein the computer system uses the results of the task to update the uncertainty of the model as a result of completing the task.

15. The computer system of clause 14, wherein the result of the task indicates a pose of the model.

16. The computer system of any of clauses 12-15, wherein the model is oriented by processing at least the image data from the first camera using a deep object pose estimator.

17. The computer system of any of clauses 12-16, wherein the first camera and the second camera are different cameras.

18. The computer system of any of clauses 12-17, wherein the image data from the first camera is used to generate a plurality of possible gestures consistent with the image data from the first camera.

19. The computer system of any of clauses 12-18, wherein the robot is moved to the area using a model-based controller that uses a target attractor defined by a motion strategy of the robot.

20. A computer-readable medium storing executable instructions that, as a result of being executed on one or more processors of a computer system, cause the computer system to at least: moving the robot into the area under control of a model-based approach using a physical model that is oriented using information from a first perception system; determining an uncertainty of information produced by the first perception system; determining that the robot is within the area based at least in part on the uncertainty; and directing the robot to perform the task under control of a second method based on information generated by a second perception system as a result of determining that the robot is in the area.

21. The computer-readable medium of clause 20, wherein: the first perception system is a stationary camera; and the second perception system is a camera moving with the robot.

22. The computer readable medium of clause 20 or 21, wherein the size of the area is determined based at least in part on an uncertainty of information produced by the first perception system.

23. The computer-readable medium of any of clauses 20-22, wherein the uncertainty of the information produced by the first perception system is determined as a distribution of a plurality of poses of the area.

24. The computer readable medium of any of clauses 20 to 23, wherein the executable instructions further cause the computer system to: determining that the robot is outside the area; and as a result of determining that the robot is outside the area, moving the robot into the area using the model-based approach.

25. The computer readable medium of any of clauses 20-24, wherein the second method is a model-free method implemented using a machine learning model trained with input from the second perception system.

26. The computer readable medium of clause 25, wherein the input comprises a simulated image generated by a simulation of the task.

27. The computer readable medium of any of clauses 20-26, wherein the task is controlling an autonomous vehicle.

28. A processor, comprising: one or more Arithmetic Logic Units (ALUs) to perform tasks by at least: moving the robot to the area using a model of the robot environment, the model using image data from the first camera for orientation; determining an uncertainty of the model using uncertainty information associated with the first camera; determining that the robot is in the region based at least in part on an uncertainty of the model; and performing a task using the robot under control of a machine learning system trained using image data from the second camera as a result of determining that the robot is in the area.

29. The processor of clause 28, wherein the second camera provides a hand view of an object to be manipulated by the robot.

30. The processor of clause 28 or 29, wherein the computer system uses the results of the task to reduce the uncertainty of the model.

31. The processor of any of clauses 28 to 30, wherein the information collected as a result of completing the task is used to obtain an improved pose of the model.

32. The processor of any of clauses 28 to 31, wherein the first camera and the second camera are different cameras.

33. The processor of any of clauses 28 to 32, wherein the image data from the first camera is used to generate a plurality of possible gestures consistent with the image data from the first camera.

In at least one embodiment, a single semiconductor platform may refer to a unique single semiconductor-based integrated circuit or chip. In at least one embodiment, a multi-chip module with increased connectivity may be used that simulates on-chip operations and is a substantial improvement over utilizing a conventional central processing unit ("CPU") and bus implementation. In at least one embodiment, the various modules may also be placed separately or in various combinations of semiconductor platforms, depending on the needs of the user.

In at least one embodiment, referring back to FIG. 14, computer programs in the form of machine-readable executable code or computer control logic algorithms are stored in main memory 1404 and/or secondary memory. The computer programs, if executed by one or more processors, enable system 1400 to perform various functions in accordance with at least one embodiment. In at least one embodiment, memory 1404, storage, and/or any other storage are possible examples of computer-readable media. In at least one embodiment, secondary memory may refer to any suitable storage device or system, such as a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, an optical disk drive, a digital versatile disk ("DVD") drive, a recording device, a universal serial bus ("USB") flash memory, and so forth. In at least one embodiment, the architecture and/or functionality of the various previous figures is implemented in the context of CPU 1402, parallel processing system 1412, an integrated circuit that is part of the capabilities of at least two CPUs 1402, parallel processing system 1412, a chipset (e.g., a set of integrated circuits designed to operate and sold as a unit to perform the relevant function, etc.), and/or any suitable combination of integrated circuits.

In at least one embodiment, the architecture and/or functionality of the various previous figures is implemented in the context of a general purpose computer system, a circuit board system, a game console system dedicated for entertainment purposes, a dedicated system, or the like. In at least one embodiment, the computer system 1400 may take the form of a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld), personal digital assistant ("PDA", digital camera, vehicle, head mounted display, handheld electronic device, mobile phone device, television, workstation, gaming console, embedded system, and/or any other type of logic.

In at least one embodiment, parallel processing system 1412 includes, but is not limited to, a plurality of parallel processing units ("PPUs") 1414 and an associated memory 1416. In at least one embodiment, PPU1414 is connected to a host processor or other peripheral device through interconnect 1418 and switch 1420 or a multiplexer. In at least one embodiment, parallel processing system 1412 distributes computing tasks across parallelizable PPUs 1414, e.g., as part of a computing task distribution across multiple graphics processing unit ("GPU") thread blocks. In at least one embodiment, although memory is shared and accessed (e.g., for read and/or write access) among some or all of PPUs 1414, such shared memory may incur performance penalties relative to using local memory and registers resident on PPUs 1414. In at least one embodiment, the operations of PPU1414 are synchronized by using commands such as __ synchreads (), where all threads in a block (e.g., executing across multiple PPUs 2114) continue after reaching a certain code execution point.

Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the invention to the specific forms or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the invention, as defined by the appended claims.

The use of the terms "a" and "an" and "the" and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, and not as a definition of the term, unless otherwise indicated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "containing" are to be construed as open-ended terms (i.e., meaning "including, but not limited to,") unless otherwise noted. The term "connected" (unmodified and referring to physical connection), should be understood to be wholly or partially encompassed, attached, or connected together, even if something intervenes. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. In at least one embodiment, the use of the term "set" (e.g., "set of items") or "subset" should be interpreted as a non-empty set comprising one or more members, unless the context indicates otherwise or contradicts it. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a respective set does not necessarily denote a proper subset of the respective set, but the subset and the respective set may be equal.

Conjunctive language, such as phrases in the form of "at least one of A, B and C" or "at least one of A, B and C," unless expressly stated otherwise or clearly contradicted by context, may be understood as commonly used with context to present items, terms, etc., either A or B or C, or any non-empty subset of a collection of A and B and C. For example, in an illustrative example of a set having three members, the conjunctive phrases "at least one of A, B and C" and "at least one of A, B, and C" refer to any of the following sets: { A }, { B }, { C }, { A, B }, { A, C }, { B, C }, and { A, B, C }. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one A, at least one B, and at least one C, each for presentation. In addition, the term "plurality" means the state of a plurality (e.g., "a plurality of items" means a plurality of items) unless otherwise stated or contradicted by context. In at least one embodiment, the number of items in the "plurality" is at least two, but can be more when explicitly or by context. Further, the phrase "based on" means "based at least in part on" rather than "based only on" unless otherwise indicated herein or otherwise clear from the context.

The operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In one embodiment, processes such as those described herein (or variations and/or combinations thereof) are performed by hardware or combinations thereof under control of one or more computer systems configured with executable instructions and implemented as code (e.g., executable instructions, one or more computer programs, or one or more application programs) that are executed collectively on one or more processors. In one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of instructions executable by one or more processors. In one embodiment, the computer-readable storage medium is a non-transitory computer-scale storage medium that does not include transitory signals (e.g., propagating transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues) within the transceiver of the transitory signals. In one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having executable instructions stored thereon (or other memory to store executable instructions) that, when executed by one or more processors of a computer system (e.g., as a result of being executed), cause the computer system to perform operations described herein. In one embodiment, the set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more individual ones of the plurality of non-transitory computer-readable storage media lack all of the code, while the plurality of non-transitory computer-readable storage media collectively store all of the code. In one embodiment, the executable instructions are executed such that different instructions are executed by different processors-e.g., a non-transitory computer readable storage medium stores instructions and the main CPU executes some instructions while the graphics processor unit executes other instructions. In one embodiment, different components of a computer system have independent processors, and different processors execute different subsets of instructions.

Thus, in one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such computer system is configured with suitable hardware and/or software that enables the performance of the operations. Further, a computer system that implements an embodiment of the disclosure is a single device, and in another embodiment is a distributed computer system that includes multiple devices that operate differently, such that the distributed computer system performs the operations described herein, and such that a single device does not perform all of the operations.

The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate embodiments of the invention and does not pose a limitation on the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.

All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

Unless specifically stated otherwise, it may be appreciated that throughout the description, terms such as "processing," "computing," "determining," or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulates and/or transforms data represented as physical (e.g., electronic) quantities within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices.

In a similar manner, the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory and converts that electronic data into other electronic data that may be stored in registers and/or memory. As a non-limiting example, a "processor" may be a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU). A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and/or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process may refer to a plurality of processes for executing instructions sequentially or in parallel, continuously or intermittently. In at least one embodiment, the terms "system" and "method" are used interchangeably herein to the extent that the system may embody one or more methods and the methods may be considered a system.

In this document, reference may be made to obtaining, acquiring, receiving, or entering analog or digital data into a subsystem, computer system, or computer-implemented machine. In at least one embodiment, the process of obtaining, receiving, or inputting analog and digital data may be accomplished in a number of ways, such as by receiving the data as parameters of a function call or a call to an application program interface. In some embodiments, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transmitting the data via a serial or parallel interface. In another embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transferring the data from the providing entity to the acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or rendering analog or digital data may be accomplished by transmitting the data as input or output parameters of a function call, parameters of an application programming interface, or an interprocess communication mechanism.

While the above discussion sets forth example implementations of the described techniques, other architectures can be used for implementing the described functionality, and are intended to be within the scope of the present disclosure. Further, although a particular allocation of responsibilities is defined above for discussion purposes, the various functions and responsibilities may be allocated and divided in different ways, depending on the circumstances.

Furthermore, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

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