阅读说明：本技术 半导体存储器装置、控制器、存储器系统及其操作方法 (Semiconductor memory device, controller, memory system and operating method thereof ) 是由 金珍燮 于 2020-10-15 设计创作，主要内容包括：本技术包括一种操作控制器的方法,该控制器控制包括多个存储块的半导体存储器装置。该方法包括：从主机接收针对多个存储块之中的任意一个存储块中包括的数据的读取请求；并且控制半导体存储器装置以使用读取历史表读取与该读取请求相对应的数据。该读取历史表包括分别用于针对该任意一个存储块的多个读取通过操作的读取电压。(The present technology includes a method of operating a controller that controls a semiconductor memory device including a plurality of memory blocks. The method comprises the following steps: receiving a read request for data included in any one of a plurality of memory blocks from a host; and controls the semiconductor memory apparatus to read data corresponding to the read request using the read history table. The read history table includes read voltages respectively used for a plurality of read pass operations for the arbitrary one of the memory blocks.)

1. A method of operating a controller that controls a semiconductor memory device including a plurality of memory blocks, the method comprising:

receiving a read request from a host for data in a selected memory block among the plurality of memory blocks; and is

Controlling the semiconductor memory device to read data corresponding to the read request using a read history table.

Wherein the read history table includes read voltages used in previous successful read operations to the selected memory block.

2. The method of claim 1, wherein controlling the semiconductor memory device to read data corresponding to the read request using the read history table comprises:

generating a first read command corresponding to the read request and transmitting the first read command to the semiconductor memory device;

determining whether a first error correction failure occurs for read data corresponding to the first read command; and is

When the first error correction failure occurs, a first read voltage for a first read operation among the plurality of read voltages in the read history table is determined as a read voltage to be used for a next read operation, the first read operation being a most recently successful read operation.

3. The method of claim 2, wherein controlling the semiconductor memory device to read data corresponding to the read request using the read history table further comprises:

transferring a set parameter command corresponding to the first read voltage to the semiconductor memory device; and is

A second read command corresponding to the read request is generated and transmitted to the semiconductor memory device.

4. The method of claim 3, wherein controlling the semiconductor memory device to read data corresponding to the read request using the read history table further comprises:

determining whether a second error correction failure occurs for read data corresponding to the second read command; and is

When the second error correction failure occurs, determining a second read voltage for a second read operation, which is a second most recently successful read operation, among the plurality of read voltages in the read history table as a read voltage to be used for a next read operation.

5. A method of operating a controller that controls a semiconductor memory device including a plurality of memory blocks, the method comprising:

receiving a read request for data included in a selected memory block among the plurality of memory blocks from a host;

controlling the semiconductor memory device to read data corresponding to the read request using a read history table; and is

Controlling the semiconductor memory device to perform a read operation using an additional read method when error correction of read data using the read history table fails, and updating the read history table according to a result of the read operation using the additional read method,

wherein the read history table includes read voltages used in a previous successful read pass operation on the selected memory block.

6. The method of claim 5, wherein controlling the semiconductor memory device to perform the read operation and update the read history table using the additional read method comprises: controlling the read operation of the semiconductor memory device using a read retry table.

7. The method of claim 6, wherein controlling the read operation of the semiconductor memory device using the read retry table comprises:

controlling the read operation of the semiconductor memory device using a first read voltage selected from a plurality of read voltages in the read retry table; and is

Controlling the read operation of the semiconductor memory device using a second read voltage selected from the plurality of read voltages in the read retry table when error correction of read data using the first read voltage fails.

8. The method of claim 6, wherein controlling the read operation of the semiconductor memory device using the read retry table comprises:

controlling the read operation of the semiconductor memory device using a first read voltage selected from a plurality of read voltages in the read retry table; and is

When error correction of read data using the first read voltage is successful, the read history table is updated based on the first read voltage.

9. The method of claim 5, wherein controlling the semiconductor memory device to perform the read operation and update the read history table using the additional read method comprises: the read operation of the semiconductor memory device is controlled using an optimal read voltage search method.

10. The method of claim 9, wherein controlling the read operation of the semiconductor memory device using the optimal read voltage search method comprises:

controlling the semiconductor memory device to repeatedly perform a read operation using a plurality of reference read voltages, respectively, to generate a plurality of read results;

determining an optimal read voltage based on the plurality of read results received from the semiconductor memory device; and is

Controlling the semiconductor memory device to perform a read operation based on the optimal read voltage.

11. The method of claim 10, wherein controlling the read operation of the semiconductor memory device using the optimal read voltage search method comprises: when error correction of read data using the optimal read voltage is successful, the read history table is updated based on the optimal read voltage.

12. The method of claim 5, wherein controlling the semiconductor memory device to read data corresponding to the read request using the read history table comprises:

generating a first read command corresponding to the read request and transmitting the first read command to the semiconductor memory device;

determining whether a first error correction failure occurs for read data corresponding to the first read command; and is

When the first error correction failure occurs, a first read voltage for a first read operation among the plurality of read voltages in the read history table is determined as a read voltage to be used for a next read operation, the first read operation being a most recently successful read operation.

13. A controller that controls a semiconductor memory device including a plurality of memory blocks, the controller comprising:

a read history table storage device that stores a read history table including a first read voltage and a second read voltage for a first read pass operation and a second read pass operation, respectively, for a selected memory block among the plurality of memory blocks;

a read voltage controller adjusting a read voltage for a read operation of the semiconductor memory device based on the read history table; and

an error correction block performing an error correction operation on first data received from the semiconductor memory device and corresponding to a read request received from a host;

wherein the read voltage controller controls the semiconductor memory device to select the most recently updated first read voltage from among the first read voltage and the second read voltage and to perform the read operation corresponding to the read request based on the first read voltage when the error correction operation for the first data fails.

14. The controller according to claim 13, wherein the controller is a microprocessor,

wherein the error correction block further: performing an error correction operation on second data provided from the semiconductor memory device as a result of the read operation based on the first read voltage, and

wherein the read voltage controller controls the semiconductor memory device to select the second read voltage updated before the first read voltage and perform the read operation corresponding to the read request based on the second read voltage when the error correction operation for the second data fails.

15. The controller of claim 14, further comprising:

a read retry table storage device that stores a read retry table,

wherein the error correction block further: performing an error correction operation on third data provided from the semiconductor memory device as a result of the read operation based on the second read voltage, and

wherein the read voltage controller controls the semiconductor memory device to perform the read operation corresponding to the read request based on a third read voltage among a plurality of read voltages in the read retry table when the error correction operation for the third data fails.

16. The controller according to claim 15, wherein the controller is a microprocessor,

wherein the error correction block further: performing an error correction operation on fourth data provided from the semiconductor memory device as a result of the read operation based on the third read voltage, and

wherein the read voltage controller further updates the third read voltage into the read history table when the error correction operation for the fourth data is successful.

17. The controller of claim 14, further comprising:

an optimal read voltage search component that searches for a valley of the threshold voltage distribution based on a plurality of reference read voltages,

wherein the error correction block further: performing an error correction operation on third data provided from the semiconductor memory device as a result of the read operation based on the second read voltage, and

wherein the read voltage controller controls the semiconductor memory device to perform the read operation corresponding to the read request based on an optimal read voltage corresponding to the valley searched by the optimal read voltage search component when the error correction operation for the third data fails.

18. The controller as set forth in claim 17, wherein,

wherein the error correction block further: performing an error correction operation on fourth data provided from the semiconductor memory device as a result of the read operation based on the optimal read voltage, and

wherein the read voltage controller further updates the optimal read voltage into the read history table when the error correction operation for the fourth data is successful.

19. A method of operation of a controller, the method of operation comprising:

controlling a memory device to perform a first read operation of reading data a plurality of times with a plurality of most recently successful read voltages, respectively, the plurality of most recently successful read voltages being maintained in a group;

controlling the memory device to perform a second read operation when the first read operation fails, the data being read with a read voltage different from each of the most recently successful read voltages; and is

When the first read operation or the second read operation is successful, updating the group according to a successful read voltage of the first read operation or the second read operation.

Technical Field

The present disclosure relates to an electronic device, and more particularly, to a semiconductor memory device, a controller, and a method of operating a memory system including the semiconductor memory device and the controller.

Background

The semiconductor memory device may be formed in a two-dimensional structure in which strings are horizontally arranged on a semiconductor substrate, or in a three-dimensional structure in which strings are vertically stacked on a semiconductor substrate. Three-dimensional memory devices are designed to overcome the integration limitations of two-dimensional memory devices and, thus, may include multiple memory cells vertically stacked on a semiconductor substrate.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor memory device having improved read performance, a controller, and a method of operating a memory system including the semiconductor memory device and the controller.

A semiconductor memory device including a plurality of memory blocks may be controlled by a method of operating a controller according to an embodiment of the present disclosure. The method comprises the following steps: receiving a read request from a host for data in a selected memory block among a plurality of memory blocks; and controls the semiconductor memory apparatus to read data corresponding to the read request using the read history table. The read history table includes read voltages used in previous successful read operations for the selected memory block.

A semiconductor memory device including a plurality of memory blocks may be controlled by a method of operating a controller according to an embodiment of the present disclosure. The method comprises the following steps: receiving a read request for data included in a selected memory block among the plurality of memory blocks from the host, controlling the semiconductor memory device to read data corresponding to the read request using the read history table, and controlling the semiconductor memory device to perform a read operation using an additional read method, and when error correction of the read data using the read history table fails, updating the read history table according to a result of the read operation using the additional read method. The read history table includes read voltages used in previous successful read pass operations for the selected memory block.

In an embodiment, controlling the semiconductor memory apparatus to perform the read operation using the additional read method and updating the read history table may include controlling the read operation of the semiconductor memory apparatus using the read retry table.

In an embodiment, controlling the semiconductor memory apparatus to perform the read operation using the additional read method and updating the read history table may include controlling the read operation of the semiconductor memory apparatus using the optimal read voltage search method.

A controller according to an embodiment of the present disclosure controls a semiconductor memory device including a plurality of memory blocks. The controller includes a read history table storage, a read voltage controller, and an error correction block. The read history table storage stores a read history table including a first read voltage and a second read voltage for a first read pass operation and a second read pass operation, respectively, for a selected memory block among the plurality of memory blocks. The read voltage controller adjusts a read voltage for a read operation of the semiconductor memory device based on the read history table. The error correction block performs an error correction operation on first data received from the semiconductor memory device and corresponding to a read request received from a host. When the error correction operation on the first data fails, the read voltage controller controls the semiconductor memory device to select a most recently updated first read voltage from among the first read voltage and the second read voltage, and performs a read operation corresponding to a read request based on the first read voltage.

A method of operation of a controller comprising: the memory device is controlled to perform a first read operation to read data multiple times using multiple most recently successful read voltages, respectively. A number of most recently successful read voltages are maintained in the group. The method of operation further comprises: the method includes controlling the memory device to perform a second read operation when the first read operation fails, reading data using a read voltage different from each of the most recently successful read voltages, and updating the group according to a successful read voltage of the first read operation or the second read operation when the first read operation succeeds or the second read operation succeeds.

The present technology can improve the read performance of a semiconductor memory device, a controller, and a memory system including the semiconductor memory device and the controller.

Drawings

Fig. 1 is a block diagram illustrating a memory system including a controller according to an embodiment of the present disclosure.

Fig. 2 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

FIG. 3 is a diagram illustrating an embodiment of the memory cell array of FIG. 2.

Fig. 4 is a circuit diagram illustrating any one of the memory blocks BLK1 through BLKz of fig. 3.

Fig. 5 is a circuit diagram illustrating another embodiment of any one of the memory blocks BLK1 through BLKz of fig. 3.

Fig. 6 is a circuit diagram illustrating an embodiment of any one of the memory blocks BLK1 through BLKz of the memory cell array of fig. 2.

Fig. 7 is a flowchart illustrating a method of operating a controller according to an embodiment.

FIG. 8 is a flow chart illustrating the method of operation of FIG. 7 in greater detail.

Fig. 9A, 9B, and 9C are diagrams for describing an embodiment of performing a read operation with reference to a Read History Table (RHT) for a memory block including a single-level cell (SLC).

Fig. 10 is a block diagram illustrating a memory system including a controller according to another embodiment of the present disclosure.

FIG. 11 is a flow chart illustrating a method of operating a controller according to the embodiment of FIG. 10.

FIG. 12 is a flow chart illustrating the method of operation of FIG. 11 in greater detail.

Fig. 13A, 13B, 13C, and 13D are diagrams exemplarily describing update of the RHT.

Fig. 14 is a block diagram illustrating a memory system including a controller according to yet another embodiment of the present disclosure.

Fig. 15 is a flowchart illustrating a method of operating a controller according to the embodiment of fig. 14.

FIG. 16 is a flow chart illustrating the method of operation of FIG. 15 in greater detail.

Fig. 17 is a diagram for describing steps S315 and S325 of fig. 16.

Fig. 18A is a block diagram illustrating a memory system including a controller according to yet another embodiment of the present disclosure.

FIG. 18B is a flow diagram illustrating a method of operating a controller according to the embodiment of FIG. 18A.

Fig. 19A, 19B, and 19C are diagrams illustrating RHTs according to embodiments of the present disclosure.

Fig. 20 is a diagram for describing the RHT shown in fig. 19C.

Fig. 21 is a diagram illustrating threshold voltage distributions of multi-level cells (MLCs).

Fig. 22 is a diagram showing an example of an RHT for a memory block including MLCs.

Fig. 23 is a block diagram illustrating a memory system including the controller of fig. 1, 10, 14, or 18A.

Fig. 24 is a block diagram showing an application example of the memory system of fig. 23.

Fig. 25 is a block diagram illustrating a computing system including the memory system described with reference to fig. 24.

Detailed Description

The specific structural and functional descriptions are provided only to describe embodiments of the present disclosure. However, the present invention may be embodied in various forms and may be configured in various forms. Thus, the present invention is not limited to any of the disclosed embodiments, nor to any of the specific details provided herein. Moreover, references throughout this specification to "an embodiment," "another embodiment," etc., do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment. The term "embodiments" as used herein does not necessarily refer to all embodiments.

Fig. 1 is a block diagram illustrating a memory system including a controller according to an embodiment of the present disclosure.

Referring to fig. 1, a memory system 1000 includes a semiconductor memory device 100 and a controller 200. In addition, the memory system 1000 communicates with a host. Each of the semiconductor memory device 100 and the controller 200 may be provided as one chip, one package, and/or one device. Alternatively, the memory system 1000 may be provided as one memory device.

The controller 200 controls the overall operation of the semiconductor memory device 100. In addition, the controller 200 controls the operation of the semiconductor memory device 100 based on a command received from a host.

The semiconductor memory device 100 operates in response to control of the controller 200. The semiconductor memory device 100 includes a memory cell array having a plurality of memory blocks. In an embodiment, the semiconductor memory device 100 may be a flash memory device.

The controller 200 may receive a write request, a read request, and the like from a host, and control the semiconductor memory apparatus 100 based on the received request. More specifically, the controller 200 may generate a command for controlling the operation of the semiconductor memory apparatus 100 and transmit the command to the semiconductor memory apparatus 100.

The semiconductor memory apparatus 100 is configured to receive a command and an address from the controller 200 and access a region selected by the address in the memory cell array. That is, the semiconductor memory device 100 performs an internal operation corresponding to a command on an area selected by an address.

For example, the semiconductor memory device 100 may perform a program operation, a read operation, and an erase operation. During a programming operation, the semiconductor memory device 100 may program data in a region selected by an address. During a read operation, the semiconductor memory device 100 may read data from an area selected by an address. During an erase operation, the memory device 100 may erase data stored in an area selected by an address.

Controller 200 includes a read voltage controller 210, an error correction block 230, and a Read History Table (RHT) storage 250.

The read voltage controller 210 may manage and adjust a read voltage for reading data stored in the semiconductor memory device 100. For example, when data read from the semiconductor memory device 100 is not corrected by the error correction block 230, the read voltage controller 210 may adjust at least one read voltage for a read operation of the semiconductor memory device 100. According to the present disclosure, the read voltage controller 210 may adjust a read voltage for a read operation of the semiconductor memory device 100 based on the RHT stored in the RHT storage device 250.

The error correction block 230 is configured to detect and correct an error of data received from the semiconductor memory apparatus 100 by using an Error Correction Code (ECC). The read voltage controller 210 may control the read voltage according to the error detection result of the error correction block 230, and may control the semiconductor memory apparatus 100 to perform re-reading. For example, the error correction block 230 may generate an ECC for data to be stored in the semiconductor memory device 100. The generated ECC may be stored in the semiconductor memory apparatus 100 together with data. Thereafter, the error correction block 230 may detect and correct an error of data read from the semiconductor memory device 100 based on the stored ECC. For example, the error correction block 230 has a set error correction capability. Data including erroneous bits (or failed bits) that exceed the error correction capability of the error correction block 230 is referred to as "uncorrectable ecc (uecc) data". When the data read from the semiconductor memory apparatus 100 is UECC data, the read voltage controller 210 may control the semiconductor memory apparatus 100 to perform the read operation again by adjusting the read voltage.

The RHT storage device 250 may store the RHT. The RHT may include a read voltage used in a previous read operation. For example, the RHT may include information about the read voltage (read pass voltage) that was successful in the previous read operation. Such a read pass voltage may have been applied to normal data that does not include errors, or to data that has errors but is within the correction capabilities of error correction block 230.

When data read from the semiconductor memory device 100 is not corrected by the error correction block 230, the read voltage controller 210 may adjust a read voltage used in the semiconductor memory device 100. For example, the read voltage controller 210 may adjust the read voltage based on the RHT stored in the RHT storage device 250. That is, since the read level is adjusted based on the read voltage of the previous read pass and the data is read using the adjusted read level, the probability that an error of the read data can be corrected by the error correction block 230 may increase.

In accordance with the present disclosure, the RHT stored in the RHT storage device 250 includes read voltages used in previous successful read operations, each of which is sequentially added to the RHT. That is, the RHT according to the present disclosure includes a read voltage used in a most recent successful read operation and a read voltage used in an immediately previous successful read operation. Thus, the RHT may store read voltages used in read operations of at least two read passes in the order in which the read operations are performed. During a read operation, when UECC data is repeatedly received from the semiconductor memory device 100, i.e., whenever the error correction block 230 repeatedly fails to correct an error in read data received from the semiconductor memory device 100, the read voltage controller 210 adjusts the read voltage of the semiconductor memory device 100 with reference to the read voltages stored in the RHT in time-based order. For example, when an error correction failure occurs for read data received from the semiconductor memory apparatus 100, the read voltage controller 210 sets a read voltage used in a read operation of a most recent read pass among the voltages of the RHT as the read voltage of the semiconductor memory apparatus 100. The semiconductor memory device 100 performs the read operation again based on the set read voltage. Thereafter, if and when error correction of read data received from the semiconductor memory apparatus 100 using the voltage of the most recent read pass fails, the read voltage controller 210 sets a read voltage used in a read pass read operation preceding the read pass read operation of the most recent read pass, among the voltages of the RHT, as the read voltage of the semiconductor memory apparatus 100.

That is, according to the controller 200 according to the embodiment of the present disclosure, when error correction failure repeatedly occurs for the same data, the read voltage of the semiconductor memory device 100 is adjusted by sequentially applying the read voltages used in the read operation of the previous read pass from the voltage of the most recent read pass. Thus, one or more read voltages used in a read operation of a previous read pass are applied, and thus the probability of successfully reading the current data is increased. Thus, the performance of the memory system 1000 is improved.

Fig. 2 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

Referring to fig. 2, the semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, a control logic 140, and a voltage generator 150.

The memory cell array 110 includes a plurality of memory blocks BLK1 through BLKz connected to the address decoder 120 through word lines WL. The plurality of memory blocks BLK1 through BLKz are connected to the read and write circuit 130 through bit lines BL1 through BLm. Each of the plurality of memory blocks BLK1 through BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells that may be configured with a vertical channel structure. The memory cell array 110 may be configured as a two-dimensional structure or a three-dimensional structure. Each of the plurality of memory cells in the memory cell array may store at least one bit of data. For example, each of the plurality of memory cells in the memory cell array 110 may be a single-layer cell (SLC) storing one bit of data, a multi-layer cell (MLC) storing two bits of data, a triple-layer cell storing three bits of data, or a quadruple-layer cell storing four bits of data. Still further, the memory cell array 110 may include a plurality of memory cells each storing five or more bits of data.

The address decoder 120, the read and write circuit 130, the control logic 140, and the voltage generator 150 operate as peripheral circuits that drive the memory cell array 110. The address decoder 120 is connected to the memory cell array 110 through word lines WL. Address decoder 120 is configured to operate in response to control by control logic 140. The address decoder 120 receives an address through an input/output buffer (not shown) inside the semiconductor memory device 100. When power is supplied to the semiconductor memory device 100, the peripheral circuit may read information stored in the CAM block, and the peripheral circuit may control the memory cell array to perform a data input/output operation of the memory cells under conditions set according to the read information.

The address decoder 120 is configured to decode a block address of the received addresses. The address decoder 120 selects at least one memory block according to the decoded block address. In addition, during the read operation, the address decoder 120 applies the read voltage Vread generated in the voltage generator 150 to the selected word line of the selected memory block and applies the pass voltage Vpass to the remaining unselected word lines at the time of the read voltage applying operation. In addition, during a program verify operation, the address decoder 120 applies a verify voltage generated in the voltage generator 150 to a selected word line of a selected memory block and applies a pass voltage Vpass to remaining unselected word lines.

The address decoder 120 is configured to decode a column address of the received address. The address decoder 120 transmits the decoded column address to the read and write circuit 130.

The read operation and the program operation for the semiconductor memory device 100 are performed in units of pages. The addresses received at the time of requesting the read operation and the program operation include a block address, a row address, and a column address. The address decoder 120 selects one memory block and one word line according to a block address and a row address. The column address is decoded by the address decoder 120 and supplied to the read and write circuit 130. In this specification, a memory cell connected to one word line may be referred to as a "physical page".

The address decoder 120 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

The read and write circuit 130 includes a plurality of page buffers PB1 through PBm. The read and write circuit 130 may operate as a "read circuit" during a read operation of the memory cell array 110 and may operate as a "write circuit" during a write operation of the memory cell array 110. The plurality of page buffers PB1 through PBm are coupled to the memory cell array 110 through bit lines BL1 through BLm. During a read operation and a program verify operation, in order to sense a threshold voltage of a memory cell, the plurality of page buffers PB1 to PBm sense a change in the amount of current flowing according to a program state of the corresponding memory cell through a sense node while continuously supplying a sense current to a bit line connected to the memory cell, and latch the sensed change as sense data. The read and write circuits 130 operate in response to page buffer control signals output from the control logic 140.

During a read operation, the read and write circuit 130 senses DATA of the memory cell, temporarily stores the read DATA, and outputs the DATA to an input/output buffer (not shown) of the semiconductor memory device 100. In an embodiment, the read and write circuit 130 may include a column selection circuit or the like in addition to a page buffer (or page register).

Control logic 140 is connected to address decoder 120, read and write circuits 130, and voltage generator 150. The control logic 140 receives a command CMD and a control signal CTRL through an input/output buffer (not shown) of the semiconductor memory device 100. The control logic 140 may be configured to control the overall operation of the semiconductor memory device 100 in response to the control signal CTRL. In addition, the control logic 140 outputs a control signal for adjusting the sense node precharge potential level of the plurality of page buffers PB1 through PBm. The control logic 140 may control the read and write circuits 130 to perform read operations of the memory cell array 110.

In response to the control signal output from the control logic 140, the voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation. To generate the plurality of voltages having various voltage levels, the voltage generator 150 may include a plurality of pumping capacitors that receive the internal power supply voltage, and generate the plurality of voltages by selectively activating the plurality of pumping capacitors in response to control of the control logic 140.

The address decoder 120, the read and write circuits 130, and the voltage generator 150 may be used to perform read operations, write operations, and erase operations on the memory cell array 110. These components perform read, write, and erase operations on the memory cell array 110 based on control by the control logic 140.

FIG. 3 is a diagram illustrating an embodiment of the memory cell array of FIG. 2.

Referring to fig. 3, the memory cell array 110 includes a plurality of memory blocks BLK1 through BLKz. Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such a plurality of memory cells are arranged in the + X direction, + Y direction, and + Z direction. The structure of each memory block is described in more detail with reference to fig. 4 and 5.

Fig. 4 is a circuit diagram illustrating any one of the memory blocks BLK1 through BLKz of fig. 2.

Referring to fig. 4, the memory block BLKa includes a plurality of cell strings CS11 through CS1m and CS21 through CS2 m. In an embodiment, each of the plurality of cell strings CS11 through CS1m and CS21 through CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged in the row direction (i.e., + X direction). In fig. 4, two cell strings are arranged in the column direction (i.e., + Y direction). However, this is for clarity; three or more cell strings may be arranged in the column direction.

Each of the plurality of cell strings CS11 through CS1m and CS21 through CS2m includes at least one source select transistor SST, first through nth memory cells MC1 through MCn, a pipe transistor PT, and at least one drain select transistor DST.

Each of the selection transistors SST and DST and the memory cells MC1 through MCn may have a similar structure. In an embodiment, each of the selection transistors SST and DST and the memory cells MC1 through MCn may include a channel layer, a tunneling insulation layer, a charge storage layer, and a blocking insulation layer. In an embodiment, a pillar for providing a channel layer may be provided in each cell string. According to an embodiment of the present disclosure, a pillar for providing at least one of a channel layer, a tunneling insulation layer, a charge storage layer, and a blocking insulation layer may be provided in each cell string.

The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

In the embodiment, the source selection transistors of the cell strings arranged in the same row are connected to a source selection line extending in the row direction, and the source selection transistors of the cell strings arranged in different rows are connected to different source selection lines. In fig. 4, the source select transistors of the cell strings CS11 to CS1m of the first row are connected to a first source select line SSL 1. The source select transistors of the cell strings CS21 to CS2m of the second row are connected to a second source select line SSL 2.

In another embodiment, the source select transistors of the cell strings CS11 through CS1m and the cell strings CS21 through CS2m may be commonly connected to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and (p +1) th to nth memory cells MCp +1 to MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in the-Z direction and are connected in series between the source select transistor SST and the tunnel transistor PT. The (p +1) th to nth memory cells MCp +1 to MCn are sequentially arranged in the + Z direction and are connected in series between the pipe transistor PT and the drain select transistor DST. The first to pth memory cells MC1 to MCp and the (p +1) th to nth memory cells MCp +1 to MCn are connected to each other through a pipe transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string are connected to the first to nth word lines WL1 to WLn, respectively.

The gate of the pipe transistor PT of each cell string is connected to the line PL.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp +1 to MCn. The cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m of the first row are connected to a first drain select line DSL 1. The drain select transistors of the cell strings CS21 to CS2m of the second row are connected to a second drain select line DSL 2.

The cell strings arranged in the column direction are connected to bit lines extending in the column direction. In fig. 4, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL 1. The cell strings CS1m and CS2m of the mth column are connected to the mth bit line BLm.

Memory cells connected to the same word line in cell strings arranged in the row direction configure one page. For example, memory cells connected to the first word line WL1 among the cell strings CS11 through CS1m of the first row constitute one page. Memory cells connected to the first word line WL1 among the cell strings CS21 through CS2m of the second row constitute another page. The cell strings arranged in one row direction may be selected by selecting any one of the drain select lines DSL1 and DSL 2. One page in the selected cell string may be selected by selecting any one of the word lines WL1 through WLn.

In another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11 to CS1m or the cell strings CS21 to CS2m arranged in the row direction may be connected to even bit lines, respectively, and odd-numbered cell strings among the cell strings CS11 to CS1m or the cell strings CS21 to CS2m arranged in the row direction may be connected to odd bit lines, respectively.

In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is disposed to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCp. Optionally, at least one dummy memory cell is disposed to reduce an electric field between the drain select transistor DST and the memory cells MCp +1 to MCn. As more dummy memory cells are disposed, the reliability of the operation of the memory block BLKa is improved, but the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa may be reduced, but the reliability of the operation for the memory block BLKa may be reduced.

In order to effectively control the dummy memory cells, each of the dummy memory cells may have a desired threshold voltage. Before or after the erase operation on the memory block BLKa, a program operation may be performed on all or some of the dummy memory cells. When an erase operation is performed after a program operation is performed, the dummy memory cells may have a desired threshold voltage by controlling voltages applied to dummy word lines connected to the respective dummy memory cells.

Fig. 5 is a circuit diagram illustrating another embodiment of any one of the memory blocks BLK1 through BLKz of fig. 3.

Referring to fig. 5, the memory block BLKb includes a plurality of cell strings CS11 'to CS1m' and CS21 'to CS2 m'. Each of the plurality of cell strings CS11 'to CS1m' and CS21 'to CS2m' extends in the + Z direction. Each of the plurality of cell strings CS11 'to CS1m' and CS21 'to CS2m' includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) under the memory block BLKb.

The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn. The source selection transistors of the cell strings arranged in the same row are connected to the same source selection line. The source selection transistors of the cell strings CS11 'to CS1m' arranged in the first row are connected to a first source selection line SSL 1. The source selection transistors of the cell strings CS21 'to CS2m' arranged in the second row are connected to a second source selection line SSL 2. In another embodiment, the source selection transistors of the cell strings CS11 'to CS1m' and CS21 'to CS2m' may be commonly connected to one source selection line.

The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first to nth memory cells MC1 to MCn are connected to the first to nth word lines WL1 to WLn, respectively.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 through MCn. The drain select transistors of the cell strings arranged in the row direction are connected to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 'to CS1m' of the first row are connected to a first drain select line DSL 1. The drain select transistors of the cell strings CS21 'to CS2m' of the second row are connected to a second drain select line DSL 2.

Therefore, the memory block BLKb of fig. 5 has a similar equivalent circuit to the memory block BLKa of fig. 4, except that the pipe transistor PT is excluded from each cell string.

In another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11 'to CS1m' or the cell strings CS21 'to CS2m' arranged in the row direction may be connected to even bit lines, respectively, and odd-numbered cell strings among the cell strings CS11 'to CS1m' or the cell strings CS21 'to CS2m' arranged in the row direction may be connected to odd bit lines, respectively.

In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is disposed to reduce an electric field between the source select transistor SST and the memory cells MC1 through MCn. Optionally, at least one dummy memory cell is disposed to reduce an electric field between drain select transistor DST and memory cells MC1 through MCn. As more dummy memory cells are disposed, the reliability of the operation of the memory block BLKb is improved, but the size of the memory block BLKb increases. As fewer memory cells are provided, the size of the memory block BLKb may be reduced, but the reliability of the operation for the memory block BLKb may be reduced.

In order to effectively control the dummy memory cells, each dummy memory cell may have a desired threshold voltage. Before or after the erase operation on the memory block BLKb, a program operation may be performed on all or some of the dummy memory cells. When an erase operation is performed after a program operation is performed, the dummy memory cells may have a desired threshold voltage by controlling voltages applied to dummy word lines connected to the respective dummy memory cells.

Fig. 6 is a circuit diagram illustrating an example of any one of the memory blocks BLK1 through BLKz included in the memory cell array 110 of fig. 2.

Referring to fig. 6, the memory block BLKc includes a plurality of cell strings CS1 through CSm. The plurality of cell strings CS1 to CSm may be connected to a plurality of bit lines BL1 to BLm, respectively. Each of the cell strings CS1 to CSm includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

Each of the selection transistors SST and DST and the memory cells MC1 through MCn may have a similar structure. In an embodiment, each of the selection transistors SST and DST and the memory cells MC1 through MCn may include a channel layer, a tunneling insulation layer, a charge storage layer, and a blocking insulation layer. In an embodiment, a pillar for providing a channel layer may be provided in each cell string. According to an embodiment of the present disclosure, a pillar for providing at least one of a channel layer, a tunneling insulation layer, a charge storage layer, and a blocking insulation layer may be provided in each cell string.

The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn.

The first to nth memory cells MC1 to MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 through MCn.

Memory cells connected to the same word line constitute one page. The cell strings CS1 to CSm may be selected by selecting the drain select line DSL. One page among the selected cell strings may be selected by selecting any one of the word lines WL1 through WLn.

In another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Even-numbered cell strings of the cell strings CS1 through CSm may be respectively connected to even bit lines, and odd-numbered cell strings may be respectively connected to odd bit lines.

Fig. 7 is a flowchart illustrating a method of operating a controller according to an embodiment.

Referring to fig. 7, a method of operating a controller 200 according to an embodiment of the present disclosure includes: a read request is received from the host (S100), and a read operation of the semiconductor memory device is controlled using the RHT (S200).

In step S100, the memory system 1000 receives a read request from a host. More specifically, the controller 200 of the memory system 1000 receives a read request from a host. The controller 200 may receive a logical address storing read data from a host along with a read request. The controller 200 may translate the received logical address into a physical address. In step S200, the controller 200 may control the semiconductor memory apparatus 100 to read data corresponding to the received read request based on the converted physical address.

In step S200, the controller 200 may control a read operation of the semiconductor memory device by using the RHT stored in the RHT storage device 250. Details of step S200 are described below with reference to fig. 8 to 9C.

FIG. 8 is a flow chart illustrating the method of operation of FIG. 7 in greater detail. Referring to fig. 8, a detailed configuration of step S200 of fig. 7 is shown. That is, according to an embodiment of the present disclosure, step S200 of fig. 7 includes steps S210, S220, S230, S240, S250, and S260 shown in fig. 8.

The controller 210 controls the semiconductor memory device 100 to perform a read operation corresponding to a read request received from a host (S210). To this end, the controller 200 may transfer a read command and a physical address corresponding thereto to the semiconductor memory apparatus 100. The semiconductor memory apparatus 100 may perform a read operation on a page corresponding to the received physical address based on the currently set read voltage and transfer read data to the controller 200.

In step S220, the error correction block 230 of the controller 200 performs an error correction operation on the read data received from the semiconductor memory device 100. When the error correction is successful as a result of the error correction (S220: no), the read data may be transferred to the host, and the read operation may be ended.

When it is determined that the error correction fails (S220: YES), the read voltage controller 210 refers to the read voltage included in the RHT stored in the RHT storage device 250 (S230). In step S230, the read voltage currently set in the semiconductor memory device 100 is compared with the last read voltage among the read voltages included in the RHT.

When the read voltage set in the semiconductor memory device is not the last read voltage among the read voltages in the RHT (S240: no), the method proceeds to step S250. In step S250, a read voltage to be used for the next read operation is determined based on the update sequence of the read voltages included in the RHT. As error correction failure is repeated as a result of the determination in step S220, in step S250, a read voltage to be used for the next read operation is determined by sequentially selecting read voltages from the most recently updated read voltage to the least recently updated read voltage among the read voltages in the RHT. A specific example of the method of determining the read voltage in step S250 is described below with reference to fig. 9A to 9C.

In step S260, the read voltage controller 210 controls the semiconductor memory device to use the determined read voltage for a read operation. In step S260, the read voltage controller 210 may set a read voltage for a read operation of the semiconductor memory device 100 using the set parameter command. Thereafter, the method proceeds to step S210 again, and controls the semiconductor memory device 100 to perform a read operation corresponding to a read request received from the host.

As a result of the determination in step S240, when the read voltage set in the semiconductor memory device is the last read voltage among the read voltages included in the RHT (S240: yes), this means that an error correction failure has occurred using all the read voltages stored in the RHT. Therefore, in this case, the read operation ends.

Fig. 9A, 9B, and 9C are diagrams for describing an embodiment of performing a read operation with reference to an RHT for a memory block including a single-layer cell (SLC). First, referring to fig. 9A, a threshold voltage distribution including SLCs and RHT of a read voltage for reading the SLCs are shown. Hereinafter, description is made with additional reference to fig. 8.

The SLC has any one of an erase state E and a program state P1 as a threshold voltage state. RHT includes three read voltages for each of the plurality of memory blocks BLK1 through BLKz included in the semiconductor memory device 100. In fig. 9A to 9C, for convenience, only the read voltage of the ith memory block BLKi including the page to be read among the plurality of memory blocks BLK1 to BLKz is shown. The threshold voltage distributions illustrated in fig. 9A to 9C are threshold voltage distributions of memory cells included in a page to be read. Referring to RHT, read voltages VR1 ", VR1', and VR1 are shown corresponding to a plurality of read operations R1_ t1, R1_ t2, and R1_ t3, respectively. The multiple read operations R1_ t1, R1_ t2, and R1_ t3 included in the RHT are the three most recent read operations. More specifically, the read operation R1_ t1 indicates a read operation of a last read pass, i.e., a last updated read voltage. Therefore, the read voltage used in the read operation of the last read pass of the ith memory block BLKi is VR1 ".

Read operation R1_ t2 indicates the read operation of the second most recent read pass. Therefore, for the ith memory block BLKi, the read voltage used in the read operation of the most recent read pass before the read operation R1_ t1 is VR 1'. That is, the read voltage VR1 'is the read voltage updated second in the RHT among the three read voltages VR1 ", VR1', and VR 1.

Finally, read operation R1_ t3 indicates the read operation of the third most recent read pass. Therefore, for the ith memory block BLKi, the read voltage used in the read operation of the most recent read pass before the read operation R1_ t2 is VR 1. That is, the read voltage VR1 is a read voltage that is initially updated in the RHT among the three read voltages VR1 ", VR1', and VR 1.

In summary, among the read operations of the last three read passes of the i-th memory block BLKi, the read voltage VR1 is used in the read operation R1_ t3 performed first, the read voltage VR' is used in the read operation R1_ t2 of the next read pass, and the read voltage VR "is used in the read operation R1_ t1 performed last.

Each time step S250 is repeatedly performed, the read voltages are selected in the order indicated by the arrow direction above RHT. That is, when an error correction failure for read data initially occurs in step S220, in step S250 executed thereafter, the read voltage VR1 ″ used in the read operation R1_ t1 of the most recently executed read pass is determined as the read voltage to be used in the next read operation. Referring to fig. 9A, a read voltage VR1 ″ is a read voltage existing in a valley between the erase state E and the program state P1, and is a read voltage generating the least errors. Therefore, according to the threshold voltage distribution shown in FIG. 9A, error correction of read data may be successful as a result of performing a read operation based on the read voltage VR1' selected after the initial error correction failed (S220: YES). If successful, the read operation ends.

Fig. 9B shows a threshold voltage distribution different from that of fig. 9A. The RHT shown in FIG. 9B is the same as the RHT shown in FIG. 9A. When an error correction failure for read data initially occurs in step S220, as described above, in step S250 executed thereafter, the read voltage VR1 ″ used in the read operation R1_ t1 of the most recently executed read pass may be determined as the read voltage to be used in the next read operation. Referring to fig. 9B, the read voltage VR1 ″ is significantly separated from the valley between the erased state E and the programmed state P1, and is a read voltage that outputs a relatively large number of errors. Therefore, according to the threshold voltage distribution shown in FIG. 9B, the error correction of the read data may again fail as a result of performing the read operation based on the selected voltage VR1' after the error correction fails (S220: YES). Therefore, the RHT is referred to (S230), and it is determined whether the read voltage VR1 ″ currently set in the semiconductor memory device 100 is the last read voltage VR1 of the RHT (S240). The last read voltage of the RHT may be the read voltage VR1 used during the initial read pass read operation R1_ t3 among the read voltages VR1 ", VR1' and VR1 in the RHT. Since the read voltage VR1 ″ currently set in the semiconductor memory device 100 is different from the last read voltage VR1 of the RHT, the method proceeds to step S250 to determine a read voltage to be used in the next read operation. In step S250, the read voltage VR' used in the read operation R1_ t2 of the second read pass may now be determined as the read voltage to be used in the next read operation. Referring to fig. 9B, a read voltage VR1' exists in a valley between the erase state E and the program state P1, and is a read voltage generating the least errors. Therefore, according to the threshold voltage distribution shown in FIG. 9B, the error correction of the read data may be successful as a result of performing the read operation based on the voltage VR1' selected after the second error correction failed (S220: YES). If successful, the read operation ends.

Fig. 9C shows a threshold voltage distribution different from that of fig. 9A or 9B. The RHT shown in fig. 9C is the same as the RHT shown in fig. 9A and 9B. As described above, when an error correction failure for read data initially occurs in step S220, as described above, in step S250 executed thereafter, the read voltage VR1 ″ used in the read operation R1_ t1 of the most recently executed read pass may be determined as the read voltage to be used in the next read operation. Referring to fig. 9C, as a result of performing a read operation by the read voltage VR1 ″, error correction on read data may fail. When the second error correction failure occurs as described above, in step S250 executed thereafter, the read voltage VR1' used in the read pass read operation R1_ t2 executed second may be determined as the read voltage to be used in the next read operation. Referring to fig. 9C, as a result of performing a read operation by the read voltage VR1', error correction on read data may fail. When the third error correction failure occurs, in step S250 executed thereafter, the read voltage VR1 used in the read operation R1_ t3 of the initially executed read pass among the read operations R1_ t1, R1_ t2, and R1_ t3 included in the RHT may be determined as a read voltage to be used in the next read operation. Referring to fig. 9C, as a result of performing a read operation by the read voltage VR1, error correction on read data may fail.

Therefore, as a result of the determination of the subsequent step S240, since the read voltage currently set in the semiconductor memory device 100 is the same as the last read voltage VR1 in the RHT, the read operation ends. This means that even if the read operation is repeatedly performed sequentially using all the read voltages in the RHT, the error correction fails. Therefore, it can be considered that the read operation corresponding to the read request received from the host has finally failed.

As described above, according to embodiments of the present disclosure, the RHT stored in the RHT storage device includes a read voltage used in a read operation of a previous read pass. Each time an error correction failure repeatedly occurs during a read operation, the controller controls the semiconductor memory device 100 to sequentially select from the most recently updated read voltage VR1 ″ to the initially updated read voltage VR1 among the plurality of read voltages in the RHT to use the read voltage in the read operation of the semiconductor memory device 100. Therefore, since the read voltages are sequentially used in the read operation from the read voltage VR1 ″ used in the operation of the most recent read pass, the probability of successfully performing error correction increases. Accordingly, the performance of the memory system including the semiconductor memory device 100 and the controller 200 is improved.

The RHT shown in fig. 9A to 9C includes three read voltages VR1 ", VR' and VR1 for each memory block. This means that the RHT includes read voltages for the three most recent read passes of read operations R1_ t1, R1_ t2, and R1_ t 3. In this specification, the number of read voltages included in the RHT, and thus the number of read operation retries, is defined as "the depth of the RHT". In the embodiment shown in fig. 9A-9C, RHT includes 3 read voltages, corresponding to three read passes of the read operation, respectively, and thus has a depth of 3. However, this is merely an example, and the depth of the RHT may be determined differently as needed. As the depth of the RHT increases, read voltages corresponding to more read passes of read operations are stored in the RHT. Thus, the capacity of the RHT storage device 250 for storing the RHT is increased while the reading performance can be improved. On the other hand, when the depth of RHT is reduced, read voltages corresponding to read operations with fewer read passes are included in RHT. Thus, although less capacity of the RHT storage device 250 is required, read performance may be degraded. Therefore, the depth of RHT can be set in consideration of this trade-off.

Fig. 10 is a block diagram illustrating a memory system including a controller according to another embodiment of the present disclosure.

Referring to fig. 10, a memory system 1001 includes a semiconductor memory device 100 and a controller 201. The semiconductor memory device 100 of fig. 10 is the same as or substantially the same as the semiconductor memory device 100 described with reference to fig. 1 and 2.

Controller 201 includes a read voltage controller 210, an error correction block 230, an RHT storage 250, and a read retry table storage 270. The controller 201 shown in fig. 10 is the same as or substantially the same as the controller 200 shown in fig. 1, except that the controller 201 further includes a read retry table storage 270.

The read retry table storage 270 stores a Read Retry Table (RRT). The RRT includes a set number of read voltages, which may be predetermined. When error correction failure for the same data repeatedly occurs, the read voltage controller 210 repeats the read operation by sequentially applying the read voltages stored in the RRT. The RRT and the read operation using the RRT are well known in the art of the present disclosure, and thus a description thereof is omitted.

Based on the controller 201 according to another embodiment of the present disclosure, when an error correction failure to read data occurs, the read voltage controller 210 first performs a read operation using the RHT, however, when an error correction failure repeatedly occurs using all read voltages in the RHT, the read voltage controller 210 may perform a read operation using the RRT. A method of operating the controller 201 according to another embodiment of the present disclosure is described below with reference to fig. 11 to 13D.

FIG. 11 is a flow chart illustrating a method of operating a controller according to the embodiment of FIG. 10.

Referring to fig. 11, the method of operating the controller 201 according to the embodiment of fig. 10 includes: a read request is received from a host (S100), a read operation of the semiconductor memory device is controlled using the RHT (S200), and the read operation of the semiconductor memory device is controlled and the RHT is updated using the RTT (S300).

In step S100, the memory system 1000 receives a read request from a host. More specifically, the controller 201 of the memory system 1000 receives a read request from a host. The controller 201 may receive a logical address storing read data from a host along with a read request. The controller 201 may translate the received logical address to a physical address. In steps S200 and S300, the controller 201 may control the semiconductor memory apparatus 100 to read data corresponding to the received read request based on the converted physical address.

In step S200, the controller 201 may control a read operation of the semiconductor memory device using the RHT stored in the RHT storage device 250. Step S200 may include steps S210, S220, S230, S240, S250, and S260 shown in fig. 8. That is, step S200 of fig. 11 may be performed the same as or substantially the same as the steps described with reference to fig. 8 to 9C.

As a result of repeatedly performing the read operation in step S200, when error correction for read data repeatedly fails, a read operation using an additional read method may be performed. In the embodiment of fig. 11, the additional read method may be a read method using an RRT.

According to the embodiment of fig. 11, step S300 is performed as an additional reading method. More specifically, when the error correction fails as a result of performing the read operation using all of the read voltages VR1 ", VR1', and VR1 in the RHT, step S200 ends and step S300 is performed. When the error correction for the read data is successful while step S200 is performed, the read operation may end and step S300 may not be performed. Hereinafter, the description is made in more detail with reference to fig. 12.

FIG. 12 is a flow chart illustrating the method of operation of FIG. 11 in greater detail.

Referring to fig. 12, when a read operation using a read voltage included in the RHT fails, a read voltage to be used in a next read operation is determined with reference to the RRT (S310). In this case, the first read voltage of the RRT may be determined as a read voltage to be used in the next read operation.

Thereafter, the semiconductor memory device is controlled to use the determined read voltage in a read operation (S320). In step S320, the read voltage controller 210 may set a read voltage used in a read operation of the semiconductor memory device 100 using the set parameter command.

Thereafter, the semiconductor memory device 100 is controlled to perform a read operation corresponding to a read request received from the host (S330). Accordingly, a read operation may be performed using the first read voltage in the RRT.

In step S340, it is determined whether an error correction failure occurs for read data to be received from the semiconductor memory device 100 (S230). When the error correction fails (S340: YES), it is determined whether the read voltage currently used in the read operation is the last read voltage in the RRT (S350). Since the read operation is performed using the first read voltage of the current RRT (S350: no), the method proceeds to step S310 to determine the second read voltage in the RRT as the read voltage to be used in the next read operation, and repeatedly performs the read operation (S310). Therefore, when error correction failure is repeated, the read operation can be performed using all read voltages up to the last read voltage in the RRT.

When it is determined that the error correction is successful (S340: No), the error correction data may be transmitted to the host. In this case, the RHT is updated based on the read voltage used in the current read operation (S360). Error correction success means that the currently performed read operation is the current most recent read pass read operation. Thus, the read voltage used in the current read operation is added to the RHT as the most recently successful read voltage. The updated RHT may be used in a read operation corresponding to the next read request from the host.

Fig. 13A, 13B, 13C, and 13D are diagrams exemplarily describing update of the RHT. In the initial state, the RHT may not include any read voltage.

Referring to fig. 13A, a read voltage VR1 is used in a read operation of a first page included in an ith memory block BLKi by a first request from a host. The read voltage VR1 may be a voltage included in the RRT. Since the read data according to the read voltage VR1 is successfully error corrected (S340: NO), the read voltage used in the read pass may be updated into RHT, denoted as RHT _0 (S360).

Referring to fig. 13B, a read operation for a second page included in the ith memory block BLKi may be performed by a second request from the host. In this case, first, according to step S200 of fig. 11, the read operation of the semiconductor memory device is controlled using the previously updated RHT _ 0. According to the threshold voltage distribution of fig. 13B, when a read operation is performed using the read voltage VR1 included in RHT _0 of fig. 13A, an error correction failure may occur. Accordingly, the process proceeds to step S300 of fig. 11 to control a read operation of the semiconductor memory device using the RRT.

In the example of fig. 13B, it is assumed that the read voltage VR1a is included among a plurality of read voltages in the RRT. In the course of repeatedly performing a read operation using a plurality of read voltages included in the RRT, the read operation may be performed by the read voltage VR1 a. Therefore, in step S340 of FIG. 12, the error correction may be successful (S340: NO). Since the error correction is successfully performed according to the read data of the read voltage VR1a, the read voltage used in the read pass may be updated into RHT _0 (S360). Therefore, RHT is updated based on the read voltage VR1a used in the current read operation. More specifically, the read voltage VR1a is added to RHT _0 shown in FIG. 13A to generate an updated RHT, denoted RHT _ a. Referring to the updated RHT (RHT _ a), a read voltage VR1a used in a read operation R1_ t1 of a most recently performed read pass and a read voltage VR1 used in a read operation R1_ t2 of a read pass performed before the read operation R1_ t1, i.e., a read voltage VR1 used in fig. 13A, are included.

Referring to fig. 13C, a read operation for a third page included in the ith memory block BLKi may be performed by a third request from the host. In this case, first, according to step S200 of fig. 11, the read operation of the semiconductor memory device is controlled using the previously updated RHT _ a. In step S200, a read operation may be sequentially performed using the read voltages VR1a and VR1 included in RHT _ a of fig. 13B. According to the threshold voltage distribution of fig. 13C, when a read operation is performed using the read voltages VR1a and VR1 included in RHT _ a, an error correction failure may repeatedly occur. Accordingly, the process proceeds to step S300 of fig. 11 to control a read operation of the semiconductor memory device using the RRT.

In the example of fig. 13C, it is assumed that the read voltage VR1b is included among the plurality of read voltages included in the RRT. In the course of repeatedly performing a read operation using a plurality of read voltages included in the RRT, the read operation may be performed by the read voltage VR1 b. Therefore, in step S340 of FIG. 12, the error correction may be successful (S340: NO). Since the read data according to the read voltage VR1b is successfully error-corrected, the read voltage used in the read pass can be updated into RHT _ a. Therefore, RHT is updated based on the read voltage VR1b used in the current read operation. More specifically, the read voltage VR1B is added to RHT _ a shown in FIG. 13B to generate an updated RHT, denoted as RHT _ B. Referring to the updated RHT (RHT _ b), a read voltage VR1b used in the read operation R1_ t1 of the most recently performed read pass and a read voltage VR1 used in the read operation R1_ t3 of the first performed read pass are included.

Referring to fig. 13C, since the depth of RHT _ b is 3, three read voltages VR1b, VR1a, and VR1 for the ith memory block BLKi are included in the RHT _ b.

Referring to fig. 13D, a read operation for the fourth page included in the ith memory block BLKi may be performed by a fourth request from the host. In this case, first, according to step S200 of fig. 11, the read operation of the semiconductor memory device is controlled using the previously updated RHT _ b. In step S200, a read operation may be sequentially performed using the read voltages VR1b, VR1a, and VR1 included in the RHT _ b of fig. 13C. According to the threshold voltage distribution of fig. 13C, when a read operation is performed using the read voltages VR1b, VR1a, and VR1 included in RHT _ b, an error correction failure may repeatedly occur. Accordingly, the process proceeds to step S300 of fig. 11 to control a read operation of the semiconductor memory device using the RRT.

In the example of fig. 13D, it is assumed that the read voltage VR1c is included among the plurality of read voltages included in the RRT. In the course of repeatedly performing a read operation using a plurality of read voltages included in the RRT, the read operation may be performed by the read voltage VR1 c. Therefore, in step S340 of FIG. 12, the error correction may be successful (S340: NO). Since the read data according to the read voltage VR1c is successfully error-corrected, the read voltage used in the read pass can be updated into RHT _ b. Therefore, RHT is updated based on the read voltage VR1c used in the current read operation. More specifically, the read voltage VR1C is added to RHT _ b shown in FIG. 13C to generate an updated RHT, denoted as RHT _ C.

The maximum depth of RHT may be 3, in which case, since the depth of RHT _ b is 3, in order to add a new read voltage VR1c, one of the three read voltages VR1b, VR1a, VR1 currently in RHT _ b needs to be removed. In the embodiment of the present disclosure, the read voltage that is the earliest update, i.e., the read voltage VR1, is removed. Thus, the updated RHT _ c includes read voltages VR1c, VR1b, and VR1a used in the three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t 3.

Fig. 14 is a block diagram illustrating a memory system including a controller according to yet another embodiment of the present disclosure.

Referring to fig. 14, a memory system 1002 includes the semiconductor memory device 100 and a controller 202. The semiconductor memory device 100 of fig. 14 is the same as or substantially the same as the semiconductor memory device 100 described with reference to fig. 1 and 2.

Controller 202 includes a read voltage controller 210, an error correction block 230, an RHT storage device 250, and an optimal read voltage search component 280. The controller 202 shown in FIG. 14 is the same as or substantially the same as the controller 200 shown in FIG. 1, except that the controller 202 further includes an optimal read voltage search component 280.

The optimal read voltage search component 280 searches for an optimal read voltage based on the threshold voltage distributions of the memory cells of the page to be read. More specifically, the optimal read voltage search component 280 controls the semiconductor memory device to repeatedly perform a read operation based on a plurality of reference read voltages, analyze data corresponding to the plurality of reference read voltages, and search for a valley between two adjacent threshold voltage states. The optimum read voltage search method of the optimum read voltage search component 280 is described below with reference to fig. 16 to 17.

Fig. 15 is a flowchart illustrating a method of operating a controller according to the embodiment of fig. 14.

Referring to fig. 15, a method of operating the controller 202 according to the embodiment of fig. 14 includes: a read request is received from a host (S100), a read operation of the semiconductor memory device is controlled using the RHT (S200), and the read operation of the semiconductor memory device is controlled using an optimal read voltage search method and the RHT is updated (S301).

In step S100, the memory system 1000 receives a read request from a host. More specifically, the controller 200 of the memory system 1000 receives a read request from a host. The controller 202 may receive a logical address from the host storing read data along with a read request. The controller 202 may translate the received logical address to a physical address. In steps S200 and S301, the controller 202 may control the semiconductor memory apparatus 100 to read data corresponding to the received read request based on the converted physical address.

In step S200, the controller 202 may control a read operation of the semiconductor memory device using the RHT stored in the RHT storage device 250. Step S200 may include steps S210, S220, S230, S240, S250, and S260 shown in fig. 8. That is, step S200 of fig. 15 may be performed the same as or substantially the same as the steps described with reference to fig. 8 to 9C.

As a result of repeatedly performing the read operation in step S200, when error correction for read data fails a plurality of times (for example, after all read voltages in the RHT are used), a read operation using an additional read method may be performed. In the embodiment of fig. 15, the additional read method may be a read method using an optimal read voltage search method.

According to the embodiment of fig. 15, step S301 is performed as an additional reading method. More specifically, according to the control of the optimum read voltage search component 280, the semiconductor memory device 100 repeatedly performs a read operation based on a plurality of reference read voltages. An optimal read voltage corresponding to a valley of the threshold voltage distribution is determined based on a plurality of read results according to a plurality of reference read voltages, and a read operation is performed based on the determined optimal read voltage.

A specific embodiment of step S301 is described in more detail with reference to fig. 16 and 17.

FIG. 16 is a flow chart illustrating the method of operation of FIG. 15 in greater detail. Fig. 17 is a diagram for describing steps S315 and S325 of fig. 16. Hereinafter, a method of operating a controller according to an embodiment of the present disclosure is described with reference to fig. 16 and 17 together.

Referring to fig. 16, when the read operation using the read voltage included in the RHT fails, the optimum read voltage search component 280 controls the semiconductor memory device 100 to perform the read operation based on the plurality of reference read voltages VR1_1 to VR1_7 (S315). More specifically, the optimum read voltage search component 280 may generate read commands corresponding to the plurality of reference read voltages VR1_1 through VR1_7, transmit the read commands to the semiconductor memory device 100, and receive read results based on the plurality of reference read voltages VR1_1 through VR1_ 7. According to the example shown in fig. 17, a read operation is performed based on a plurality of reference read voltages VR1_1 to VR1_7 between the erase state E and the program state P1. Read data that is the result of a read operation performed by each of the reference read voltages VR1_1 through VR1_7 may be transferred to the controller 202.

Thereafter, the optimum read voltage search component 280 determines an optimum read voltage corresponding to a valley of the threshold voltage distribution based on the plurality of read results (S325). In the example shown in fig. 17, the number of bits of 1 (the number is represented as N _ B1) included in the data read by the first reference read voltage VR1_1 among the plurality of reference read voltages VR1_1 to VR1_7 may be the number of memory cells having threshold voltages smaller than the first reference read voltage VR1_1 in the threshold voltage distribution of fig. 17. The number of bits of 1 (the number is represented as N _ B2) included in the data read by the second reference read voltage VR1_2 among the plurality of reference read voltages VR1_1 to VR1_7 may be the number of memory cells having a threshold voltage smaller than the second reference read voltage VR1_2 in the threshold voltage distribution of fig. 17. Thus, the number of memory cells having a threshold voltage between the first reference read voltage VR1_1 and the second reference read voltage VR1_2 may be obtained by subtracting N _ B2 from N _ B1. In this manner, the optimal read voltage search component 280 can calculate the number of memory cells included in each of the plurality of segments defined by the plurality of reference read voltages VR1_1 through VR1_ 7. Thereafter, the optimal read voltage search component 280 can determine a segment between VR1_3 and VR1_4 and between VR1_4 and VR1_5 that includes the least number of memory cells, and can determine a fourth reference read voltage VR1_4 that is commonly included in such segments as the optimal read voltage.

Thereafter, the controller 202 controls the semiconductor memory device 100 to perform a read operation based on the determined optimal read voltage (S335). In step S335, the read voltage controller 210 may set the determined optimum read voltage to a read voltage used in a read operation of the semiconductor memory apparatus 100 using the set parameter command. In addition, in step S335, the controller 202 may transmit a read command corresponding to the read request received from the host to the semiconductor memory apparatus 100. The semiconductor memory device 100 may perform a read operation in response to a received read command. In step S335, the semiconductor memory device 100 may perform a read operation based on the determined optimal read voltage (e.g., VR1_4) and transfer the read data to the controller 202.

The error correction block 230 of the controller 202 performs an error correction operation on read data received from the semiconductor memory device 100. When the error correction of the read data from the semiconductor memory device fails (S345: yes), the read operation may end.

When the error correction of the read data from the semiconductor memory device is successful (S345: no), the error-corrected data may be transferred to the host. Also, in this case, the RHT is updated based on the read voltage used in the current read operation, i.e., VR1_4 (S355). Error correction success means that the currently performed read operation is the current most recent read pass read operation. Thus, the read voltage used in the current read operation (e.g., VR1_4) is added to the RHT as the most recently successful read voltage. The updated RHT may be used in a read operation corresponding to the next read request from the host.

Fig. 18A is a block diagram illustrating a memory system including a controller according to yet another embodiment of the present disclosure.

Referring to fig. 18A, the memory system 1003 includes the semiconductor memory device 100 and a controller 203. The semiconductor memory device 100 of fig. 18A is the same as or substantially the same as the semiconductor memory device 100 described with reference to fig. 1 and 2.

Controller 203 includes read voltage controller 210, error correction block 230, RHT storage 250, RRT storage 270, and optimal read voltage search component 280. The controller 203 shown in fig. 18A is the same or substantially the same as the controller 200 shown in fig. 1, except that the controller 203 further includes an RRT memory device 270 and an optimal read voltage search component 280.

The RRT memory device 270 of FIG. 18A may be the same or substantially the same as the RRT memory device 270 described with reference to FIG. 10. Also, the optimal read voltage search component 280 of FIG. 18A may be the same or substantially the same as the optimal read voltage search component 280 described with reference to FIG. 14. Therefore, the description of the RRT memory device 270 and the optimum read voltage search component 280 is omitted here.

FIG. 18B is a flow diagram illustrating a method of operating a controller according to the embodiment of FIG. 18A.

Referring to fig. 18B, a method of operating the controller 203 according to the embodiment of fig. 18A includes: the method includes receiving a read request from a host (S100), controlling a read operation of the semiconductor memory device using the RHT (S200), controlling the read operation of the semiconductor memory device using the RRT and updating the RHT (S300), and controlling the read operation of the semiconductor memory device using an optimal read voltage search method and updating the RHT (S301).

In step S100, the memory system 1000 receives a read request from a host. More specifically, the controller 200 of the memory system 1000 receives a read request from a host. The controller 203 may receive a logical address storing read data from the host along with the read request. The controller 203 may translate the received logical address to a physical address. In steps S200, S300, and S301, the controller 203 may control the semiconductor memory apparatus 100 to read data corresponding to the received read request based on the converted physical address.

In step S200, the controller 203 may control a read operation of the semiconductor memory device using the RHT stored in the RHT storage device 250. Step S200 may include steps S210, S220, S230, S240, S250, and S260 shown in fig. 8. That is, step S200 of fig. 18B may be performed the same as or substantially the same as the steps described with reference to fig. 8 to 9C.

As a result of repeatedly performing the reading operation through step S200, when error correction for the read data repeatedly fails, step S300 is performed. More specifically, when an error correction failure occurs in the process of attempting to read data using all the read voltages VR1 ", VR1', and VR1 included in the RHT, step S200 ends and step S300 is performed. When the error correction for the read data is successful, the read operation may end, and step S300 may not be performed. That is, step S300 of fig. 18B may be performed the same as or substantially the same as described with reference to fig. 12 to 13D.

As a result of repeatedly performing the read operation according to the RRT in step S300, when error correction for read data repeatedly fails, step S301 is performed. More specifically, according to the control of the optimum read voltage search component 280, the semiconductor memory device 100 repeatedly performs a read operation based on a plurality of reference read voltages. An optimal read voltage corresponding to a valley of the threshold voltage distribution is determined based on a plurality of read results according to a plurality of reference read voltages, and a read operation is performed based on the determined optimal read voltage. Step S301 may include steps S315, S325, S335, S345, and S355 shown in fig. 16. That is, step S301 of fig. 18B may be performed the same as or substantially the same as described with reference to fig. 16 and 17.

Fig. 19A, 19B, and 19C are diagrams illustrating RHTs according to embodiments of the present disclosure.

First, referring to fig. 19A, RHT including a read voltage for each of the memory blocks BLK1 through BLKz is shown. In the embodiment of fig. 19A, the RHT has a depth of 3. Thus, for each of the memory blocks BLK1 through BLKz, RHT includes read voltages used in the three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t 3. More specifically, for the first memory block BLK1, the RHT includes read voltages VR1_ a1, VR1_ b1, and VR1_ c1 used in three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t 3. In addition, for the second memory block BLK2, the RHT includes read voltages VR1_ a2, VR1_ b2, and VR1_ c2 used in three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t 3. In this way, the read voltages VR1_ az, VR1_ bz, and VR1_ cz used in the three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t3 are stored in the RHT for the z-th memory block BLKz. As described above, the RHT shown in fig. 19A has a depth of 3. However, this is merely an example; the RHT may be a different depth, taking into account the above trade-off.

Referring to fig. 19B, there is shown an RHT including read voltages for pages P1 through Pn included in each of the memory blocks BLK1 through BLKz. In the embodiment of fig. 19B, the RHT has a depth of 3. Accordingly, for each of pages P1 through Pn of each of memory blocks BLK1 through BLKz, read voltages used in the three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t3 are stored in RHT. More specifically, the RHT includes read voltages VR1_ a11, VR1_ b11, VR1_ c11 used in three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t3 for the first page P1 of the first memory block BLK 1. In addition, the RHT includes read voltages VR1_ a21, VR1_ b21, VR1_ c21 used in three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t3 for the second page P2 of the first memory block BLK 1. In this way, the RHT includes read voltages VR1_ an1, VR1_ bn1, and VR1_ cn1 used in three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t3 for the nth page Pn of the first memory block BLK 1. The RHT may include read voltages used in three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t3 for each of pages P1 to Pn included in the other memory blocks BLK2 to BLKz. The RHT shown in fig. 19B has a depth of 3, which is an example. As previously described, the RHT may have any suitable depth.

When the RHT includes a read voltage for each of the plurality of pages P1 through Pn included in the memory block, the performance of the memory systems 1000, 1001, 1002, and 1003 is improved, but the capacity of the RHT memory device 250 is increased. Accordingly, the plurality of pages P1 through Pn included in the memory block may be grouped to include a read voltage for each group in the RHT.

Referring to fig. 19C, there is shown an RHT including read voltages for page groups GR1 to GRk included in each of the memory blocks BLK1 to BLKz. One page group may include a plurality of pages. In the embodiment of fig. 19C, the RHT has a depth of 3. Thus, for each of the page groups GR1 to GRk of each of the memory blocks BLK1 to BLKz, RHT includes read voltages used in the three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t 3. More specifically, for the first page GR1 of the first memory block BLK1, the RHT includes read voltages VR1_ a11, VR1_ b11, and VR1_ c11 used in three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t 3. In addition, the RHT includes read voltages VR1_ a21, VR1_ b21, and VR1_ c21 used in three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t3 for the second page GR2 of the first memory block BLK 1. In this way, the RHT includes read voltages VR1_ ak1, VR1_ bk1 and VR1_ ck1 used in three most recently passed read operations R1_ t1, R1_ t2 and R1_ t3 for the k-th page group GRk of the first memory block BLK 1. The RHT may include read voltages used in three most recent read pass read operations R1_ t1, R1_ t2, and R1_ t3 for each of page groups GR1 to GRk included in the other memory blocks BLK2 to BLKz. As described above, 3 is an example as the depth of the RHT shown in fig. 19C, and the RHT may be any suitable depth.

Fig. 20 is a diagram for describing the RHT shown in fig. 19C. Referring to fig. 20, each of a plurality of memory blocks BLK1 through BLKz included in a memory cell array 110 of a semiconductor memory device 100 includes first through nth pages Page 1 through Page n. The first to nth pages Page 1 to Page n may be grouped into first to kth Page groups GR1 to GRk. In the example of fig. 20, each of the first to k-th page groups GR1 to GRk includes 8 pages, but the present disclosure is not limited thereto. A page group may include any suitable number of pages.

Fig. 21 is a diagram illustrating threshold voltage distributions of multi-level cells (MLCs). According to the MLC, two bits of data can be stored in one memory cell. To store two bits of data, the threshold voltage of the memory cell belongs to any one of the erase state E, the first program state P1, the second program state P2, and the third program state P3. The first, second, and third read voltages VR1, VR2, and VR3 are used to distinguish threshold voltages of MLCs. According to an embodiment of the present disclosure, the RHT may be used for each of the first to third read voltages VR1 to VR3 used in reading the MLC.

Fig. 22 is a diagram showing an example of an RHT for a memory block including MLCs.

Referring to fig. 22, there is shown an RHT _ MLC including first to third read voltages for each of memory blocks BLK1 to BLKz. In the embodiment of fig. 22, the RHT has a depth of 2. Thus, for each of memory blocks BLK1 through BLKz, RHT includes the read voltages used in the read operations of the two most recent read passes. More specifically, for a read operation of the MLC, as shown in fig. 21, sub-read operations may be performed using the first to third read voltages VR1 to VR3, respectively. The first sub read operation is a sub read operation for distinguishing the erase state E and the first program state P1 from each other, the second sub read operation is a sub read operation for distinguishing the first program state P1 and the second program state P2 from each other, and the third sub read operation is a sub read operation for distinguishing the second program state P2 and the third program state P3 from each other.

In the RHT _ MLC of fig. 22, the RHT includes read voltages VR1_ a1 and VR1_ b1 used in first sub-read operations R1_ t1 and R1_ t2 of two most recent read passes for the first memory block BLK 1. In addition, the RHT includes read voltages VR2_ a1 and VR2_ b1 used in second sub-read operations R2_ t1 and R2_ t2 of two most recent read passes for the first memory block BLK 1. In addition, the RHT includes read voltages VR3_ a1 and VR3_ b1 used in third sub-read operations R3_ t1 and R3_ t2 of two most recent read passes for the first memory block BLK 1. The same applies to the other memory blocks BLK2 to BLKz.

Fig. 22 illustrates an RHT _ MLC for an MLC storing 2-bit data per memory cell, but the present disclosure is not limited thereto. In particular, the RHT and the read operation using the RHT according to embodiments of the present disclosure may be applied to a Triple Layer Cell (TLC), a Quadruple Layer Cell (QLC), or a memory cell storing 5 or more bits of data.

Fig. 23 is a block diagram illustrating a memory system including the controller of fig. 1, 10, 14, or 18A.

Referring to fig. 23, a memory system 1000 includes a semiconductor memory device 1100 and a controller 1200. The semiconductor memory device 1100 may be the semiconductor memory device described with reference to fig. 2.

The controller 1200 is connected to a Host (Host) and the semiconductor memory device 1100. The controller 1200 is configured to access the semiconductor memory apparatus 1100 in response to a request from a Host (Host). For example, the controller 1200 is configured to control a read operation, a write operation, an erase operation, and a background operation of the semiconductor memory device 1100. The controller 1200 is configured to provide an interface between the semiconductor memory apparatus 1100 and a host. The controller 1200 is configured to drive firmware for controlling the semiconductor memory apparatus 1100. The controller 1200 may be the controller 200, 201, 202, or 203 described with reference to fig. 1, 10, 14, or 18A.

Controller 1200 includes Random Access Memory (RAM)1210, processor 1220, host interface 1230, memory interface 1240, and error correction block 1250. The RAM 1210 may be used as any one of an operation memory of the processor 1220, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 1100 and the host. The processor 1220 controls the overall operation of the controller 1200. In addition, the controller 1200 may temporarily store program data provided by the host during a write operation.

The host interface 1230 includes a protocol for performing data exchange between the host and the controller 1200. In an embodiment, the controller 1200 is configured to communicate with the host through at least one of various interface protocols such as: a Universal Serial Bus (USB) protocol, a multi-media card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and/or a proprietary protocol.

The memory interface 1240 interfaces with the semiconductor memory device 1100. For example, the memory interface may include a NAND interface or a NOR interface.

The error correction block 1250 is configured to detect and correct an error of data received from the semiconductor memory apparatus 1100 by using an Error Correction Code (ECC). The processor 1220 may control a read voltage according to the error detection result of the error correction block 1250 and control the semiconductor memory device 1100 to perform re-reading. In an embodiment, an error correction block may be provided as a component of the controller 1200.

The controller 1200 and the semiconductor memory device 1100 may be integrated into one semiconductor device. In an embodiment, the controller 1200 and the semiconductor memory device 1100 may be integrated into one semiconductor device to configure a memory card such as the following: PC card (personal computer memory card international association (PCMCIA)), compact flash Card (CF), smart media card (SM and SMC), memory stick, multimedia card (MMC, RS-MMC or micro MMC), SD card (SD, mini SD, micro SD and SDHC) and/or universal flash memory (UFS), etc.

The controller 1200 and the semiconductor memory device 1100 may be integrated into one semiconductor device to form a semiconductor drive (solid state drive (SSD)). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operation speed of a host connected to the memory system 1000 is significantly improved.

As another example, the memory system 1000 is provided as one of various components of an electronic device such as: a computer, an ultra mobile pc (umpc), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components configuring a computing system.

In embodiments, the semiconductor memory device 1100 or the memory system 1000 may be mounted as various types of packages. For example, the semiconductor memory device 1100 or the memory system 1000 may be packaged and mounted in a method such as: package on package (PoP), Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack (die in wafer pack), die in wafer form (die in wafer form), Chip On Board (COB), ceramic dual in-line package (CERDIP), plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), wafer scale manufacturing package (WFP), or wafer scale processing stack package (WSP).

Fig. 24 is a block diagram showing an application example of the memory system of fig. 23.

Referring to fig. 24, the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups, for example, k groups.

In fig. 24, the k groups communicate with the controller 2200 through the first to k-th channels CH1 to CHk, respectively. Each semiconductor memory chip is configured and operates similarly to one of the semiconductor memory devices 1100 described with reference to fig. 2.

Each group is configured to communicate with the controller 2200 through a common channel. The controller 2200 is configured similarly to the controller 1200 described with reference to fig. 17, and is configured to control a plurality of memory chips of the semiconductor memory apparatus 2100 through a plurality of channels CH1 to CHk.

Fig. 25 is a block diagram illustrating a computing system including the memory system described with reference to fig. 24.

Computing system 3000 includes a central processing device 3100, Random Access Memory (RAM)3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

The memory system 2000 is electrically connected to the central processing device 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through a system bus 3500. Data provided through the user interface 3300 or processed by the central processing device 3100 is stored in the memory system 2000.

In fig. 25, a semiconductor memory device 2100 is connected to a system bus 3500 through a controller 2200. However, the semiconductor memory apparatus 2100 may be configured to be directly connected to the system bus 3500. The functions of the controller 2200 are performed by the central processing device 3100 and the RAM 3200.

In fig. 25, a memory system 2000 described with reference to fig. 24 is provided. However, the memory system 2000 may be replaced with the memory system 1000 described with reference to fig. 23. In an embodiment, the computing system 3000 may be configured to include the memory systems 1000 and 2000 described with reference to fig. 23 and 24.

The embodiments disclosed herein are merely specific examples presented to describe and facilitate an understanding of the technical content of the present disclosure. However, the disclosed embodiments are not intended to limit the scope of the invention. It will be apparent to those skilled in the art to which the disclosure pertains that various modifications may be made to any of the disclosed embodiments within the spirit and scope of the invention.