阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 李旭 于 2020-06-19 设计创作，主要内容包括：本发明提供能够提高动作的性能和存储单元的可靠性的半导体存储装置。本发明的实施方式的半导体存储装置具备存储单元阵列(21)、控制对阱区的施加电压的CPWELL电压控制电路(37)和控制对源极线(CELSRC)的施加电压的CELSRC电压控制电路(36)。在写入数据之前,针对选择栅极线(SGS)和字线(WL),在第一定时使它们连接的晶体管导通,在第二定时施加接地电压来使晶体管关断。CELSRC电压控制电路(36)在从第一定时到第三定时之间的第四定时对源极线(CELSRC)施加第一电压,CPWELL电压控制电路(37)在从第一定时到第二定时之间的第五定时对阱区施加第一电压,在从第五定时到第二定时之间的第六定时施加接地电压。(The invention provides a semiconductor memory device capable of improving operation performance and reliability of a memory cell. A semiconductor memory device according to an embodiment of the present invention includes a memory cell array (21), a CPWELL voltage control circuit (37) that controls a voltage applied to a well region, and a CELSRC voltage control circuit (36) that controls a voltage applied to a source line (CELSRC). Before data is written, transistors connected to a select gate line (SGS) and a Word Line (WL) are turned on at a first timing, and a ground voltage is applied to the transistors at a second timing to turn off the transistors. A CELSRC voltage control circuit (36) applies a first voltage to a source line (CELSRC) at a fourth timing between the first timing and a third timing, and a CPWELL voltage control circuit (37) applies the first voltage to the well region at a fifth timing between the first timing and the second timing, and applies a ground voltage at a sixth timing between the fifth timing and the second timing.)

1. A semiconductor memory device has:

a semiconductor substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction;

the well region is formed on the surface layer of the semiconductor substrate;

the source line is formed on the well region on the surface of the semiconductor substrate;

a first selection gate line disposed above the well region and stacked in a third direction orthogonal to the first direction and the second direction;

a plurality of word lines arranged above the first select gate lines and stacked in the third direction;

a second selection gate line disposed above the plurality of word lines, stacked in the third direction;

a plurality of bit lines arranged over the second select gate lines and extending in the first direction;

a memory cell array having a plurality of memory strings extending in the third direction and respectively connected between the corresponding bit lines and the source lines;

a well voltage control unit for controlling a voltage applied to the well region;

a source voltage control unit that controls a voltage applied to the source line; and

a row voltage control unit for switching application of voltages to the first selection gate line, the plurality of word lines, and the second selection gate line,

before writing data to 1 memory cell included in the memory cell array, the row voltage control unit applies a voltage to the first selection gate line, a selection word line, which is the word line connected to at least 1 memory cell among the plurality of word lines, and the word line arranged below the selection word line at a first timing to turn on the transistors connected to each other, switches the voltage applied to the first selection gate line at a second timing later than the first timing to turn off the transistors connected to the first selection gate line, and switches the voltages applied to the selection word line and the word line arranged below the selection word line at a third timing after the first timing to turn off the transistors connected to each other,

the source voltage control section applies a first voltage to the source line at a fourth timing between the first timing and the third timing,

the well voltage control section applies the first voltage to the well region at a fifth timing between the first timing and the second timing, and applies a ground voltage to the well region at a sixth timing between the fifth timing and the second timing.

2. The semiconductor memory device according to claim 1,

the channel of the memory string is boosted to a predetermined voltage by the first voltage applied from the source line.

3. The semiconductor memory device according to claim 2,

the first timing, the fourth timing, and the fifth timing are simultaneous.

4. The semiconductor memory device according to claim 2,

the first timing and the fourth timing are simultaneous, and the fifth timing is later than the fourth timing.

5. The semiconductor memory device according to claim 2,

the fourth timing and the fifth timing are simultaneous, the fourth timing being later than the first timing.

6. The semiconductor memory device according to claim 2,

the first voltage is higher than a second voltage,

the second voltage is a voltage applied to the source line by the source voltage control unit when data is written into the selected memory cell.

7. The semiconductor memory device according to claim 6,

the source voltage control unit switches the voltage applied to the source line to the second voltage at the sixth timing.

8. The semiconductor memory device according to claim 6,

the source voltage control unit switches the voltage applied to the source line to the second voltage at a seventh timing between the sixth timing and the second timing.

Technical Field

The present embodiment relates to a semiconductor memory device.

Background

As a semiconductor storage device, a NAND flash memory is known.

Disclosure of Invention

The present embodiment provides a semiconductor memory device capable of improving the performance of operation and the reliability of memory cells.

The semiconductor memory device of the present embodiment includes: a semiconductor substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction; the well region is formed on the surface layer of the semiconductor substrate; and a source line formed on the well region on the surface of the semiconductor substrate. Further, the present invention also includes: a first selection gate line disposed above the well region and stacked in a third direction orthogonal to the first direction and the second direction; a plurality of word lines arranged above the first select gate lines and stacked in the third direction; and a second selection gate line disposed over the plurality of word lines, stacked in the third direction. Further comprising: a plurality of bit lines arranged over the second select gate lines and extending in the first direction; a memory cell array having a plurality of memory strings extending in the third direction and respectively connected between the corresponding bit lines and the source lines; a well voltage control unit for controlling a voltage applied to the well region; a source voltage control unit that controls a voltage applied to the source line; and a row decoder for switching application of voltages to the first selection gate line, the plurality of word lines, and the second selection gate line, respectively.

Before writing data to 1 memory cell included in the memory cell array, the row decoder applies a voltage to the first selection gate line, a selection word line, which is the word line connected to at least the 1 memory cell, among the plurality of word lines, and the word line arranged below the selection word line at a first timing to turn on the transistors connected to each other, switches the voltage applied to the first selection gate line at a second timing later than the first timing to turn off the transistors connected to the first selection gate line, and switches the voltage applied to the selection word line and the word line arranged below the selection word line at a third timing after the first timing to turn off the transistors connected to each other.

Further, the source voltage control unit applies the first voltage to the source line at a fourth timing between the first timing and the third timing. The well voltage control unit applies the first voltage to the well region at a fifth timing between the first timing and the second timing, and applies a ground voltage to the well region at a sixth timing between the fifth timing and the second timing.

Drawings

Fig. 1 is a block diagram showing an example of the configuration of a nonvolatile memory according to an embodiment of the present invention.

Fig. 2 is a diagram showing an example of a circuit configuration of a block of a memory cell array of a three-dimensional configuration NAND memory.

Fig. 3 is a cross-sectional view of a block of a memory cell array of a three-dimensional structure NAND memory.

Fig. 4 is a block diagram illustrating a voltage supply path to each wiring connected to the memory cell array.

Fig. 5 (a) and (b) are diagrams showing the procedure of writing data to a block.

Fig. 6 is a diagram showing potential changes of the respective wirings at the time of the channel precharge and the program operation in the comparative example.

Fig. 7 is a diagram showing potential changes of the respective wirings in the channel precharge and program operations in the first embodiment.

Fig. 8 is a diagram showing potential changes of the respective wirings in the channel precharge and program operations in the second embodiment.

Fig. 9 is a diagram showing potential changes of the respective wirings in the channel precharge and programming operations in the third embodiment.

Fig. 10 is a diagram showing potential changes of the respective wirings in the channel precharge and program operations in the fourth embodiment.

Fig. 11 is a diagram showing potential changes of the respective wirings in the channel precharging and programming operations in the fifth embodiment.

FIG. 12 is a threshold voltage distribution example of the nonvolatile memory 2 of 3 bit/Cell.

Fig. 13 is a diagram showing data encoding according to the present embodiment.

Fig. 14 is a diagram showing a potential change of each wiring in a programming operation.

Fig. 15 is a circuit diagram showing a state of the string unit SU in the programming operation.

Fig. 16 is a graph showing a relationship among the number of cycles, the program operation, and the verify operation in the sequence of the write operation.

Fig. 17 is a graph showing a relationship between the number of cycles and the bit line voltage in the sequence of the write operation.

Fig. 18 is a timing chart showing the voltage of the selected word line in the sequence of the write operation.

Description of the reference numerals

2: a non-volatile memory; 21: a NAND memory cell array; 22: an input-output circuit; 24: a logic control circuit; 26: a register; 27: a sequencer; 28: a voltage generation circuit; 30: a row decoder; 31: a sense amplifier unit; 32: a pad group for input and output; 34: a pad group for logic control; 35: a power input terminal group; 36: a CELSRC voltage control circuit; 37: a CPWELL voltage control circuit; 38: the output end is connected with the transistor; 100: a semiconductor substrate; 333. 332, 331: a wiring layer; 334: a memory aperture; 335: a barrier insulating film; 336: a charge storage layer; 337: a gate insulating film; 338: a conductor post; 339. 340, 341: and a contact plug.

Detailed Description

The embodiments are described below with reference to the drawings.

(first embodiment)

(1. formation)

(1-1. constitution of nonvolatile memory)

Fig. 1 is a block diagram showing an example of the configuration of the nonvolatile memory according to the present embodiment. The nonvolatile memory 2 as a semiconductor storage device includes: the memory cell array 21, the input/output circuit 22, the logic control circuit 24, the register 26, the sequencer 27, the voltage generation circuit 28, the row decoder 30, the sense amplifier unit 31, the pad group 32 for input/output, the pad group 34 for logic control, and the terminal group 35 for power input.

The memory cell array 21 includes a plurality of nonvolatile memory cell transistors (not shown) associated with word lines and bit lines.

The transmission/reception signal DQ < 7: 0> and the data strobe signal DQS,/DQS. The input-output circuit 22 outputs a signal DQ < 7: the command and address within 0> are transferred to the register 26. Further, write data and read data are transmitted and received between the input-output circuit 22 and the sense amplifier unit 31.

The logic control circuit 24 receives a chip enable signal/CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal/WE, read enable signals RE,/RE, and a write protect signal/WP from an external memory controller (not shown). Further, the logic control circuit 24 transmits a ready/busy signal/RB to the memory controller, and notifies the state of the nonvolatile memory 2 to the outside.

The voltage generation circuit 28 generates voltages necessary for operations such as writing, reading, and erasing of data based on a command from the sequencer 27.

The column decoder 30 receives a block address and a column address within an address from the register 26, selects a corresponding block based on the block address, and selects a corresponding word line based on the column address.

In reading data, the sense amplifier unit 31 senses read data read from the memory cell transistor to the bit line, and transfers the sensed read data to the input/output circuit 22. At the time of writing of data, the sense amplifier unit 31 transfers the write data written via the bit line to the memory cell transistor. The sense amplifier unit 31 has a plurality of sense amplifiers SA.

In order to transmit and receive signals including data to and from an external memory controller (not shown), the input/output pad group 32 includes a signal DQ < 7: 0> and a plurality of terminals (pads) corresponding to the data strobe signals DQS,/DQS.

The pad group 34 for logic control includes a plurality of terminals (pads) corresponding to a chip enable signal/CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal/WE, read enable signals RE,/RE, and write protect signals WP/WP for transmitting and receiving signals to and from an external memory controller (not shown).

The power supply input terminal group 35 includes a plurality of terminals to which power supply voltages Vcc, VccQ, Vpp and ground voltage Vss are input in order to supply various operation power supplies from the outside to the nonvolatile memory 2. The power supply voltage Vcc is a circuit power supply voltage generally applied from the outside as an operation power supply, and is, for example, a voltage of about 2.5V. As for the power supply voltage VccQ, for example, a voltage of 1.2V is input. The power supply voltage VccQ is used as a power supply for driving an input-output system for transmitting a reception signal between an external memory controller (not shown) and the nonvolatile memory 2.

The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of input 12V. For example, when the nonvolatile memory 2 is used in an environment where a high power supply voltage cannot be supplied, a voltage may not be supplied from the power supply voltage Vpp. Even when the power supply voltage Vpp is not supplied, various operations can be performed as long as the power supply voltage Vcc is supplied to the nonvolatile memory 2. That is, the power supply voltage Vcc is a power supply normally supplied to the nonvolatile memory 2, and the power supply voltage Vpp is a power supply additionally and arbitrarily supplied according to the usage environment, for example.

At the time of readout of data, the sense amplifier unit 31 detects data read out from the NAND memory cell array 21. Further, at the time of writing of data, the sense amplifier unit 31 temporarily stores the write data input from the memory controller, and transfers to the NAND memory cell array 21.

(1-2. constitution of memory cell array)

The memory cell array 21 of the three-dimensionally structured NAND memory includes a plurality of blocks. Fig. 2 is a diagram showing an example of a circuit configuration of a block in which a NAND memory is three-dimensionally structured. Fig. 3 is a cross-sectional view of a block of a three-dimensional configuration NAND memory. The other blocks of the memory cell array 21 also have the same circuit configuration as in fig. 2 and the same cross-sectional configuration as in fig. 3.

As shown in FIG. 2, the block BLK has, for example, 4 string units SU (SU 0-SU 3). Further, each string unit SU has a plurality of NAND strings NS. Each NAND string NS has, for example, 8 memory cell transistors MT (MT0 to MT7) and select gate transistors ST1, ST 2. The memory cell transistor MT includes a gate and a charge storage layer, and holds data in a nonvolatile manner.

The number of the memory cell transistors MT is not limited to 8, and may be, for example, 32, 48, 64, or 96. The select gate transistors ST1 and ST2 are represented as 1 transistor in circuit, and may be the same as the memory cell transistors in structure. In addition, in order to improve, for example, the off characteristics, a plurality of selection gate transistors may be used as the selection gate transistors ST1 and ST2, respectively. In addition, dummy cell transistors may be provided at positions where the periodicity of the memory cell transistors MT is disturbed, such as between the memory cell transistors MT and the select gate transistors ST1 and ST 2.

The memory cell transistor MT is arranged so as to be connected in series between the select gate transistors ST1 and ST 2. The memory cell transistor MT7 on one end side is connected to one end of the select gate transistor ST1, and the memory cell transistor MT0 on the other end side is connected to one end of the select gate transistor ST 2.

The gates of the select gate transistors ST1 of the string units SU0 to SU3 are connected to the select gate lines SGD0 to SGD3, respectively. On the other hand, the gates of the select gate transistors ST2 of the plurality of string units SU located in the same block BLK are commonly connected to the same select gate line SGS. In addition, the control gates of the memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. That is, word lines WL0 to WL7 and a select gate line SGS are commonly connected between the plurality of string units SU0 to SU3 in the same block BLK, and the select gate line SGD is independent of the string units SU0 to SU3 in the same block BLK.

Word lines WL0 to WL7 are connected to control gate electrodes of the memory cell transistors MT0 to MT7 constituting the NAND string NS, respectively, and the memory cell transistors MTi (i is 0 to n) in each NAND string NS are connected in common via the same word line WLi (i is 0 to n). That is, the control gate electrodes of the memory cell transistors MTi corresponding to each NAND string NS in the block BLK (the height in the direction of D3 is the same in fig. 3) are connected to the same word line WLi. In the following description, the NAND string NS may be simply referred to as a "string".

The other end (end on the side not connected to the memory cell transistor MT7) of the select gate transistor ST1 of the NAND string NS is connected to one of the m bit lines. In the same block BLK, the bit line BL is commonly connected to the NAND string NS at any one of the string units SU0 to SU 3. Further, bit lines BL are commonly connected with the corresponding NAND strings NS across a plurality of blocks BLK. The other end (end on the side not connected to the memory cell transistor MT 0) of the select gate transistor ST2 is connected to the source line CELSRC. The source line CELSRC is commonly connected to the NAND strings NS across the blocks BLK.

As described above, the data of the memory cells (memory cell transistors MT) located in the same block BLK are uniformly erased. On the other hand, data is read and written in units of the memory cell group MG (or in units of pages). In this specification, a plurality of memory cells connected to 1 word line WLi and belonging to 1 string unit SU are defined as a memory cell group MG. In the read operation and the write operation, 1 word line WLi and 1 select gate line SGD are selected in accordance with the physical address, and the memory cell group MG is selected.

In fig. 3, the direction D1 corresponds to the direction in which the bit line BL extends, the direction D2 corresponds to the direction in which the word line WL and the select gate lines SGD and SGS extend, and the direction D3 corresponds to the stacking direction of the word line WL and the select gate lines SGD and SGS. In addition, the D1 direction is parallel to the surface of the semiconductor substrate 100, the D2 direction is parallel to the surface of the semiconductor substrate 100 and orthogonal to the D1 direction, and the D3 direction is perpendicular to the surface of the semiconductor substrate 100 and orthogonal to the D1 direction and the D2 direction.

As shown in fig. 3, a plurality of NAND strings NS are formed on the P-type well region (P-well). That is, a plurality of wiring layers 333 functioning as the selection gate lines SGS, a plurality of wiring layers 332 functioning as the word lines WLi, and a plurality of wiring layers 331 functioning as the selection gate lines SGD are stacked on the p-type well region.

Memory holes 334 are formed to penetrate the wiring layers 333, 332, and 331 and reach the p-type well region. A barrier insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the side surfaces of the memory hole 334, and a conductive pillar 338 is filled in the memory hole 334. The conductive body column 338 is made of, for example, polysilicon, and functions as a region where a channel is formed when the memory cell transistor MT and the select gate transistors ST1 and ST2 included in the NAND string NS operate.

In each NAND string NS, a select gate transistor ST2, a plurality of memory cell transistors MT, and a select gate transistor ST1 are formed on a p-type well region. A wiring layer functioning as a bit line BL is formed above the conductive pillar 338. A contact plug 339 for connecting the conductive body pillar 338 and the bit line BL is formed on the upper side of the conductive body pillar 338.

In addition, an n + -type impurity diffusion layer and a p + -type impurity diffusion layer are formed in the surface of the p-type well region. Contact plug 340 is formed on the n + -type impurity diffusion layer, and a wiring layer functioning as a source line CELSRC is formed on contact plug 340. Further, a contact plug 341 is formed on the p + -type impurity diffusion layer, and a wiring layer functioning as a well line CPWELL is formed on the contact plug 341.

The above configuration shown in fig. 3 is arranged in plural in the depth direction (direction D2) of the paper surface of fig. 3, and 1 string unit SU is formed by a set of plural NAND strings arranged in a row in the depth direction.

(1-3. Voltage supply to respective wirings connected to the memory cell array)

Fig. 4 is a block diagram illustrating a voltage supply path to each wiring of the memory cell array. The voltage generation circuit 28 includes a plurality of SG drivers 28A that supply voltages to the signal lines SG0 to SG4, respectively, and a plurality of CG drivers 28B that supply voltages to the signal lines CG0 to CG7, respectively. These signal lines SG0 to SG4 and CG0 to CG7 are branched by the column decoder 30 and connected to the wirings of the blocks BLK. That is, the signal lines SG0 to SG3 function as global drain side select gate lines, and are connected to the select gate lines SGD0 to SGD3 as local select gate lines in each block BLK via the row decoder 30. The signal lines CG0 to CG7 function as global word lines and are connected to word lines WL0 to WL7 as local word lines in each block BLK via the row decoder 30. Signal line SG4 functions as a global source side select gate line, and is connected to a select gate line SGs serving as a local select gate line in each block BLK via row decoder 30.

The voltage generation circuit 28 is controlled by the sequencer 27 to generate various voltages. The SG driver (selection gate line driver) 28A and the CG driver (word line driver) 28B supply the generated voltages to the corresponding signal lines SG0 to SG4 and CG0 to CG7, respectively.

For example, each CG driver 28B selects and supplies one of the voltages VPGM and VPASS according to the corresponding signal line CG and word line WL in accordance with the target of the operation (row address) in the write operation. The CG driver 28B connected to the signal line CG corresponding to the word line WLn to be subjected to the write operation supplies the voltage VPGM. The CG drivers 28B connected to the signal lines CGn ± 1, CGn ± 2 and the like corresponding to the other word lines WLn ± 1, WLn ± 2 and the like supply the voltage VPASS. The voltage VPASS is a voltage that turns on the memory cell transistor MT. The voltage VPGM is a voltage for injecting electrons into the charge storage layer using a tunneling phenomenon, and VPGM > VPASS.

The column decoder 30 includes a plurality of switch circuit groups 30A corresponding to the respective blocks, and a plurality of block decoders 30B provided corresponding to the switch circuit groups 30A. Each switching circuit group 30A includes a plurality of transistors TR _ SG0 to TR _ SG3 that respectively connect signal lines SG0 to SG3 to select gate lines SGD0 to SGD3, a plurality of transistors TR _ CG0 to TR _ CG7 that respectively connect signal lines CG0 to CG7 to word lines WL0 to WL7, and a transistor TR _ SG4 that connects signal line SG4 to select gate line SGs. The transistors TR _ SG0 to TR _ SG4 and the transistors TR _ CG0 to TR _ CG7 are high voltage resistant transistors.

When the block decoder 30B is designated by the row address, the block selection signal BLKSEL is supplied to the gates of the transistors TR _ SG0 to TR _ SG4 and the transistors TR _ CG0 to TR _ CG 7. Thus, in the switching circuit group 30A that receives the block selection signal BLKSEL from the block decoder 30B specified by the row address, the transistors TR _ SG0 to TR _ SG4 and the transistors TR _ CG0 to TR _ CG7 are turned on, and therefore, the voltages supplied from the voltage generation circuit 28 to the signal lines SG0 to SG4 and the signal lines CG0 to CG7 are supplied to the selection gate lines SGD0 to SGD3, SGs, and the word lines WL0 to WL7 included in the block BLK to be operated.

That is, the voltage generation circuit 28 and the row decoder 30 supply the voltage VPGM to the selected word line WLn and supply the voltage VPASS to the other unselected word lines WLn ± 1, WLn ± 2, and the like. For example, the voltage VSG1 is supplied to the select gate line SGD (SGD _ sel) connected to the select gate transistor ST1 belonging to the operation-subject string unit SU, the voltage VSG2 is supplied to the select gate line SGD (SGD _ usel) connected to the select gate transistor ST1 not belonging to the operation-subject string unit SU, and the voltage VSG3 is supplied to the select gate line SGS connected to the select gate transistor ST2 in each block BLK. The voltage generation circuit 28 and the row decoder 30 function as a row voltage control unit.

The voltage VSG1 is a voltage that turns on the select gate transistor ST1 connected to the bit line BL to which data "0" is applied and turns off the select gate transistor ST1 connected to the bit line BL to which data "1" is applied. In the programming operation, an operation of raising the threshold voltage of the memory cell transistor MT is referred to as "programming 0" or "writing 0'", and data "0" is given to the bit line BL to be programmed with "0". On the other hand, the operation of maintaining the threshold voltage of the memory cell transistor MT is referred to as "1" programming "," writing "1'", or "write inhibit", and data "1" is given to the bit line BL to be programmed with "1". The ground voltage Vss (e.g., 0V) at the "L" level is applied to the bit line BL to which the data "0" is given. The "H" level, for example, 2.5V is applied to the bit line BL to which the data "1" is given.

Further, the voltage VSG2 is a voltage (for example, ground voltage Vss) that turns off the select gate transistor ST 1. The voltage VSG3 is a voltage (e.g., ground voltage Vss) that turns off the select gate transistor ST 2.

The CELSRC voltage control circuit 36 receives the power supply voltage Vcc from the power supply input terminal group 35, and controls the voltage supplied to the source line CELSRC. The source lines CELSRC are commonly connected to the blocks BLK. The CPWELL voltage control circuit 37 receives the ground voltage Vss from the power input terminal group 35, and supplies the ground voltage Vss to the well line CPWELL. In addition, the well line CPWELL is also commonly connected to each block BLK. The source line CELSRC and the well line CPWELL are connected via the output terminal connection transistor 38. The CPWELL voltage control circuit 37 and the output terminal connection transistor 38 function as a well voltage control unit.

When the voltage of the well line CPWELL is raised to the same value as the voltage of the source line CELSRC, the output-side connection transistor 38 is turned on. That is, when the voltage of the well line CPWELL is increased to the same value as the voltage of the source line CELSRC, the output-side connection transistor 38 is turned on to short-circuit the source line CELSRC and the well line CPWELL. By short-circuiting the source line CELSRC, the coupling capacitance between the source line CELSRC and the well line CPWELL disappears, and therefore, the voltage rise of the source line CELSRC can be accelerated. The CELSRC voltage control circuit 36 functions as a source voltage control unit.

(1-4. threshold voltage distribution of memory cell transistor)

Fig. 12 is a diagram showing an example of a threshold voltage region in the present embodiment. In FIG. 12, an example of threshold voltage distribution of the nonvolatile memory 2 of 3bit/Cell is shown. In the nonvolatile memory 2, information is stored by the amount of charge stored in the charge storage film of the memory cell. Each memory cell has a threshold voltage corresponding to the amount of charge. Then, the plurality of data values stored in the memory cell are associated with a plurality of regions of threshold voltage (threshold voltage regions), respectively.

The 8 distributions (mountain shapes) described as Er, a, B, C, D, E, F, and G in fig. 12 show threshold voltage distributions in the respective threshold regions in the 8 threshold regions. In this manner, each memory cell has a threshold voltage distribution divided by 7 boundaries. The horizontal axis of fig. 12 shows the threshold voltage, and the vertical axis shows the distribution of the number of memory cells (number of cells).

In this embodiment, a region having a threshold voltage of Vr1 or less is referred to as a region Er, a region having a threshold voltage of more than Vr1 and no more than Vr2 is referred to as a region a, a region having a threshold voltage of more than Vr2 and no more than Vr3 is referred to as a region B, and a region having a threshold voltage of more than Vr3 and no more than Vr4 is referred to as a region C. In this embodiment, a region having a threshold voltage higher than Vr4 and no greater than Vr5 is referred to as a region D, a region having a threshold voltage higher than Vr5 and no greater than Vr6 is referred to as a region E, a region having a threshold voltage higher than Vr6 and no greater than Vr7 is referred to as a region F, and a region having a threshold voltage higher than Vr7 is referred to as a region G.

The threshold voltage distributions corresponding to the regions Er, a, B, C, D, E, F, and G are referred to as distributions Er, a, B, C, D, E, F, and G (first to eighth distributions), respectively. Vr1 to Vr7 are threshold voltages at the boundaries of the respective regions.

In the nonvolatile memory 2, a plurality of data values are associated with a plurality of threshold voltage regions (i.e., threshold voltage distributions) of memory cells, respectively. This correspondence is called data encoding. The data code is predetermined, and at the time of writing (programming) of data, charges are injected into the memory cell so as to fall within a threshold voltage region corresponding to the stored data value in accordance with the data code. At the time of reading, a read voltage is applied to the memory cell, and data is determined according to whether the threshold voltage of the memory cell is lower or higher than the read voltage.

Fig. 13 is a diagram showing data encoding according to the present embodiment. In the present embodiment, 8 threshold voltage distributions (threshold voltage regions) shown in fig. 12 are associated with 8 data values of 3 bits, respectively. The relationship between the threshold voltage and the data value of the bit corresponding to the upper, middle, and lower pages is as follows.

The memory cell having the threshold voltage in the Er region is in a state of storing "111".

The memory cell having the threshold voltage in the a region stores "101".

The memory cell having the threshold voltage in the B region stores "001".

The memory cell having a threshold voltage in the C region is in a state of storing "011".

The memory cell having the threshold voltage in the D region stores "010".

The memory cell having the threshold voltage in the E region is in a state of storing "110".

The memory cell having the threshold voltage in the F region stores "100".

The memory cell having the threshold voltage in the G region stores "000".

In this manner, each region of the threshold voltage can represent the state of 3-bit data of each memory cell. In addition, when the memory cell is in an unwritten state (an "erased" state), the threshold voltage of the memory cell is in the Er region. In the symbols shown here, only 1-bit data changes between any 2 adjacent states, as in the case of storing "111" data in the Er (erase) state and "101" data in the a state. As described above, the coding shown in fig. 6 is a gray code in which only 1bit of data changes between arbitrary 2 adjacent regions.

(2. act)

(2-1. concrete example of write operation)

First, the writing operation according to the present embodiment will be briefly described. The write action includes a program action and a verify action.

The programming operation is an operation of raising a threshold voltage by injecting electrons into the charge storage layer (or maintaining the threshold voltage by inhibiting injection). Hereinafter, the operation of raising the threshold voltage is referred to as "programming" 0 "or" writing "0'", and data "0" is given to the bit line BL to be programmed with "0". On the other hand, the operation of maintaining the threshold voltage is referred to as "1" programming "," writing "1'", or "write inhibit", and data "1" is given to the bit line BL to be programmed with "1".

The verify operation is an operation of determining whether or not the threshold voltage of the memory cell transistor MT has reached a target level by reading data after the program operation. The memory cell transistor MT which has reached the target level is thereafter inhibited from writing.

By repeating the above combination of the programming action and the verifying action, the threshold voltage of the memory cell transistor MT rises to the target level.

Fig. 14 shows a potential change of each wiring in the programming operation. As shown, program data is first transferred to each bit line BL. Specifically, the ground voltage Vss (e.g., 0V) is applied as the "L" level to the bit line BL to which the data "0" is given, and the "H" level, e.g., 2.5V, is applied to the bit line BL to which the data "1" is given.

Further, the potential of the selection gate line SGD _ sel in the selection string unit SU _ sel in the selection block BLK is made 2.5V, for example. This potential is a voltage that turns on the select gate transistor ST1 corresponding to the bit line BL to which data "0" (0V) is applied and turns off the select gate transistor ST1 corresponding to the bit line BL to which data "1" (2.5V) is applied. On the other hand, the voltage Vss is applied to the select gate line SGD _ usel in the non-select string unit SU _ usel in the select block BLK, and the select gate transistor ST1 becomes off. Further, the voltage Vss is also applied to the select gate line SGS in the select block BLK, and the select gate transistor ST2 is turned off.

Then, a voltage VPGM is applied to the selected word line WL _ sel in the selected block BLK, and a voltage VPASS is applied to the other unselected word lines WL _ usel. The voltage VPGM is a voltage for injecting electrons into the charge storage layer using a tunneling phenomenon, and VPGM > VPASS.

Fig. 15 shows the pattern of the string unit SU in the programming action. In fig. 15, 2 NAND strings corresponding to the bit line BL targeted for the "0" program action and the bit line BL targeted for the "1" program action (non-program object) are illustrated. Since the word line WL3 is selected, the voltage VPGM is applied to the selected word line WL3, and the voltage VPASS is applied to the unselected word lines WL0 to WL2 and WL4 to WL 7.

In the NAND string corresponding to the bit line BL targeted for the "0" program operation, the select-gate transistor ST1 is turned on. Therefore, the channel potential Vch of the memory cell transistor MT3 connected to the selected word line WL3 becomes 0V. As a result, a potential difference between the gate and the channel increases, and as a result, electrons are injected into the charge storage layer, so that the threshold voltage of the memory cell transistor MT3 increases.

On the other hand, in the NAND string corresponding to the bit line BL targeted for the "1" program operation (non-program target), the select gate transistor ST1 is turned off. Therefore, the channel of the memory cell transistor MT3 connected to the selected word line WL3 is electrically floated, and the channel potential Vch rises (becomes a channel boost state) due to capacitive coupling with the word line WL and the like. As a result, electrons are not injected into the charge storage layer, and the threshold voltage of the memory cell transistor MT3 is maintained (the threshold voltage does not fluctuate to such an extent that the threshold voltage distribution level shifts to a higher threshold voltage distribution).

(2-2. sequence on write action)

Next, a sequence of the write operation of the present embodiment will be described. Fig. 16 and 17 show an example of a case where data is written by repeating a combination of a program operation and a verify operation 19 times. This repetitive action is called a "loop".

Fig. 16 shows target levels of the verify operation performed in each cycle. As shown in the figure, the verification operation is performed for only the "a" level in the first and second cycles. That is, in the verify operation, the voltage VfyA is applied to the selected word line WL, and the voltages VfyB to VfyG are not applied. In the next third and fourth cycles, the verify operation is performed for the "a" level and the "B" level. That is, in the verify operation, the voltages VfyA and VfyB are sequentially applied to the selected word line WL, and the voltages VfyC to VfyG are not applied.

In the fifth and sixth cycles, the verify operation is performed for the "a" level, the "B" level, and the "C" level. That is, during the verify operation, the voltages VfyA, VfyB, and VfyC are applied to the selected word line WL in this order, and the voltages VfyD to VfyG are not applied. Then, the verify operation for the "a" level is performed until the sixth cycle. This is because it is known from experience that programming for the "a" level is substantially complete after, for example, 6 cycles.

In the seventh and eighth cycles, the verify operation is performed for the "B" level, the "C" level, and the "D" level. That is, the voltages VfyB, VfyC, and VfyD are sequentially applied to the selected word line WL during the verify operation. The verify operation for the "B" level is performed until the eighth program operation. In the ninth and tenth cycles, the verify operation is performed for the "C" level, the "D" level, and the "E" level. That is, the voltages VfyC, VfyD, and VfyE are sequentially applied to the selected word line WL during the verify operation. Then, the verify operation for the "C" level is performed until the tenth cycle.

In the same manner, the verify operation is performed until the "G" level is written, and the cycle is repeated 19 times at most.

Fig. 17 corresponds to fig. 16, and shows the state of the bit line corresponding to the target level of the threshold voltage in each cycle. In fig. 17, the label "1" means that data "1" is assigned to the corresponding bit line BL, and the label "0" means that data "0" is assigned.

As shown in the figure, in the case where the threshold voltage of the memory cell transistor MT should be maintained at the "Er" level, data "1" is given to the bit line BL in all cycles. That is, in the write operation period, the select gate transistor ST1 is always turned off.

When the target level of the threshold voltage is the "a" level, that is, the memory cell transistor MT whose threshold voltage is increased from the value in the "Er" level to the value in the "a" level, the "0" programming operation can be performed in the first to sixth cycles. This corresponds to a cycle in which the verify operation for the "a" level is performed. The bit line BL is given data "0" until the verify operation is passed, and is given data "1" after the pass. In the cycle after the seventh programming operation, data "1" is given to the bit line BL, and writing is inhibited.

When the target level is the "B" level, that is, the memory cell transistor MT whose threshold voltage is increased from a value within the "Er" level to a value within the "B" level, the "0" programming operation can be performed in the first to eighth cycles. This corresponds to a cycle in which the verify operation for the "B" level is performed. In the third to eighth cycles, data "0" is given to the bit line BL until the verify operation is passed, and data "1" is given after the pass. In the ninth and subsequent cycles after the completion of the programming operation, data "1" is given to the bit line BL, and writing is inhibited.

Thereafter, the program operation to the "C" to "G" levels is similarly performed.

Fig. 18 shows the potential of the selected word line in the above operation. In each cycle, after a program operation is performed by applying a voltage VPGM to the selected word line WL, a verify operation is performed by applying voltages VfyA to VfyG of levels corresponding to the cycle in advance.

(2-3. data write sequence)

Next, a description will be given of a data writing sequence in the NAND memory cell array 21. Fig. 5 is a diagram showing a data writing sequence to a block. Fig. 5 (a) shows a write sequence in the case of writing data from the source side to the drain side, and fig. 5 (b) shows a write sequence in the case of writing data from the drain side to the source side.

As shown in fig. 5 (a), when data is written from the source side to the drain side, first, a write operation is performed on the memory cell group MG corresponding to the word line WL0 in the string unit SU 0. Specifically, in the programming operation, the voltage VSG1 is applied to the select gate line SDG0, and the voltage VSG2 is applied to the select gate lines SDG1 to SGD 3. A voltage VPGM is applied to the selected word line WL0, and a voltage VPASS is applied to the unselected word lines WL 1-WL 7. Next, a write operation is performed on the memory cell group MG corresponding to the word line WL0 in the string unit SU 1. Specifically, in the programming operation, the voltage VSG1 is applied to the select gate line SDG1, and the voltage VSG2 is applied to the select gate lines SDG0, SGD2, and SGD 3. A voltage VPGM is applied to the selected word line WL0, and a voltage VPASS is applied to the unselected word lines WL 1-WL 7. Next, similarly, writing to the memory cell group MG corresponding to the word line WL0 in the string unit SU2 and writing to the memory cell group MG corresponding to the word line WL0 in the string unit SU3 are performed sequentially.

After the write of the word line WL0 of all the string units SU within the selection block BLK is completed, the write of the word line WL1 is transferred. Similarly to the writing of the word line WL0, the writing of the word line WL1 is also performed in the order of the string unit SU0 → the string unit SU1 → the string unit SU2 → the string unit SU 3. In this manner, writing is performed sequentially from the word line WL0 located on the source side (lower side in the direction of D3) to the word line WL7 located on the drain side (upper side in the direction of D3).

On the other hand, as shown in fig. 5 (b), when data is written from the drain side to the source side, first, a write operation is performed on the memory cell group MG corresponding to the word line WL7 in the string unit SU 0. Specifically, in the programming operation, the voltage VSG1 is applied to the select gate line SDG0, and the voltage VSG2 is applied to the select gate lines SDG1 to SGD 3. A voltage VPGM is applied to the selected word line WL7, and a voltage VPASS is applied to the unselected word lines WL 0-WL 6. Next, a write operation is performed on the memory cell group MG corresponding to the word line WL7 in the string unit SU 1. Specifically, in the programming operation, the voltage VSG1 is applied to the select gate line SDG1, and the voltage VSG2 is applied to the select gate lines SDG0, SGD2, and SGD 3. A voltage VPGM is applied to the selected word line WL7, and a voltage VPASS is applied to the unselected word lines WL 0-WL 6. Next, similarly, writing to the memory cell group MG corresponding to the word line WL7 in the string unit SU2 and writing to the memory cell group MG corresponding to the word line WL7 in the string unit SU3 are performed sequentially.

After the write of the word line WL7 is completed for all the string units SU within the selection block BLK, the write of the word line WL6 is transferred. Similarly to the writing of the word line WL7, the writing of the word line WL6 is also performed in the order of the string unit SU0 → the string unit SU1 → the string unit SU2 → the string unit SU 3. In this manner, writing is performed sequentially from the word line WL7 located on the drain side (upper side in the direction of D3) to the word line WL0 located on the source side (lower side in the direction of D3).

(2-4. channel precharge action)

The memory cell array 21 of the present embodiment has a three-dimensional structure, and each NAND string NS is formed in a columnar shape in the memory hole 334 as shown in fig. 3. Therefore, the channel of the memory cell transistor MT included in each NAND string NS may vary.

Thus, when a program operation is performed on a certain memory cell group MG (page), the channel boosting in the NAND string NS corresponding to the bit line BL which is the target of the "1" program operation (non-program target) may be affected by the potential of the channel of the memory cell transistor MT. In particular, when the channel of the memory cell transistor MT has a potential that is negative (smaller than the ground voltage Vss) at the start time of the programming operation, even if the channel potential is boosted by capacitive coupling, the potential difference between the channel and the gate of the memory cell transistor MT may become larger than the potential difference necessary for injecting electrons from the channel into the charge storage layer. That is, there is a possibility that erroneous writing (program crosstalk) to the memory cell transistor MT which is not the target of the program operation occurs.

As shown in fig. 2 and 3, in the three-dimensional memory cell array 21 of the present embodiment, a plurality of string units SU are included in 1 block BLK, and each word line is commonly connected to the plurality of string units SU. As a result, in the selected block BLK, there are string units SU (selected string units SU _ sel) including the memory cell group MG (page) to be subjected to the write operation and string units SU (unselected string units SU _ usel) not including the memory cell group MG to be subjected to the write operation.

In the write operation, since the voltage VSG2 is applied to the select gate line SDG corresponding to the non-selected string unit SU _ usel, the select gate transistor ST1 is turned off. Further, the voltage VSG3 is applied to the select gate line SGS of the selected block BLK, and thus the select gate transistor ST2 becomes an off state. That is, the channel of the NAND string NS in the non-selected string unit SU _ usel is in a floating state independent of potential. In this state, if the voltage VPGM is applied to the selected word line WLn, the potential of the channel of the NAND string NS in the non-selected string unit SU _ usel is boosted (becomes a state in which the channel is boosted) due to capacitive coupling. Thus, the potential difference between the gate of the memory cell transistor MT and the channel of the NAND string NS in the non-selected string unit SU _ usel is suppressed to be small, and writing is not performed.

However, regarding the NAND string NS in the non-selected string unit SU _ usel, when the channel of the memory cell transistor MT has a negative (lower than the ground voltage Vss) potential at the start time point of the programming operation, even if the channel potential is boosted by the capacitive coupling, the potential difference between the channel and the gate of the memory cell transistor MT may be larger than the potential difference necessary for injecting electrons from the channel into the charge storage layer. That is, there is a possibility that erroneous writing (program crosstalk) to the memory cell transistor MT of the non-selected string unit SU _ usel occurs.

In order to improve the program crosstalk, it is conceivable to perform an operation (a channel precharge operation) of stabilizing an initial potential of a channel of the NAND string NS in the non-selected string unit SU _ usel before applying the voltage VPGM to the selected word line WL _ sel.

As a method of raising the initial potential of the channel, for example, there are a method of applying a potential from the bit line BL (a channel precharge operation from the bit line side) and a method of applying a potential from the source line CELSRC (a channel precharge from the source line side).

When a potential is applied from the source line CELSRC, the select gate transistor ST2 is turned on, and the memory cell transistors MT connected to the word lines WL0 to WLn are turned on. When the memory cell transistors MT connected to the word lines WL0 to WLn are written and the threshold voltage rises, a high voltage (for example, 8V) that causes the memory cell transistors MT to be in a conductive state regardless of the threshold voltage needs to be applied to the word lines WL0 to WLn. On the other hand, in the case where the memory cell transistors MT connected to the word lines WL0 to WLn are unwritten and the threshold voltage does not rise, the voltage applied to the word lines WL0 to WLn may be about 1V. As shown in fig. 5 (b), if data is written from the drain side to the source side, the memory cell transistors MT connected to the word lines WL0 to WLn are in an unwritten state during channel precharge. Thus, when the channel is precharged from the source line side, by writing data from the drain side to the source side as shown in fig. 5 (b), the voltage applied to the word lines WL0 to WLn can be made low, and reduction in power consumption and increase in operation speed can be achieved.

(2-5. potential variation of each wiring in channel precharging and data writing)

Next, the potential of each line in the selection block BLK at the time of channel precharge will be described. Fig. 6 is a diagram showing potential changes of the respective wirings in the selection block BLK at the time of the channel precharge and programming operation in the comparative example. In fig. 6, a period from time t0 to time t2 is a period during which a channel precharge operation is performed (hereinafter, referred to as a channel precharge period). The time t2 is followed by a period of time during which the voltage VPGM is applied (hereinafter referred to as a programming period). Hereinafter, the channel precharge period and the program period are also collectively expressed as a period of the program operation. In this embodiment, a time t2 before the start of boosting of the select gate line SGD _ sel is referred to as a channel precharge period, and a time t2 and later is referred to as a program period.

In each of fig. 6 and subsequent figures, the selected word line WLn is denoted as a selected word line WL _ sel, and the unselected word lines (unselected word lines WLn-1, WLn-2, etc.) located on the source side of the selected word line WL _ sel among the unselected word lines WLn ± 1, WLn ± 2, etc. are denoted as source-side unselected word lines WL _ usel(s). Non-selected word lines (non-selected word lines WLn +1, WLn +2, etc.) among the non-selected word lines WLn ± 1, WLn ± 2, etc., which are located on the drain side than the selected word line WL _ sel are shown as drain-side non-selected word lines WL _ usel (d). The same description will be made in the following description.

First, a potential change in the channel precharge period is explained. At time t0, the ground voltage Vss (e.g., 0V) is applied from the voltage generation circuit 28 to the select gate line SGD via the row decoder 30, and the select gate transistor ST1 is turned off. On the other hand, the select gate transistor ST2 is turned on by applying, for example, 5V to the select gate line SGS.

Further, the voltage generation circuit 28 applies, for example, 1V to the selected word line WL _ sel and the source side unselected word line WL _ usel(s) via the row decoder 30, and turns on the memory cell transistor MT connected to these word lines. On the other hand, the ground voltage Vss (e.g., 0V) is applied to the drain-side unselected word line WL _ usel (d), and the memory cell transistor MT connected to these word lines is turned off.

The CELSRC voltage control circuit 36 applies, for example, 2V as a precharge voltage to the source line CELSRC. Further, the CPWELL voltage control circuit 37 applies the ground voltage Vss (e.g., 0V) to the well line CPWELL.

That is, the potential of the channel of the memory cell transistor MT connected to the selected word line WL _ sel and the source side unselected word line WL _ usel(s) is boosted (stabilized, precharged) by the potential supplied from the source line CELSRC.

Next, at time t1(< t2), the ground voltage Vss (e.g., 0V) is applied to the select gate line SGS, and the select gate transistor ST2 is turned off. In addition, a ground voltage Vss (e.g., 0V) is applied to the selected word line WL _ sel and the source-side unselected word line WL _ usel(s), and the memory cell transistor MT connected to these word lines is turned off.

Next, the application of the voltage VPGM as a voltage for writing data to the selected word line WL _ sel is started. At time t2, by applying, for example, 2.5V to the select gate line SGD _ sel of the select string unit SU _ sel, the select gate transistor ST1 is turned on or off in accordance with the potential of the bit line BL. The select gate line SGS _ sel of the select string unit SU _ sel still maintains the ground voltage Vss (e.g., 0V), and the select gate transistor ST2 continues to maintain the off-state.

On the other hand, the selection gate line SGD _ usel and the selection gate line SGS _ sel of the non-selection string unit SU _ usel still maintain the ground voltage Vss (e.g., 0V). Thereby, the select gate transistors ST1, ST2 of the unselected string units SU _ usel continue to maintain the off state.

Next, a voltage VPGM is applied to the selected word line WL _ sel, and a voltage VPASS is applied to the unselected word lines WL _ usel. In the NAND string NS including the memory cell transistor MT as a write target in the selected string unit SU _ sel, the select gate transistor ST1 on the bit line side is in an on state, and thus the potential of the bit line BL is transmitted to the channel of each NAND string NS of the selected string unit SU _ sel. Therefore, after the voltage VPGM is applied to the selected word line WL _ sel, the threshold voltage of the selected memory cell transistor MT rises in accordance with the voltage VPGM. (data writing to the selected memory cell transistor MT is performed.)

On the other hand, in the NAND string NS in the selected string unit SU _ sel which does not include the memory cell transistor MT as the write target and in the NAND string NS in the unselected string unit SU _ usel, the bit line side select gate transistor ST1 and the source side select gate transistor ST2 are both in an off state, and therefore the channels are in a floating state independent of potential. In this state, if the voltage VPGM is applied to the selection word line WL _ sel, the potential of the channel of the NAND string NS is boosted due to capacitive coupling. Thus, the potential difference between the gate of the memory cell transistor MT and the channel of the NAND string NS in the unselected string unit SU _ usel is small, and thus undesired writing (injection of electrons, increase in threshold voltage) is suppressed.

Here, since the select gate line SGS is connected to all the string units SU in the block BLK, it has a relatively large parasitic capacitance. This requires a relatively long time to raise and lower the potential. In the comparative example shown in fig. 6, in the channel precharge period, the potential of the selection gate line SGS rises gently from time t0, and it takes a certain time until it rises to the applied potential (e.g., 5V). Further, it takes a certain time until the potential of the select gate line SGS gradually decreases from time t1 and decreases to the applied potential (ground potential Vss). That is, the select gate transistor ST2 becomes on after a certain time has elapsed from the time t0, and becomes off after a certain time has elapsed from the time t 1. In this case, at the start of the program period at time t2, the potential of the select gate line SGS may not be completely lowered, and the select gate transistor ST2 may be in an on state. In such a case, the channel potential is discharged from the source side, and the initial potential is lowered (the boosting of the channel potential is discharged). Accordingly, the channel precharge effect is reduced, and there is a possibility that erroneous writing occurs in the memory cell transistor MT which is not a target of writing. Further, if the boosting of the selected word line WL _ sel, the unselected word line WL _ usel, and the select gate line SGD _ sel is started after waiting for the select gate transistor ST2 to become the off state, the operation time from the start of the channel precharge to the completion of the programming (the period of the programming operation) becomes long after time t2 as the start point of the programming period.

Fig. 7 is a diagram showing potential changes of the respective wirings in the selected block BLK in the channel precharge and programming operation in the first embodiment. The potential change of each wiring in the programming period in this embodiment mode is the same as the comparative example shown in fig. 6. The present embodiment is different from the comparative example in that a voltage for boosting and stepping down the auxiliary selection gate line SGS is applied to the well line CPWELL in the channel precharge period.

In the present embodiment, first, at time t0, the output connection transistor 38 is switched on, so that the well line CPWELL and the source line CELSRC are at the same potential. That is, the same voltage (e.g., 2V) as the precharge voltage is applied to the well line CPWELL. Then, at time t1, the ground voltage Vss (e.g., 0V) is applied to the select gate line SGS. Next, at time t11 which is later than time t1 by a predetermined time Δ ta1, the output terminal connection transistor 38 is turned off, whereby the well line CPWELL is disconnected from the source line CELSRC, and the ground voltage Vss (for example, 0V) is applied to the well line CPWELL from the CPWELL voltage control circuit 37. At time t11, the potential of the well line CPWELL decreases from 2V to the ground potential Vss, and the assist effect due to the capacitive coupling between the well line CPWELL and the select gate line SGS acts, accelerating the discharge (potential decrease) of the select gate line SGS.

That is, at the start of the program period at time t2, the potential of the select gate line SGS can be sufficiently lowered, and the select gate transistor ST2 can be reliably turned off, so that writing can be performed while maintaining the initial potential of the channel that has been charged by channel precharge, and erroneous writing in the memory cell transistor MT that is not the target of writing can be suppressed. This can improve the reliability of the memory cell. Further, according to this embodiment, since the select gate transistor ST2 can be quickly turned off, the channel precharge period can be controlled to be shorter, and the program start timing (t2) can be advanced. In other words, the time period for the programming operation can be shortened, and the performance of the operation can be improved.

In this embodiment, as shown in fig. 5 (b), data writing is performed from the drain side to the source side. Thus, the threshold voltage of the memory cell transistor MT does not increase in the range from the source line side word line WL0 to the write target word line WLn. This can reduce the voltage applied to the word lines WL0 to WLn during the precharge operation, thereby reducing power consumption and increasing the operation speed.

In this embodiment, the initial potential of the channel is applied from the source line CELSRC, not the bit line BL. This enables the operation of setting the bit line BL to the potential corresponding to the write data to be performed in parallel with the precharge operation, and the time period for the program operation can be further shortened.

(second embodiment)

Next, a semiconductor memory device according to a second embodiment of the present invention will be described. The semiconductor memory device of the present embodiment is different from the first embodiment in timing of applying a voltage to the select gate line SGS and the well line CPWELL in the channel precharge period. The configuration of the semiconductor device and the potential change of other wirings are the same as those in the first embodiment, and therefore, the description thereof is omitted. Hereinafter, the potential application timing to the selection gate line SGS and the well line CPWELL in the channel precharge period will be described.

Fig. 8 is a diagram showing potential changes of the respective wirings in the channel precharge and program operations in the second embodiment. First, at time t0, for example, 5V is applied to the select gate line SGS to turn on the select gate transistor ST2, and the potential of the select gate line SGS is raised. Next, at time t01 later than time t0 by a predetermined time Δ tb, the output connection transistor 38 is switched on, so that the well line CPWELL is at the same potential as the source line CELSRC. That is, the same voltage (e.g., 2V) as the precharge voltage is applied to the well line CPWELL.

By applying a voltage to the well line CPWELL later than the timing of applying a voltage to the select gate line SGS by a predetermined time, an assist effect by capacitive coupling between the well line CPWELL and the select gate line SGS is exerted, and charging (potential rise) of the select gate line SGS is accelerated. Therefore, the selection gate transistor ST2 can be turned on more quickly than in the first embodiment.

Next, in order to turn off the select gate transistor ST2, at time t02, the ground voltage Vss (e.g., 0V) is applied to the select gate line SGS. Since the select gate transistor ST2 is switched to the on state faster than in the first embodiment, the time t02 can be set earlier than the time t1 by the predetermined time Δ ta 2. Finally, at time t1, the output connection transistor 38 is turned off, thereby disconnecting the well line CPWELL from the source line CELSRC, and applying the ground voltage Vss (e.g., 0V) to the well line CPWELL from the CPWELL voltage control circuit 37. At time t1, the potential of the well line CPWELL decreases from 2V to the ground potential Vss, and the assist effect due to the capacitive coupling between the well line CPWELL and the select gate line SGS acts, accelerating the discharge (potential decrease) of the select gate line SGS.

That is, according to the present embodiment, the increase in the potential of the select gate line SGS can be accelerated by the assist effect of the boosting of the well line CPWELL, and therefore the fall start timing (time t02) of the potential of the select gate line SGS can be advanced. Thus, the period until the program start time (time t2) is long, and the potential of the select gate line SGS can be sufficiently lowered at the start of the program period at time t 2. Therefore, at time t2, since the select gate transistor ST2 can be reliably turned off and writing can be performed while maintaining the initial potential of the channel that has been charged by the channel precharge, erroneous writing in the memory cell transistor MT that is not the target of writing can be suppressed. This can improve the reliability of the memory cell. In addition, according to this embodiment, since the select gate transistor ST2 can be turned off more quickly, the channel precharge time period can be controlled to be shorter, and the program start time (t2) can be further advanced. That is, by further shortening the time period for the programming operation, the performance of the operation can be further improved.

(third embodiment)

Next, a semiconductor memory device according to a third embodiment of the present invention will be described. The semiconductor memory device of the present embodiment is different from the second embodiment in the timing of applying a voltage to the select gate line SGS and the source line CELSRC in the channel precharge period. The configuration of the semiconductor device and the potential change of the other wirings are the same as those in the second embodiment, and therefore, the description thereof is omitted. Hereinafter, the potential application timing to the select gate line SGS and the source line CELSRC in the channel precharge period will be described.

Fig. 9 is a diagram showing potential changes of the respective wirings in the channel precharge and programming operations in the third embodiment. First, at time t0, for example, 5V is applied to the select gate line SGS to turn on the select gate transistor ST2, and the potential of the select gate line SGS is raised. At time t0, CELSRC voltage control circuit 36 applies ground voltage Vss (e.g., 0V) to source line CELSRC.

Next, at time t01 later than time t0 by a predetermined time (Δ tb), CELSRC voltage control circuit 36 applies, for example, 2V as a precharge voltage to the source line CELSRC. At time t01, the output connection transistor 38 is switched on, whereby the well line CPWELL is at the same potential as the source line CELSRC. That is, the same voltage (e.g., 2V) as the precharge voltage is applied to the well line CPWELL.

By applying a voltage to the source line CELSRC later than the timing of applying a voltage to the select gate line SGS by a predetermined time, an assist effect by capacitive coupling between the source line CELSRC and the select gate line SGS is exerted, and charging (potential rise) of the select gate line SGS is further accelerated. Further, since the source line CELSRC and the well line CPWELL are boosted at the same timing, the coupling capacitance between the source line CELSRC and the well line CPWELL does not affect the boosting, and the boosting speed can be increased. This allows the select gate transistor ST2 to be turned on more quickly than in the second embodiment.

Next, in order to turn off the select gate transistor ST2, at time t03, the ground voltage Vss (e.g., 0V) is applied to the select gate line SGS. Since the select gate transistor ST2 is switched to the on state faster than in the second embodiment, the time t03 can be set to be earlier than the time t1 by the predetermined time Δ ta3(Δ ta3> Δ ta 2). Finally, at time t1, the output connection transistor 38 is turned off, thereby disconnecting the well line CPWELL from the source line CELSRC, and the ground voltage Vss (e.g., 0V) is applied to the well line CPWELL from the CPWELL voltage control circuit 37. At time t1, the potential of the well line CPWELL decreases from 2V to the ground potential Vss, and the assist effect due to the capacitive coupling between the well line CPWELL and the select gate line SGS acts, accelerating the discharge (potential decrease) of the select gate line SGS.

That is, according to the present embodiment, the potential of the select gate line SGS can be increased more quickly by the assist effect of the boosting of the source line CELSRC in addition to the assist effect of the boosting of the well line CPWELL, and therefore the fall start timing (time t03) of the potential of the select gate line SGS can be advanced. Thus, since the period of time until the program start time (time t2) is long, the potential of the select gate line SGS can be sufficiently lowered at the start of the program period of time t 2. Therefore, at time t2, since the select gate transistor ST2 can be reliably turned off and writing can be performed while maintaining the initial potential of the channel that has been charged by the channel precharge, erroneous writing in the memory cell transistor MT that is not the target of writing can be suppressed. This can improve the reliability of the memory cell. In addition, according to this embodiment, since the select gate transistor ST2 can be turned off more quickly, the channel precharge time period can be controlled to be shorter, and the program start time (t2) can be further advanced. That is, by further shortening the time period for the programming operation, the performance of the operation can be further improved.

(fourth embodiment)

Next, a semiconductor memory device according to a fourth embodiment of the present invention will be described. The semiconductor memory apparatus of the present embodiment is different from the third embodiment in that the voltages applied to the source line CELSRC and the well line CPWELL in the channel precharge period. Fig. 10 is a diagram showing potential changes of the respective wirings in the channel precharge and program operations in the fourth embodiment. As shown in fig. 10, at time t01, CELSRC voltage control circuit 36 applies voltage Va (Va >2V) as a precharge voltage to source line CELSRC. At time t01, the output connection transistor 38 is switched on, whereby the well line CPWELL is at the same potential as the source line CELSRC. That is, the same voltage Va as the precharge voltage is applied to the well line CPWELL.

By setting the precharge voltage applied to the source line CELSRC to be higher than the timing of applying the voltage to the select gate line SGS by a predetermined time, the assist effect by the capacitive coupling becomes more remarkable, and the charging (potential rise) of the select gate line SGS is further accelerated. This allows the select gate transistor ST2 to be turned on more quickly than in the third embodiment.

Next, in order to turn off the select gate transistor ST2, at time t04, the ground voltage Vss (e.g., 0V) is applied to the select gate line SGS. Since the select gate transistor ST2 is switched to the on state faster than in the third embodiment, the time t04 can be set to be earlier than the time t1 by the predetermined time Δ ta4(Δ ta4> Δ ta 3). Finally, at time t1, CELSRC voltage control circuit 36 switches the voltage applied to source line CELSRC to 2V. Further, the output connection transistor 38 is turned off, thereby disconnecting the well line CPWELL from the source line CELSRC, and the ground voltage Vss (e.g., 0V) is applied to the well line CPWELL from the CPWELL voltage control circuit 37.

At time t1, the potential of the well line CPWELL decreases from Va to the ground voltage Vss, so that the assist effect by the capacitive coupling between the well line CPWELL and the select gate line SGS becomes more significant, and the discharge (potential decrease) of the select gate line SGS is accelerated.

That is, according to this embodiment, at time t2, since the select gate transistor ST2 can be reliably turned off and writing can be performed while maintaining the initial potential of the channel that has been charged by channel precharging, erroneous writing in the memory cell transistor MT that is not the target of writing can be suppressed. This can improve the reliability of the memory cell. Further, since the select gate transistor ST2 can be turned off more quickly, there is a possibility that the channel precharge period is controlled to be shorter and the program start timing (t2) is further advanced. That is, by further shortening the time period for the programming operation, the performance of the operation can be further improved.

(fifth embodiment)

Next, a semiconductor memory device according to a fifth embodiment of the present invention will be described. The semiconductor memory apparatus of the present embodiment is different from the fourth embodiment in the timing of switching (lowering) the voltage of the source line CELSRC in the channel precharge period. Fig. 11 is a diagram showing potential changes of the respective wirings in the channel precharging and programming operations in the fifth embodiment. As shown in fig. 11, at time t12 later than time t1 by a predetermined time Δ tc, CELSRC voltage control circuit 36 switches the voltage applied to source line CELSRC to 2V. As described above, by setting the timing of lowering the voltage of the source line CELSRC later than the timing of lowering the voltage of the well line CPWELL, the auxiliary effect of capacitive coupling between the well line CPWELL and the select gate line SGS and the auxiliary effect of capacitive coupling between the source line CELSRC and the select gate line SGS are added, and therefore, the discharge (potential lowering) of the select gate line SGS can be further accelerated.

That is, according to this embodiment, at time t2, since the select gate transistor ST2 can be reliably turned off and writing can be performed while maintaining the initial potential of the channel that has been charged by channel precharging, erroneous writing in the memory cell transistor MT that is not the target of writing can be suppressed. This can improve the reliability of the memory cell. Further, since the select gate transistor ST2 can be made to turn off more quickly, there is a possibility that the channel precharge period is controlled to be shorter, and the program start timing (t2) is further advanced. That is, by further shortening the time period for the programming operation, the performance of the operation can be further improved.

Several embodiments of the present invention have been described, but these embodiments are shown as an example and are not intended to limit the scope of the invention. These new embodiments may be implemented in other various ways, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.