Read voltage calibration based on host IO operation
阅读说明：本技术 基于主机io操作的读取电压校准 (Read voltage calibration based on host IO operation ) 是由 S·瑞特南 K·坦派罗 A·马尔谢 K·K·姆奇尔拉 H·R·桑吉迪 P·S·费利 罗婷 于 2018-08-28 设计创作，主要内容包括：本发明揭示用于基于主机输入输出操作的基于快闪的存储系统的读取电压校准的装置及技术。在实例中,一种存储器装置包含：“与非”存储器阵列,其具有存储器单元的多个块的群组；及存储器控制器,其用于优化所述存储器阵列的读取电压校准。在实例中,优化技术包含：监测针对相应块发生的读取操作；基于所述读取操作来识别用于触发读取电平校准的条件；及对所述相应块或包含所述相应块的存储器组件执行所述读取电平校准。在另一实例中,基于用于读取所述相应块的阈值电压来执行所述校准,可在由所述读取电平校准执行的取样操作内评估用于读取所述相应块的所述阈值电压时考量用于读取所述相应块的所述阈值电压。(Devices and techniques for read voltage calibration for flash-based storage systems based on host input-output operations are disclosed. In an example, a memory device includes: a NAND memory array having groups of multiple blocks of memory cells; and a memory controller for optimizing read voltage calibration of the memory array. In an example, the optimization technique includes: monitoring read operations occurring for the respective block; identifying a condition for triggering a read level calibration based on the read operation; and performing the read level calibration on the respective block or a memory component that includes the respective block. In another example, the calibration is performed based on a threshold voltage for reading the respective block, which may be considered in evaluating the threshold voltage for reading the respective block within a sampling operation performed by the read level calibration.)
1. A memory device, comprising:
a NAND memory array having groups of multiple blocks of memory cells; and
a memory controller operably coupled to the memory array, the memory controller to perform operations comprising:
monitoring read operations occurring for respective blocks of the memory array;
identifying a condition for triggering a read level calibration based at least in part on the read operation occurring for the respective block; and
performing the read level calibration based on threshold voltage levels of a respective group of a plurality of blocks hosting the respective block in response to the identified condition, wherein the read level calibration is performed based at least in part on threshold voltages used to read the respective block.
2. The memory device of claim 1, wherein monitoring the read operations includes tracking a number of reads for the respective block, and wherein the condition for triggering the read level calibration is identified based at least in part on the number of reads occurring for the respective block exceeding a determined number of reads.
3. The memory device of claim 2, the operations of the memory controller further comprising monitoring erase operations occurring for the respective block, wherein the condition for triggering the read level calibration is further identified based on a number of erases for the respective block exceeding a determined number of erases.
4. The memory device of claim 3, wherein the number of reads for the respective block is tracked with a first counter saved in a memory accessible by the memory controller, wherein the number of erases for the respective block is tracked with a second counter saved in the memory accessible by the memory controller, and wherein the first counter is reset for an erase occurring for the respective block.
5. The memory device of claim 1, wherein monitoring the read operations includes tracking a number of reads for the respective group of a plurality of blocks hosting the respective block, and wherein the condition for triggering the read level calibration is identified based at least in part on the number of reads occurring for the respective group of a plurality of blocks exceeding a determined number of reads.
6. The memory device of claim 1, wherein the condition for triggering the read level calibration is further based in part on a Raw Bit Error Rate (RBER) of read operations occurring for at least the respective block of the memory array.
7. The memory device of claim 1, wherein performing the read level calibration includes performing sampling for reading the threshold voltage of the respective block and for reading threshold voltages of other blocks in the group of a plurality of blocks located in the memory array.
8. The memory device of claim 7, wherein the other blocks in the memory array included in the sample are identified within the memory array based on a number of read operations performed in respective blocks of the other blocks.
9. The memory device of claim 7, wherein the other blocks in the memory array included in the sample are identified within the memory array based on at least one of: randomly sampling the other blocks in the memory array, sampling the other blocks in the memory array based on a data age, or sampling the other blocks in the memory array based on an original bit error rate (RBER) corresponding to the other blocks.
10. The memory device of claim 1, wherein read operations for the respective block are monitored by monitoring read operations for one or more portions of the respective block.
11. The memory device of claim 10, wherein the monitored portion of the respective block includes a page of the respective block.
12. The memory device of claim 1, wherein the memory device is operably coupled to a host, wherein the host causes a command to perform a respective read in the plurality of blocks in the memory array, and wherein the respective read comprises a plurality of reads occurring for a logical block address corresponding to a page located within the respective block.
13. The memory device of claim 1, wherein the read level calibration updates one or more read voltage levels used to read one or more pages of the respective block in subsequent read operations occurring for the one or more pages of the respective block.
14. The memory device of claim 1, wherein the block of memory cells of the memory array includes at least one of: single level cell SLC, multi-level cell MLC, three-layer cell TLC, or four-layer cell QLC nand memory cell.
15. The memory device of claim 1, wherein the memory array is arranged as a stack of three-dimensional 3D nand dies, and wherein the respective group of a plurality of blocks hosting the respective block corresponds to a group of blocks provided by a respective die in the stack of 3D nand dies.
16. A method for optimizing voltage read level calibration in a memory device, the method comprising a plurality of operations performed by a memory controller of a nand memory array, and the memory array having a group of a plurality of blocks of memory cells, wherein the operations comprise:
monitoring read commands issued to respective blocks of the memory array;
identifying a condition for triggering a read level calibration based at least in part on the read command issued to the respective block; and
performing the read level calibration based on threshold voltage levels of respective groups of a plurality of blocks hosting the respective blocks in response to the identified condition, wherein the read level calibration is performed based at least in part on threshold voltages used to read the respective blocks;
wherein the read level calibration updates a read voltage level used to read a page of the respective block in a subsequent read operation for the page of the respective block.
17. The method of claim 16, wherein monitoring the read command includes tracking a number of reads for the respective block, and wherein the condition for triggering the read level calibration is identified based at least in part on the number of reads occurring for the respective block exceeding a determined number of reads.
18. The method of claim 17, the operations of the memory controller further comprising:
monitoring for erase commands occurring for the respective block, wherein the condition for triggering the read level calibration is further identified based on a number of erases for the respective block exceeding a determined number of erases;
wherein the number of reads for the respective block is tracked with a first counter, wherein the number of erases for the respective block is tracked with a second counter, and wherein the first counter is reset for an erase occurring for the respective block.
19. The method of claim 16, wherein monitoring the read operations includes tracking a number of reads for the respective group of a plurality of blocks hosting the respective block, and wherein the condition for triggering the read level calibration is identified based at least in part on the number of reads occurring for the respective group of a plurality of blocks exceeding a determined number of reads.
20. The method of claim 16, wherein the condition for triggering the read level calibration is further based in part on a Raw Bit Error Rate (RBER) of read operations occurring for at least the respective block of the memory array.
21. The method of claim 16, wherein performing the read level calibration includes performing sampling for reading the threshold voltages of the respective blocks and for reading threshold voltages of other blocks in the group of a plurality of blocks located in the memory array.
22. The method of claim 21, wherein the other blocks in the memory array included in the sample are identified within the memory array based on a number of read operations performed in respective blocks of the other blocks.
23. The method of claim 16, wherein read operations for the respective block are monitored by monitoring read operations for one or more portions of the respective block.
24. A device-readable storage medium that provides instructions that when executed by a controller of a memory device optimize voltage read level calibration in the memory device, wherein the instructions cause the controller to perform operations comprising:
monitoring read operations occurring with respect to respective blocks of a NAND memory array of the memory device, the NAND memory array having a group of a plurality of blocks of memory cells;
identifying a condition for triggering a read level calibration based at least in part on the read operation occurring for the respective block; and
performing the read level calibration based on threshold voltage levels of respective groups of a plurality of blocks hosting the respective blocks in response to the identified condition;
wherein the read level calibration is performed based at least in part on a threshold voltage used to read the respective block, and wherein the threshold voltage of the respective block is evaluated within a sampling operation performed in the memory array by the read level calibration.
25. The device-readable storage medium of claim 24, wherein monitoring the read operations includes tracking a number of reads for the respective block, and wherein the condition for triggering the read level calibration is identified based at least in part on the number of reads occurring for the respective block exceeding a determined number of reads.
26. The device-readable storage medium of claim 25, the operations caused by the instructions further comprising:
monitoring erase operations occurring for the respective block, wherein the condition for triggering the read level calibration is further identified based on a number of erases for the respective block exceeding a determined number of erases;
wherein the number of reads for the respective block is tracked with a first counter, wherein the number of erases for the respective block is tracked with a second counter, and wherein the first counter is reset for an erase occurring for the respective block.
27. The device-readable storage medium of claim 24, wherein monitoring the read operations includes tracking a number of reads for the respective group of a plurality of blocks that host the respective block, and wherein the condition for triggering the read level calibration is identified based at least in part on the number of reads occurring for the respective group of a plurality of blocks exceeding a determined number of reads.
28. The device-readable storage medium of claim 24, wherein the condition for triggering the read level calibration is further based in part on a Raw Bit Error Rate (RBER) of read operations occurring for at least the respective block of the memory array.
29. The device-readable storage medium of claim 24, wherein the sampling operation includes reading sampled threshold voltages from one or more of the respective blocks and reading sampled threshold voltages from one or more of the other blocks in the group of a plurality of blocks located in the memory array.
30. The device-readable storage medium of claim 29, wherein the other blocks are identified within the memory array based on a number of read operations performed in respective ones of the other blocks.
31. The device-readable storage medium of claim 24, wherein read operations for the respective block are monitored by monitoring read operations for one or more portions of the respective block.
Background
Memory devices are typically provided in computers or other electronic devices as internal semiconductor integrated circuits. There are many different types of memory, including volatile and non-volatile memory.
Volatile memory requires power to hold its data and includes, among other things, Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), or Synchronous Dynamic Random Access Memory (SDRAM).
Non-volatile memory can retain stored data when not powered and includes, among others, flash memory, Read Only Memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Static RAM (SRAM), Erasable Programmable ROM (EPROM), resistance variable memory (e.g., Phase Change Random Access Memory (PCRAM)), Resistive Random Access Memory (RRAM), Magnetoresistive Random Access Memory (MRAM), or 3D XPointTMA memory.
Flash memory is used as non-volatile memory for various electronic applications. Flash memory devices typically include one or more groups of single transistor, floating gate, or charge trapping memory cells that allow for high memory density, high reliability, and low power consumption.
Two common types of flash memory array architectures include the nand and nor architectures, named in logical form, in which the basic memory cell configuration of each architecture is arranged. The memory cells of a memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled together in series, source to drain, between a source line and a bit line.
Semiconductor memory arrays of both the NOR and NAND architectures are accessed by a decoder that activates a particular memory cell by selecting the word line coupled to the memory cell gate. In a nor architecture semiconductor memory array, a selected memory cell, once activated, has its data value placed on a bit line to cause different currents to flow according to the state in which the particular cell is programmed. In a nand architecture semiconductor memory array, a high bias voltage is applied to the drain side Select Gate (SGD) line. The word lines coupled to the gates of each group of unselected memory cells are driven by a specified pass voltage (e.g., Vpass) to operate each group of unselected memory cells as a pass transistor (e.g., for passing current in a manner that is unrestricted by their stored data values). Then, current flows from the source line through each series-coupled group to the bit lines (limited only by the selected memory cells of each group) to place the currently-encoded data values of the selected memory cells on the bit lines.
Each flash memory cell in a nor or nand architecture semiconductor memory array can be individually or collectively programmed to one or several program states. For example, a Single Level Cell (SLC) may represent one of two programmed states (e.g., 1 or 0) to represent one bit of data.
However, flash memory cells can also represent one of more than two program states to allow higher density memory to be fabricated without increasing the number of memory cells, as each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In a particular example, an MLC may refer to a memory cell that may store two bits of data per cell (e.g., one of four programmed states), a three-level cell (TLC) may refer to a memory cell that may store three bits of data per cell (e.g., one of eight programmed states), and a four-level cell (QLC) may store four bits of data per cell. MLC is used herein in its broader context to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states).
Conventional memory arrays are two-dimensional (2D) structures arranged on a surface of a semiconductor conductor substrate. To increase memory capacity for a given area and reduce cost, the size of individual memory cells has been reduced. However, there are technical limitations to reducing the size of individual memory cells, and thus the memory density of 2D memory arrays. In response, 3D memory structures, such as three-dimensional (3D) "nand" architecture semiconductor memory devices, are being developed to further increase memory density and reduce memory cost.
Such 3D nand devices typically include strings of memory cells coupled in series (e.g., drain to source) between one or more source-side Select Gates (SGS) proximate to the source and one or more drain-side Select Gates (SGD) proximate to the bit line. In an example, an SGS or SGD may include one or more Field Effect Transistors (FETs) or Metal Oxide Semiconductor (MOS) structure devices, among others. In some examples, the strings will extend vertically through multiple vertical spacers containing respective word lines. A semiconductor conductor structure, such as a polysilicon structure, may extend adjacent to the string memory cells to form a channel of the memory cell string. In the example of a vertical string, the polysilicon structures may be in the form of vertically extending pillars. In some examples, the string may be "folded" and thus arranged relative to the U-shaped post. In other examples, multiple vertical structures may be stacked on top of each other to form a stacked array of memory cell strings.
Memory arrays or devices can be combined together to form, for example, a Solid State Drive (SSD), Universal Flash Storage (UFS)TM) Device, multi-media card (MMC) solid state memory device, embedded MMC device (eMMC)TM) Etc. of the memory system. SSDs can be used, among other things, as the main storage device for a computer, with its moving parts having, for example, performance, size, weight, robustness, operating temperature range, and power consumption advantages over traditional hard disk drives. For example, SSDs may reduce seek time, latency, or other delays associated with disk drives (e.g., electromechanical, etc.). SSDs use non-volatile memory cells, such as flash memory cells, to eliminate internal battery supply requirements to thus allow the drive to be more widely used and miniaturized.
An SSD may include a number of memory devices, including a number of dies or logical units (e.g., logical unit numbers or LUNs), and may include one or more processors or other controllers that perform the logical functions needed to operate the memory devices or interface with external systems. Such SSDs may include one or more flash memory dies that include a number of memory arrays and peripheral circuitry thereon. A flash memory array may include a number of blocks of memory cells organized into a number of physical pages. In many examples, an SSD will also include DRAM or SRAM (or other forms of memory die or other memory structures). The SSD can receive commands from the host associated with memory operations, such as read or write operations for transferring data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory device and the host, or erase operations for erasing data from the memory device.
In nand-based flash memory systems, the read voltage threshold (Vt) required to successfully perform a read operation is subject to shifting from time to time. These shifts can be caused by well-known stresses on nand flash memory such as read disturb, data retention, cross-temperature effects, and other constraints. Furthermore, different nand blocks within a memory array experience varying amounts of stress that induce varying amounts of charge loss or charge gain; likewise, different NAND blocks of an array are typically written to and read from at different temperatures. Thus, mismatches between the NAND Vt and the read voltage actually used by the memory system can occur in many scenarios. Various techniques for read voltage calibration are used by many nand memory systems to adjust the read voltage according to the nand Vt. However, existing methods for initiating and utilizing read voltage calibration often fail to fully account for voltage threshold shifts that have occurred in particular regions of the memory being read to cause unwanted data errors from requested and performed read operations, additional calibration and adjustment operations, and delays and performance degradation of the storage system.
Drawings
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. The same numbers with different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present disclosure.
FIG. 1 illustrates an example of an environment including a memory device.
Fig. 2-3 illustrate schematic diagrams of examples of a 3D nand architecture semiconductor memory array.
FIG. 4 illustrates an example block diagram of a memory module.
FIG. 5 illustrates a block diagram of an example system including a memory device suitable for implementing optimization techniques for read voltage calibration.
FIG. 6 illustrates a sequence of operation diagram of an example memory device configuration suitable for performing an optimization technique for read voltage calibration.
FIG. 7 illustrates a flow diagram of an example set of operations suitable for performing an optimization technique for read voltage calibration.
Fig. 8 is a block diagram illustrating an example of a machine upon which one or more embodiments may be implemented.
Detailed Description
The systems, processes, and configurations discussed herein relate to optimization techniques for triggering and performing read voltage calibration of NAND memory devices. Specifically, example techniques are disclosed that use the physical footprint of a host read IO in real time for select blocks or other areas of a memory array to be sampled by voltage level calibration. The calibration of the read voltages may be based on the most frequently read data locations to thus reduce the trigger rate and calibrate the Vt shift of the target baseline stress condition. Furthermore, example techniques are disclosed that enable intelligence and adaptive block sampling criteria that facilitate active areas of a memory array (e.g., respective blocks and groups of blocks most frequently accessed by a host IO) to calibrate nand read voltages for best possible read performance in current and future operations. Furthermore, example techniques are disclosed for identifying conditions for triggering read voltage calibration and tracking the state of regions of a memory array involved in host IO operations, including read and erase activities for respective blocks and groups of blocks.
Electronic devices, such as mobile electronic devices (e.g., smart phones, tablet computers, etc.), electronic devices used in automotive applications (e.g., automotive sensors, control units, driving assistance systems, passenger security or comfort systems, etc.), and internet-connected devices or devices (e.g., internet of things (IoT) devices, etc.), have different storage requirements depending, among other things, on the type of electronic device, the use environment, performance expectations, and so forth.
The electronic device may be divided into several main components: a processor (e.g., a Central Processing Unit (CPU) or other host processor), memory (e.g., one or more volatile or non-volatile Random Access Memory (RAM) memory devices such as dynamic RAM (dram), mobile or low power double data rate synchronous dram (ddr sdram), etc.), and storage devices (e.g., non-volatile memory (NVM) devices such as flash memory, Read Only Memory (ROM), SSD, MMC, or other memory card structures or assemblies, etc.). In a particular example, the electronic device may include a user interface (e.g., a display, a touchscreen, a keyboard, one or more buttons, etc.), a Graphics Processing Unit (GPU), a power management unit, a baseband processor, or one or more transceiver circuits, among others.
FIG. 1 illustrates an example of an environment 100 including a host device 105 and a memory device 110 configured to communicate via a communication interface. The host device 105 or the memory device 110 may be included in various products 150, such as internet of things (IoT) devices (e.g., refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, drones, etc.) for supporting processing, communication, or control of the products 150.
Memory device 110 includes a memory controller 115 and a memory array 120, memory array 120 including, for example, a number of individual memory dies, such as a stack of three-dimensional (3D) "nand" dies. In 3D architecture semiconductor memory technology, vertical structures are stacked to increase the number of layers, physical pages and thus density of memory devices (e.g., storage devices). In an example, memory device 110 may be a discrete memory or storage component of host device 105. In other examples, memory device 110 may be part of an integrated circuit, such as a system on a chip (SOC) or the like, stacked or otherwise included on one or more other components of host device 105.
One or more communication interfaces may be used between the memory device 110 and one or more other components of the host device 105, such as a Serial Advanced Technology Attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMCTMAn interface or one or more other connectors or interfaces). Host device 105 may include a host system, an electronic device, a processor, a memory card reader, or one or more other electronic devices outside of memory device 110. In some examples, host 105 may be a machine having some or all of the components discussed with reference to machine 800 of fig. 8.
The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array to, for example, transfer (e.g., write or erase) or from (e.g., read) data of one or more of the memory cells, planes, sub-blocks, or pages of the memory array. Memory controller 115 may include, among other things, circuitry or firmware including one or more components or integrated circuits. For example, the memory controller 115 may include one or more memory control units, circuits, or components configured to control access across the memory array 120 and provide a translation layer between the host 105 and the memory device 110. The memory controller 115 may include one or more input/output (I/O) circuits, lines, or interfaces to transfer data to or from the memory array 120. Memory controller 115 may include memory manager 125 and array controller 135.
Memory manager 125 may include, among other things, circuitry or firmware such as several components or integrated circuits associated with various memory management functions. For purposes of this disclosure, example memory operation and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have analog memory operation or management functions. Such nand management functions include wear leveling (e.g., garbage collection or reclamation), error detection or correction, block retirement, or one or more other memory management functions. The memory manager 125 may parse or format host commands (such as commands received from a host) into device commands (such as commands associated with operation of a memory array, etc.) or generate device commands for the array controller 135 or one or more other components of the memory device 110 (such as for accomplishing various memory management functions).
The memory manager 125 may include a set of management tables 130 configured to hold various information associated with one or more components of the memory device 110, such as various information associated with a memory array or one or more memory cells coupled to the memory controller 115. For example, the management table 130 may include information regarding the block age, block erase count, error history, or one or more error counts (e.g., write operation error count, read bit error count, read operation error count, erase error count, etc.) of one or more blocks of memory cells coupled to the memory controller 115. In a particular example, a bit error may be referred to as an uncorrectable bit error if the number of detected errors for one or more of the error counts is above a threshold. The management table 130 may hold, among other things, a count of correctable or uncorrectable bit errors.
The array controller 135 may include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of a memory device 110 coupled to the memory controller 115. The memory operation may be based on host commands (e.g., associated with wear leveling, error detection or correction, etc.) received from the host 105 or generated internally by the memory manager 125, for example.
The array controller 135 may include an Error Correction Code (ECC) component 140, which may include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of a memory device 110 coupled to the memory controller 115. The memory controller 115 may be configured to proactively detect and recover from error events (bit errors, operational errors, etc.) associated with various operations or storage of data, while maintaining the integrity of data transferred between the host 105 and the memory device 110 or maintaining the integrity of stored data (e.g., using redundant RAID storage, etc.), and may remove (e.g., retire) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.
Memory array 120 may include a number of memory cells arranged, for example, in a number of devices, planes, sub-blocks, or pages. As an example, a 48GB TLC nand memory device may include 18,592 bytes (B) of data per page ((16,384+2208) bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device, which stores 2 bits of data per cell (i.e., 4 programmable states), may include 18,592 bytes (B) of data per page ((16,384+2208) bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but with the write time required for the semiconductor of the corresponding TLC memory device and twice the program/erase (P/E) cycle. Other examples may include other numbers or arrangements. In some examples, the memory device or a portion thereof may be selectively operated in SLC mode or a desired MLC mode (e.g., TLC, QLC, etc.).
In operation, data is typically written to or read from a NAND memory device 110 in a page and erased in a block. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells, as desired. The data transfer size of a NAND memory device 110 is commonly referred to as a page, while the data transfer size of the host is commonly referred to as a sector.
Although the data of a page may include a number of bytes of user data (e.g., a data payload including a number of sectors of data) and its corresponding metadata, the size of a page typically refers only to a number of bytes for storing user data. As an example, a data page having a page size of 4KB may include 4KB of user data (e.g., 8 sectors of a sector size of presentation 512B) and metadata corresponding to a number of bytes of the user data (e.g., 32B, 54B, 224B, etc.), such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.) or other metadata associated with the user data.
Different types of memory cells or memory arrays 120 may provide different page sizes, or require different amounts of metadata associated with different page sizes. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata needed to ensure the integrity of a data page (e.g., a memory device with a higher bit error rate requires more error correction code data bytes than a memory device with a lower bit error rate). As an example, a multi-level cell (MLC) "nand" flash device may have a higher bit error rate than a corresponding single-level cell (SLC) "nand flash device. Thus, MLC devices require more metadata bytes of error data than corresponding SLC devices.
FIG. 2 illustrates a block including an organization into blocks (e.g., block A201A, block B201B, etc.) and sub-blocks (e.g., sub-block A)0201A0Subblock An201Ansub-Block B0201B0sub-Block Bn201BnEtc.) of a number of strings of memory cells (e.g., a first a)0
Each string of memory cells includes a source-to-drain stack in the Z-direction on either a source line (SRC)235 or a source side Select Gate (SGS) (e.g., first A)0
Within a physical page, each layer represents a row of memory cells and each string of memory cells represents a column. A sub-block may include one or more physical pages. A block may include a number (e.g., 128, 256, 384, etc.) of sub-blocks (or physical pages). Although illustrated herein as having two blocks, each block having two sub-blocks, each sub-block having a single physical page, each physical page having three strings of memory cells, and each string having 8 layers of memory cells, in other examples, the
Each memory cell in
In an example, the
Fig. 3 illustrates an example schematic diagram of a portion of a nand architecture semiconductor memory array 300 including a plurality of memory cells 302 and a sense amplifier or device 360, the plurality of memory cells 302 arranged in a two-dimensional array of strings (e.g., first string 305 through third string 307) and layers (e.g., illustrated as respective Word Lines (WL) WL 0310 through WL 7317, drain-side Select Gate (SGD) lines 325, source-side Select Gate (SGS) lines 330, and so on). For example, the memory array 300 may illustrate an example schematic of a portion of one physical page of memory cells such as the 3D nand architecture semiconductor memory device illustrated in fig. 2.
Each string of memory cells is coupled to a source line (SRC) using a respective source-side Select Gate (SGS), e.g., first SGS 331-third SGS333, and to a respective data line, e.g., first Bit Line (BL) BL 0320-third bit line BL 2322, using a respective drain-side Select Gate (SGD), e.g., first SGD 326-third SGD 328. Although 8 layers (e.g., using Word Lines (WL) WL 0310-WL 7317) and 3 data lines (BL 0326-BL 2328) are illustrated in the example of fig. 3, other examples may include memory cell strings having more or fewer layers or data lines, as desired.
In a NAND architecture semiconductor memory array, such as the example memory array 300, the state of a selected memory cell 302 can be accessed by sensing a change in current or voltage associated with a particular data line containing the selected memory cell. The memory array 300 may be accessed (e.g., by control circuitry, one or more processors, digital logic, etc.) using one or more drivers. In an example, the one or more drivers may activate a particular memory cell or group of memory cells by driving a particular potential to one or more data lines (e.g., bit lines BL 0-BL 2), access lines (e.g., word lines WL 0-WL 7), or select gates, depending on the type of operation desired to be performed on the particular memory cell or group of memory cells.
To program or write data to the memory cells, a program voltage (Vpgm) (e.g., one or more program pulses, etc.) may be applied to the selected word line (e.g., WL4) and thus to the control gates of each memory cell coupled to the selected word line (e.g., first Control Gate (CG)341 through third CG 343 of the memory cell coupled to WL 4). The programming pulses may begin at or approximately at, for example, 15V and, in a particular example, may increase in amplitude during the application of each programming pulse. When a programming voltage is applied to the selected word line, a potential such as a ground potential (e.g., Vss) may be applied to the data line (e.g., bit line) and substrate (and thus the channel between source and drain) of the memory cell targeted for programming to cause charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the channel to the floating gate of the targeted memory cell.
In contrast, a pass voltage (Vpass) may be applied to one or more word lines having memory cells that are not targeted for programming, or an inhibit voltage (e.g., Vcc) may be applied to data lines (e.g., bit lines) having memory cells that are not targeted for programming to, for example, inhibit charge transfer from the channel to the floating gates of such non-targeted memory cells. The turn-on voltage may vary depending on, for example, the proximity of the applied turn-on voltage to the word line targeted for programming. The inhibit voltage may include a supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external power source or supply (e.g., a battery, a dc-dc converter, etc.).
As an example, if a programming voltage (e.g., 15V or more than 15V) is applied to a particular word line such as WL4, a turn-on voltage of 10V may be applied to one or more other word lines such as WL3, WL5, etc. to inhibit programming of non-target memory cells or to save values stored on such memory cells that are not targeted for programming. The turn-on voltage required to inhibit programming of non-target memory cells may be reduced as the distance between the applied programming voltage and the non-target memory cells increases. For example, when a programming voltage of 15V is applied to WL4, a turn-on voltage of 10V may be applied to WL3 and WL5, a turn-on voltage of 8V may be applied to WL2 and WL6, a turn-on voltage of 7V may be applied to WL1 and WL7, and so on. In other examples, the turn-on voltage or number of word lines, etc. may be higher or lower or more or less.
Sense amplifier 360 coupled to one or more of the data lines (e.g., first bit line BL 0320, second bit line BL 1321, or third bit line BL 2322) may detect the state of each memory cell in the respective data line by sensing the voltage or current on the particular data line.
Between the application of one or more programming pulses, such as Vpgm, a verify operation can be performed to determine whether the selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, it can be inhibited from further programming. Additional programming pulses may be applied if the selected memory cell has not reached its intended programmed state. If the selected memory cell does not reach its intended programmed state after a certain number (e.g., the maximum number) of programming pulses, the selected memory cell, or a string, block, or page of such selected memory cells, can be marked as defective.
To erase a memory cell or group of memory cells (e.g., erase is typically performed in a block or sub-block), an erase voltage (Vers) (e.g., typically Vpgm) may be applied to the substrate (and thus the channel between the source and drain) of the memory cell targeted for erase (e.g., using one or more bit lines, select gates, etc.) while the word line of the targeted memory cell is held at a potential such as ground potential (e.g., Vss) to cause charge transfer (e.g., direct injection or fowler-nordheim (FN)) tunneling from the floating gate to the channel of the targeted memory cell, etc.).
FIG. 4 illustrates an example block diagram of a
The
The
One or more devices external to
The
The following techniques and configurations discussed herein provide techniques implemented within a NAND memory device for aspects of read voltage calibration. The techniques and configurations discussed herein may be particularly applicable to 3D nand flash-based storage systems, such as systems embodying the 3D nand architecture features discussed above. However, it should be understood that the disclosed read voltage calibration techniques and configurations may also be applied to other forms of NAND flash devices, including components applied to NAND flash devices in other form factors or arrangements.
In nand-based flash memory systems, nand memory arrays include various blocks that experience different amounts of charge loss and charge gain, and various blocks that are programmed (written) at different temperatures. Thus, the Vt of any particular block or region of the memory array for reading may be different from another block or another region of the memory array. Furthermore, the Vt for a particular block or region of memory is oftentimes subject to shifting due to stress and the Vt may thus shift in either direction.
Read disturb is an example of affecting Vt stress that occurs for nand flash devices. When a host or application retrieves particular data from a flash device, read disturb stresses can accumulate when the host utilizes a particularly high read rate or read intensive application of the data, depending on how the data is spread within the flash device. For example, if a Logical Block Address (LBA) maps to a particular physical location of a NAND block, stress may be induced on unselected word lines due to bias conditions within the block and the memory cells may become biased against each other.
The cross temperature effect is another example of affecting Vt stress that occurs for nand flash devices. Due to the temperature difference between the write time and the read time, the cross temperature effect causes a shift of the cell Vt (positive or negative Vt shift) in the NAND block. For example, when writing data to a NAND flash device (such as an SSD drive or SD/MMC card), the Vt required to read the data is based on the ambient temperature at the time the data was written. However, because data can remain resident on the flash device for long periods of time, the flash device cannot be read at the same temperature.
A mismatch between the read voltage used to read a block and the Vt of a particular block can result in data errors. The representation of data errors (fail bit count) may be measured in a nand memory system as the "Raw Bit Error Rate (RBER)". Thus, RBER varies with the mismatch between the read voltage and Vt. Thus, in the operation of many legacy memory systems based on nand flash, RBER provides a measure for determining whether the read voltage is incorrect and whether voltage calibration should be performed.
RBER can be minimized by adjusting the read voltage according to Vt using read voltage calibration. Reactive or prospective methods can be used to induce read voltage calibration. Using a reactive approach, read voltage calibration is performed in response to read errors that occur during host read IO. The reactive method uses a target criterion to directly calibrate the read voltage in response to read errors. In contrast, the prospective approach to read voltage calibration uses a sampling approach to periodically track the mean Vt shift and initiate calibration before significant errors occur. Existing methods for prospectively performing read level calibration involve sampling the RBER at different read voltages and selecting the best read voltage to optimize (e.g., reduce) the RBER. For example, the storage device firmware may calibrate the NAND read voltage by: the method includes scanning multiple pages in various locations in a NAND memory array, performing reads at the multiple pages at various read voltages, measuring the resulting RBER, and selecting one of the read voltages using a minimum error rate.
Therefore, the main purpose of read voltage calibration is to minimize the error handling trigger rate of the system that will occur during host read IO. The various blocks of the memory device are sampled using a prospective read voltage calibration process to determine an average threshold voltage and to periodically track average Vt shifts of the various blocks of the memory device. The block sampling criteria used in read voltage calibration, such as by sampling most blocks of a flash device, affects the accuracy of the resulting read voltage settings. For example, many read voltage calibration techniques utilize random block sampling or data age-based sampling, which tends to correlate voltage calibration with most states of the flash device. However, the majority of the state of a flash device does not necessarily correspond to the majority of blocks on the flash device that are accessed by a host read IO at a particular time. Thus, existing methods of majority-state-based sampling criteria for prospective read voltage calibration are not completely effective in reducing the error handling trigger rate or RBER.
A simple explanation of the reason for sampling inefficiency is that the Vt of the location corresponding to the host read IO is not necessarily aligned with the voltage setting determined from the majority state of the sampled storage device. For example, consider a scenario in which an SSD hard disk stores archived media files that are rarely accessed by a host (which occupy up to 70% of the total drive space). However, the host accesses other files on the remaining 30% of the hard disk space relatively frequently. In this scenario, calibrating the read voltage based on random sampling of the blocks would not be optimal, as the resulting calibration would tend to overcompensate for the presence of the archival media file. Therefore, calibrating the read voltage based on the majority state of the sampling drivers cannot accurately adjust the threshold voltage and therefore cannot reduce error handling triggers associated with host IO and the most frequently accessed portion of host data.
The techniques discussed herein include using the physical footprint of the host read IO in real time to select a sample block for read voltage calibration. In host IO based sampling, a controller of a memory device tracks host IO footprint at the page, word line, or physical block level and uses this tracking information to identify read voltage calibration block sampling candidates. The controller calibrates the read voltage based on the most frequently read data to thereby reduce the trigger rate. In an example, such tracking techniques may involve tracking read locations and read frequencies in host IO operations for subsequent sampling and monitoring error rates occurring for such locations. Also in an example, this tracking technique may involve tracking a number of reads or erases for a particular unit (e.g., page, block, die, etc.) of memory.
Because of the use of the physical footprint of the host IO, the memory device is operable to more efficiently detect and calibrate the NAND Vt shifts and target reference stress conditions of read-intensive applications. Furthermore, the memory device may utilize more intelligent block sampling criteria to facilitate block or other physical cell calibration of the memory most frequently accessed by the host IO for the nand read voltage for best possible read performance.
Thus, the techniques discussed herein improve error handling trigger rate by aligning nand Vt shifts with host read IO footprints at the physical level. The techniques also achieve improved read performance/latency of the target reference relative to existing calibration methods with minimal or no impact on normal user workload. Additionally, due to target benchmarks and user workloads, the techniques help mitigate nand trigger rate requirements, which helps eliminate nand over-design that would otherwise result in a loss of nand endurance or performance.
FIG. 5 provides a block diagram of an example system 500 including a memory device 510 (e.g., an SSD storage device, SD/MMC card, etc.) suitable for implementing the read voltage calibration optimization discussed herein. As shown in the figure, memory device 510 includes a
In an example, a block of memory cells of the
The memory device 510 is shown operably coupled to a
Controller 540 is depicted as including memory 544 (e.g., volatile memory), processing circuitry 546 (e.g., a microprocessor), and storage medium 548 (e.g., non-volatile memory) for executing instructions (e.g., instructions hosted by storage medium 548, loaded into memory 544, and executed by processing circuitry 546) to perform control operations 542 for managing and using
The functions provided by control operations 542 may include IO operation monitoring 550 (e.g., for monitoring read and erase operations resulting from host commands), host operation processing 560 (e.g., for interpreting and processing host commands 525, and issuing further commands to
In an example, IO operation monitoring 550 operates to track reads and writes to a memory array and also to track accompanying read and write operations related to voltage levels and calibration. Further, IO operation monitoring 550 may identify various blocks and characteristics of block operations within
In an example, read voltage control 570 is used to establish, change, and provide voltage values for reading a particular region of memory, such as a corresponding block in
In an example, read
In an example, read
In an example, the data determined by IO operation monitoring 550 is used to change the characteristics of the voltage calibration operation performed by
In another example, the particular memory location tracked by IO operation monitoring 550 or the condition of the memory location tracked by IO operation monitoring 550 may be used by error detection process 590 to determine the likelihood of a read voltage deviating from a miscalibrated memory location. Thus, the features of the IO operation monitoring 550, host operation processing 560, and error detection processing 590 may collectively operate to trigger a read level calibration operation and identify characteristics (e.g., sampling locations) of the read level calibration operation.
As discussed herein, the
In addition, the techniques discussed herein may utilize the physical footprint of the host IO from the conditional block sampling to calibrate subsequent and current read operations. This approach can be used when a customer wishes to optimize the read voltage for a particular reference, user mode, read access mode. The techniques discussed herein may provide granular tracking of read voltage levels of respective memory locations and data blocks in multiple memory locations to thereby allow calibration techniques to address relevant areas in a more efficient and targeted manner.
In addition to the techniques discussed herein, various existing calibration methods may also be integrated with and used with the
FIG. 6 illustrates a sequence diagram 600 of operation of an example memory device configuration suitable for performing optimization techniques for read voltage calibration. As shown in the figure, a
As an example, a read or write command received from the
In an example, read operations and erase operations (e.g., erase operations implemented via a write operation that rewrites a region of memory) are tracked in conjunction with
In an example, a NAND erase
Likewise, in the example, the NAND read
In an example, the
In a further example, the tracking granularity or tracking frequency of read or erase operations in the
In an example, the
In another example, other locations in the memory array can be identified (e.g., locations not identified as exceeding the read threshold (from determination 625) or exceeding the erase threshold (from determination 615)) and added to the set of
In a further example, the sampling operation performed by the
In yet another example, the
FIG. 7 illustrates a flow diagram 700 of an example set of operations suitable for performing an optimization technique for read voltage calibration. In examples, the operations of flow diagram 700 may be implemented by a controller of a storage device (e.g., controllers 115, 540) through a combination of execution operations in software, firmware, or configured hardware. However, some or all aspects of the following techniques may be implemented by other components (e.g., initiated by a host) in conjunction with other forms of command, control, and formulation.
In an example, the operations of flow diagram 700 may be implemented in a memory device that includes a nand memory array having a plurality of groups of blocks of memory cells and a memory controller operably coupled to the memory array, where the memory controller is adapted (e.g., configured, arranged, programmed) to perform the respective operations. In another example, the operations of flow diagram 700 may be implemented in a method performed by or to a memory controller of a NAND memory array having groups of multiple blocks of memory cells. In an example, the operations of flowchart 700 may be implemented in a device-readable storage medium that provides instructions that, when executed (e.g., by a controller of a memory device), perform the respective operations.
Flow diagram 700 is shown beginning with the monitoring of IO operations (operation 710), such as read and erase operations occurring for a particular memory address. A particular location (e.g., a respective block) in the memory array corresponding to a memory address (e.g., LBA) of a read or erase operation is identified after such monitoring (operation 720). For example, monitoring of read and erase operations may determine whether a read has occurred for a respective block of a memory array, where such a respective block is identified based on the block including a page corresponding to the identified location (e.g., the location in the memory array to which the LBA is mapped).
Flow diagram 700 then tracks a count of IO operations that occur for a particular location in memory (e.g., a respective block or group of blocks). As depicted in the figure, tracking may include tracking a read count of the memory location using a read counter (operation 730) and tracking an erase count of the memory location using an erase counter (operation 740). These counts may be implemented in the read counter and the erase counter, respectively, as indicated above for FIG. 6. For example, a first counter, which may be maintained in memory accessible by the memory controller, tracks the number of reads to the memory location, and a second counter, which may be maintained in memory accessible by the memory controller, tracks the number of erases to the memory location. In an example, tracking of read counts is tracked at a respective block level, and tracking of erase counts is tracked at a respective block level. In another example, tracking of read counts is tracked at the die level (e.g., for a die including multiple blocks). Also in an example, an erase occurring for a memory location (e.g., an erase of a corresponding block) increments an erase counter while a read counter is reset (e.g., reset to zero). In a further example, an erase counter is not implemented or utilized to allow tracking of erase counts (in operation 740) is an optional operation.
The flow diagram 700 then identifies a condition for triggering read level calibration (operation 750). In an example, the conditions for triggering the read position calibration may be based on one or more of: a read operation, a state of a read counter, or a state of an erase counter occurring for the respective block. As an example, the condition for triggering read level calibration may result from monitoring a plurality of read operations for respective blocks of a memory array. In another example, the condition is identified based on a number of reads occurring for the respective block exceeding a determined number of reads. Also as an example, conditions for triggering read level calibration may be identified based on a number of erasures for a respective block exceeding a determined number of erasures.
In additional examples, the condition for triggering read level calibration may occur based on an evaluation of the group of the plurality of blocks rather than the respective block, such as tracking a number of reads that occur for the group of the plurality of blocks (the group hosting the respective block) to identify the condition when the number of reads exceeds a determined number of reads. Also in additional examples, the condition for triggering the read level calibration may occur based in part on a Raw Bit Error Rate (RBER) of read operations occurring for at least the respective block of the memory array.
In response to the identified condition (from operation 750), a read level calibration operation may be performed on the memory device (operation 760). In an example, the read level voltage calibration operation includes performing sampling of various areas of the memory array to sample threshold voltage values and determine read voltage levels. In an example, such sampling includes sampling of the threshold voltage levels of the respective blocks identified from monitoring the read operation. In another example, such sampling includes sampling of threshold voltage levels of respective groups of a plurality of blocks hosting respective blocks.
The read level calibration operation determines one or more values of the read voltage that more accurately reflect the threshold voltage of the respective block; this value is then used to update the read voltage level used to read one or more pages of the respective block (operation 770). The updated read voltage levels may then be utilized in subsequent read operations for reading one or more pages having a respective block (operation 780). In another example, read voltage levels are updated and utilized based on a group of blocks (e.g., for respective dies); in yet another example, read voltage levels are tracked, updated, and utilized based on a subset of the respective block (e.g., for respective pages or other groups of memory cells within the block).
Based on the techniques discussed above, the read voltage may be triggered, identified, and tracked based on the host IO state rather than the overall inaccurate memory array state. Thus, it should be understood that the techniques discussed herein may be optimized to track the pattern of reads occurring at the physical level to improve the accuracy of any resulting voltage adjustments. Furthermore, the techniques for sampling and trigger voltage calibration may be modified to be used integrated with existing calibration methods to provide minimal or even zero impact compared to conventional sampling.
Fig. 8 illustrates a block diagram of an example machine 800 on which any one or more of the techniques (e.g., methods) discussed herein may be performed. In alternative embodiments, the machine 800 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 800 may operate as a server machine, a client machine, or in a server-client network environment. In an example, the machine 800 may operate as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 800 may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a mobile telephone, a web appliance, an IoT device, an automotive system, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Moreover, although only a single machine is illustrated in the figures, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.
Examples described herein may include or be operable by logic, components, devices, packages, or mechanisms. A circuit system is a collection of circuits (e.g., a set of circuits) implemented in tangible physics (e.g., simple circuits, gates, logic, etc.) that includes hardware. The circuitry membership may vary flexibly over time and with potential hardware variability. The circuitry includes members that may perform particular tasks in operation, either individually or in combination. In an example, the hardware of the circuitry may be designed unchanged to implement a particular operation (e.g., hardwired). In an example, the hardware of the circuitry may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including computer-readable media physically modified (e.g., magnetic, electrical, movable placement of mass-invariant particles, etc.) to encode instructions for a particular operation. When physical components are connected, the underlying electrical properties of the hardware components change, for example, from an insulator to a conductor, or vice versa. The instructions enable participating hardware (e.g., execution units or load mechanisms) to create members of the circuitry in hardware via the variable connections to perform portions of particular tasks while in operation. Thus, when the device operates, the computer-readable medium is communicatively coupled to other components of the circuitry. In an example, any of the physical components may be used in more than one member of more than one circuitry. For example, in operation, an execution unit may be used in a first circuit of a first circuitry at one point in time and reused by a second circuit in the first circuitry or a third circuit in a second circuitry at a different time.
A machine (e.g., computer system) 800 (e.g., host device 105, memory device 110, etc.) may include a hardware processor 802 (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a hardware processor core, or any combination thereof, such as memory controller 115, etc.), a main memory 804, and a static memory 806, some or all of which may communicate with each other via an interconnect (e.g., bus) 808. The machine 800 may further include a display unit 810, an alphanumeric input device 812 (e.g., a keyboard), and a User Interface (UI) navigation device 814 (e.g., a mouse). In an example, the display unit 810, the input device 812, and the UI navigation device 814 may be a touch screen display. Additionally, the machine 800 may include a storage device (e.g., a driver unit) 816, a signal generation device 818 (e.g., a speaker), a network interface device 820, and one or more sensors 816 (e.g., a Global Positioning System (GPS) sensor, compass, accelerometer, or other sensor). The machine 800 may include an output controller 828 connected, for example, serially (e.g., Universal Serial Bus (USB)), in parallel or otherwise wired or wireless (e.g., Infrared (IR), Near Field Communication (NFC), etc.) to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).
The storage 816 may include a machine-readable medium 822 on which is stored one or more sets of data structures or instructions 824 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 824 may also reside, completely or at least partially, within the main memory 804, static memory 806, or within the hardware processor 802 during execution thereof by the machine 800. In an example, one or any combination of the hardware processor 802, the main memory 804, the static memory 806, or the storage device 816 may constitute the machine-readable medium 822.
Although the machine-readable medium 822 is illustrated as a single medium, the term "machine-readable medium" can include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) that are configured to store the one or more instructions 824.
The term "machine-readable medium" can include any medium that is capable of storing, encoding or carrying instructions for execution by the machine 800 and that cause the machine 800 to perform any one or more of the techniques of this disclosure or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media can include solid-state memory and optical and magnetic media. In an example, a mass machine-readable medium includes a machine-readable medium having a plurality of constant (e.g., stationary) mass particles. Thus, a mass machine-readable medium is not a transitory propagating signal. Particular examples of a mass machine-readable medium may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.
Instructions 824 (e.g., software, programs, an Operating System (OS), etc.) or other data are stored on the storage device 821 and may be accessed by the memory 804 for use by the processor 802. Memory 804, such as DRAM, is typically faster but volatile, and thus is a different type of storage device than storage device 821, such as SSD, which is suitable for long-term storage, including when in a "cut-off condition. Instructions 824 or data used by a user or the machine 800 are typically loaded into memory 804 for use by the processor 802. When memory 804 is full, virtual space from storage 821 may be allocated to supplement memory 804; however, because the storage 821 device is typically slower than the memory 804 and the write speed is typically at least twice slower than the read speed, using virtual memory can significantly reduce the user experience due to storage latency (as compared to memory 804 (e.g., DRAM)). Furthermore, using storage device 821 for virtual memory may substantially shorten the usable life of storage device 821.
And virtual memoryMemory versus virtual memory compression (e.g. virtual memory compression)
Storage devices optimized for mobile electronic devices or mobile storage devices typically include MMC solid state storage devices (e.g., micro secure digital (microSD)TM) Cards, etc.). MMC devices include several parallel interfaces (e.g., an 8-bit parallel interface) with a host device and are typically components that are removable and separable from the host device. By contrast, eMMCTMDevice attached to circuit board and treated as a component of host device, its read speed and based on serial ATATMSSD devices (serial AT (advanced technology) attachment or SATA) are comparable. However, mobile device performance requirements are continually increasing, e.g., to fully implement virtual or augmented reality devices, to take advantage of increased network speeds, and so forth. In response to this demand, the storage device has been transitioned from the parallel communication interface to the serial communication interface. A Universal Flash Storage (UFS) device including a controller and firmware communicates with a host device using a Low Voltage Differential Signaling (LVDS) serial interface with a dedicated read/write path to further facilitate greater read/write speeds.
Utilizing any of a number of transport protocols, such as frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), hypertext transfer protocol (HTTP), and the like, the instructions 824 may be further transmitted or received over a communication network 826 using a transmission medium via the network interface device 820. Example communication networks may include a Local Area Network (LAN), a Wide Area Network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a Plain Old Telephone System (POTS) network, and a wireless data network (e.g., referred to as
The foregoing detailed description includes references to the accompanying drawings, which form a part hereof. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only the elements shown or described are provided. Moreover, the inventors also contemplate examples using any combination or permutation of the elements shown or described (or one or more aspects thereof) with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.
In this document, the terms "a" or "an" are used, independently of any other instance or use of "at least one" or "one or more," as is common in patent documents, to include one or more than one. In this document, the term "or" is used to refer to a non-exclusive or, such that "a or B" may include "a but not B," "B but not a," and "a and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain-english equivalents of the respective terms "comprising" and "wherein". Furthermore, in the following claims, the terms "comprising" and "including" are open-ended, i.e., a system, device, article, or process that includes elements in addition to those listed after such term in a claim is still considered to be within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
In various examples, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of operational circuitry, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a Digital Signal Processor (DSP), or any other type of processor or processing circuit, including groups of processors or multi-core devices.
As used in this disclosure, the term "horizontal" is defined as a plane parallel to a conventional plane or surface of a substrate (e.g., the plane beneath a wafer or die), regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "on …", "above …", and "below …" are defined with respect to a conventional plane or surface on the top or exposed surface of the substrate, regardless of the orientation of the substrate; meanwhile, "on …" is intended to imply that a structure is in direct contact (if not explicitly indicated to the contrary) with respect to another structure on which it is located; the terms "above …" and "below …" expressly contemplate identifying the relative placement of structures (or layers, features, etc.), unless expressly so identified, which expressly includes, but is not limited to, direct contact between the identified structures. Similarly, the terms "above …" and "below …" are not limited to a horizontal orientation, as a structure may be "above" a reference structure if it is the outermost portion of the construction in question at some point in time, even though such structure extends vertically relative to the reference structure, rather than being horizontally oriented.
The terms "wafer and" substrate "are used generically herein to refer to any structure on which an integrated circuit is formed and to such structures during the various stages of integrated circuit fabrication. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
Various embodiments in accordance with the present invention and described herein include memories that utilize a vertical structure of memory cells, such as a nand string of memory cells. As described herein, the directional adjective will be considered relative to the surface of the substrate on which the memory cell is formed (i.e., the vertical structure will be considered to extend away from the substrate surface, the bottom end of the vertical structure will be considered to be the end closest to the substrate surface and the top end of the vertical structure will be considered to be the end furthest from the substrate surface).
As used herein, directional adjectives such as horizontal, vertical, orthogonal, parallel, and the like may refer to a relative orientation, and unless otherwise specified, are not intended to require strict adherence to a particular geometric property. For example, as used herein, a vertical structure need not be strictly perpendicular to a surface of a substrate, but may be substantially perpendicular to the surface of the substrate, and may form an acute angle (e.g., between 60 degrees to 120 degrees, etc.) with the surface of the substrate.
In some embodiments described herein, different doping configurations may be applied to the source side Select Gate (SGS), Control Gate (CG), and drain side Select Gate (SGD), each of which may be formed of or at least include polysilicon in this example, thus allowing these layers (e.g., polysilicon, etc.) to have different etch rates when exposed to an etch solution. For example, in forming a monolithic pillar in a 3D semiconductor device, the SGS and CG may form a recess, while the SGD may remain less or even not recessed. Thus, these doping configurations may enable selective etching into different layers (e.g., SGS, CG, and SGD) in a 3D semiconductor device by using an etching solution, such as tetramethylammonium hydroxide (TMCH).
As used herein, operating a memory cell includes reading from, writing to, or erasing a memory cell. The operation of bringing a memory cell to a desired state is referred to herein as "programming" and can include both writing to or erasing from the memory cell (e.g., the memory cell can be programmed to an erased state).
In accordance with one or more embodiments of the present disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located within or outside of a memory device is capable of determining (e.g., selecting, setting, adjusting, calculating, changing, clearing, communicating, adapting, deriving, defining, utilizing, modifying, applying, etc.) a number of wear cycles or a wear state (e.g., recording wear cycles, counting operations of the memory device as operations of the memory device occur, tracking operations incurred by the memory device, evaluating memory device characteristics corresponding to the wear state, etc.).
In accordance with one or more embodiments of the present disclosure, a memory access device may be configured to provide wear cycle information to a memory device using each memory operation. Memory device control circuitry, such as control logic, may be programmed to compensate for memory device performance changes corresponding to wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.
It will be understood that when an element is referred to as being "on," "connected to" or "coupled with" another element, it can be directly on, connected or coupled with the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled with" another element, there are no intervening elements or layers present. Two elements may be coupled or directly coupled unless otherwise indicated if they are shown in the drawings with a line connecting them.
The method examples described herein may be at least partially machine or computer implemented. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include, for example, encoding of microcode, assembly language code, higher level language code, or the like. Such code may include computer readable instructions for performing various methods. The code may form part of a computer program product. Further, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, e.g., during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks such as compact disks and digital optical disks, magnetic cassettes, memory cards or strips, Random Access Memories (RAMs), Read Only Memories (ROMs), Solid State Drives (SSDs), Universal Flash Storage (UFS) devices, embedded mmc (emmc) devices, and the like.
Additional examples of the described embodiments of the invention are set forth according to the structures and techniques described above and specified in the examples and claims below.
Example 1 is a memory device, comprising: a NAND memory array having groups of multiple blocks of memory cells; and a memory controller operably coupled to the memory array, the memory controller for performing operations comprising: monitoring read operations occurring for respective blocks of the memory array; identifying a condition for triggering a read level calibration based at least in part on the read operation occurring for the respective block; and in response to the identified condition, performing the read level calibration based on threshold voltage levels of a respective group of a plurality of blocks hosting the respective block, wherein the read level calibration is performed based at least in part on threshold voltages used to read the respective block.
In example 2, the subject matter of example 1 includes monitoring the read operations by tracking a number of reads for the respective block, and wherein the condition for triggering the read level calibration is identified based at least in part on the number of reads occurring for the respective block exceeding a determined number of reads.
In example 3, the subject matter of example 2 includes the operations of the memory controller, the operations further comprising monitoring erase operations occurring for the respective block, wherein the condition for triggering the read level calibration is further identified based on a number of erases for the respective block exceeding a determined number of erases.
In example 4, the subject matter of example 3 includes tracking the number of reads for the respective block with a first counter saved in a memory accessible by the memory controller, wherein tracking the number of erases for the respective block with a second counter saved in the memory accessible by the memory controller, and wherein resetting the first counter for erases occurring for the respective block.
In example 5, the subject matter of examples 1-4 includes monitoring the read operations by tracking a number of reads for the respective group of a plurality of blocks that host the respective block, wherein the condition for triggering the read level calibration is identified based at least in part on the number of reads occurring for the respective group of a plurality of blocks exceeding a determined number of reads.
In example 6, the subject matter of examples 1-5 includes that the condition for triggering the read level calibration is further based in part on a Raw Bit Error Rate (RBER) of read operations occurring for at least the respective block of the memory array.
In example 7, the subject matter of examples 1-6 includes performing the read level calibration by performing sampling for reading the threshold voltage of the respective block and for reading threshold voltages of other blocks in the group of a plurality of blocks located in the memory array.
In example 8, the subject matter of example 7 includes identifying, within the memory array, the other blocks in the memory array included in the sample based on a number of read operations performed in respective blocks of the other blocks.
In example 9, the subject matter of examples 7-8 includes identifying within the memory array the other blocks in the memory array included in the sample based on at least one of: randomly sampling the other blocks in the memory array, sampling the other blocks in the memory array based on a data age, or sampling the other blocks in the memory array based on a Raw Bit Error Rate (RBER) corresponding to the other blocks.
In example 10, the subject matter of examples 1-9 includes monitoring read operations for the respective block by monitoring the read operations for one or more portions of the respective block.
In example 11, the subject matter of example 10 includes that the monitored portion of the respective block includes a page of the respective block.
In example 12, the subject matter of examples 1-11 includes, wherein the memory device is operably coupled to a host, wherein the host causes a command to perform a respective read in the plurality of blocks in the memory array, and wherein the respective read includes a plurality of reads occurring for a logical block address corresponding to a page located within the respective block.
In example 13, the subject matter of examples 1-12 includes the read level calibration updating one or more read voltage levels used to read one or more pages of the respective block in subsequent read operations occurring for the one or more pages of the respective block.
In example 14, the subject matter of examples 1-13 includes that the block of memory cells of the memory array includes at least one of: single Level Cell (SLC), multi-level cell (MLC), Triple Layer Cell (TLC), or Quadruple Layer Cell (QLC) "nand" memory cells.
In example 15, the subject matter of examples 1-14 includes arranging the memory array as a stack of three-dimensional (3D) "nand" dies, wherein the respective group of a plurality of blocks hosting the respective block corresponds to a group of blocks provided by a respective die in the stack of 3D "nand" dies.
Example 16 is a method for optimizing voltage read level calibration in a memory device, the method comprising a plurality of operations performed by a memory controller of a nand memory array, and the memory array having a group of a plurality of blocks of memory cells, wherein the operations comprise: monitoring read commands issued to respective blocks of the memory array; identifying a condition for triggering a read level calibration based at least in part on the read command issued to the respective block; and in response to the identified condition, performing the read level calibration based on threshold voltage levels of a respective group of a plurality of blocks hosting the respective block, wherein the read level calibration is performed based at least in part on threshold voltages used to read the respective block; wherein the read level calibration updates a read voltage level used to read a page of the respective block in a subsequent read operation for the page of the respective block.
In example 17, the subject matter of example 16 includes monitoring the read operations by tracking a number of reads for the respective block, and wherein the condition for triggering the read level calibration is identified based at least in part on the number of reads occurring for the respective block exceeding a determined number of reads.
In example 18, the subject matter of example 17 includes monitoring erase operations occurring for the respective block, wherein the condition for triggering the read level calibration is further identified based on a number of erases for the respective block exceeding a determined number of erases.
In example 19, the subject matter of example 18 includes tracking the number of reads for the respective block with a first counter saved in a memory accessible by the memory controller, wherein tracking the number of erases for the respective block with a second counter saved in the memory accessible by the memory controller, and wherein resetting the first counter for erases occurring for the respective block.
In example 20, the subject matter of examples 16-19 includes monitoring the read operations by tracking a number of reads for the respective group of a plurality of blocks that host the respective block, and wherein the condition for triggering the read level calibration is identified based at least in part on the number of reads that occur for the respective group of a plurality of blocks exceeding a determined number of reads.
In example 21, the subject matter of examples 16-20 includes that the condition for triggering the read level calibration is further based in part on a Raw Bit Error Rate (RBER) of read operations occurring for at least the respective block of the memory array.
In example 22, the subject matter of examples 16-21 includes performing the read level calibration by performing sampling for reading the threshold voltage of the respective block and for reading threshold voltages of other blocks in the group of a plurality of blocks located in the memory array.
In example 23, the subject matter of example 22 includes identifying, within the memory array, the other blocks in the memory array included in the sample based on a number of read operations performed in respective blocks of the other blocks.
In example 24, the subject matter of examples 22-23 includes identifying within the memory array the other blocks in the memory array included in the sample based on at least one of: randomly sampling the other blocks in the memory array, sampling the other blocks in the memory array based on a data age, or sampling the other blocks in the memory array based on a Raw Bit Error Rate (RBER) corresponding to the other blocks.
In example 25, the subject matter of examples 16-24 includes monitoring read operations for the respective block by monitoring the read operations for one or more portions of the respective block.
In example 26, the subject matter of example 25 includes that the monitored portion of the respective block includes a page of the respective block.
In example 27, the subject matter of examples 16-26 includes the memory device operably coupled to a host, wherein the host causes a command to perform a respective read in the plurality of blocks in the memory array, and wherein the respective read includes a plurality of reads occurring for logical block addresses corresponding to pages located within the respective block.
In example 28, the subject matter of examples 16-27 includes the read level calibration updating one or more read voltage levels used to read one or more pages of the respective block in subsequent read operations occurring for the one or more pages of the respective block.
In example 29, the subject matter of examples 16-28 includes that the block of memory cells of the memory array includes at least one of: single Level Cell (SLC), multi-level cell (MLC), Triple Layer Cell (TLC), or Quadruple Layer Cell (QLC) "nand" memory cells.
In example 30, the subject matter of examples 16-29 includes arranging the memory array as a stack of three-dimensional (3D) "nand" dies, wherein the respective group of a plurality of blocks that host the respective block corresponds to a group of blocks provided by a respective die in the stack of 3D "nand" dies.
Example 31 is a device-readable storage medium that provides instructions that when executed by a controller of a memory device optimize voltage read level calibration in the memory device, wherein the instructions cause the controller to perform operations in accordance with any of the techniques of examples 1-30.
Example 32 is an apparatus comprising respective means for performing any of the methods or techniques of examples 1-30.
Example 33 is a system, apparatus, or device to perform the operations of any of examples 1-30.
Example 34 is a tangible machine-readable medium comprising instructions for performing or implementing the operations of any of examples 1-30.
Example 35 is a method for performing the operations of any of examples 1-30.
The above description is intended to be illustrative and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, for example, by one of ordinary skill in the art after reviewing the above description. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, various features may be grouped together in specific embodiments to simplify the present disclosure. This should not be construed as an admission that any of the non-claimed features are essential to any of the claims. Rather, inventive subject matter may not have all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.