阅读说明：本技术 高填充率逐步扫描型spad激光雷达电路 (High-filling-rate step-by-step scanning type SPAD laser radar circuit ) 是由 朱樟明 胡进 刘马良 杨银堂 于 2020-05-09 设计创作，主要内容包括：本发明公开了一种逐步扫描型的单SPAD像素电路,该单SPAD像素电路包括单光子雪崩二极管、晶体管M1、晶体管M2、与门AND和晶体管M3,单光子雪崩二极管的阴极连接到第一电压端,单光子雪崩二极管的阳极连接晶体管M1的漏极、晶体管M2的漏极和与门AND的第一输入端,晶体管M1的栅极连接复位信号端,晶体管M1的源极和晶体管M3的源极连接至接地端,晶体管M2的栅极连接窗口控制信号端,晶体管M2的源极连接第二电压端,与门AND的第二输入端连接窗口控制信号端,与门AND的输出端连接晶体管M3的栅极,晶体管M3的漏极连接总线。本发明提供的逐步扫描型的紧凑的单SPAD像素电路,该单SPAD像素电路由单个SPAD和较少的晶体管构成,从而增加了硅片的利用率,降低了成本。(The invention discloses a single SPAD pixel circuit of a progressive scanning type, which comprises a single photon avalanche diode, a transistor M1, a transistor M2, an AND gate AND AND a transistor M3, wherein the cathode of the single photon avalanche diode is connected to a first voltage end, the anode of the single photon avalanche diode is connected with the drain of the transistor M1, the drain of the transistor M2 AND the first input end of the AND gate AND, the gate of the transistor M1 is connected with a reset signal end, the source of the transistor M1 AND the source of the transistor M3 are connected to the ground end, the gate of the transistor M2 is connected with a window control signal end, the source of the transistor M2 is connected with a second voltage end, the second input end of the AND gate AND is connected with a window control signal end, the output end of the AND gate is connected with the gate of the transistor M3, AND the drain of the transistor. The step-by-step scanning type compact single SPAD pixel circuit provided by the invention is composed of a single SPAD and a few transistors, so that the utilization rate of a silicon wafer is increased, and the cost is reduced.)

1. A single SPAD pixel circuit of a step-and-scan type, comprising: a single photon avalanche diode, a transistor M1, a transistor M2, an AND gate AND a transistor M3, wherein,

the cathode of the single photon avalanche diode is connected to a first voltage end, the anode of the single photon avalanche diode is connected to the drain of the transistor M1, the drain of the transistor M2 AND the first input end of the AND gate AND, the gate of the transistor M1 is connected to a reset signal end, the source of the transistor M1 AND the source of the transistor M3 are connected to the ground end, the gate of the transistor M2 is connected to a window control signal end, the source of the transistor M2 is connected to a second voltage end, the second input end of the AND gate AND is connected to the window control signal end, the output end of the AND gate AND is connected to the gate of the transistor M3, AND the drain of the transistor M3 is connected to the bus.

2. The single SPAD pixel circuit of step-by-step scanning type according to claim 1, wherein the transistors M1 and M3 are NMOS transistors and the transistor M2 is a PMOS transistor.

3. A time-division multiplexed STOP generating circuit, comprising: a plurality of gate signal generation modules for generating window control signals, a plurality of groups of single SPAD pixel modules and a plurality of transistors M4, wherein each single SPAD pixel module comprises N rows and M columns of single SPAD pixel circuits, the number of the gate signal generation modules is N, and the single SPAD pixel circuits in the same row in each single SPAD pixel module provide the window control signals through the same gate signal generation module, the single SPAD pixel circuits in different rows in each single SPAD pixel module provide the window control signals through different gate signal generation modules, wherein,

the single SPAD pixel circuits in the same column in each single SPAD pixel module are commonly connected with a bus, and are connected with the drain of a transistor M4 through the bus, the gate of the transistor M4 is connected with the ground terminal, and the source of the transistor M4 is connected with a voltage source.

4. The time-division multiplexed STOP generating circuit of claim 3, wherein the gating signal generating module comprises:

the first counting module is used for counting the repeated times of each window control signal;

the second counting module is used for increasing the counting times of the second counting module once when the repetition times of the window control signals counted by the first timing module reach the preset times;

and the third counting module is used for driving the third timing module to calculate the driving clock in S periods when the rising edge of the driving clock occurs, wherein S is the counting frequency of the third timing module, and when the counting frequency of the third timing module is equal to the current counting frequency of the second timing module, the window control signal is in a high level.

5. The time-division multiplexed STOP generation circuit of claim 3, comprising a single photon avalanche diode, a transistor M1, a transistor M2, an AND gate AND, AND a transistor M3, wherein,

the cathode of the single photon avalanche diode is connected to a first voltage end, the anode of the single photon avalanche diode is connected to the drain of the transistor M1, the drain of the transistor M2 AND the first input end of the AND gate AND, the gate of the transistor M1 is connected to a reset signal end, the source of the NM1 AND the source of the transistor M3 are connected to the ground end, the gate of the transistor M2 is connected to a window control signal end, the source of the transistor M2 is connected to a second voltage end, the second input end of the AND gate AND is connected to the window control signal end, the output end of the AND gate AND is connected to the gate of the transistor M3, AND the drain of the transistor M3 is connected to the bus.

6. The time-division multiplexing STOP generation circuit of claim 5, wherein the transistor M1 and the transistor M3 are N-type transistors and the transistor M2 is a P-type transistor.

7. The time-division multiplexing STOP generation circuit of claim 6, wherein the drains of the transistors M3 of the single SPAD pixel circuits in the same column in each of the single SPAD pixel modules are commonly connected to the bus and connected to the drain of the transistor M4 through the bus.

8. The time-division multiplexing STOP generation circuit of claim 3, wherein the transistor M4 is a PMOS transistor.

Technical Field

The invention belongs to the technical field of laser radars, and particularly relates to a step-by-step scanning type single SPAD pixel circuit and a time division multiplexing STOP generation circuit.

Background

In recent years, laser ranging systems have become a key technology in many fields, such as spacecraft navigation and autopilot assistance. To obtain better spatial resolution, more pixel cells are required and the fill factor is also increased. The fill factor is defined as the proportion of the photosensitive area that is occupied throughout the illuminated area. The smaller the non-photosensitive area, the better the spatial continuity of the image.

In a lidar chip, a photosensor is responsible for converting the returned optical signal into an electrical signal. For long-distance application, a plurality of SPADs are generally required to synthesize a macropixel and combine a certain algorithm to solve the non-ideal effect, so that the area of a Single pixel is increased, particularly the cost is increased in the application of a large-array pixel array, in order to obtain the distance corresponding to each pixel, each pixel generally corresponds to a Time To Digital Converter (TDC), but the TDC itself needs to consume a certain silicon area, and more importantly, the area is a non-photosensitive area, thus reducing the fill factor of the pixel.

In conventional solutions the TDC can be placed outside the pixel array, but this requires data and address lines to be brought out of the entire pixel array. But for large array pixel applications, the number of data lines and address lines will increase dramatically as the number of pixels increases. In view of the limitations of the manufacturing process in integrated circuits, a certain distance is required between signal lines (metal lines). The sharply increased metal lines force the distance between pixels to be large, which in turn reduces the fill factor. Another approach also includes the use of a shared TDC approach, i.e., several pixels share a TDC. This approach has a significant limitation on the scenarios used. When more than one of several pixels sharing a TDC is triggered, the data can only be discarded, which is unacceptable outdoors, especially in high light conditions.

Therefore, with the rapid development of the semiconductor technology, the research and implementation of the laser radar circuit applied to the large-scale array and having a high pixel filling rate have great significance and application prospects.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a single SPAD pixel circuit of a step-by-step scanning type and a STOP generation circuit of time division multiplexing. The technical problem to be solved by the invention is realized by the following technical scheme:

a single SPAD pixel circuit of the step-by-step scanning type, comprising: a single photon avalanche diode, a transistor M1, a transistor M2, an AND gate AND a transistor M3, wherein,

the cathode of the single photon avalanche diode is connected to a first voltage end, the anode of the single photon avalanche diode is connected to the drain of the transistor M1, the drain of the transistor M2 AND the first input end of the AND gate AND, the gate of the transistor M1 is connected to a reset signal end, the source of the transistor M1 AND the source of the transistor M3 are connected to the ground end, the gate of the transistor M2 is connected to a window control signal end, the source of the transistor M2 is connected to a second voltage end, the second input end of the AND gate AND is connected to the window control signal end, the output end of the AND gate AND is connected to the gate of the transistor M3, AND the drain of the transistor M3 is connected to the bus.

In one embodiment of the present invention, the transistor M1 and the transistor M3 are NMOS transistors, and the transistor M2 is a PMOS transistor.

An embodiment of the present invention further provides a time-division multiplexing STOP generation circuit, including: a plurality of gate signal generation modules for generating window control signals, a plurality of groups of single SPAD pixel modules and a plurality of transistors M4, wherein each single SPAD pixel module comprises N rows and M columns of single SPAD pixel circuits, the number of the gate signal generation modules is N, and the single SPAD pixel circuits in the same row in each single SPAD pixel module provide the window control signals through the same gate signal generation module, the single SPAD pixel circuits in different rows in each single SPAD pixel module provide the window control signals through different gate signal generation modules, wherein,

the single SPAD pixel circuits in the same column in each single SPAD pixel module are commonly connected with a bus, and are connected with the drain of a transistor M4 through the bus, the gate of the transistor M4 is connected with the ground terminal, and the source of the transistor M4 is connected with a voltage source.

In one embodiment of the present invention, the gating signal generating module comprises:

the first counting module is used for counting the repeated times of each window control signal;

the second counting module is used for increasing the counting times of the second counting module once when the repetition times of the window control signals counted by the first timing module reach the preset times;

and the third counting module is used for driving the third timing module to calculate the driving clock in S periods when the driving clock rises, wherein S is the counting number of the third timing module, and when the counting number of the third timing module is equal to the current counting number of the second timing module, the window control signal is in a high level.

In one embodiment of the invention, the single photon avalanche diode, transistor M1, transistor M2, AND gate AND, AND transistor M3 are included, wherein,

the cathode of the single photon avalanche diode is connected to a first voltage end, the anode of the single photon avalanche diode is connected to the drain of the transistor M1, the drain of the transistor M2 AND the first input end of the AND gate AND, the gate of the transistor M1 is connected to a reset signal end, the source of the NM1 AND the source of the transistor M3 are connected to the ground end, the gate of the transistor M2 is connected to a window control signal end, the source of the transistor M2 is connected to a second voltage end, the second input end of the AND gate AND is connected to the window control signal end, the output end of the AND gate AND is connected to the gate of the transistor M3, AND the drain of the transistor M3 is connected to the bus.

In one embodiment of the present invention, the transistor M1 and the transistor M3 are N-type transistors, and the transistor M2 is a P-type transistor.

In one embodiment of the invention, the drains of the transistors M3 of the single SPAD pixel circuits in the same column in each single SPAD pixel module are commonly connected to the bus, and are connected to the drain of the transistor M4 through the bus.

In one embodiment of the present invention, the transistor M4 is a PMOS transistor.

The invention has the beneficial effects that:

the invention provides a compact single SPAD pixel circuit based on a gated step-by-step scanning type, which is composed of a single SPAD and a few transistors, thereby increasing the utilization rate of a silicon wafer and reducing the cost.

The invention also provides a time division multiplexing STOP generating circuit, thereby reducing the complexity of wiring among pixels, and simultaneously combining the mode of placing the TDC at the periphery of the photosensitive element, under the condition of the same silicon area, the invention can realize larger spatial resolution and higher filling factor.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic circuit diagram of a single SPAD pixel circuit of step-by-step scanning type according to an embodiment of the present invention;

FIG. 2 is a timing diagram of the single SPAD pixel circuit of step-and-scan type in FIG. 1 according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a gate-controlled step-by-step scanning imaging system according to an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of a time-division multiplexing STOP generating circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the timing of the control signals of a time-division multiplexing STOP generating circuit according to an embodiment of the present invention;

FIG. 6 is a flowchart illustrating a method for generating a window control signal according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating a timing relationship between a driving clock and a system clock according to an embodiment of the present invention;

fig. 8 is a timing diagram of a gated step-by-step scanning-based imaging according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.