阅读说明：本技术 增强侧面光强的发光二极管芯片及其制造方法 (Light emitting diode chip for enhancing side light intensity and manufacturing method thereof ) 是由 兰叶 王江波 吴志浩 于 2021-05-18 设计创作，主要内容包括：本公开提供了一种增强侧面光强的发光二极管芯片及其制造方法,属于半导体技术领域。发光二极管芯片的衬底的第二表面上布置有多个尖刺结构,第二表面为与第一表面相对的一面,所述尖刺结构为直角三棱柱,所述直角三棱柱包括第一棱柱面和第二棱柱面,所述第一棱柱面垂直于所述第二表面,所述第二棱柱面连接所述第一棱柱面和所述第二表面,且所述第二棱柱面与所述第二表面之间的夹角为θ,0°＜θ≤90°,每个所述直角三棱柱的所述第二棱柱面均朝向所述衬底的中心线。采用该发光二极管芯片可以增强侧面光强。(The disclosure provides a light emitting diode chip for enhancing side light intensity and a manufacturing method thereof, and belongs to the technical field of semiconductors. The LED chip comprises a substrate, wherein a plurality of spine structures are arranged on a second surface of the substrate of the LED chip, the second surface is a surface opposite to the first surface, the spine structures are right-angle triangular prisms, each right-angle triangular prism comprises a first prism surface and a second prism surface, the first prism surface is perpendicular to the second surface, the second prism surface is connected with the first prism surface and the second surface, an included angle between the second prism surface and the second surface is theta, theta is larger than 0 degree and smaller than or equal to 90 degrees, and the second prism surface of each right-angle triangular prism faces to the central line of the substrate. The side light intensity can be enhanced by adopting the light emitting diode chip.)

1. A light emitting diode chip for enhancing side light intensity comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, and the P-type semiconductor layer and on the P-type electrode, the protective layer is laid on the insulating layer, its characterized in that:

the substrate comprises a substrate and a substrate, wherein a plurality of spine structures are arranged on a second surface of the substrate, the second surface is a surface opposite to the first surface, the spine structures are right-angle triangular prisms, each right-angle triangular prism comprises a first prism surface and a second prism surface, the first prism surface is perpendicular to the second surface, the second prism surface is connected with the first prism surface and the second surface, an included angle between the second prism surface and the second surface is theta, theta is larger than 0 degree and smaller than or equal to 90 degrees, and the second prism surface of each right-angle triangular prism faces to the central line of the substrate.

2. The light-emitting diode chip of claim 1, wherein the θ of each of the right triangular prisms gradually decreases from the center of the substrate to the edge of the substrate.

3. The light emitting diode chip of claim 2, wherein θ is greater than or equal to 45 ° and less than or equal to 75 °.

4. The light-emitting diode chip according to claim 3, wherein the second surface of the substrate includes, from the center of the substrate to the edge of the substrate, a first region, a second region and a third region which are adjacent to each other in this order, θ corresponding to the plurality of right-angled triangular prisms located in the first region is 65 ° to 75 °, θ corresponding to the plurality of right-angled triangular prisms located in the second region is 55 ° to 65 °, and θ corresponding to the plurality of right-angled triangular prisms located in the third region is 45 ° to 55 °.

5. The light emitting diode chip as claimed in any one of claims 1 to 4, wherein each of the plurality of spike structures protrudes from the second surface to a same height.

6. The light-emitting diode chip as claimed in any one of claims 1 to 4, wherein the substrate is a patterned sapphire substrate, the first surface of the patterned sapphire substrate has a plurality of uniformly spaced pyramidal protrusions, the base diameter of each pyramidal protrusion is 1.3-1.7 um, and the height of each pyramidal protrusion is 0.8-1.2 um.

7. A method of fabricating a light emitting diode chip with enhanced side light intensity, the method comprising:

providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;

growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the first surface of the substrate in sequence;

forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;

forming a P-type electrode on the P-type semiconductor layer;

forming an N-type electrode on the N-type semiconductor layer in the groove;

insulating layers are formed in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode;

forming a protective layer on the insulating layer;

thinning the substrate;

forming a plurality of spike structures on a second surface of the substrate, wherein the spike structures are right-angled triangular prisms, each right-angled triangular prism comprises a first prism surface and a second prism surface, the first prism surface is perpendicular to the second surface, the second prism surface is connected with the first prism surface and the second surface, an included angle between the second prism surface and the second surface is theta, theta is larger than 0 degree and smaller than or equal to 90 degrees, and the second prism surface of each right-angled triangular prism faces the central line of the substrate.

8. The method of manufacturing according to claim 7, wherein the forming a plurality of spike structures on the second surface of the substrate comprises:

forming a plurality of the right triangular prisms on the second surface of the substrate, corresponding to the theta gradually decreasing, from the center of the substrate to the edge of the substrate.

9. The manufacturing method according to claim 7, wherein before growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer in this order on the first surface of the substrate, the manufacturing method further comprises:

it is right the substrate carries out graphical processing, graphical sapphire substrate the first surface has the toper arch of a plurality of interval equipartitions, every the bellied bottom diameter of toper is 1.3 ~ 1.7um, every the bellied height of toper is 0.8 ~ 1.2 um.

10. The method of manufacturing of claim 7, wherein after forming the plurality of spike structures on the second surface of the substrate, the method further comprises:

and carrying out invisible cutting and scratching on the substrate, wherein when the substrate is subjected to invisible cutting and scratching, the length of a light spot formed by laser gathering is 5-7 um.

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a light emitting diode chip for enhancing side light intensity and a method for manufacturing the same.

Background

A Light Emitting Diode (LED) is a semiconductor device capable of Emitting Light. By adopting different semiconductor materials and structures, LEDs can cover the full color range from ultraviolet to infrared, and have been widely used in economic life for display, decoration, communication, and the like.

The chip is a core device of the LED, and in the related art, the LED chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, and the protective layer is laid on the insulating layer. The insulating layer includes a passivation layer and a Distributed Bragg Reflection (DBR) layer, which are sequentially stacked.

Through setting up the DBR layer in the above-mentioned flip LED chip, can increase substantially LED's luminous efficacy. Wherein, a part of light emitted by the active layer can be emitted from the P-type semiconductor layer, and the DBR layer can reflect the part of light back to the active layer, so that the part of light is finally emitted from the substrate direction, thereby improving the light emitting efficiency of the LED. However, the DBR layer has a problem of strong axial light, so that the light emitting intensity of the LED chip in the vertical direction is strong, and when the DBR layer is far away from the vertical direction, the light emitting intensity is significantly reduced, so that the light emitting from the side surface of the LED chip is weak, and the viewing angle of the display screen becomes limited.

Disclosure of Invention

The embodiment of the disclosure provides a light emitting diode chip for enhancing side light intensity and a manufacturing method thereof, which can enhance the side light intensity of the light emitting diode chip. The technical scheme is as follows:

on one hand, the light-emitting diode chip for enhancing the side light intensity comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, the protective layer is laid on the insulating layer,

the substrate comprises a substrate and a substrate, wherein a plurality of spine structures are arranged on a second surface of the substrate, the second surface is a surface opposite to the first surface, the spine structures are right-angle triangular prisms, each right-angle triangular prism comprises a first prism surface and a second prism surface, the first prism surface is perpendicular to the second surface, the second prism surface is connected with the first prism surface and the second surface, an included angle between the second prism surface and the second surface is theta, theta is larger than 0 degree and smaller than or equal to 90 degrees, and the second prism surface of each right-angle triangular prism faces to the central line of the substrate.

Optionally, the θ of each right triangular prism is gradually decreased from the center of the substrate to the edge of the substrate.

Alternatively, 45 ≦ θ ≦ 75.

Optionally, from the center of the substrate to the edge of the substrate, the second surface of the substrate includes a first region, a second region, and a third region that are adjacent to each other in this order, where θ corresponding to the plurality of right-angled triangular prisms located in the first region is 65 ° to 75 °, θ corresponding to the plurality of right-angled triangular prisms located in the second region is 55 ° to 65 °, and θ corresponding to the plurality of right-angled triangular prisms located in the third region is 45 ° to 55 °.

Optionally, the height of each spike structure protruding from the second surface is equal.

Optionally, the substrate is graphical sapphire substrate, graphical sapphire substrate the first surface has the toper arch of a plurality of interval equipartitions, every the bellied bottom diameter of toper is 1.3 ~ 1.7um, every the bellied height of toper is 0.8 ~ 1.2 um.

In another aspect, a method for manufacturing a light emitting diode chip for enhancing side light intensity is provided, the method comprising:

providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;

growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the first surface of the substrate in sequence;

forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;

forming a P-type electrode on the P-type semiconductor layer;

forming an N-type electrode on the N-type semiconductor layer in the groove;

insulating layers are formed in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode;

forming a protective layer on the insulating layer;

thinning the substrate;

forming a plurality of spike structures on a second surface of the substrate, wherein the spike structures are right-angled triangular prisms, each right-angled triangular prism comprises a first prism surface and a second prism surface, the first prism surface is perpendicular to the second surface, the second prism surface is connected with the first prism surface and the second surface, an included angle between the second prism surface and the second surface is theta, theta is larger than 0 degree and smaller than or equal to 90 degrees, and the second prism surface of each right-angled triangular prism faces the central line of the substrate.

Optionally, the forming a plurality of spike structures on the second surface of the substrate includes:

forming a plurality of the right triangular prisms on the second surface of the substrate, corresponding to the theta gradually decreasing, from the center of the substrate to the edge of the substrate.

Optionally, before growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the first surface of the substrate in this order, the manufacturing method further includes:

it is right the substrate carries out graphical processing, graphical sapphire substrate the first surface has the toper arch of a plurality of interval equipartitions, every the bellied bottom diameter of toper is 1.3 ~ 1.7um, every the bellied height of toper is 0.8 ~ 1.2 um.

Optionally, after forming the plurality of spike structures on the second surface of the substrate, the manufacturing method further includes:

and carrying out invisible cutting and scratching on the substrate, wherein when the substrate is subjected to invisible cutting and scratching, the length of a light spot formed by laser gathering is 5-7 um.

The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:

by forming a plurality of spike structures on the second surface of the substrate. Each spine structure is a right-angle triangular prism, a second prismatic surface of each right-angle triangular prism faces the central line of the substrate, the second prismatic surface is an inclined surface, the included angle between the second prismatic surface and the second surface is theta, and theta is larger than 0 degree and smaller than or equal to 90 degrees. When the second prismatic surface faces the central line of the substrate, the second prismatic surface inclines from the center of the substrate to the edge direction of the substrate, at the moment, the spine structure can play a role in guiding light, so that part of axial light emitted from the bottom of the substrate can be guided to the side light emitting of the chip through the spine structure more, the light emitting opening angle of the chip can be increased, the proportion of the side light emitting of the chip is increased, and the side light intensity of the light emitting diode chip is further enhanced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a light emitting diode chip for enhancing side light intensity according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a spike structure provided in an embodiment of the present disclosure;

FIG. 3 is a bottom view of a second surface of a substrate provided by embodiments of the present disclosure;

FIG. 4 is a schematic distribution diagram of P-type pads and N-type pads provided by the embodiment of the present disclosure;

fig. 5 is a flowchart of a method for manufacturing a light emitting diode chip with enhanced side light intensity according to an embodiment of the present disclosure;

fig. 6 is a flowchart of a method for manufacturing an led chip with enhanced side light intensity according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a light spot provided by the embodiment of the disclosure;

fig. 8 is a schematic distribution diagram of a light spot provided by the embodiment of the disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a light emitting diode chip for enhancing side light intensity provided by an embodiment of the present disclosure, and as shown in fig. 1, the light emitting diode chip includes a substrate 1, an N-type semiconductor layer 2, an active layer 3, a P-type semiconductor layer 4, an N-type electrode 5, a P-type electrode 6, an insulating layer 7, and a protective layer 8. An N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 are sequentially stacked on the first surface 1a of the substrate 1. A groove extending to the N-type semiconductor layer 2 is formed in the P-type semiconductor layer 4, an N-type electrode 5 is arranged on the N-type semiconductor layer 2 in the groove, and the P-type electrode 5 is arranged on the P-type semiconductor layer 4. An insulating layer 7 is laid in the groove and on the N-type electrode 5, and on the P-type semiconductor layer 4 and the P-type electrode 6, and a protective layer 8 is laid on the insulating layer 7.

A plurality of spike structures 11 are disposed on a second surface 1b of the substrate 1, the second surface 1b being a surface opposite to the first surface 1 a.

Fig. 2 is a schematic structural diagram of a spike structure provided in an embodiment of the present disclosure, and as shown in fig. 2, the spike structure 11 is a right-angle triangular prism, and the right-angle triangular prism includes a first prism surface 11a and a second prism surface 11 b. With reference to fig. 1, the first prism face 11a is perpendicular to the second surface 1b, the second prism face 11b connects the first prism face 11a and the second surface 1b, an included angle between the second prism face 11b and the second surface 1b is θ, θ is greater than 0 ° and less than or equal to 90 °, and the second prism face 11b of each right-angled triangular prism faces the center line of the substrate 1.

The embodiment of the disclosure forms a plurality of spine structures on the second surface of the substrate. Each spine structure is a right-angle triangular prism, a second prismatic surface of each right-angle triangular prism faces the central line of the substrate, the second prismatic surface is an inclined surface, the included angle between the second prismatic surface and the second surface is theta, and theta is larger than 0 degree and smaller than or equal to 90 degrees. When the second prismatic surface faces the central line of the substrate, the second prismatic surface inclines from the center of the substrate to the edge direction of the substrate, at the moment, the spine structure can play a role in guiding light, so that part of axial light emitted from the bottom of the substrate can be guided to the side light emitting of the chip through the spine structure more, the light emitting opening angle of the chip can be increased, the proportion of the side light emitting of the chip is increased, and the side light intensity of the light emitting diode chip is further enhanced.

Wherein the center line of the substrate 1 is a line passing through the center point of the substrate 1 and perpendicular to the substrate 1. In the embodiment of the present disclosure, when the second surface 1b of the substrate 1 is rectangular, the center point of the substrate 1 is the intersection of the diagonals of the rectangle. When the second surface 1b of the substrate 1 is circular, the center line point of the substrate 1 is the center of the circle.

Alternatively, θ for each right triangular prism gradually decreases from the center of the substrate 1 to the edge of the substrate 1. The closer to the edge of the substrate 1, the smaller the included angle theta is, the larger the light-emitting opening angle of the chip is, so that the lateral light-emitting proportion of the chip can be further increased, and the side light intensity of the light-emitting diode chip is enhanced.

Fig. 3 is a bottom view of the second surface of the substrate provided by the embodiment of the disclosure, and as shown in fig. 3, an orthographic projection of each spike structure 11 on the second surface 1b of the substrate 1 is rectangular. When θ corresponding to each spike structure is gradually decreased from the center of the substrate to the edge of the substrate, the length of the rectangle corresponding to the orthographic projection of each spike structure 11 on the second surface 1b of the substrate 1 is longer and longer correspondingly.

Alternatively, 45 ≦ θ ≦ 75.

If the angle of θ is too small, the effect of guiding the light to the side direction is poor. If the angle of theta is too large, a reverse light guide effect is achieved, and the lateral light emission of the chip is further reduced.

Alternatively, the decrease in θ for each spike structure 11 is 5 ° from the center of the substrate 1 to the edge of the substrate 1.

Illustratively, referring to fig. 3, the second surface 1b of the substrate 1 includes a first region S1, a second region S2, and a third region S3, which are adjacent in this order, from the center of the substrate 1 to the edge of the substrate 1, and θ corresponding to the plurality of right-angled triangular prisms located in the first region S1 is 65 ° to 75 °, θ corresponding to the plurality of right-angled triangular prisms located in the second region S2 is 55 ° to 65 °, and θ corresponding to the plurality of right-angled triangular prisms located in the third region S3 is 45 ° to 55 °.

Note that, in the embodiment of the present disclosure, the first region S1, the second region S2, and the third region S3 may be rectangular annular regions or circular annular regions.

Alternatively, referring to fig. 1, the height L of each spike structure 11 protruding from the second surface 1b is equal. At this time, it can be ensured that the end of each spike structure 11 far from the second surface 1b is located on the same plane. Meanwhile, the production and the manufacture are convenient.

Illustratively, the height L of each spine structure 11 protruding from the second surface 1b is 2.5-3.5 um.

Optionally, the substrate 1 is a patterned sapphire substrate. The first surface 1a of graphical sapphire substrate has a plurality of toper arch 12 of interval equipartition, and the bottom diameter of every toper arch 12 is 1.3 ~ 1.7um, and the height of every toper arch 12 is 0.8 ~ 1.2 um.

In the patterned sapphire substrate in the related art, the diameter of the conical protrusions on the surface of the patterned sapphire substrate is usually 2.0-2.5 um, and the height of the conical protrusions is 1.8-2.0 um. Compared with the graphical sapphire substrate provided in the related art, the graphical sapphire substrate provided by the disclosure has smaller size, and the small-size graph can improve the effect of light diffuse reflection, further improve the angle of light emission, thereby improving the light emitting efficiency of the chip.

Illustratively, the interval between any two adjacent conical protrusions 12 is 0.3-0.5 um.

Alternatively, the N-type semiconductor layer 2 is N-type doped GaN, the active layer 3 includes InGaN layers and GaN layers alternately stacked, and the P-type semiconductor layer 4 is P-type doped GaN.

Alternatively, each of the N-type electrode 5 and the P-type electrode 6 includes a Cr layer, an Al layer, a Cr layer, a Ti layer, and an Al layer, which are sequentially stacked.

Alternatively, the insulating layer 7 includes a passivation layer and a distributed bragg reflector layer, which are sequentially stacked.

Wherein the passivation layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500 nm. The silicon oxide has higher hardness, and can effectively protect the chip.

The distributed Bragg reflection layer comprises silicon oxide layers and titanium oxide layers which are alternately stacked, and the number of the silicon oxide layers and the titanium oxide layers is 30-40, such as 36.

Alternatively, the protective layer 8 may be a silicon oxide layer. The thickness is 400 to 600nm, such as 500 nm. The protective layer can prevent the epitaxial wafer from being corroded by oxygen and water vapor in the air.

Optionally, the light emitting diode chip further includes an N-type pad 9 and a P-type pad 10. The insulating layer 7 is provided with an N-type via hole 7a extending to the N-type electrode 5 and a P-type via hole 7b extending to the P-type electrode 6. The N-type pad 9 is located on the insulating layer 7 around the N-type via hole 7a and the N-type via hole 7a, and the P-type pad 10 is located on the insulating layer 7 around the P-type via hole 7b and the P-type via hole 7 b.

Illustratively, the N-type pad 9 and the P-type pad 10 are each a Ti/Al/Ti/Al/Ti/Au stacked structure. The thickness of the first Ti layer and the thickness of the third Ti layer are both 20nm, the thickness of the second Al layer and the thickness of the fourth Al layer are both 1000nm, the thickness of the fifth Ti layer is 100nm, and the thickness of the sixth Au layer is 300 nm. The Ti layer can play a role in adhesion, and the Al layer can play a role in reflection so as to reflect light rays emitted to the P-type bonding pad or the N-type bonding pad and increase light rays emitted from the transparent substrate. The Au layer serves as a solder layer, and the chip can be fixed on the circuit board by solder.

It should be noted that, in the embodiment of the present disclosure, as shown in fig. 1, a part of the protective layer 8 is further coated on the sidewalls of the N-type pad 9 and the P-type pad 10.

Fig. 4 is a schematic distribution diagram of P-type pads and N-type pads provided by an embodiment of the present disclosure, and referring to fig. 4, N-type pads 9 and P-type pads 10 are disposed on insulating layer 7 at intervals, and the disposed areas of N-type pads 9 and P-type pads 10 on insulating layer 7 are the same in size, so as to facilitate forming stable electrical connection with a circuit board.

The embodiment of the disclosure provides a manufacturing method of a light emitting diode chip for enhancing side light intensity, which is suitable for manufacturing a flip light emitting diode chip shown in fig. 1. Fig. 5 is a flowchart of a method for manufacturing a light emitting diode chip with enhanced side light intensity according to an embodiment of the present disclosure, and referring to fig. 5, the method for manufacturing includes:

step 501, a substrate is provided.

Wherein the substrate includes opposing first and second surfaces. The substrate may be a sapphire substrate.

Step 502, growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate in sequence.

Optionally, this step 502 may include:

an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate by using a Metal-organic Chemical Vapor Deposition (MOCVD) technology.

Step 503, forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.

Optionally, this step 503 may include:

forming a patterned photoresist on the P-type semiconductor layer by adopting a photoetching technology;

forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer by adopting an Inductively Coupled Plasma etching (ICP); wherein, the etching depth can be 5 um.

Step 504, a P-type electrode is formed on the P-type semiconductor layer.

Optionally, this step 504 may include:

forming a negative photoresist on the P-type semiconductor layer by using a photoetching technology;

forming an electrode material on the negative photoresist and the P-type semiconductor layer by adopting an evaporation technology;

and removing the negative photoresist and the electrode material on the negative photoresist, and forming a P-type electrode by the electrode material on the P-type semiconductor layer.

The P-type electrode comprises a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially laminated.

And 505, forming an N-type electrode on the N-type semiconductor layer in the groove.

Optionally, this step 505 may include:

forming a negative photoresist on the N-type semiconductor layer in the groove by adopting a photoetching technology;

forming an electrode material on the negative photoresist and the N-type semiconductor layer in the groove by adopting an evaporation technology;

and removing the negative photoresist and the electrode material on the negative photoresist, and forming an N-type electrode by the electrode material on the N-type semiconductor layer in the groove.

The N-type electrode comprises a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially laminated.

Step 506, forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode.

In an embodiment of the present disclosure, the insulating layer includes a passivation layer and a distributed bragg reflector layer that are sequentially stacked.

Illustratively, the passivation layer may be formed using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

Step 507, forming a protective layer on the insulating layer.

Wherein the protective layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500 nm.

Illustratively, the protective layer may be formed by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

And step 508, thinning the substrate.

Step 509, forming a plurality of spike structures on the second surface of the substrate.

The spine structure is a right-angle triangular prism, the right-angle triangular prism comprises a first prismatic surface and a second prismatic surface, the first prismatic surface is perpendicular to the second surface, the second prismatic surface is connected with the first prismatic surface and the second surface, an included angle between the second prismatic surface and the second surface is theta, theta is larger than 0 degree and smaller than or equal to 90 degrees, and the second prismatic surface of each right-angle triangular prism faces the central line of the substrate.

The embodiment of the disclosure forms a plurality of spine structures on the second surface of the substrate. Each spine structure is a right-angle triangular prism, a second prismatic surface of each right-angle triangular prism faces the central line of the substrate, the second prismatic surface is an inclined surface, the included angle between the second prismatic surface and the second surface is theta, and theta is larger than 0 degree and smaller than or equal to 90 degrees. When the second prismatic surface faces the central line of the substrate, the second prismatic surface inclines from the center of the substrate to the edge direction of the substrate, at the moment, the spine structure can play a role in guiding light, so that part of axial light emitted from the bottom of the substrate can be guided to the side light emitting of the chip through the spine structure more, the light emitting opening angle of the chip can be increased, the proportion of the side light emitting of the chip is increased, and the side light intensity of the light emitting diode chip is further enhanced.

The embodiment of the present disclosure provides another method for manufacturing a light emitting diode chip with enhanced side light intensity, which is suitable for manufacturing the flip chip light emitting diode chip shown in fig. 1. Fig. 6 is a flowchart of a method for manufacturing a light emitting diode chip with enhanced side light intensity according to an embodiment of the present disclosure, and referring to fig. 6, the method for manufacturing includes:

step 601, a substrate is provided.

Wherein the substrate includes opposing first and second surfaces. The substrate may be a sapphire substrate.

Step 602, a substrate is patterned.

Wherein, the first surface of graphical sapphire substrate has the toper arch of a plurality of interval equipartitions, and the bellied bottom diameter of every toper is 1.3 ~ 1.7um, and the bellied height of every toper is 0.8 ~ 1.2 um.

Step 603, growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence.

Alternatively, this step 603 may be the same as step 502 and will not be described in detail here.

Step 604, forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.

Alternatively, step 604 may be the same as step 503 and will not be described in detail herein.

Optionally, the manufacturing method further comprises:

depositing Indium Tin Oxide (ITO) transparent conductive material on the epitaxial layer;

forming a patterned photoresist on the transparent conductive material by adopting a photoetching technology;

corroding the transparent conductive material by a wet method to form a transparent conductive layer;

and removing the patterned photoresist.

Among them, hydrochloric acid solution may be used as the etching solution.

Step 605 forms a P-type electrode on the P-type semiconductor layer.

Alternatively, step 605 may be the same as step 504 and will not be described in detail here.

And 606, forming an N-type electrode on the N-type semiconductor layer in the groove.

Alternatively, step 606 may be the same as step 505 and will not be described in detail herein.

Step 607, forming an insulating layer in the recess and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode.

Alternatively, this step 607 may be the same as step 506 and will not be described in detail here.

Step 608 is to form an N-type via hole extending to the N-type electrode and a P-type via hole extending to the P-type electrode on the insulating layer.

Optionally, step 608 may include:

forming a patterned photoresist on the insulating layer by adopting a photoetching technology;

adopting a dry etching technology to form an N-type communication hole extending to the N-type electrode and a P-type communication hole extending to the P-type electrode in the insulating layer;

and removing the patterned photoresist.

Step 609 forms a P-type pad on the insulating layer in and around the P-type via hole in the P-type via hole, and an N-type pad on the insulating layer in and around the N-type via hole.

Illustratively, the N-type bonding pad and the P-type bonding pad are both of a Ti/Al/Ti/Al/Ti/Au laminated structure. The thickness of the first Ti layer and the thickness of the third Ti layer are both 20nm, the thickness of the second Al layer and the thickness of the fourth Al layer are both 1000nm, the thickness of the fifth Ti layer is 100nm, and the thickness of the sixth Au layer is 300 nm.

Illustratively, step 609 may include:

forming a negative photoresist on the insulating layer by using a photolithography technique;

forming pad materials in the N-type communicating holes, the P-type communicating holes and the negative photoresist by adopting an evaporation technology;

and removing the negative photoresist and the pad material on the negative photoresist, wherein the pad material in the N-type communication hole and on the insulating layer around the N-type communication hole forms an N-type pad, and the pad material in the N-type communication hole and on the insulating layer around the N-type communication hole forms a P-type pad.

Step 610, a protective layer is formed on the insulating layer.

Alternatively, this step 610 may be the same as step 507 and will not be described in detail herein.

Step 611, thinning the substrate.

In the embodiment of the present disclosure, the final thickness of the thinned substrate is about 60-120 um, for example, 80 um. And the loss of light in the substrate is reduced under the condition of ensuring the supporting strength.

Step 612, forming a plurality of spike structures on the second surface of the substrate.

The spine structure is a right-angle triangular prism, the right-angle triangular prism comprises a first prismatic surface and a second prismatic surface, the first prismatic surface is perpendicular to the second surface, the second prismatic surface is connected with the first prismatic surface and the second surface, an included angle between the second prismatic surface and the second surface is theta, theta is larger than 0 degree and smaller than or equal to 90 degrees, and the second prismatic surface of each right-angle triangular prism faces the central line of the substrate.

Optionally, θ for each right triangular prism tapers from the center of the substrate to the edge of the substrate.

Alternatively, 45 ≦ θ ≦ 75.

Optionally, from the center of the substrate to the edge of the substrate, the second surface of the substrate includes a first region, a second region, and a third region that are adjacent in this order, θ corresponding to the plurality of right-angled triangular prisms located in the first region is 65 ° to 75 °, θ corresponding to the plurality of right-angled triangular prisms located in the second region is 55 ° to 65 °, and θ corresponding to the plurality of right-angled triangular prisms located in the third region is 45 ° to 55 °.

Optionally, the height L of each spike structure protruding from the second surface is equal. At this time, one end of each spine structure far away from the second surface can be ensured to be positioned on the same plane. Meanwhile, the production and the manufacture are convenient.

Illustratively, the height L of each spine structure protruding from the second surface is 2.5-3.5 um.

In the embodiment of the disclosure, a plurality of spine structures may be formed on the second surface of the substrate by overlapping the negative glue and the positive glue. For example, a negative photoresist is first prepared on the second surface of the substrate, and after exposure and development according to a mask plate, a plurality of protrusions having a rectangular structure are formed on the second surface of the substrate. And then preparing positive photoresist on the bulges of the plurality of rectangular structures, and changing the bulges of the plurality of rectangular structures into a plurality of right-angle triangular prism-shaped sharp structures after exposure and development according to a mask plate.

For example, before the positive photoresist is exposed and developed, the positive photoresist can be heated by ultraviolet curing, and the positive photoresist is baked at 100-150 ℃ for 30 minutes. And (3) changing the baking temperature to ensure that the finally formed spine structure has different theta. The higher the temperature, the smaller θ.

Step 613, invisible cutting and scribing the substrate.

In the disclosed embodiments, laser stealth dicing techniques may be employed to stealth scribe the substrate. The laser invisible cutting is used as a scheme for cutting the wafer by laser, so that the problems of grinding wheel scribing are well avoided. The laser invisible cutting is that single pulse of pulse laser is optically shaped to be transmitted through the surface of a material to be focused in the material, the energy density in a focus area is high, and a multi-photon absorption nonlinear absorption effect is formed, so that the material is modified to form cracks. Each laser pulse acts at equal intervals to form equal-interval damage, and then a modified layer can be formed in the material. The molecular bonds of the material are broken at the modified layer position, and the connection of the material becomes fragile and easy to separate. And after cutting, fully separating the product in a manner of stretching the carrier film, and enabling a gap to be formed between the chip and the chip. The processing mode avoids damage to the chip caused by mechanical direct contact and pure water flushing.

FIG. 7 is a schematic structural diagram of a light spot provided in the embodiment of the present disclosure, and as shown in FIG. 7, in the embodiment of the present disclosure, when the chip is subjected to laser stealth dicing and scribing, the length h of the light spot R formed by laser aggregation is 5-7 um.

In the related art, when the substrate is subjected to invisible cutting and scribing, the length of a light spot formed by laser gathering is about 15 um. The length of the light spot is shorter in the embodiment of the disclosure, and the section obtained by the light spot is more beneficial to light emergent from the side surface, because the short light spot makes the side surface rougher, the proportion of the light emergent from the side surface can be further increased.

Fig. 8 is a schematic distribution diagram of light spots provided by the embodiment of the present disclosure, and as shown in fig. 8, when the chip is subjected to laser invisible cutting and scribing, laser is also optimized in position setting, and the density of the light spots R is increased at a position close to the second surface 1b, so that the light spot position distribution is favorable for increasing the light intensity at an oblique angle position, thereby improving the lateral light intensity and increasing the field angle of light.

The embodiment of the disclosure forms a plurality of spine structures on the second surface of the substrate. Each spine structure is a right-angle triangular prism, a second prismatic surface of each right-angle triangular prism faces the central line of the substrate, the second prismatic surface is an inclined surface, the included angle between the second prismatic surface and the second surface is theta, and theta is larger than 0 degree and smaller than or equal to 90 degrees. When the second prismatic surface faces the central line of the substrate, the second prismatic surface inclines from the center of the substrate to the edge direction of the substrate, at the moment, the spine structure can play a role in guiding light, so that part of axial light emitted from the bottom of the substrate can be guided to the side light emitting of the chip through the spine structure more, the light emitting opening angle of the chip can be increased, the proportion of the side light emitting of the chip is increased, and the side light intensity of the light emitting diode chip is further enhanced.

The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.