阅读说明：本技术 具有与nand串断开连接的位线以进行快速编程的存储器设备 (Memory device with bit lines disconnected from NAND strings for fast programming ) 是由 X·杨 H-Y·曾 D·杜塔 于 2019-02-09 设计创作，主要内容包括：本发明公开了用于存储器单元的快速编程和读取操作的技术。第一组位线连接到第一组NAND串并且与连接到第二组NAND串的第二组位线交织。该第一组NAND串可通过以下方式编程：驱动该第一组位线上的电压,同时使该第二组位线上的电压浮置,以减小位线间电容并提供相对高的访问速度和相对低的存储密度(例如,每个存储器单元的位)。该第二组NAND串可通过以下方式编程：并发驱动该第一组位线和该第二组位线上的电压,以提供相对低的访问速度和相对高的存储密度。(Techniques for fast programming and read operations of memory cells are disclosed. The first set of bit lines is connected to the first set of NAND strings and is interleaved with the second set of bit lines connected to the second set of NAND strings. The first set of NAND strings can be programmed by: the voltages on the first set of bit lines are driven while the voltages on the second set of bit lines are floated to reduce inter-bit line capacitance and provide relatively high access speed and relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by: voltages on the first set of bit lines and the second set of bit lines are driven concurrently to provide a relatively low access speed and a relatively high storage density.)

1. An apparatus, comprising:

a first set of NAND strings (700n,702n,704n,706n,708n,710n,712n, and 714 n);

a second set of NAND strings (790-790 p);

a first set of bit lines (B L0, B L2, B L04, B L16, B L28, B L310, B L412, and B L512) interleaved with a second set of bit lines (B L1, B L3, B L5, B L7, B L9, B L11, B L13, and B L15), and

a bit line driver (440,440a,440b) configured to drive the first set of bit lines and the second set of bit lines during programming of the second set of NAND strings, and to drive the first set of bit lines and float the second set of bit lines during programming of the first set of NAND strings.

2. The apparatus of claim 1, wherein:

each NAND string of the first and second sets of NAND strings includes a select gate transistor;

the select gate transistors in the second set of NAND strings are electrically connected to the first set of bit lines and the second set of bit lines; and is

The select gate transistors in the first set of NAND strings are electrically connected to the first set of bit lines and are not electrically connected to the second set of bit lines.

3. The apparatus of claim 1 or 2, wherein:

NAND strings (700n,702n,704n,706n,708n,710n,712n, and 714n) in the first set of NAND strings are interleaved with dummy NAND strings (701n,703n,705n,707n,709n,711n,713n, and 715 n);

each NAND string in the first set of NAND strings and each dummy NAND string includes a select gate transistor;

the select gate transistors in the first set of NAND strings are electrically connected to the first set of bit lines;

the select gate transistors in the dummy NAND string are electrically connected to the second set of bit lines; and is

The select gate transistor in the dummy NAND string has a higher threshold voltage than the select gate transistor of the NAND strings in the first set of NAND strings.

4. The apparatus of claim 1 or 2, wherein:

NAND strings (700n,702n,704n,706n,708n,710n,712n, and 714n) in the first set of NAND strings are interleaved with dummy NAND strings (701n,703n,705n,707n,709n,711n,713n, and 715 n);

each NAND string in the first set of NAND strings and each dummy NAND string includes a select gate transistor; and is

Vias (621,621a) extend between the select gate transistors and the first set of bit lines in the first set of NAND strings, but do not extend between the select gate transistors and the second set of bit lines in the dummy NAND string.

5. The apparatus of any of claims 1 to 4, wherein:

the first set of NAND strings are located a first distance (d1) from the bit line driver;

the second set of NAND strings is located a second distance (d3) from the bit line driver; and is

The second distance is greater than the first distance.

6. The apparatus of any one of claims 1 to 5, wherein:

a pitch (sp2) between NAND strings in the first set of NAND strings is greater than a pitch (sp1) between NAND strings in the second set of NAND strings.

7. The apparatus of claim 6, wherein:

each bit line in the first set of bit lines is adjacent to two bit lines in the second set of bit lines.

8. The apparatus of any one of claims 1 to 7, wherein:

during the programming of the first set of NAND strings, assigning a first time period (ths) for a change in voltage of the first set of bit lines; and is

During the programming of the second set of NAND strings, a second time period (tls) is allocated for changes in voltage of the second set of bit lines, the second time period being greater than the first time period.

9. The apparatus of claim 8, wherein:

the change in the voltage of the first set of bit lines comprises an increase to a program inhibit voltage; and is

The change in the voltage of the second set of bit lines includes an increase to the program inhibit voltage.

10. The apparatus of any one of claims 1 to 9, wherein:

the first set of NAND strings is located in one block and the second set of NAND strings is located in another block.

11. The apparatus of any one of claims 1 to 9, wherein:

the first set of NAND strings is located in one sub-block (SB0-SB3, SB4-SB7, SB8-SB11, SB12-SB15) of a block (B L K0-B L K3), and the second set of NAND strings is located in another sub-block of the block.

12. The apparatus of any one of claims 1 to 11, wherein:

a group of memory cells arranged in the first group of NAND strings includes a unit memory cell;

a group of memory cells arranged in the second group of NAND strings includes multi-bit memory cells; and is

The first set of NAND strings is configured to cache data of the second set of NAND strings.

13. A method, comprising:

during programming of a first sub-block (SB0) including an unselected NAND string (700n) connected to a first bit line (B L0), increasing a voltage on the first bit line to an inhibit voltage while floating a voltage on a bit line (B L1) adjacent to the first bit line and increasing a voltage on a selected word line (VW L sel) to a program voltage after a first period of time (ths) has elapsed since the start of increasing the voltage on the first bit line to the inhibit voltage, and

during programming of a second sub-block (SB1) including an unselected NAND string (710z) connected to the first bit line: increasing the voltage on the first bit line to the inhibit voltage while driving the voltage on the bit line adjacent to the first bit line, and increasing the voltage on the selected word line to a program voltage after a second time period (tls) greater than the first time period has elapsed since the start of increasing the voltage on the first bit line to the inhibit voltage.

14. The method of claim 13, wherein:

driving the voltage on the bit line adjacent to the first bit line at a level based on a programmed or inhibited state of an associated NAND string.

15. The method of claim 13 or 14, wherein:

the first sub-block includes NAND strings (700n,702n,704n,706n,708n,710n,712n, and 714n) that are eligible to store data interleaved with NAND strings (701n,703n,705n,707n,709n,711n,713n, and 715n) that are not eligible to store data.

Background

The present technology relates to the operation of memory devices.

Semiconductor memory devices have become increasingly popular for use in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

Charge storage materials (such as floating gates) or charge trapping materials may be used in such memory devices to store charge representing data states. The charge trapping material may be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is a bit-cost scalable (BiCS) architecture that includes a stack of alternating conductive and dielectric layers.

The memory device includes memory cells that can be arranged in series in a NAND string (e.g., a NAND chain), e.g., with select gate transistors disposed at the ends of the NAND string to selectively connect the channel of the NAND string to a source line or a bit line. However, various challenges exist in operating such memory devices.

Drawings

FIG. 1 is a block diagram of an example memory device.

FIG. 2 is a block diagram depicting one implementation of sense block 51 of FIG. 1.

Fig. 3 depicts an exemplary implementation of the power control module 116 of fig. 1 for providing voltages to a block of memory cells.

FIG. 4 is a perspective view of a memory device 500 that includes a set of blocks in an exemplary 3D configuration of the memory structure 126 of FIG. 1.

FIG. 5A depicts an exemplary cross-sectional view of a portion of B L K0 of FIG. 4, with NAND strings 700n and 710n connected to bit line B L0 through vias 621 and 621a, respectively.

Fig. 5B depicts an exemplary transistor 650.

Fig. 5C depicts a close-up view of region 622 of the stack of fig. 5A.

FIG. 5D depicts an exemplary cross-sectional view of a portion of B L K0 of FIG. 4 with NAND strings 700n and 710z disconnected from the bit line B L0.

Fig. 6 depicts an exemplary view of NAND strings in B L K0, which B L K0 is consistent with fig. 4, 5A, and 5D.

Fig. 7 depicts the control gate layer in B L K0 consistent with fig. 6.

FIG. 8 depicts additional details of SB0 and SB1 of FIGS. 6 and 7.

Fig. 9A depicts threshold voltage (Vth) distributions 900 and 901 for S L C memory cells in the erased (Er) and programmed (P) states, respectively.

FIG. 9B depicts an exemplary Vth distribution for a group of M L C memory cells in eight data states.

Fig. 9C depicts an exemplary Vth distribution for a select gate transistor.

FIG. 10A depicts voltage signals used in a series of programming cycles in an exemplary programming operation for S L C memory cells, which results in the Vth distributions of FIG. 9A.

FIG. 10B depicts voltage signals used in a series of programming cycles in an exemplary programming operation for an M L C memory cell, which results in the Vth distribution of FIG. 9B.

FIG. 11A depicts an example process for accessing a first set of NAND strings using a relatively high access speed and a second set of NAND strings using a relatively low access speed.

FIG. 11B depicts an example programming operation that can implement the process of FIG. 11A.

FIG. 11C depicts an exemplary implementation of the programming phase and the verification phase of FIG. 11B using a relatively high access speed.

FIG. 11D depicts an exemplary implementation of the programming phase and the verification phase of FIG. 11B using a relatively low access speed.

FIG. 11E depicts an exemplary read operation that can implement the process of FIG. 11A.

Fig. 11F depicts an example programming operation for an SGD transistor consistent with fig. 9C.

FIG. 12A depicts a top view of a set of blocks B L K0-B L K3 of FIG. 4, which includes NAND strings and their connections to bit lines, in an exemplary configuration for a memory device implementing the process of FIG. 11A with high and low access speed blocks.

Fig. 12B depicts an exemplary architecture consistent with fig. 12A.

FIG. 12C depicts an exemplary compute-centric architecture.

FIG. 12D depicts an exemplary memory centric architecture.

FIG. 12E depicts a top view of block B L K0 in an exemplary configuration of a memory device for implementing the process of FIG. 11A with a high access speed sub-block and a low access speed sub-block.

FIG. 12F depicts a top view of block B L K0 in an example configuration of a memory device for implementing the process of FIG. 11A with data storage NAND strings separated by insulation instead of dummy NAND strings.

FIG. 13 depicts an exemplary bit line B L0-B L2 consistent with FIGS. 8, 12A, 12E, and 12F, showing how capacitance exists between adjacent bit lines.

FIG. 14 depicts a voltage versus time curve showing a relatively fast increase and a relatively slow increase.

FIG. 15 depicts an example of voltage signals that may be used in a programming cycle of a programming operation consistent with FIG. 11B.

FIG. 16 depicts an example of voltage signals that may be used in a read operation consistent with FIG. 11E.

Detailed Description

Devices and techniques for fast programming and read operations of memory cells are described.

In some memory devices, memory cells are joined to one another, such as in NAND strings in a block or sub-block. Each NAND string includes: a plurality of memory cells connected in series between one or more drain-side select gate transistors (referred to as SGD transistors) on the drain side of the NAND string connected to a bit line; and one or more source side select gate transistors (referred to as SGS transistors) on the source side of the NAND string or other memory string or group of connected memory cells connected to the source line. Further, the memory cells may be arranged with a common control gate line (e.g., word line) serving as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. The memory cells may be connected in other types of strings, and may also be connected in other ways.

In a 3D memory structure, memory cells may be arranged in stacked vertical NAND strings, where the stack includes alternating conductive and dielectric layers. The conductive layer serves as a word line connected to the memory cell. Each NAND string can have the shape of a pillar that intersects a word line to form a memory cell.

The memory cells may include data memory cells that are eligible to store user data, as well as dummy memory cells or non-data memory cells that are not eligible to store user data. The dummy memory cell may have the same structure as the data memory cell, but the controller considers the memory cell to be ineligible for storing any type of data, including user data. The dummy word line is connected to the dummy memory cell. One or more dummy memory cells may be provided at the drain and/or source terminals of a string of memory cells to provide a gradual transition in the channel voltage gradient.

The programming of the first word line W L0 is performed using one or more programming passes, for example, until programming is complete. Next, the second word line W L1 is programmed using one or more programming passes, until programming is complete, etc. the programming pass may include a set of increasing programming voltages that are applied to the word lines in respective programming cycles or program-verify iterations, such as depicted in FIG. 10B.

The memory cells may also be programmed according to a sub-block programming order, where the memory cells connected to a word line are programmed in one sub-block, then in the next, and so on.

For example, in a memory device that is a unit per cell (also referred to as S L C or a single level cell), there are two data states, including an erased state and a programmed state, see FIG. 9A. as a multi-bit memory cell, M L C or a multi-level cell stores two or more bits per cell.

S L C is programmed relatively fast and has high endurance, but the storage density (number of bits stored per memory cell) is lower than when multiple bits are stored in each memory cell. regarding programming speed, S L C programming can be performed using only one programming pulse in many cases. because only one read voltage is needed, the read speed is also high and error correction can be simplified due to the wide margin between the two data states.

After the memory cells are programmed, the data can be read back in a read operation. A read operation may involve applying one read voltage, a series of read voltages, to a word line while a sense circuit determines whether a cell connected to the word line is in a conductive state (conducting) or a non-conductive state (off). If the cell is in a non-conductive state, the Vth of the memory cell exceeds the read voltage. The read voltage is set to a level between the threshold voltages expected for adjacent data states. During a read operation, the voltage of the unselected word lines is ramped up to a read pass voltage that is high enough to place the unselected memory cells in a strongly conductive state to avoid interfering with the sensing of the selected memory cells.

However, resistance-capacitance (RC) delays limit the ability to improve programming and reading speed. For example, when a voltage signal is applied to a bit line, an amount of time is allotted to change the voltage based on the RC time constant of the bit line. The RC time constant is a function of the bitline dimensions and materials. In addition, the capacitance between bit lines may further degrade performance.

The techniques provided herein address the above-referenced problems and others. In one aspect, different sets of NAND strings are connected to a set of bit lines. The set of bit lines may include a first set of bit lines interleaved with a second set of bit lines. The first set of NAND strings has a relatively high access speed (e.g., read/write speed) and a relatively low storage density (e.g., bits per memory cell). In contrast, the second set of NAND strings has a relatively low access speed and a relatively high storage density. For example, the time for the sensing operation may be reduced by about one-half, e.g., from 20 microseconds to 10 microseconds, and these times may represent a relatively low access speed and a relatively high access speed, respectively.

For example, the first set of NAND strings and the second set of NAND strings may be located in different sub-blocks or blocks. In addition, a first set of NAND strings can be accessed by driving voltages on a first set of bit lines while floating voltages on a second set of bit lines. Floating reduces the inter-bit line capacitance so that the time allotted for changing the voltage on the first group of bit lines is reduced, resulting in a relatively high access speed. The second set of NAND strings are accessed by concurrently driving voltages on the first set of bit lines and the second set of bit lines, wherein the time allocated to change the voltages on the first set of bit lines and the second set of bit lines is greater than in the case of a relatively high access speed.

In particular, during a programming operation for a first set of NAND strings, when a subset of bit lines in the first set of bit lines is increased from 0V to an inhibit voltage (such as 2V), floating the voltage of the second set of bit lines allows the bit line voltage of the subset of bit lines to reach and settle at 2V faster than when the voltage of the second set of bit lines is driven (e.g., at 0V).

During a sensing operation, such as a read operation or a verify test, the first and second groups of bit lines may be driven at a common level to minimize inter-bit line capacitance. In addition, the second set of bit lines draw no current during sensing of the first set of NAND strings, so that displacement current is reduced. This also allows the voltages on the first set of bit lines to be charged up faster during the sensing process.

Different sub-blocks or blocks may be provided that allow different access speeds in the same memory device.

12A and 12E the memory device can be fabricated without conductive vias (see insulation 621c and 621D in FIG. 5D) between the dummy NAND strings and the bit line, see FIG. 5D. in another approach, the first set of NAND strings are separated by stacked insulation, and the inter-NAND-string spacing (sp2, FIG. 12F) in the first set of NAND strings (e.g., B L K0) is greater than the inter-NAND-string spacing (sp1, FIG. 12A) in the second set of NAND strings (e.g., B L K1-B L K3), see insulation 1252 in FIG. 12F.

In another approach, there are conductive vias between the dummy NAND string and the bit line (see vias 621 and 621a in FIG. 5A), but the SGD transistor of the dummy NAND string is programmed to a higher Vth than the SGD transistor of the data storage NAND string. See fig. 9C. With a common control gate bias, the SGD transistors of the dummy NAND string may be in a non-conductive state and electrically disconnected from the bit line, while the data-storing NAND string may be in a conductive state and electrically connected to the bit line. This approach is advantageous because the SGD transistors can be erased and reconfigured as needed. Thus, if desired, a high access speed, low storage density block or sub-block may be changed to a low access speed, high storage density block or sub-block, and vice versa.

In one approach, the memory cells with relatively high access speeds are S L C memory cells, and the memory cells with relatively low access speeds are M L C memory cells, the S L C memory cells and the M L C memory cells may be in different blocks or different sub-blocks of a block.

These and other features are discussed further below.

FIG. 1 is a block diagram of an example memory device 100, such as a non-volatile memory system, may include one or more memory dies 108, also referred to as chips or integrated circuits, the memory dies 108 include memory structures 126 of memory cells, such as an array of memory cells, control circuitry 110, and read/write circuitry 128, the memory structures 126 are addressable by word lines via row decoders 124 and by bit lines via column decoders 132.

The read/write circuits 128 include multiple sense blocks 51-54 (sense circuits) and allow a page of memory cells to be read or programmed in parallel. Typically, the controller 122 is included in the same memory device 100 (e.g., a removable storage card) as the one or more memory dies 108. The controller may be separate from the memory die. Commands and data are transferred between the host 140 and the controller 122 via the data bus 120, and between the controller and the one or more memory dies 108 via the path 118.

The memory structure may be a 2D memory structure or a 3D memory structure. The memory structure may include one or more memory cell arrays, including a 3D array. The memory structure may comprise a monolithic 3D memory structure in which multiple memory levels are formed above (rather than in) a single substrate, such as a wafer, without an intervening substrate. The memory structure may include any type of non-volatile memory that is monolithically formed in one or more physical levels with an array of memory cells having an active area disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with operation of the memory cells, whether the associated circuitry is above or within the substrate.

The control circuitry 110 cooperates with the read/write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine 112, column redundancy circuitry 111, an on-chip address decoder 114 and a power control module 116 (power control circuitry). The state machine 112 provides chip-level control of memory operations. A memory area 113 may be provided, for example, for operating parameters and software/code. In one embodiment, the state machine is programmed by software. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuitry).

The column redundancy circuits provide mapping between spare NAND strings that replace defective primary NAND strings. The on-chip address decoder 114 provides an address interface between that used by the host or a memory controller to the hardware address used by the decoders 124 and 132. The power control module 116 controls the power and voltages supplied to the word lines, select gate lines, bit lines, and source lines during memory operations. The power control module may include drivers for word lines, SGS and SGD transistors, and source lines. See also fig. 3. In one approach, the sense block may include a bit line driver.

The power control module may include a voltage timing circuit 116 that stores data for determining when to apply the voltage signal. The data may indicate an amount of time to allocate to the voltage signal to reach a steady state voltage during the voltage increase or decrease. As described further below, the amount of time allotted for a voltage change on a bit line may vary based on the RC time constant of the bit line. When voltage signals are applied to two or more adjacent bit lines to achieve a relatively low access speed, high storage density memory cell, it is possible that the voltage signals are at different levels. For example, one bit line may be changed from 0V to 2V to inhibit programming of a NAND string, while the adjacent bit line remains at 0V to allow programming of the NAND string. A relatively long period of time should be allocated for the bit line change from 0V to 2V. In contrast, when a voltage signal is applied to a selected bit line to achieve a relatively high access speed, low storage density memory cell, the voltage signal on the adjacent bit line may be floated such that the RC time constant is reduced. A relatively short period of time may then be allocated for the bit line change from 0V to 2V. The voltage timing circuit may set the period of time for which the bit line voltage varies based on the block and/or sub-block location of the memory cell being accessed, and know whether the memory cell is configured for low or high access speed based on the connection between the NAND string (or the channel of the memory cell of the NAND string) and the bit line.

The voltage timing circuit may control a time period between a start of a change in one voltage (such as a bit line voltage) and a start of a change in another voltage (such as a word line voltage). The voltage timing circuit may also control the time period between the start of a change in a voltage (such as the bit line voltage) and an event (such as the start of discharge of a sense node in the sense circuit during sensing). See fig. 15 and 16 for, for example, voltage signals.

Voltage timing circuit 117 may be configured with hardware, firmware, and/or software for performing the techniques described herein, including the processes of the flow diagrams described herein.

In some implementations, some of the components may be combined. In various designs, one or more of the components other than memory structure 126 (alone or in combination) may be considered at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuitry may include any one or combination of control circuitry 110, state machine 112, decoders 114 and 132, power control module 116, sense blocks 51-54, read/write circuits 128, controller 122, and the like.

The off-chip controller 122 (which in one embodiment is a circuit) may include a processor 122c, storage devices (memory) such as a ROM 122a and a RAM 122b, and an Error Correction Code (ECC) engine 245. The ECC engine can correct many read errors.

The controller 122 or control circuitry 110 may be configured with hardware, firmware, and/or software for implementing the processes described herein, including the processes of the flow diagrams of fig. 11A-11K.

A memory interface 122d may also be provided. The memory interface, which communicates with the ROM, RAM and processor, is the circuitry that provides the electrical interface between the controller and the memory die. For example, the memory interface may change the format or timing of signals, provide buffers, isolate surges, latch I/O, etc. The processor may issue commands to the control circuit 110 (or any other component of the memory die) via the memory interface 122 d.

The storage device includes code, such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively or in addition, the processor may access code from a storage device 126a of the memory fabric, such as reserved areas of memory cells in one or more word lines.

For example, the controller may use code to access the memory structure, such as for program operations, read operations, and erase operations. The code may include boot code and control code (e.g., a set of instructions). Boot code is software that initializes the controller during boot or startup and enables the controller to access the memory structure. The controller may use the code to control one or more memory structures. At power up, the processor 122c fetches boot code from the ROM 122a or the storage device 126a for execution, and the boot code initializes system components and loads control code into the RAM 122 b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes drivers to perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

Generally, the control code may include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and to provide voltage waveforms, including those discussed further below. The control circuitry may be configured to execute instructions that perform the functions described herein.

In one embodiment, the host is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input/output interfaces, and/or one or more input/output devices in communication with one or more processors.

Other types of non-volatile memory may be used in addition to NAND flash memory.

Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read only memory ("EEPROM"), flash memory (which may also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), and other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND configuration or a NOR configuration.

The memory device may be formed of passive elements and/or active elements in any combination. By way of non-limiting example, the passive semiconductor memory element includes a ReRAM device element, which in some embodiments includes a resistivity-switching memory element, such as an antifuse or a phase change material, and an optional steering element, such as a diode or a transistor. Further, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

The plurality of memory elements may be configured such that they are connected in series or such that each element is individually accessible. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a set of series-connected transistors including a memory cell and an SG transistor.

A NAND memory array may be configured such that the array is made up of multiple strings of memory, where a string is made up of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements may be configured such that each element is individually accessible, such as a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and the memory elements may be configured in other ways.

The semiconductor memory elements located within and/or on the substrate may be arranged in two or three dimensions, such as a 2D memory structure or a 3D memory structure. In a 2D memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in 2D memory structures, the memory elements are arranged in a plane (e.g., in an x-y direction plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer on or in which layers of memory elements are formed, or it may be a carrier substrate that is attached to the memory elements after they are formed. As a non-limiting example, the substrate may comprise a semiconductor, such as silicon.

The memory elements may be arranged in a single memory device level in an ordered array, such as in multiple rows and/or columns. However, the memory elements may be arranged in a non-regular or non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

The 3D memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, forming a three-dimensional structure (i.e., in x, y, and z directions, where the z direction is substantially perpendicular to a major surface of the substrate and the x and y directions are substantially parallel to the major surface of the substrate).

As a non-limiting example, the 3D memory structure may be arranged vertically as a stack of multiple 2D memory device levels. As another non-limiting example, the 3D memory array may be arranged in a plurality of vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), with each column having a plurality of memory elements. These columns may be arranged, for example, in a 2D configuration in an x-y plane, resulting in a 3D arrangement of memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements may also constitute a 3D memory array.

By way of non-limiting example, in a 3D NAND memory array, memory elements can be coupled together to form a NAND string within a single level (e.g., x-y) of memory devices. Alternatively, the memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other 3D configurations are contemplated in which some NAND strings contain memory elements in a single memory level, while other strings contain memory elements that span multiple memory levels. The 3D memory array may also be designed in a NOR configuration and in a ReRAM configuration.

Typically, in monolithic 3D memory arrays, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers located at least partially within a single substrate. As a non-limiting example, the substrate may comprise a semiconductor, such as silicon. In monolithic 3D arrays, the layers that make up each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, the layers of adjacent memory device levels of a monolithic 3D memory array may be shared between the memory device levels or have intervening layers between the memory device levels.

The 2D array may be formed separately and then packaged together to form a non-monolithic memory device with multiple layers of memory. For example, a non-monolithic stacked memory may be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate may be thinned or removed from the memory device level prior to stacking, but since the memory device level is initially formed over a separate substrate, the resulting memory array is not a monolithic 3D memory array. Furthermore, multiple 2D or 3D memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

Associated circuitry is typically required to operate and communicate with the memory elements. As a non-limiting example, a memory device may have circuitry for controlling and driving memory elements to implement functions such as programming and reading. The associated circuitry may be located on the same substrate as the memory elements and/or on a separate substrate. For example, the controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.

Those skilled in the art will recognize that the techniques are not limited to the 2D and 3D exemplary structures described, but encompass all relevant memory structures within the spirit and scope of the techniques as described herein and as understood by those skilled in the art.

FIG. 2 is a block diagram depicting one implementation of sense block 51 of FIG. 1. The single sense block 51 is divided into one or more core portions referred to as sense circuits 60-63 or sense amplifiers and a common portion referred to as a managing circuit 190. In one implementation, there will be a separate sensing circuit for each bit line/NAND string and one common managing circuit 190 for a set of multiple (e.g., four or eight) sensing circuits. Each sensing circuit in a group communicates with an associated managing circuit via a data bus 172. Thus, there are one or more managing circuits in communication with the sensing circuits of a set of storage elements.

As an example, the sense circuit 60 includes a sense circuit 170 that performs sensing by determining whether the conduction current in the connected bit line is above or below a predetermined threshold level, the sense circuit may include a sense node 171 that is charged during sensing, the amount of decay of the sense node is used to determine whether the memory cell is in a conductive state or a non-conductive state, see also curve 1690 in FIG. 16. the sense circuit 60 also includes a bit line latch 184 for setting a voltage condition on the connected bit line, e.g., a predetermined state latched in the bit line latch will result in the connected bit line being pulled to a state designating program inhibit (e.g., 1.5V-3V). As an example, flag 0 may inhibit programming while flag 1 does not inhibit programming. during a program operation, a flag may be provided to the bit line (B L) selector 173, which B L selector is configured to either pass VB L _ unsel or VB L _ unsel to the bit line, the VB L is the selected voltage or the string VB 2, such as VB 2, VB, or VB, a non-unselect string (VB-3V-3 V.g., VB-3V-1-for example-for program inhibit.

During a sense operation, the B L selector may pass a sense voltage VB L _ sense (e.g., 2V) to the transistor 55 to charge the bit line, the transistor 55 may be disposed between the bit line and the sense circuit to clamp the voltage of the bit line during the sense operation, Vbl is clamped at a level equal to the control gate voltage Vblc minus Vth of the transistor, Vbl may be clamped at 2-1 ═ 1V, for example, VB L _ sense is applied to the drain of the transistor and Vbl is provided at the source of the transistor, which acts as a source follower.

If the sensing operation involves adjacent NAND strings, such as in the case of the second set of NAND strings previously mentioned, the change in adjacent bit lines results in inter-bit line capacitance and displacement current, which increases the time required to charge the bit lines. In contrast, if the sensing operation involves every other NAND string, such as in the case of the first set of NAND strings mentioned previously, the adjacent bit lines are electrically disconnected from the memory cells of the NAND strings, so there is no data state dependent change in the time these bit lines are charged. In addition, no current is drawn from the bit line to the memory cell channel. Therefore, the time allocated for charging the bit line can be reduced.

The managing circuit 190 includes a processor 192, four exemplary sets of data latches 194 and 197, and an I/O interface 196 coupled between the set of data latches 194 and the data bus 120. A set of data latches may be provided for each sense circuit, including, for example, individual latches L D L, MD L, and UD L. in some cases, additional data latches may be used L D L stores one bit for the lower page data, MD L stores one bit for the lower page data, and UD L stores one bit for the upper page data.

Processor 192 performs computations, such as to determine the data stored in the sensed storage elements and store the determined data in the set of data latches. Each set of data latches 194-197 is used to store data bits determined by processor 192 during a read operation and to store data bits imported from data bus 120 during a program operation that represents write data to be programmed into the memory. I/O interface 196 provides an interface between data latches 194 and 197 and data bus 120.

During reading, operation of the system is under the control of the state machine 112, which controls the supply of different control gate voltages to the addressed storage elements. As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuit may trip at one of these voltages and the corresponding output will be provided from the sense circuit to the processor 192 via the data bus 172. At this point, the processor 192 determines the resulting memory state by considering the trip event of the sense circuit and information about the control gate voltage applied via input line 193 from the state machine. It then computes the binary encoding of the memory state and stores the resulting data bits into data latches 194 and 197. In another embodiment of the managing circuit 190, the bit line latch serves dual purposes, both as a latch for latching the output of the sensing circuit and as a bit line latch as described above.

Some implementations may include multiple processors 192. In one embodiment, each processor 192 will include an output line (not shown) such that each of the output lines is wired-OR'd together. In some embodiments, the output lines are inverted prior to being connected to the wired-OR line. This configuration enables a quick determination during program verification testing of when the programming process is complete because the state machine receiving the wired-OR can determine when all bits being programmed have reached the desired level. For example, when each bit reaches its desired level, a logic zero for that bit will be sent to the wired-OR line (or a data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sense circuits, the state machine needs to read the wired-OR line eight times, or logic is added to processor 192 to accumulate the results of the associated bit lines so that the state machine need only read the wired-OR line one time. Similarly, by proper selection of logic levels, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

During a program or verify operation for the memory cell, the data to be programmed (write data) is stored from the data bus 120 in the set of data latches 194-197, in the L D L latch, MD L latch, and UD L latch in a three bit per storage element implementation.

Under the control of the state machine, the program operation includes a series of program voltage pulses applied to the control gates of the addressed storage elements. Each program voltage is followed by a read back (verify) to determine whether the storage element has been programmed to the desired memory state. In some cases, processor 192 monitors the read back memory state relative to the desired memory state. When the two are in agreement, the processor 192 sets the bit line latch so as to cause the bit line to be pulled to a state designating program inhibit. This inhibits the storage element coupled to the bit line from further programming even if a program pulse is present at its control gate. In other embodiments, the processor initially loads the bit line latch and the sense circuitry sets it to an inhibit value during verify.

Each set of data latches 194-197 may be implemented as a stack of data latches for each sensing circuit. In one embodiment, there are three data latches per sensing circuit 60. In some implementations, the data latches are implemented as a shift register so that the parallel data stored therein is converted to serial data for the data bus 120, and vice versa. All of the data latches corresponding to the read/write block of storage elements may be connected together to form a block shift register so that a block of data may be input or output by serial transfer. Specifically, the set of read/write circuit modules are adjusted so that their set of data latches move data in and out of the data bus in sequence as if they were part of the shift register of the entire read/write block.

A data latch identifies when an associated storage element has reached certain milestones in a programming operation, e.g., the latch can identify that the Vth of the storage element is below a particular verify voltage.A data latch indicates whether the storage element is currently storing one or more bits from a page of data.A L D L latch can be used to store lower page data.A L D L latch is flipped (e.g., from 0 to 1) when a lower page bit is stored in the associated storage element. either the MD L latch or the UD L latch is flipped when an intermediate or upper page bit, respectively, is stored in the associated storage element.

FIG. 3 depicts an exemplary implementation of the power control module 116 of FIG. 1 for providing voltages to blocks of memory cells, in this example, the memory structure 126 includes a group 410 of four related blocks B L K _0 through B L K _3, and another group 411 of four related blocks B L K _4 through B L K _ 7.

For example, control gate line 412 is connected to a set of transfer transistors 413, 414, 415, and 416, which are in turn connected to control gate lines B L K _4, B L K _5, B L K _6, and B L K _7, respectively, control gate line 417 is connected to a set of transfer transistors 418, 419, 420, and 421, which are in turn connected to control gate lines B L K _0, B L K _1, B L K _2, and B L K _3, respectively.

Typically, programming or reading operations are performed on one selected block at a time and on one selected sub-block of the block. An erase operation may be performed on a selected block or sub-block. The row decoder may connect the global control lines 402 to the local control lines 403. The control lines represent conductive paths. The voltage is provided on a global control line of many voltage drivers. Some voltage drivers may provide voltages to switches 450 connected to a global control line. Pass transistor 424 is controlled to pass voltage from the voltage driver to switch 450.

The voltage drivers may include a selected data word line (W L) driver 447, which selected data W L driver provides a voltage on a selected data word line during a program or read operation.the voltage drivers may also include drivers 448 for unselected data word lines, which may be the remaining unselected word lines other than the selected word line.the voltage drivers may also include a drain-side dummy word line driver 449 that provides a voltage on a drain-side dummy word line (such as W L DD0 and W L DD1) and a source-side dummy word line driver 451 that provides a voltage on a source-side dummy word line (such as W L DS1 and W L DS 0). see FIG. 5A.

In one approach, to provide maximum flexibility in programming these memory cells and transistors with programming voltages or other word line specific parameters, there may be a separate driver for each select gate transistor and memory cell in the NAND string, or multiple dummy transistors may be connected and connected in common to drive multiple dummy memory cells, and multiple dummy memory cells may be connected and connected in common to drive multiple dummy memory cells, such as in FIGS. 6-8.

Various components including the row decoder may receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

In one approach, well region 433 (see also FIG. 5A) is common to the blocks and may be driven by voltage drivers 430. the blocks also share a set of bit lines B L _ sel bit line voltage driver 440 supplies voltages to selected bit lines and B L _ unsel bit line voltage driver 440a supplies voltages to unselected bit lines during a program operation.

In stacked memory devices such as depicted in fig. 4-8, groups of connected memory cells can be arranged in NAND strings that extend vertically upward from the substrate. In one approach, the bottom (or source terminal) of each NAND string is in contact with the well region, and the top (or drain terminal) of each NAND string is connected to a corresponding bitline. The vertically extending NAND string has a floating channel.

FIG. 4 is a perspective view of a memory device 500 that includes a set of blocks in an exemplary 3D configuration of the memory structure 126 of FIG. 1. on a substrate 501 are exemplary blocks B L K0, B L K1, B L K2, and B L K3 of memory cells (storage elements), and peripheral regions having circuitry used by the blocks. peripheral regions 504 extend along the edges of each block, while peripheral regions 505 are at the ends of the block.

In one possible approach, the blocks are in a plane, and the length of the plane in the x-direction represents the direction in which signal paths to word lines extend in one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which signal paths to bit lines extend in one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device. The blocks may also be arranged in multiple planes.

FIG. 5A depicts an exemplary cross-sectional view of a portion of B L K0 of FIG. 4, wherein NAND strings 700n and 710z are connected to bit line B L0 through vias 621 and 621a, respectively, the block includes a stack 610 of alternating conductive and dielectric layers in which, in this example, the conductive layers include two SGD layers, one SGS layer, two source side dummy word line layers (or word lines) W L DS1 and W L DS0, two drain side dummy word line layers W L DD1 and W L DD0, and ten data word line layers (or data word lines) W8620-W L L. W L L is a source side data word line, and W L DS L is another word line layer adjacent to the source side data word line W L DS L, W L DS L is another dummy word line layer adjacent to W L DS L, W L DS L is another dummy word line layer labeled as a drain side data word line stack L, a further dummy word line layer L is shown with a NAND string or drain string stack 700, a further illustrated as a NAND string, a string.

The stack includes a substrate 611. in one approach, a portion of the source line S L includes a well region 433 (see also FIG. 3), which is an n-type source diffusion layer or well in the substrate, which is in contact with the source terminal of each string of memory cells in the block.

The NAND string 700n has a source terminal 613 at the bottom 616B of the stack 616 and a drain terminal 615 at the top 616a of the stack NAND string 710z has a source terminal 613a at the bottom 616B of the stack 616 and a drain terminal 615a at the top 616a of the stack metal-filled slots 617 and 620 may be provided periodically across the stack as interconnects extending through the stack, such as to connect the source line to a line above the stack.

In one approach, a block of memory cells includes a stack of alternating control gates and dielectric layers, and the memory cells are arranged in vertically extending memory holes in the stack.

In one approach, each block includes a trapezoidal edge, with vertical interconnects connected to each layer, including the SGS, W L, and SGD layers, and extending up to the horizontal path to the voltage drivers.

The insulating fill region 614 separates the block into sub-blocks with the NAND strings 700n and 710z in different sub-blocks.

Fig. 5B depicts an exemplary transistor 650. The transistors comprise a control gate CG, a drain D, a source S and a channel CH and may for example represent memory cells or select gate transistors.

Fig. 5C depicts a close-up view of region 622 of the stack of fig. 5A. Memory cells are formed at different levels of the stack at the intersections of the word line layers and the memory holes. In this example, SGD transistors 717 and 716 are provided above dummy memory cells 715 and 714 and data memory cell 713. These SGD transistors are located at the drain end of the NAND string.

Multiple layers may be deposited along the Sidewalls (SW) of the memory holes 630 and/or within each word line layer (e.g., using atomic layer deposition). For example, each pillar 685 or column formed of material within a memory hole can include a blocking oxide layer 663, a charge trapping layer 664 or film (such as silicon nitride (Si3N4) or other nitride), a tunnel layer 665 (e.g., comprising a gate oxide that can degrade over time), a channel 660 (e.g., comprising polysilicon), and a dielectric core 666 (e.g., comprising silicon dioxide). The word line layer may include a metal barrier layer 661 and a conductive metal 662, such as tungsten, as control gates. For example, a control gate 690-694 is provided. In this example, all layers except metal are provided in the memory hole. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars may form pillar Active Areas (AA) of the NAND string.

Each NAND string or group of connected transistors includes a channel that extends continuously from one or more source-side select gate transistors to one or more drain-side select gate transistors. For example, channels 700a, 710a, 720a, and 730a extend continuously in NAND strings 700n, 710z, 720n, and 730n, respectively. The channel 700a extends continuously in the NAND string 700n from the SGS transistor 701 to the SGD transistors 716 and 717. The channel 700a is continuous because it is uninterrupted and thus can provide a continuous conductive path in the NAND string.

When programming a memory cell, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and pass through the tunnel layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, electrons are returned to the channel.

Each of the memory holes may be filled with a plurality of ring layers including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. The core region of each of the memory holes is filled with a host material, and a plurality of ring layers are located between the core region and the word lines in each of the memory holes.

The NAND string can be considered to have a floating body channel because the length of the channel is not formed on the substrate. Further, the NAND strings are provided by a plurality of word line layers stacked on top of each other and separated from each other by dielectric layers.

FIG. 5D depicts an exemplary cross-sectional view of a portion of B L K0 of FIG. 4, where NAND strings 700n and 710z are disconnected from bit line B L0. in this case, no vias are formed in the insulation region 550 on top of the stack, so that NAND strings 700n and 710z are not connected to the bit line.regions 621c and 621D represent portions of the insulation region 550 where vias could otherwise be fabricated.

FIG. 6 depicts an example view of NAND strings in B L K0, this B L K0 being consistent with FIGS. 4, 5A, and 5D. the NAND strings are arranged in a 3D configuration in sub-blocks of a block. each sub-block includes multiple NAND strings, one example NAND string being depicted, for example, SB0, SB1, SB2, and SB3 include example NAND strings 700n, 710z, 720n, and 730n, respectively.

NAND strings 700n, 710z, 720n and 730n have channels 700a, 710a, 720a and 730a, respectively.

In addition, NAND string 700n includes SGS transistor 701, dummy memory cells 702 and 703, data memory cell 704 and 713, dummy memory cells 714 and 715, and SGD transistors 716 and 717. NAND string 710z includes SGS transistor 721, dummy memory cells 722 and 723, data memory cell 724 733, dummy memory cells 734 and 735, and SGD transistors 736 and 737. NAND string 720n includes SGS transistor 741, dummy memory cells 742 and 743, data memory cell 744-753, dummy memory cells 754 and 755, and SGD transistors 756 and 757. NAND string 730n includes SGS transistor 761, dummy memory cells 762 and 763, data memory cells 764-' 773, dummy memory cells 774 and 775, and SGD transistors 776 and 777.

One or more SGD transistors are disposed at the drain terminal of each NAND string and one or more SGS transistors are disposed at the source terminal of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 may be driven by separate control lines SGD0(0) and SGD1(0), SGD0(1) and SGD1(1), SGD0(2) and SGD1(2), and SGD0(3) and SGD1(3), respectively. In another approach, all SGD transistors in a sub-block are connected and driven together. The SGD transistors in SB0, SB1, SB2, and SB3 may be driven by separate control lines SGS (0), SGS (1), SGS (2), and SGS (3), respectively. In another approach, all SGS transistors in a block are connected and driven together.

Fig. 7 depicts control gate layers in B L K0 consistent with fig. 6 control gate layers are arranged in stack 800 and include dummy word line layers or control gate layers W L DS0, W L DS1, W L DD L and W L DD L, and data word line layers or control gate layers W360-W L, which are shared between different sub-blocks SB L-SB L the control gate layers include a common SGS control gate layer of a block optionally a separate SGS control gate layer may be provided for each sub-block, for example SB L, SB L and SB L include SGD L (0) and SGD L (0), SGD L (1) and SGD L (1), SGD L (2) and SGD L (2), and SB L (3) and SGD 36717, in addition four exemplary holes are depicted in each sub-block L, SGD 36717 and in example memory cells SGD L (SGD L, SGD 36717).

FIG. 8 depicts additional details of SB0 and SB1 of FIGS. 6 and 7, depicts the NAND string 700n of FIG. 6, and additional NAND strings 701n-707n also in SB0, the NAND strings in the sub-block having SGD transistors with connected control gates.

For example, a group of memory cells 704-704g are connected to W LL 0 in NAND strings 700n-707n, respectively.

During a programming operation, some of the NAND strings in the sub-block may be selected for programming when the associated latch has a program state, and other NAND strings in the sub-block may not be selected for programming when the associated latch has a locked state. A NAND string having a program state or a lock state is a data storage NAND string that is eligible to store data. For dummy NAND strings that are not eligible to store data, in one approach, the associated bit line may be floated during a program or read operation to reduce the capacitance seen by the bit line for the data storage NAND string.

Also depicted are exemplary NAND strings 710z and 711z in sub-block SB1, and these exemplary NAND strings have exemplary memory cells 724 and 724a, respectively, connected to W LL 0 during a program or read operation, one sub-block may be selected while the other sub-block is not selected.

FIG. 9A depicts threshold voltage (Vth) distributions 900 and 901 for S L C memory cells in the erased (Er) state and the programmed (P) state, respectively, in FIGS. 9A-9C, the vertical axis depicts a plurality of memory cells on a logarithmic scale, and the horizontal axis depicts Vth on a linear scale first, if a block of memory cells is erased, then those memory cells are in the Er state.

In this example, the memory cells are S L C memory cells, which are programmed in one or two programming cycles, e.g., using one or two programming voltages or pulses, such as by using the voltage signals of FIG. 10A.

FIG. 9B depicts an exemplary Vth distribution for a group of M L C memory cells in eight data states in one approach, at the beginning of a program operation, the memory cells are initially all in an erased state, as shown by Vth distribution 910 after the program operation is successfully completed, the memory cells assigned to the Er state are represented by Vth distribution 910a, where the Vth distribution shifts up due to program disturb.

Memory cells programmed to A, B, C, D, E, F and the G-state using verify voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG, respectively, are represented by Vth distributions 911, 912, 913, 914, 915, 916, and 917. The verify voltage is used for program verify testing of the memory cell. Read voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG may be used to read the states of these memory cells in a read operation. These verify voltages and read voltages are examples of control gate read levels for the selected word line voltage.

In an erase operation, the data memory cells transition from the Vth distribution of programmed data states (e.g., states A-G) to an erased state. The erase operation includes an erase phase in which the memory cells are biased for erase, followed by an erase-verify test. The erase-verify test may use an erase verify voltage VvEr.

Fig. 9C depicts an exemplary Vth distribution for a select gate transistor. As described, for example, in connection with FIG. 11F, a dummy NAND string can be created by programming its SGD transistors to a higher Vth distribution than the SGD transistors of the data storage NAND string. For example, at manufacture, or periodically during the life of the memory device, the SGD transistors may be erased using an erase voltage VvEr to achieve the Vth distribution 920. Subsequently, the SGD transistor may be programmed using a voltage signal similar to that in fig. 10A and 10B. Specifically, the verify voltage VvP1 or VvP2 can be used to achieve the Vth distribution 921 or 922 under states P1 or P2, respectively. The lower Vth distribution 921 is for dummy NAND strings and the higher Vth distribution 922 is for data storage NAND strings.

Assume that the sub-block includes a dummy NAND string and a data storage NAND string, and that the control gates of the SGD transistors are connected. Vth (and VvP2) for the P2 state may be set higher than Vsgd _ max, which is the highest SGD voltage applied when accessing the data storage NAND string. For example, Vsgd _ max may be an SGD voltage (see Vsg in fig. 15) applied during a precharge phase of a program operation or an SGD voltage (see Vsg in fig. 16) applied during a read operation. In one example, Vsgd _ max is 6V, and VvP2 is 6.5V-7V. With SGD Vth set high enough, the SGD transistors of the dummy NAND string will remain in a non-conductive state throughout a program or read operation of the data storage NAND string connected to the common bit line, even if Vbl is 0V. In contrast, for example, with a lower SGD Vth (e.g., 3V), the SGD transistors of the data storage NAND string may transition between a conductive state achieved by applying Vbl-0V and a non-conductive state achieved by setting Vbl-2.5V-3V. An SGD transistor will be conductive when its control gate voltage (Vsg) is greater than the sum of Vth and the drain voltage (e.g., Vbl). The Vth of the SGD transistor should not be too high to interfere with neighboring transistors.

For a dummy NAND string having multiple SGD transistors, one or more SGD transistors may be provided with a high Vth as described above.

FIG. 10A depicts voltage signals used in a series of programming cycles in an exemplary programming operation for S L C memory cells that results in the Vth distribution of FIG. 9A As mentioned, in one approach, S L C programming may be relatively fast because it involves one or sometimes two programming pulses.in FIGS. 10A and 10B, the horizontal axis represents the number of programming cycles and the vertical axis represents the voltage. Voltage signal 1050 includes programming pulse 1051 and program-verify voltage VvP 1052 in a first programming cycle, and programming pulse 1053 and program-verify voltage VvP 1054 in a second final programming cycle. applying the voltage signals to the word line selected for programming. the initial programming voltage and step size for the S L C programming of FIG. 10A may be different than the M L C programming of FIG. 10B.

FIG. 10B depicts voltage signals used in a series of program cycles in an exemplary program operation for M L C memory cells that results in the Vth distribution of FIG. 9B.

The voltage signal 1000 includes a series of programming voltages applied to the word line selected for programming, including an initial programming voltage 1001. In this example, the voltage signal includes a programming voltage that is stepped up in magnitude using a fixed or varying step size in one or more programming cycles of the programming pass. This is referred to as incremental step pulse programming, where the programming voltage starts at an initial voltage (see programming voltage 1001) and increases in steps in each successive programming cycle, for example, until the programming operation is complete. When the threshold voltage of the selected memory cell reaches the verify voltage of the assigned data state, the operation is successfully completed.

The programming operation may include a single programming pass or multiple programming passes, each of which is programmed using, for example, incremental step pulses.

The verify signals in each program cycle (including the example verify signal 1002) may include one or more verify voltages based on the assigned data state being verified for the program cycle. As the programming operation progresses, the verification test may include a lower allocation data state, then a medium allocation data state, then a higher allocation data state. The example verify signal depicts three verify voltages as a simplification. See also the verification phase of fig. 15.

For example, at the beginning of a programming operation, all memory cells may initially be in an erased state. After the programming operation is complete, data can be read from the memory cells using a read voltage between the Vth distributions. At the same time, a read pass voltage Vread (e.g., 8V-10V, also referred to as a pass voltage or turn-on voltage) is applied to the remaining (unselected) word lines. By testing whether the Vth of a given memory cell is above or below one or more read reference voltages, the system can determine the data state represented by the memory cell. These voltages are demarcation voltages because they are divided between the Vth ranges of different data states.

Example encodings of the bits for the Er, A, B, and C states are 11, 10, 00, and 01, respectively, in the format of Upper Page (UP) bits/lower page (L P) bits.

Three pages of data may be stored with eight data states or three bits per cell. Example codes for bits for A, B, C, D, E, F and the G state are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. The data of the lower page can be determined by reading the memory cells using the read voltages of VrA and VRE. See also fig. 21. The data of the middle page can be determined by reading the memory cells using the read voltages of VrB, VrD, and VrF. The data of the upper page can be determined by reading the memory cells using the read voltages of VrC and VrG.

FIG. 11A depicts an example process for accessing a first set of NAND strings using a relatively high access speed and a second set of NAND strings using a relatively low access speed. Step 1100 includes accessing a first set of NAND strings connected to a first set of bit lines using a relatively high access speed while floating the voltages of a second set of bit lines. A relatively high access speed refers to changing the bit line voltage from an existing voltage to a requested voltage in a relatively short period of time. See fig. 14. Step 1101 includes accessing a second set of NAND strings connected to the first set of bit lines and the second set of bit lines using a relatively low access speed. The second set of bit lines is not connected to the first set of NAND strings, or to the SGD transistors of the first set of NAND strings, but these SGD transistors are in a non-conductive state due to their high Vth, so that the second set of bit lines is not electrically connected to the memory cells of the first set of NAND strings. In other words, the second set of bit lines are not electrically connected to the channels of the memory cells of the first set of NAND strings. The lack of an electrical connection between two points in a memory device refers to the lack of a conductive path between the two points. For example, an access may include a program or read operation. Further, the groups of NAND strings can be accessed alternately, repeatedly, or sequentially in any order.

For example, in FIG. 12A, the first set of NAND strings may include NAND strings 700n,702n,704n,706n,708n,710n,712n, and 714n in B L K0, and the second set of NAND strings may include NAND strings 790-790p in B L K1, the first set of bit lines may include B L00, B L12, B L24, B L36, B L48, B L510, B L612, and B L712, e.g., even numbered bit lines, and the second set of bit lines may include B L1, B L3, B L5, B L7, B L9, B L11, B L13, and B L15, e.g., odd numbered bit lines step 1100 may involve changing or otherwise driving voltages on even numbered bit lines associated with accessing the first set of NAND strings while causing voltages on odd numbered NAND strings to change or otherwise drive voltages on floating bit lines associated with accessing each of the second set of NAND strings.

FIG. 11B depicts an example programming operation in which the process of FIG. 11A may be implemented, step 1100 begins a programming operation for a selected word line (W L sel) of a selected sub-block, step 1101 sets latches for selected memory cells based on the program data, e.g., the latches may specify a data state assigned to the memory cells, if the data state is an erased state, the latches specify that the memory cells have a locked state and should be inhibited from programming, if the data state is a programmed state, the latches specify that the memory cells have a programmed state and should be programmed, step 1102 begins a programming cycle for W L sel, step 1103 includes performing a precharge phase, see at t0-t3 of FIG. 15, step 1104 includes reading the latches of the selected memory cells, e.g., to determine whether the memory cells are in the locked state or the programmed state, step 1105 includes performing a programming phase, see FIGS. 11C and 11D, and at t3-t8 of FIG. 15. step 1106 includes performing a verify phase, see FIGS. 11C and 11D, and at t 8-16 of FIG. 15.

Step 1107 includes updating the latches based on the results of the verification test in the verification phase. For example, at step 1106, the latch may be updated from a programmed state to a locked out state for memory cells that pass the verification test. Decision step 1108 determines whether there is a next programming cycle. If many memory cells have not completed programming, e.g., are in a programmed state, the next programming cycle can be performed. If the decision step is true, then step 1111 includes stepping Vpgm and the next programming cycle begins at step 1102. If decision step 1108 is false, decision step 1109 determines whether there is a next word line and/or sub-block to program. If decision step 1109 is true, another program operation begins at step 1100. If decision step 1109 is false, step 1110 represents the end of the program operation.

FIG. 11C depicts an exemplary implementation of the program phase and verify phase of FIG. 11B using a relatively high access speed, for example, this may apply to S L C memory cells in a first set of NAND strings connected to a first set of bit lines, the program phase includes steps 1120 and 1121, and the verify phase includes step 1122 and 1124 for the first set of bit lines, step 1120 includes increasing Vbl to an inhibit voltage (e.g., 2V) for memory cells having a locked-out state (e.g., by assigning a first time period for the voltage increase, such as t2-t3 in FIG. 15), and setting Vbl to 0V for memory cells having a programmed state concurrently, which includes floating the voltage of the second set of bit lines.

Step 1122 includes setting the voltage on W L sel to a verify voltage (e.g., VvE, VvF, or VvG in fig. 15), and setting the voltage on unselected W L to vread step 1123 includes increasing the voltages of the first and second sets of bit lines to B L _ sense as previously discussed in connection with fig. 2 (e.g., by allocating a first time period for the increase, such as t9-t10 in fig. 15).

In steps 1120 and 1123, the first time period may be the same or different. Generally, when a relatively high access speed is used, a given first time period may be allocated for a given change (e.g., increase or decrease) in Vbl. The first period may be allocated in proportion to a change in Vbl.

FIG. 11D depicts an exemplary implementation of the program phase and verify phase of FIG. 11B using a relatively low access speed, for example, this may apply to M L C memory cells in a second set of NAND strings connected to a first set of bit lines and a second set of bit lines, the program phase includes steps 1130 and 1131, and the verify phase includes step 1132 1134. for the first set of bit lines and the second set of bit lines, step 1130 includes increasing Vbl to a program inhibit voltage for memory cells having a locked out state (e.g., by assigning a second time period, such as t2-t3 in FIG. 15, to the voltage increase), and setting Vbl to 0V for memory cells having a programmed state. the second time period may be greater than the first time period in FIG. 11C due to the larger RC time constant of the bit lines when the second set of NAND strings are accessed. step 1131 includes increasing the voltage on W L sel to Vpass after the second time period, and increasing the voltage on unselected word lines to Vpass.

Step 1132 includes setting the voltage on W L sel to a verify voltage, and the voltage on the unselected W L to Vread step 1133 increases the voltages of the first and second sets of bit lines to B L _ sense (e.g., by allocating a second time period for the increase, such as t9-t10 in FIG. 15.) step 1134 includes sensing the conductive state of the selected memory cell on W L sel in the second set of NAND strings for each verify voltage.

In steps 1130 and 1133, the second time period may be the same or different. When a relatively low access speed is used, a given second time period may be allocated for a given change (e.g., increase or decrease) in Vbl. The second period of time may be allocated in proportion to the change in Vbl.

FIG. 11E depicts an example read operation that can implement the process of FIG. 11A. the read operation begins at step 1140. step 1141 includes setting the voltage on W L sel to a read voltage, and setting the voltage on unselected W L to Vread. see example read voltages VrA and Vree in FIG. 16. step 1142 includes setting the voltage of the sense circuit. for example, the sense circuit may include a sense node that is charged to a specified voltage. see FIG. 2. then, steps 1143a and 1144a or 1143B and 1144B, respectively, may be performed to achieve a relatively high or relatively low access speed read operation. step 1143a includes increasing the voltages of the first and second sets of bit lines to B L _ sense (e.g., by assigning a first time period to the increase, such as t2-t3 in FIG. 16). step 1144a involves reading the first set of NAND strings.

Step 1143B includes increasing the voltages of the first and second sets of bit lines to B L _ sense (e.g., by assigning a second time period to the increase, such as t2-t3 in fig. 16.) step 1144B involves reading the second set of NAND strings.

Step 1145 includes storing the read result in a latch. For example, a single bit may be stored for each read voltage to indicate whether the memory cell is in a conductive or non-conductive state when the read voltage is applied. The read operation is completed at step 1146.

Another approach is to provide a voltage kick (voltage kick) for the voltage of the second set of bit lines when reading the first set of NAND strings connected to the first set of bit lines. This may help couple the voltages of the first set of bit lines to reduce ramp time. See curve 1680a of figure 16. A voltage kick may also be provided for the voltage of the first set of bit lines.

Fig. 11F depicts an example programming operation for an SGD transistor consistent with fig. 9C. As mentioned, a dummy NAND string can be reversibly created in which the channels of the memory cells are electrically disconnected from the respective bit lines by providing a sufficiently high Vth to the SGD transistors of the dummy NAND string to hold the SGD transistors in a non-conductive state. The SGD transistors of the data storage NAND strings have a lower Vth, which allows the SGD transistors to transition between a conductive state (when the data storage NAND string is selected for programming or reading) and a non-conductive state (when the data storage NAND string is not selected for programming or reading). Step 1150 includes programming SGD transistors in a first set of NAND strings connected to a first set of bit lines using a lower verify voltage (VvP1), and step 1151 includes programming SGD transistors in dummy NAND strings interleaved with the first set of NAND strings (and connected to a second set of bit lines) using a higher verify voltage (VvP2), wherein VvP2> VvP 1. As mentioned, an incremental step pulse programming process may be used, such as in fig. 10A or 10B.

FIG. 12A depicts a top view of a set of blocks B L K0-B L K3 of FIG. 4, including NAND strings and their connections to bit lines, in an exemplary configuration of a memory device for implementing the process of FIG. 11A with high and low access speed blocks.

Similarly, there are sixteen bit lines B L0-B L15 that are shared by different blocks, the bit lines being connected to column decoder 132, as discussed in connection with FIG. 1. the column decoder receives VB L _ sel and VB L _ unsel from bit line drivers 440 and 440a, respectively, and may route these voltages to sense circuits 60-75 in a set of sense circuits 99. each sense circuit may then route one of the bit line voltages to the corresponding bit line based on the flags, as discussed in connection with FIG. 2. path 132a extends between the column decoder and the sense circuits, and path 118 extends between the column decoder and controller 122 (FIG. 1).

In one example, B L K0 (one block) is used for S L C memory cells for relatively high access speeds, and B L K1-B L K3 (another block) is used for M L C memory cells for relatively low access speeds in this case, each memory cell in the second block (B L K1-B L K3) stores a greater number of bits (storage density) than each memory cell in the first block (B L K L). The one or more high access speed blocks may be closest to the column decoder 132 to minimize RC delay during voltage changes on the bit lines.

In the case of every other memory cell storing one bit in B L K0, the effective storage density is one-half bit per memory cell.

In one option, different time periods may be assigned for varying the bit line voltages based on the distance of the block from the read/write circuits, where a shorter time is assigned when the distance is smaller.

In addition, high access speed blocks may be used as a cache for lower speed blocks. See fig. 12B. For example, in a programming operation for a lower speed block, data may be initially programmed to the higher speed block acting as a cache and then transferred to the lower speed block. Data may also be initially programmed into a higher speed portion of a block, such as one sub-block, and then transferred to a lower speed portion of the block, such as another sub-block. These methods allow external controllers to achieve relatively high access speeds by: memory cells with high access speeds are programmed and read, and then focus on other tasks while subsequently data is moved either internally within a block or between blocks to memory cells with lower access speeds.

For example, SB0 includes data-storing NAND strings (e.g., non-dummy NAND strings, valid NAND strings, or NAND strings eligible to store data) 700n,702n,704n,706n,708n,710n,712n, and 714n, and dummy NAND strings 701n,703n,705n,707n,709n,711n,713n, and 715n, the data-storing NAND strings are interleaved with the dummy NAND strings, one of which is located between a pair of adjacent data-storing NAND strings, in other words, a first set of NAND strings 700n,702n,704n,706n,708n,710n, 715n, 710n,712n, and 714n, a first set of NAND strings 700n, 703n,705n, 714n, 703n, 710n,712n, and 714n are interleaved with the SB0 in the high access speed block B L K0 consistent with FIG. SB4 in the low access speed block B L K1.

In another option, there is more than one dummy NAND string between a pair of adjacent data storage NAND strings. In addition, the NAND strings in the sub-blocks are shown aligned in the x-direction with one bit line extending directly over the top of the NAND string, but other arrangements are possible. For example, the NAND strings in a sub-block may be staggered to provide a denser layout.

The sub-blocks of B L K0 are evenly configured with data storage NAND strings alternating with dummy NAND strings the sub-blocks of B L K1-B L K2 are also evenly configured with consecutive data storage NAND strings and no dummy NAND strings.

In this example, as mentioned in connection with FIG. 11A, the first set of bit lines may include B0, B2, B04, B16, B28, B310, B412, and B512, e.g., even numbered bit lines, and the second set of bit lines may include B61, B73, B85, B97, B9, B011, B113, and B215, e.g., odd numbered bit lines.

FIG. 12B depicts an exemplary architecture consistent with FIG. 12A. the method of FIG. 12A allows memory devices on one chip to provide high and low access speeds.A computing system is typically limited by the access speed of its memory rather than the CPU speed.one method is to provide a dedicated cache (such as a storage level memory or S L C fast cache) on one chip for use by lower speed memory on another chip.

The exemplary architecture combines a CPU and memory devices in four units 1230a-1230d to allow data transfer between these memory devices.

In particular, in unit 1230a, the CPU 1230 may be provided with a high access speed cache, such as L1, L2, or L3 cache 1231. for example, the CPU may be the processor 122C in the off-chip controller 122 of FIG. 1. memory 1232 represents a set of blocks of FIG. 12A on a common chip, while cache 1233 represents the portion of the block that provides the high access speed.

Similarly, unit 1230b includes a CPU1236 with L1, L2, or L3 cache 1237 and memory 1234 with cache 1235, unit 1230c includes a CPU 1238 with L1, L2, or L3 cache 1239 and memory 1240 with cache 1241, and unit 1230d includes a CPU 1244 with L1, L2, or L3 cache 1245 and memory 1242 with cache 1243 memory devices 1232, 1234, 1240, and 1242 may communicate with each other to transfer data.

FIG. 12C depicts an exemplary compute centric architecture, the method includes memory on one chip and CPU on another chip, and DRAM therebetween, the CPU includes L1, L, or L03 cache, the method has an indirect cost due to cache and memory being on different chips, specifically, unit 1260a includes CPU1262 (with either 3625, L, or L33 cache 1263), memory 1260, and DRAM1261 between CPU and memory unit 1260b includes CPU 1264 (with either L, L, or L cache 1265), memory 1267, and DRAM 1266 between CPU and memory unit 1260C includes CPU1272 (with either L, L, or L3 cache 1273), memory 1270, and DRAM 1271 between CPU and memory unit 1260d includes CPU 1274 (with either CPU 381, 462, or L cache 1275), and DRAM 1272, and memory 1274 may communicate with each other, CPU1272, DRAM 1274 may communicate with DRAM 1273, memory 1273, cache 1273, and DRAM 1273.

The method also has an indirect cost as the CPU cache and memory are on different chips unit 1280a includes a CPU 1280 (with L1, L2, or L03 cache 1281), a memory 1283, and a cache between the CPU and memory 1282 unit 1280b includes a CPU 1286 (with L11, L2, or L3 cache 1287), a memory 1284, and a cache between the CPU and memory 1285 unit 1280c includes a CPU 1288 (with L1, L2, or L3 cache 1289), a memory 1291, and a cache between the CPU and memory 1290 unit 1280D includes a CPU 1294 (with L1, L2, or L3 cache 1295), a memory 1292, and a cache 1293 between the CPU and memory 1293 1294, 1293 and 1293 devices 1294, 1293, 1292, and 1293 devices communicating data with each other.

FIG. 12E depicts a top view of block B L K0 in an exemplary configuration of a memory device for implementing the process of FIG. 11A with a high access speed sub-block and a low access speed sub-block region 1250 of B L K0 includes SB0 as the high access speed sub-block and region 1251 of B L K0 includes SB1-SB3 as the low access speed sub-block.

FIG. 12F depicts a top view of block B L K0 in an exemplary configuration of a memory device for implementing the process of FIG. 11A with data storage NAND strings 700n,702n,704n,706n,708n,710n,712n, 714n, 716n, and 718n separated by insulation instead of dummy NAND strings.

FIG. 13 depicts an exemplary bit line B L-B L consistent with FIGS. 8, 12A, 12E, and 12F, showing how capacitance (Cap.) exists between adjacent bit lines, the magnitude of the capacitance depending on factors such as the spacing between bit lines, the material and length and width of the bit lines, and the voltage signal on the bit lines.

In some cases, three adjacent bit lines may receive the same voltage signal, such as when Vbl is increased from 0V to 2V to inhibit programming of the NAND strings during the programming pulse.in this case, the inter-bit line capacitance is relatively low.in another example, Vbl is increased from 0V to 2V on B L1, but remains at 0V for B L0 and B L2, such as when B L0 and B L2 are connected to selected NAND strings that are not inhibited during the programming pulse.in this case, the inter-bit line capacitance is relatively high.Another example is when one adjacent bit line receives the same voltage signal as B L1 but the other adjacent bit line receives a different voltage signal than B L1.in this case, the inter-bit line capacitance is modest.

Generally, when a set of adjacent NAND strings is programmed, the time allotted for the bit line voltage to change must be set based on a worst case scenario (e.g., worst case inter-bit line capacitance). The techniques provided herein may reduce the worst-case inter-bit line capacitance by floating every other bit line during programming. The floating bit line exhibits minimal capacitance to the active bit line for voltage changes. This approach ensures that the voltage floats on two adjacent bit lines of the active bit line. Furthermore, by electrically disconnecting every other bit line (dummy bit line) from the memory cell channels of the respective NAND strings during sensing, this avoids data state dependent bit line charging times and current draw from bit lines to channels for these dummy bit lines. This also reduces the inter-bit line capacitance.

FIG. 14 depicts a voltage versus time curve showing a relatively fast increase and a relatively slow increase. At t0, the controller commands the voltage driver to change its output from 0V to the requested voltage, Vreq. When a voltage driver is connected to a bit line, the time to change the voltage is affected by the RC time constant of the bit line. In one example (curve 1400), the increase occurs relatively quickly in time period ths (hs ═ high speed). In another example (curve 1401), the increase occurs relatively slowly in the time period tls (ls ═ low speed). The time periods ths and tls may represent time periods t2-t3 or t9-t10 in FIG. 15, where Vbl is increased from 0V to 2V, for example. During a programming operation, voltage timing circuit 117 (FIG. 1) may allocate time for changing the bit line voltage based on knowing whether the voltage is floating on an adjacent bit line. If the voltage floats on an adjacent bit line, a shorter access time (e.g., ths) may be allocated. If the voltage is not floating, a longer access time (e.g., tls) may be allocated. For example, the allocated time period may be set for various changes in the voltage signal that occur during a program or read operation. See, for example, fig. 15 and 16. Different allocation periods may be set for the same change in voltage signal for high speed access or low speed access of the memory cell.

Similarly, during a sense operation, which may occur as a verify test of a program operation or as a separate read operation, voltage timing circuit 117 may allocate a shorter time to charge the bit line voltage when every other bit line is used for sensing than when each bit line is used.

A relatively high access speed is obtained by assigning a relatively short period of time to vary the voltage on the word line, while a relatively low access speed is obtained by assigning a relatively long period of time to vary the voltage on the word line (e.g., by the same amount).

In fig. 15 and 16, the vertical dimension represents voltages and the horizontal dimension represents time, with time points t0-t 16. the depicted time period corresponds to one programming cycle and includes a precharge phase 1587(t0-t3), a program phase 1588(t3-t9), and a verify phase 1589(t9-t 16.) an exemplary voltage of the signals is also depicted, voltage signal 1500 represents VW L n (i.e., the voltage of the selected word line), voltage signal 1510 represents Vwl _ unsel (i.e., the voltage of the remaining unselected word lines), voltage signal 1530 represents the select gate voltage (e.g., Vsgd and/or Vsgs), and voltage signal 1540 represents Vbl (i.e., the bit line voltage).

The voltage signal 1500 is represented by, for example, a curve 1501 at an initial value (such as 0V), a curve 1502 representing a first further increase in W L n from the initial value to an intermediate value (e.g., Vpass), a curve 1503 in which W L n remains at Vpass, a curve 1504 representing a second further increase from Vpass to Vpgm, a curve 1505 representing a hold period at Vpgm, a curve 1506 representing a decrease from Vpgm to the initial value, and a curve 1507 representing verify voltages VvE, VvF and VvG.

During a program operation, exemplary time periods during which the voltage allocated for VW L sel increases are t3-t4 (increasing from the initial voltage to Vpass), t6-t7 (increasing from Vpass to Vpgm), t10-t11 (increasing from the initial voltage to VvE), t12-t13 (increasing from VvE to VvF), and t14-t15 (increasing from VvF to VvG).

The voltage signal 1510 is represented by the following curve: a curve 1511 at an initial value (such as 0V), a curve 1512 representing the increase in Vwl _ unsel from the initial value to the pass value (e.g., Vpass), and a curve 1513 where Vwl _ unsel remains at Vpass from t3 to t 4.

During the precharging of the selected select gate transistor and the unselected select gate transistors, the voltage signal 1530 is represented by curve 1531. The selected Select Gate (SG) transistors are located in a selected sub-block (the sub-block selected for programming) and the unselected SG transistors are located in an unselected sub-block (the sub-block not selected for programming). Subsequently, a curve 1532 having Vsg _ sel of 2.5V represents the voltage of the selected SG transistor, and a curve 1533 having Vsg _ unsel of 2.5V represents the voltage of the unselected SG transistor.

In one approach, during precharging of active bit lines (e.g., selected and unselected bit lines connected to selected and unselected NAND strings in a selected sub-block, respectively), voltage signal 1540 is represented by curve 1541 depicting a voltage Vbl _ active of 2V. then, curve 1542 depicts a voltage Vbl _ unsel of 2V (voltage on the unselected bit lines), and curve 1543 depicts a voltage Vbl _ sel of 0V (voltage on the selected bit line.) if applicable, the voltage on the dummy bit line may be floated and will tend to follow the voltage of the adjacent active bit line.

During the precharge phase, a positive Vbl active (curve 1541) is provided to the drain side of the channel of the string to remove residual electrons and provide a small amount of boost (such as 1V-2V). At this time, the SGD transistors of the selected and unselected sub-blocks are in a conductive state, e.g., at a voltage of 6V. This allows the bit line voltage to be transferred to the drain side channel. At this point, the SGS transistors of the selected and unselected sub-blocks may also be in a conductive state, e.g., at a voltage of 6V (curve 1531) to allow the source line voltage (Vsl) to pass to the source end of the channel.

VW L n and Vwl _ unsel are ramped up in the program phase, starting for example from t2 to provide capacitive coupling of the channels of unselected NAND strings then, at t6-t7, VW L n is ramped up further to the peak program pulse level of Vpgm and held at Vpgm until t8. after the program pulse, VW L n is ramped down to Vss (0V) at t8 then, in the verify phase, one or more verify tests are performed by applying one or more control gate read voltages (curve 1507) on W L n and sensing the conductive state of the memory cells in the selected NAND string of the selected sub-block for each read voltage.

During the program phase and the verify phase, Vsg _ sel may be set to, for example, 2.5V and 0V for the selected sub-block (curve 1532) and the unselected sub-block (curve 1533), respectively. During the programming pulse, with Vbl ═ 0V (curve 1543), Vsg _ sel is high enough to provide the SG _ sel transistor in a conductive state for the selected NAND string. However, it is low enough that by setting a high Vbl for these strings, the SG _ sel transistors can be set in a non-conductive state for the unselected NAND strings. During the program phase and the verify phase, Vbl _ unsel may remain up to 2V for the unselected NAND strings (curve 1542). Vbl _ sel may be increased during the verify phase as part of the sensing process of bit line charging.

During the verify phase, the SGD transistor is in a strongly conductive state to allow sensing of the selected memory cell. Thus, for the selected NAND string, the drain-side select gate transistor is in a conducting state during the precharge phase and the programming phase. Vsg unselected is lowered to a reduced level, such as 0V, which provides SG unselected transistors in a non-conductive state for strings in the unselected sub-blocks. After the verify phase, at t16, Vbl is reduced to 0V, so that the SGD transistor is turned off and the channel region has a floating voltage.

The time lines and dots in fig. 14 and 15 represent both the high access speed case and the low access speed case. In fig. 14 and 15, after t3 and t2, respectively, the value of the point in time for the high access speed case will be lower than the value of the point in time for the low access speed case.

Curve 1650 represents VW L sel in this example, in a configuration using M L C memory cells with eight data states, the read operation includes two read voltages VrA and VRE for reading the lower page data increasing from an initial voltage such as 0V to VrA at t2 and increasing from VrA to VRE at t 6.

Curve 1660 represents the voltage Vwl _ unsel on the unselected word lines. Vwl _ unsel increases from the initial voltage to Vpass at t2, remains at Vpass until t10, and then decreases back to the initial voltage.

Curve 1670 represents the voltage Vsg on the SGD transistor and the SGS transistor. Referring to curve 1671 for the selected subblock, Vsg increases from the initial voltage to a conduction level (such as 6V) at t2, remains at that level until t10, and then decreases back to the initial voltage. The Vsg is high enough to provide the SGD and SGS transistors in a strongly conductive state to allow sensing to occur. For the unselected subblocks, curve 1672 shows that Vsg may be set to 0V to keep the SGD and SGS transistors in a non-conductive state so that they do not interfere with the sensing of the selected subblock.

Curve 1680 represents Vbl, i.e., the bit line voltage. Vbl increases from the initial voltage to a positive voltage (such as 2V) at t2, remains at this level until t10, and then decreases back to the initial voltage. In one approach, a common voltage signal may be applied to the dummy bit line and the active bit line. Exemplary time periods allocated for changing Vbl include t2-t3, where Vbl, when charged by it, may be increased from 0V to 2V, e.g., in preparation for sensing, or to other suitable levels for sensing. The time period may be a first time period that is relatively short when reading a relatively high access speed portion of the memory device or a second time period that is relatively long when reading a relatively low access speed portion of the memory device. For example, another example of a time period that may be set to be shorter or longer for a high access speed or a low access speed, respectively, is a time period from the start of an increase in Vbl (at t 2) to the start of a sensing operation (at t 4).

Curve 1680a shows the option of increasing Vbl with voltage kick, as mentioned in connection with fig. 11E. A voltage signal with a kick refers to, for example, a voltage signal that temporarily increases from a starting voltage to a peak voltage and then slightly decreases to a final voltage. The requested output of the voltage driver is set to a peak voltage and then to a final voltage such that the voltage increases from the starting voltage to the final voltage faster than the requested output of the voltage driver changes directly from the starting voltage to the final voltage. The peak voltage may be, for example, up to 10% -30% higher than the final voltage. The voltage signal has an overshoot that is higher than the desired final voltage. In one approach, Vbl may be increased to a peak of 2.2V and then decreased to a final voltage of 2V, representing a 20% overshoot. Curve 1680b shows the option of Vbl increase without voltage kick.

In general, during sensing of a first set of NAND strings, the bit line drivers may be configured to drive the first set of bit lines without a voltage kick while driving a second set of bit lines with a voltage kick, where the first set of bit lines is connected to the data storage NAND strings and the second set of bit lines is connected to the dummy NAND strings. Voltage kicks may also be used to drive the first set of bit lines.

Curve 1680 represents Vsense, the voltage in the sense node of the sense circuit. At t2, Vsense increases from the initial voltage to a positive voltage, such as 2V. At t4, when VrA is applied, the sense node is allowed to communicate with the bit line. The amount of decay in the sense node is determined to evaluate whether the memory cell is in a conductive state or a non-conductive state. If the memory cell has VrA > Vth and is therefore in a conductive state, curve 1693 shows that the sense node voltage will decay below the trip voltage Vtrip at sense time t 5. If the memory cell has VrA ≦ Vth and is therefore in a non-conductive state, curve 1691 shows that the sense node voltage will not decay significantly at sense time t 5.

Similarly, at t8, when VrE is applied, the sense node is allowed to communicate with the bit line. If the memory cell has VRE > Vth and is therefore in a conductive state, curve 1694 shows that the sense node voltage will decay below the trip voltage Vtrip at sense time t 9. If the memory cell has VRE ≦ Vth and is therefore in a non-conductive state, curve 1692 shows that the sense node voltage will not decay significantly at sense time t 5.

Sensing of the S L C memory cell can be done similarly, except that VW L sel is set to a single read voltage Vr (FIG. 9A).

In one implementation, a device includes a first set of NAND strings (700n,702n,704n,706n,708n,710n,712n, and 714n), a second set of NAND strings (790 p), a first set of bit lines (B L0, B L2, B L04, B L16, B L28, B L310, B L412, and B L512) interleaved with a second set of bit lines (B L1, B L3, B L5, B L7, B L9, B L11, B L13, and B L15), and bit line drivers (440,440a,440B) configured to drive the first set of bit lines and the second set of bit lines during programming of the second set of NAND strings and to drive and float the first set of bit lines during programming of the first set of NAND strings.

In another implementation, a method includes, during programming of a first sub-block (SB0) including unselected NAND strings (700n) connected to a first bit line (B L0), increasing a voltage on the first bit line to an inhibit voltage while floating a voltage on a bit line (B L1) adjacent to the first bit line and increasing a voltage on a selected word line (VW L sel) to a program voltage (e.g., starting at t3 in FIG. 15) after a first time period (ths) has elapsed since the start of increasing the voltage on the first bit line to the inhibit voltage, and during programming of a second sub-block (SB1) including unselected NAND strings (710z) connected to the first bit line, increasing the voltage on the first bit line to the inhibit voltage while driving a voltage on a bit line adjacent to the first bit line and after a second time period (tls) has elapsed since the start of increasing the voltage on the first bit line to the inhibit voltage is increased to the selected word line, e.g., at t3 in FIG. 15.

In another implementation, a device includes a NAND string (700n,702n,704n,706n,708n,710n,712n, and 714n) in a first block (B L K0), a NAND string (790) in a second block (B L K1), a first set of bit lines (B L00, B L12, B L24, B L36, B L48, B L510, B L612, and B L712) interleaved with a second set of bit lines (B L1, B L3, B L5, B L7, B L9, B L11, B L13, B L, and B L15) connected to the NAND string in the first block and the NAND string in the second block, and disconnected from the NAND string in the first block and connected to the NAND string in the second block, a means for driving the second set of bit lines in the first block and the NAND string during programming of the second set of bit lines (a, 440a, and a means for driving the second set of bit lines in the first block).

The means for driving the first set of bit lines and floating the second set of bit lines, and the means for driving the first set of bit lines and the second set of bit lines, may include the controller 122, the control circuitry 110, the power control module 116 including the voltage timing circuit 117, the read/write circuit 128 including the column decoder 132 and the bit line voltage drivers 440 and 440a, and the B L selector 173, or other logic hardware, and/or other executable code stored on a computer readable storage medium or device of FIGS. 1-3.

In another implementation, a device includes a set of NAND strings extending vertically in a stack, the set of NAND strings including a NAND string eligible to store data (700n) and a NAND string not eligible to store data (710z), the NAND string eligible to store data including memory cells (704 and 713) arranged along a channel (700a) and the NAND string not eligible to store data including memory cells (724 and 733) arranged along a channel (710a), and a bit line (B L0) extending horizontally and directly over the NAND string eligible to store data and the NAND string not eligible to store data, the bit line electrically connected to and disconnected from the channel of the NAND string eligible to store data.

In another implementation, a system includes a controller (110,122) and a memory die (108) coupled to the controller, the memory die including a first group including a plurality of groups of coupled memory cells (700n,702n,704n,706n,708n,710n,712n, and 714n), a second group including a plurality of groups of coupled memory cells (790 p), a first group of bit lines (B L0, B L2, B L04, B L16, B L28, B L310, B L412, and B L512), the first group of bit lines interleaved with a second group of bit lines (B L1, B L3, B L5, B L7, B L9, B2 11, B L13, and B L15), and a bit line driver (440,440a) configured to drive bit lines in the second group in response to a programming command directed to the second group, and to drive bit lines in the second group in response to the second group of bit lines and to the second group of bit lines L11, and to drive bit lines in response to the second group of bit lines, and to the second group of bit lines, the floating programming command.

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.