阅读说明：本技术 一种3D集成式Micro LED及其制作方法 (3D integrated Micro L ED and manufacturing method thereof ) 是由 仇美懿 林耀辉 庄家铭 于 2020-04-15 设计创作，主要内容包括：本发明公开了一种3D集成式Micro LED及其制作方法,所述Micro LED包括导电衬底,若干个设于导电衬底正面上的基底层,设置在基底层正面上并填充在基底层之间的阻挡层,所述阻挡层将基底层隔绝,设置在基底层上发光柱体,所述发光柱体包括设于基底层上的第一半导体层、将第一半导体层的包裹的有源层、将有源层包裹的第二半导体层,覆盖在发光柱体和阻挡层上的透明导电层,所述透明导电层将多个发光柱体形成导电连接,设于导电衬底背面的第一电极,设于透明导电层上的第二电极,所述发光柱体实现360度出光,且其发光角度为180度。(The invention discloses a 3D integrated Micro L ED and a manufacturing method thereof, wherein the Micro L ED comprises a conductive substrate, a plurality of base layers arranged on the front surface of the conductive substrate, a barrier layer arranged on the front surface of the base layers and filled between the base layers, and a light emitting column arranged on the base layers, wherein the barrier layer isolates the base layers, the light emitting column comprises a first semiconductor layer arranged on the base layers, an active layer wrapping the first semiconductor layer, a second semiconductor layer wrapping the active layer, and a transparent conductive layer covering the light emitting column and the barrier layer, the transparent conductive layer enables the plurality of light emitting columns to form conductive connection, a first electrode arranged on the back surface of the conductive substrate and a second electrode arranged on the transparent conductive layer, the light emitting column realizes 360-degree light emitting, and the light emitting angle of the light emitting column is 180 degrees.)

1. A3D integrated Micro L ED, comprising:

a conductive substrate, a conductive layer,

a plurality of base layers disposed on the front side of the conductive substrate,

a barrier layer disposed on the front side of the substrate layers and filled between the substrate layers, the barrier layer insulating the substrate layers,

a light emitting pillar disposed on the base layer, the light emitting pillar including a first semiconductor layer disposed on the base layer, an active layer wrapping the first semiconductor layer, and a second semiconductor layer wrapping the active layer,

a transparent conductive layer overlying the light emitting pillars and the barrier layer, the transparent conductive layer conductively connecting the plurality of light emitting pillars,

a first electrode disposed on the back surface of the conductive substrate, a second electrode disposed on the transparent conductive layer,

the light-emitting cylinder realizes 360-degree light-emitting, and the light-emitting angle is 180 degrees.

2. The 3D integrated Micro L ED, according to claim 1, wherein the light emitting pillars are columnar structures with a spacing of 3-50 μm.

3. The 3D integrated Micro L ED of claim 1, wherein the base layer includes an AlN layer disposed on a conductive substrate, an AlGaN layer disposed between the AlN layer and the U-GaN layer, and a U-GaN layer.

4. The 3D integrated Micro L ED according to claim 3, wherein the barrier layer has a height equal to or greater than a height of the base layer, and is made of an opaque insulating material.

5. The 3D integrated Micro L ED according to claim 4, wherein the base layer has a thickness of 1.5-2 μm, the barrier layer has a thickness of 2-3 μm, and the barrier layer is made of silicon nitride or indium nitride.

6. The 3D integrated Micro L ED, according to claim 1, wherein the conductive substrate is a silicon substrate with a thickness of 80-150 μm;

the transparent conducting layer is an ITO layer, and the thickness of the transparent conducting layer is 100-200 nm;

the first electrode has a structure of Al/Ti/Pt/Au, and the thickness of the first electrode is 100-200nm/50-80nm/50-100nm/200-3000 nm;

the second electrode has a structure of Cr/Pt/Au, and the thickness of the second electrode is 3-50nm/50-100nm/200-3000 nm.

7. The 3D integrated Micro L ED according to claim 1, further comprising a protective layer disposed on the transparent conductive layer outside the second electrode, the protective layer being made of an insulating layer material.

8. A method for manufacturing a 3D integrated Micro L ED is characterized by comprising the following steps:

firstly, forming a base layer and a first semiconductor layer on the front surface of a conductive substrate,

etching the first semiconductor layer and the substrate layer to the surface of the conductive substrate to form a plurality of columnar structures;

forming a barrier layer on the front surface of the exposed conductive substrate, wherein the barrier layer isolates the base layer;

forming an active layer and a second semiconductor layer on the first semiconductor layer in sequence to form a light emitting column;

fifthly, forming a transparent conducting layer on the light emitting columns and the barrier layer, and enabling the plurality of light emitting columns to be in conducting connection;

sixthly, forming a first electrode on the back surface of the conductive substrate, and forming a second electrode on the transparent conductive layer;

the light-emitting cylinder realizes 360-degree light-emitting, and the light-emitting angle is 180 degrees.

9. The method of claim 8, wherein 2 etches are performed in step (two),

the first etching is rough etching, the first semiconductor layer and the substrate layer are etched until the surface of the conductive substrate is etched, and a plurality of columnar structures are formed;

and the second etching is fine etching, only the first semiconductor layer is etched until reaching the surface of the substrate layer, so that the first semiconductor layer forms a columnar structure, and the cross section area of the first semiconductor layer is smaller than that of the substrate layer.

10. The method of claim 8, wherein between the step (three) and the step (four), a new first semiconductor layer with a predetermined thickness is formed on the etched first semiconductor layer, such that the thickness of the entire first semiconductor layer is equal to the thickness of the first semiconductor layer before etching.

Technical Field

The invention relates to the technical field of diodes, in particular to a 3D integrated Micro L ED and a manufacturing method thereof.

Background

The Micro light-Emitting Diode (Micro L light-Emitting Diode, Micro L ED) is a light-Emitting Diode with the size of micron, because the size of the Micro L ED is smaller, the Micro L ED can be used as a pixel on a display panel, and the display panel prepared by adopting the Micro L ED can be called a Micro L ED display panel.

Referring to fig. 1, a conventional Micro L ED chip includes a substrate 10, a first semiconductor layer 20 disposed on the substrate 10, an active layer 30 and a first electrode 51 disposed on the first semiconductor layer 20, a second semiconductor layer 40 disposed on the active layer 30, and a second electrode 52 disposed on the second semiconductor layer 40. the conventional Micro L ED chip is limited by outer layer crystal growth, and the light emitting angle is generally between 110 to 130 degrees.

In addition, the active layer 30 of the conventional Micro L ED chip is only disposed on the plane of the first semiconductor layer 20, is a 2D light emitting structure, and belongs to planar light emission.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a 3D integrated Micro L ED, which can realize light emission of 360 degrees and has a light emission angle of 180 degrees.

The technical problem to be solved by the invention is to provide a 3D integrated Micro L ED, which has small volume and high pixel height.

The invention also aims to solve the technical problem of providing a manufacturing method of the 3D integrated Micro L ED, which can realize 360-degree light emission and has a light-emitting angle of 180 degrees.

In order to solve the above technical problem, the present invention provides a 3D integrated Micro L ED, comprising:

a conductive substrate, a conductive layer,

a plurality of base layers disposed on the front side of the conductive substrate,

a barrier layer disposed on the front side of the substrate layers and filled between the substrate layers, the barrier layer insulating the substrate layers,

a light emitting pillar disposed on the base layer, the light emitting pillar including a first semiconductor layer disposed on the base layer, an active layer wrapping the first semiconductor layer, and a second semiconductor layer wrapping the active layer,

a transparent conductive layer overlying the light emitting pillars and the barrier layer, the transparent conductive layer conductively connecting the plurality of light emitting pillars,

a first electrode disposed on the back surface of the conductive substrate, a second electrode disposed on the transparent conductive layer,

the light-emitting cylinder realizes 360-degree light-emitting, and the light-emitting angle is 180 degrees.

As an improvement of the scheme, the light-emitting columns are of a columnar structure, and the interval between the light-emitting columns is 3-50 mu m.

As an improvement of the scheme, the substrate layer comprises an AlN layer, an AlGaN layer and a U-GaN layer, the AlN layer is arranged on the conductive substrate, and the AlGaN layer is arranged between the AlN layer and the U-GaN layer.

As an improvement of the scheme, the height of the barrier layer is larger than or equal to that of the base layer, and the barrier layer is made of opaque insulating materials.

As an improvement of the scheme, the thickness of the substrate layer is 1.5-2 μm, the thickness of the barrier layer is 2-3 μm, and the material of the barrier layer is silicon nitride or indium nitride.

As an improvement of the scheme, the conductive substrate is a silicon substrate, and the thickness of the conductive substrate is 80-150 mu m;

the transparent conducting layer is an ITO layer, and the thickness of the transparent conducting layer is 100-200 nm;

the first electrode has a structure of Al/Ti/Pt/Au, and the thickness of the first electrode is 100-200nm/50-80nm/50-100nm/200-3000 nm;

the second electrode has a structure of Cr/Pt/Au, and the thickness of the second electrode is 3-50nm/50-100nm/200-3000 nm.

As an improvement of the above, the liquid crystal display further comprises a protective layer disposed on the transparent conductive layer other than the second electrode, the protective layer being made of an insulating layer material.

Correspondingly, the invention also provides a manufacturing method of the 3D integrated Micro L ED, which comprises the following steps:

firstly, forming a base layer and a first semiconductor layer on the front surface of a conductive substrate,

etching the first semiconductor layer and the substrate layer to the surface of the conductive substrate to form a plurality of columnar structures;

forming a barrier layer on the front surface of the exposed conductive substrate, wherein the barrier layer isolates the base layer;

forming an active layer and a second semiconductor layer on the first semiconductor layer in sequence to form a light emitting column;

fifthly, forming a transparent conducting layer on the light emitting columns and the barrier layer, and enabling the plurality of light emitting columns to be in conducting connection;

sixthly, forming a first electrode on the back surface of the conductive substrate, and forming a second electrode on the transparent conductive layer;

the light-emitting cylinder realizes 360-degree light-emitting, and the light-emitting angle is 180 degrees.

As an improvement of the above scheme, 2 times of etching is carried out in the step (II),

the first etching is rough etching, the first semiconductor layer and the substrate layer are etched until the surface of the conductive substrate is etched, and a plurality of columnar structures are formed;

and the second etching is fine etching, only the first semiconductor layer is etched until reaching the surface of the substrate layer, so that the first semiconductor layer forms a columnar structure, and the cross section area of the first semiconductor layer is smaller than that of the substrate layer.

As an improvement of the scheme, the method further comprises the following steps between the step (three) and the step (four): and forming a new first semiconductor layer with a preset thickness on the etched first semiconductor layer, so that the thickness of the whole first semiconductor layer is the thickness of the first semiconductor layer before etching.

The implementation of the invention has the following beneficial effects:

1. according to the invention, the characteristic of electrical conduction from top to bottom of the conductive substrate is utilized, and the plurality of light-emitting columns are arranged on the conductive substrate, wherein the active layer of each light-emitting column wraps the first semiconductor layer, and the second semiconductor layer wraps the active layer to form a columnar structure, so that light can be emitted at 360 degrees, and the light-emitting angle can reach 180 degrees.

2. The plurality of light-emitting columns are arranged on the conductive substrate, and the L ED display screen with smaller and higher pixels can be obtained by adjusting the distance between the light-emitting columns.

3. According to the invention, by utilizing the characteristic of vertical electrical conduction of the conductive substrate, a plurality of light-emitting columns are arranged on the conductive substrate to form an array mode, and the integration of Micro L ED is realized by matching with the first electrode and the second electrode, so that the problem of mass transfer is solved.

4. According to the invention, the plurality of light-emitting columns are formed on the conductive substrate, the problem of substrate peeling by laser is solved by utilizing the characteristic of up-down electrical conduction of the conductive substrate, the plurality of light-emitting columns are connected together to form conductive connection by the transparent conductive layer, only one second electrode needs to be formed on the transparent conductive layer, and one first electrode is formed on the back surface of the conductive substrate, so that the number of electrodes is effectively reduced, and the cost is reduced.

Drawings

FIG. 1 is a schematic structural diagram of a conventional Micro L EDd;

FIG. 2 is a schematic diagram of a 3D integrated Micro L ED according to the present invention;

FIG. 3 is a perspective view of a 3D integrated Micro L ED of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.

Referring to fig. 2 and 3, the present invention provides a 3D integrated Micro L ED, which includes a conductive substrate 10, a plurality of base layers 20 disposed on a front surface of the conductive substrate 10, barrier layers 30 disposed on the conductive substrate 10 and filled between the base layers, light emitting pillars 40 disposed on the base layers 20, a transparent conductive layer 50 covering the light emitting pillars 40 and the barrier layers 30, a second electrode 72 disposed on the transparent conductive layer 50, and a first electrode 71 disposed on a rear surface of the conductive substrate 10.

The invention integrates a plurality of light emitting columns 40 on the conductive substrate 10, and in order to ensure the electrical conduction between the upper and lower parts of the conductive substrate 10 and to omit the step of laser substrate stripping, the conductive substrate 10 of the invention is made of conductive material. In addition, in order to prevent light leakage and improve the light extraction efficiency of the chip, the conductive substrate 10 of the present invention is made of a material that is opaque to light. Preferably, the conductive substrate 10 is made of silicon.

Preferably, the thickness of the conductive substrate 10 is 80 to 150 μm. Preferably, the thickness of the conductive substrate 10 is 80 to 120 μm. If the thickness of the conductive substrate 10 is less than 80 μm, the thickness is too thin and is liable to crack, which does not function as a support and a connection; if the thickness is more than 150 μm, the voltage of the chip increases.

The conductive substrate 10 of the present invention may be, but is not limited to, a 2 inch silicon substrate, a 4 inch silicon substrate, or a 6 inch silicon substrate.

The light emitting pillars 40 and the conductive substrate 10 have a large difference in material, so that a large lattice mismatch exists between the light emitting pillars 40 and the conductive substrate 10, and in order to ensure that the light emitting pillars 40 can be integrated on the conductive substrate 10, the base layer 20 is disposed between the front surface of the conductive substrate 10 and the light emitting pillars 40, so as to reduce the lattice mismatch.

In order to ensure independent light emission between the light emitting pillars 40, the barrier layer 30 is filled between the substrate layers 20 to isolate the substrate layers 20, thereby ensuring that the substrate layers 20 are also independent. In addition, the barrier layer 30 of the present invention also plays a role of preventing light leakage from the side of the base layer 20, and therefore, the barrier layer 30 of the present invention is made of an opaque insulating material, and the height of the barrier layer 30 is greater than or equal to the height of the base layer 20. Preferably, the material of the barrier layer 30 is silicon nitride or indium nitride.

The base layer 20 of the present invention may have a single-layer structure or a laminated structure. When the base layer 20 has a stacked structure, the effect of reducing the lattice mismatch is more preferable, but if the thickness of the stacked structure is too large, the effect is rather reduced. Preferably, the thickness of the substrate layer 20 is 1.5 to 2 μm. Correspondingly, the thickness of the barrier layer 30 is 2-3 μm.

The material of the base layer 20 is between the conductive substrate 10 and the light emitting pillar 40, and preferably, the base layer 20 includes one or more layers selected from an AlN layer, an AlGaN layer, and a U-GaN layer. Preferably, the base layer 20 includes an AlN layer provided on the conductive substrate, an AlGaN layer provided between the AlN layer and the U-GaN layer, and a U-GaN layer.

The shape of the base layer 20 is circular, square, triangular or irregular, but is not limited thereto.

The light-emitting column 40 of the present invention is a column-shaped light-emitting structure, which can realize 360 degrees light emission, and the light-emitting angle can reach 180 degrees. The light emitting pillar 40 includes a first semiconductor layer 41 disposed on the base layer 20, an active layer 42 wrapping the first semiconductor layer 41, and a second semiconductor layer 43 wrapping the active layer 42.

In order to ensure that the first semiconductor layer 41 can be etched to form a layer-column structure and not affect the pairing of electrons and holes between the first semiconductor layer 41 and the second semiconductor layer 43, the thickness of the first semiconductor layer 41 is 2.5-3 μm. If the thickness of the first semiconductor layer 41 is too small, it is not easy to form a columnar structure wrapped by the active layer 42; if the thickness of the first semiconductor layer 41 is too large, the pair of electrons and holes is unbalanced, which affects the generation of photons.

Unlike the conventional light emitting structure, the active layer 42 of the present invention is not only disposed on the front surface of the first semiconductor layer 41, but also wraps the sidewall of the first semiconductor layer 41, so that the light emitting pillar 40 of the present invention can realize 3D light emission.

In addition, a plurality of light emitting columns 40 are arranged on the conductive substrate 10, and the L ED display screen with smaller and higher pixels can be obtained by adjusting the distance between the light emitting columns 40, and further, the light emitting columns 40 can enlarge the light emitting angle of the chip to be omnibearing, can emit light from the original 2D, and can be improved to 3D, and further improve the pixels.

The shape of the light emitting cylinder 40 is a cylinder, a cone or a polygonal cylinder, but is not limited thereto.

The transparent conductive layer 50 of the present invention covers the light emitting pillars 40 and the barrier layer 30 to electrically connect the plurality of light emitting pillars 40. Preferably, the transparent conductive layer 50 is an ITO layer, and has a thickness of 100 to 200 nm.

Since the present invention integrates a plurality of light emitting pillars 40 on the same conductive substrate 10, wherein the light emitting pillars 40 have a small interval therebetween, and contaminants such as dust and debris are easily adhered to the light emitting pillars 40, thereby causing a short circuit of a chip, etc., in order to protect the light emitting pillars 40, a protective layer 60 is disposed on the transparent conductive layer 40 except for the second electrodes 72, and the protective layer 60 is made of an insulating material. Preferably, the protective layer 60 is made of SiO₂Or Al₂O₃The thickness of the material is 100-300 nm.

The first electrode 71 is disposed on the back surface of the conductive substrate 10, the second electrode 72 is disposed on the transparent conductive layer 50, and the first electrode 71 and the second electrode 72 are disposed on the upper and lower sides of the conductive substrate 10, so as to electrically connect the conductive substrate 10 and the plurality of light-emitting pillars 40 on the conductive substrate 10.

The first electrode 71 is Al/Ti/Pt/Au, and has a thickness of 100-200nm/50-80nm/50-100nm/200-3000 nm. The first electrode 71 has Al as an adhesion layer, and if the thickness is less than 100nm, the thickness is too thin and poor adhesion, and if the thickness is more than 200nm, the first electrode is easy to migrate due to high temperature; ti is used as a barrier layer, if the thickness of the Ti is less than 50nm, the barrier effect is poor, and if the thickness of the Ti is more than 80nm, the voltage of the chip is increased; pt is used as a lamination barrier layer to prevent Al migration, if the thickness of the Pt is less than 50nm, the migration prevention effect is poor, and if the thickness of the Pt is more than 100nm, the thickness of the Pt is too thick, so that waste is caused; if the thickness of Au used as the conductive layer is less than 200nm, the thickness is too thin, which is not favorable for subsequent welding, and if the thickness is more than 3000nm, the thickness is too thick, which causes waste.

The second electrode 72 has a structure of Cr/Pt/Au, and a thickness of 3-50nm/50-100nm/200-3000 nm. Cr in the second electrode 72 serves as an ohmic contact layer, and is weak if its thickness is less than 3nm, and absorbs light if its thickness is more than 50 nm; pt is used as a barrier layer to prevent Cr from diffusing upwards, if the thickness of the barrier layer is less than 50nm, the effect of preventing diffusion cannot be achieved, and if the thickness of the barrier layer is more than 100nm, the thickness is too large, so that waste is caused; au is used as a conductive layer, if the thickness of the Au is less than 200nm, the thickness is too thin, which is not favorable for packaging and routing, and if the thickness of the Au is more than 3000nm, the thickness is too thick, which causes waste.

According to the invention, the characteristic of up-down electrical conduction of the conductive substrate is utilized, the plurality of light-emitting columns are arranged on the conductive substrate, the active layer of each light-emitting column wraps the first semiconductor layer, the second semiconductor layer wraps the active layer to form a columnar structure, 360-degree light emitting can be realized, and the light-emitting angle can reach 180 degrees.

According to the invention, by utilizing the characteristic of vertical electrical conduction of the conductive substrate, a plurality of light-emitting columns are arranged on the conductive substrate to form an array mode, and the integration of Micro L ED is realized by matching with the first electrode and the second electrode, so that the problem of mass transfer is solved.

According to the invention, the plurality of light-emitting columns are formed on the conductive substrate, the problem of substrate peeling by laser is solved by utilizing the characteristic of up-down electrical conduction of the conductive substrate, the plurality of light-emitting columns are connected together to form conductive connection by the transparent conductive layer, only one second electrode needs to be formed on the transparent conductive layer, and one first electrode is formed on the back surface of the conductive substrate, so that the number of electrodes is effectively reduced, and the cost is reduced.

Correspondingly, the invention also provides a manufacturing method of the 3D integrated Micro L ED, which is characterized by comprising the following steps:

firstly, forming a base layer and a first semiconductor layer on the front surface of a conductive substrate;

in order to ensure the effect of electrical conduction up and down of the conductive substrate and omit the step of peeling the substrate by laser, the conductive substrate of the invention is made of conductive material. In addition, in order to prevent light leakage and improve the light extraction efficiency of the chip, the conductive substrate of the invention is made of a non-light-tight material. Preferably, the conductive substrate is made of silicon.

Preferably, the thickness of the conductive substrate is 80-150 μm. Preferably, the thickness of the conductive substrate is 80-120 μm. If the thickness of the conductive substrate is less than 80 μm, the conductive substrate is too thin and is easy to crack, and the conductive substrate does not play a role in supporting and connecting; if the thickness is more than 150 μm, the voltage of the chip increases.

The conductive substrate of the present invention may be a 2-inch silicon substrate, a 4-inch silicon substrate, or a 6-inch silicon substrate, but is not limited thereto.

The difference between the materials of the first semiconductor layer and the conductive substrate is large, so that large lattice mismatch exists between the first semiconductor layer and the conductive substrate, and in order to ensure that the light-emitting column can be integrated on the conductive substrate, the base layer is arranged between the front surface of the conductive substrate and the light-emitting column, so that the effect of reducing the lattice mismatch is achieved.

The base layer of the present invention may have a single-layer structure or a stacked-layer structure. When the base layer is a stacked structure, the effect of reducing the lattice mismatch is better, but if the thickness of the stacked structure is too thick, the effect is rather reduced. Preferably, the thickness of the substrate layer is 1.5-2 μm. Correspondingly, the thickness of the barrier layer is 2-3 mu m.

The material of the base layer is between the conductive substrate and the light emitting pillar, and preferably, the base layer comprises one or more of an AlN layer, an AlGaN layer and a U-GaN layer. Preferably, the substrate layer comprises an AlN layer, an AlGaN layer and a U-GaN layer, the AlN layer is arranged on the conductive substrate, and the AlGaN layer is arranged between the AlN layer and the U-GaN layer.

In order to ensure that the first semiconductor layer can be etched to form a layer columnar structure and not influence pairing of electrons and holes between the first semiconductor layer and the second semiconductor layer, the thickness of the first semiconductor layer is 2.5-3 mu m. If the thickness of the first semiconductor layer is too small, the columnar structure is not easy to form and is wrapped by the active layer; if the thickness of the first semiconductor layer is too large, the pairing of electrons and holes is unbalanced, which affects the generation of photons.

Etching the first semiconductor layer and the substrate layer to the surface of the conductive substrate to form a plurality of columnar structures;

specifically, the first semiconductor layer and the substrate layer are etched by a yellow light patterning and ICP etching method.

In order to facilitate the active layer to wrap the first semiconductor layer, the invention needs to perform two times of etching. The first etching is rough etching, the first semiconductor layer and the substrate layer are etched until the surface of the conductive substrate is etched, and a plurality of columnar structures are formed; and the second etching is fine etching, only the first semiconductor layer is etched until reaching the surface of the substrate layer, so that the first semiconductor layer forms a columnar structure, and the cross section area of the first semiconductor layer is smaller than that of the substrate layer.

Because the material of the base layer is similar to that of the first semiconductor layer, the base layer and the first semiconductor layer can be etched simultaneously by adopting the same etching process after the base layer and the first semiconductor layer are formed on the conductive substrate, so that the operation is simpler, the efficiency is higher, and the etching effect is better.

The invention separates two times for etching, and can form a first semiconductor layer with area smaller than that of the substrate layer, so that the active layer can wrap the first semiconductor layer. In addition, the first semiconductor layer with the required shape can be independently etched according to the requirement, and the etching precision is higher. Furthermore, the first semiconductor layer is etched by adopting a twice etching method, so that the distance between the first semiconductor layers can be ensured to be 3-50 mu m.

Since the light emitting pillars of the present invention are formed on the base layer, the area of the base layer is equal to or larger than that of the first semiconductor layer. Preferably, the shape of the substrate layer is circular, square, triangular or irregular, but not limited thereto.

Thirdly, forming a barrier layer on the front surface of the exposed conductive substrate;

specifically, a barrier layer is formed on the front surface of the exposed conductive substrate by adopting a PECVD deposition or magnetron sputtering method. The barrier layer is arranged between the base layers to isolate the base layers and prevent light leakage from the side surfaces of the base layers, so that the barrier layer is made of opaque insulating materials, and the height of the barrier layer is larger than or equal to that of the base layers. Preferably, the material of the barrier layer is silicon nitride or indium nitride, and the thickness of the barrier layer is 2-3 μm.

Forming an active layer and a second semiconductor layer on the first semiconductor layer in sequence to form a light emitting column;

the active layer wraps the first semiconductor layer, and the second semiconductor layer wraps the active layer to form a light emitting column. The light-emitting column body is a column-shaped light-emitting structure, can realize light emission at 360 degrees, and has a light-emitting angle of 180 degrees.

Different from the existing light-emitting structure, the active layer is not only arranged on the front surface of the first semiconductor layer, but also wraps the side wall of the first semiconductor layer, so that the chip can realize 3D light emission.

In addition, the light-emitting columns are arranged on the conductive substrate, and the L ED display screen with smaller and higher pixels can be obtained by adjusting the distance between the light-emitting columns.

The shape of the light emitting cylinder is a cylinder, a cone or a polygonal cylinder, but is not limited thereto.

Because the first semiconductor layer needs to be etched to form the columnar structure, the crystal lattice of the etched first semiconductor layer can be changed, and if the active layer is directly formed on the etched first semiconductor layer, the whole luminous column can easily generate electric leakage due to mismatching of the crystals. Therefore, after the etching of the first semiconductor layer is completed and before the active layer is formed, namely between the step (three) and the step (four), the method further comprises the following steps: and forming a new first semiconductor layer with a preset thickness on the etched first semiconductor layer, so that the thickness of the whole first semiconductor layer is the thickness of the first semiconductor layer before etching.

In the present invention, the first semiconductor layer is an N-GaN layer, the active layer is a multi-quantum well layer, and the second semiconductor layer is a P-GaN layer, but the present invention is not limited thereto.

Fifthly, forming a transparent conducting layer on the light emitting columns and the barrier layer, and enabling the plurality of light emitting columns to be in conducting connection;

specifically, a transparent conductive layer is formed on the light emitting pillars and the barrier layer by evaporation or sputtering. The transparent conductive layer of the present invention is an ITO layer, but is not limited thereto. Preferably, the thickness of the transparent conducting layer is 100-200 nm.

Sixthly, forming a first electrode on the back surface of the conductive substrate, and forming a second electrode on the transparent conductive layer;

specifically, a first electrode is formed on the back surface of the conductive substrate by vapor deposition or sputtering, and a second electrode is formed on the transparent conductive layer.

According to the invention, the first electrode is arranged on the back surface of the conductive substrate, the second electrode is arranged on the transparent conductive layer, and the first electrode and the second electrode are arranged on the upper side and the lower side of the conductive substrate, so that the upper and lower electrical conduction of the conductive substrate is realized, and the plurality of luminous columns on the conductive substrate are in conductive connection.

The first electrode has a structure of Al/Ti/Pt/Au, and has a thickness of 100-200nm/50-80nm/50-100nm/200-3000 nm. The Al in the first electrode is used as an adhesion layer, if the thickness of the Al is less than 100nm, the Al is too thin and is not good in adhesion, and if the thickness of the Al is more than 200nm, the Al is easy to migrate due to high temperature; ti is used as a barrier layer, if the thickness of the Ti is less than 50nm, the barrier effect is poor, and if the thickness of the Ti is more than 80nm, the voltage of the chip is increased; pt is used as a lamination barrier layer to prevent Al migration, if the thickness of the Pt is less than 50nm, the migration prevention effect is poor, and if the thickness of the Pt is more than 100nm, the thickness of the Pt is too thick, so that waste is caused; if the thickness of Au used as the conductive layer is less than 200nm, the thickness is too thin, which is not favorable for subsequent welding, and if the thickness is more than 3000nm, the thickness is too thick, which causes waste.

The second electrode has a structure of Cr/Pt/Au, and the thickness of the second electrode is 3-50nm/50-100nm/200-3000 nm. The Cr in the second electrode is used as an ohmic contact layer, if the thickness of the Cr is less than 3nm, the Cr is not firmly adhered, and if the thickness of the Cr is more than 50nm, the Cr absorbs light; pt is used as a barrier layer to prevent Cr from diffusing upwards, if the thickness of the barrier layer is less than 50nm, the effect of preventing diffusion cannot be achieved, and if the thickness of the barrier layer is more than 100nm, the thickness is too large, so that waste is caused; au is used as a conductive layer, if the thickness of the Au is less than 200nm, the thickness is too thin, which is not favorable for packaging and routing, and if the thickness of the Au is more than 3000nm, the thickness is too thick, which causes waste.

Forming a protective layer on the transparent conductive layer except the second electrode;

and forming a protective layer on the transparent conductive layer outside the second electrode by adopting a PECVD deposition method. Because the plurality of light-emitting columns are integrated on the same conductive substrate, the light-emitting columns are less in interval, and pollutants such as dust, debris and the like are easily adhered to the light-emitting columns, so that the chip is short-circuited and the like. Preferably, the protective layer is made of SiO₂Or Al₂O₃The thickness of the material is 100-300 nm.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.