阅读说明：本技术 半导体存储装置及其数据读出方法 (Semiconductor memory device and data reading method thereof ) 是由 犬塚雄贵 中里高明 于 2019-01-08 设计创作，主要内容包括：实施方式提供一种使存储容量增加的半导体存储装置及其数据读出方法。实施方式的半导体存储装置具备存储单元,该存储单元具有：第1电阻变化元件,能够在第1状态与电阻值比所述第1状态高的第2状态之间变化；及第2电阻变化元件,与所述第1电阻变化元件串联连接,能够在第3状态与电阻值比所述第3状态高的第4状态之间变化。所述存储单元在第1阈值电流及第1阈值电压下,发生第1急速折回,在大于所述第1阈值电流的第2阈值电流、及大于所述第1阈值电压的第2阈值电压下,发生第2急速折回。(Embodiments provide a semiconductor memory device having an increased memory capacity and a data reading method thereof. A semiconductor memory device according to an embodiment includes a memory cell including: a 1 st variable resistance element which is variable between a 1 st state and a 2 nd state having a higher resistance value than the 1 st state; and a 2 nd variable resistance element connected in series with the 1 st variable resistance element and being capable of changing between a 3 rd state and a 4 th state having a higher resistance value than the 3 rd state. The memory cell produces a 1 st snapback at a 1 st threshold current and a 1 st threshold voltage, and produces a 2 nd snapback at a 2 nd threshold current larger than the 1 st threshold current and a 2 nd threshold voltage larger than the 1 st threshold voltage.)

1. A semiconductor memory device includes a memory cell,

the memory cell has:

a 1 st variable resistance element which is variable between a 1 st state and a 2 nd state having a higher resistance value than the 1 st state; and

a 2 nd variable resistance element connected in series with the 1 st variable resistance element and being variable between a 3 rd state and a 4 th state having a higher resistance value than the 3 rd state; and is

The memory cell

The 1 st snapback occurs at the 1 st threshold current and the 1 st threshold voltage,

the 2 nd snapback occurs at a 2 nd threshold current larger than the 1 st threshold current and a 2 nd threshold voltage larger than the 1 st threshold voltage.

2. The semiconductor memory device according to claim 1, wherein

A voltage across the memory cell when a 1 st current smaller than the 1 st threshold current flows through the memory cell is a 1 st voltage when the 1 st variable resistance element is in the 1 st state, and a 2 nd voltage larger than the 1 st voltage and smaller than the 1 st threshold voltage when the 1 st variable resistance element is in the 2 nd state; and is

A voltage across both ends of the memory cell when a 2 nd current larger than the 1 st threshold current and smaller than the 2 nd threshold current flows through the memory cell is a 3 rd voltage when the 2 nd variable resistance element is in the 3 rd state, and a 4 th voltage larger than the 3 rd voltage and smaller than the 2 nd threshold voltage when the 2 nd variable resistance element is in the 4 th state.

3. The semiconductor storage device according to claim 1 or 2, wherein

The 1 st and 2 nd variable resistance elements include 1 st and 2 nd variable resistance films provided along a lamination direction, and

the memory cell includes the 1 st and 2 nd variable resistance films and a selector layer provided along a lamination direction.

4. A data reading method of a semiconductor memory device according to claim 2,

detecting a 1 st read current flowing through the memory cell when a 1 st read voltage is applied to the memory cell, the 1 st read voltage being greater than a voltage across both ends of the memory cell when the 1 st threshold current flows in the 1 st state of the 1 st variable resistance element and being less than the 1 st threshold voltage; and is

Determining that the 1 st resistance change element is in the 1 st state while the 1 st sense voltage is still applied to the memory cell when the 1 st sense current is greater than the 1 st reference current, comparing the 1 st sense current with a 2 nd reference current that is greater than the 1 st reference current, determining that the 2 nd resistance change element is in the 3 rd state when the 1 st sense current is greater than the 2 nd reference current, and determining that the 2 nd resistance change element is in the 4 th state when the 1 st sense current is equal to or less than the 2 nd reference current;

when the 1 st sense current is equal to or less than the 1 st reference current, the 1 st variable resistance element is determined to be in the 2 nd state, a 2 nd sense voltage that is greater than the 1 st threshold voltage and less than the 2 nd threshold voltage is applied to the memory cell, a 2 nd sense current flowing in the memory cell is detected, when the 2 nd sense current is greater than the 2 nd reference current, the 2 nd variable resistance element is determined to be in the 3 rd state, and when the 2 nd sense current is equal to or less than the 2 nd reference current, the 2 nd variable resistance element is determined to be in the 4 th state.

5. A data reading method of a semiconductor memory device according to claim 2,

detecting a 1 st read voltage appearing across the memory cell when a 1 st reference current smaller than the 1 st threshold current flows through the memory cell, determining that the 1 st resistance change element is in the 1 st state when the 1 st read voltage is a 5 th voltage, and determining that the 1 st resistance change element is in the 2 nd state when the 1 st read voltage is a 6 th voltage larger than the 5 th voltage,

detecting a 2 nd read voltage appearing across the memory cell when a 2 nd reference current larger than the 1 st threshold current and smaller than the 2 nd threshold current flows through the memory cell, determining that the 2 nd variable resistance element is in the 3 rd state when the 2 nd read voltage is a 7 th voltage, and determining that the 2 nd variable resistance element is in the 4 th state when the 2 nd read voltage is an 8 th voltage larger than the 7 th voltage.

Technical Field

Background

As a semiconductor Memory device for storing large-capacity data, for example, a variable resistance semiconductor Memory device is known in which information is stored by changing the resistance value of a Memory cell, such as a Phase Change Memory (PCM). Among these, a semiconductor memory device is known in which a plurality of resistance variable films are used for 1 memory cell to store multi-bit data in order to further increase the memory capacity.

Disclosure of Invention

Drawings

Fig. 1 is a block diagram of a semiconductor memory device according to embodiment 1.

Fig. 2 is a circuit diagram showing a configuration of a memory cell array of the semiconductor memory device.

Fig. 3 is a perspective view showing the structure of the memory cell array.

Fig. 4(a) and (b) are cross-sectional views showing the structure of a memory cell of the semiconductor memory device.

Fig. 5 is a graph showing current-voltage characteristics of the memory cell.

Fig. 6 is a graph showing a relationship between data stored in the memory cell and current-voltage characteristics.

Fig. 7 is a flowchart showing the data reading operation.

Fig. 8(a) and (b) are waveform diagrams showing voltages applied to the memory cell and the reference current in the read operation.

Fig. 9 is a diagram showing a relationship between the reading operation and the current-voltage characteristic.

Fig. 10 is a circuit diagram showing a read circuit that can be used in the read operation.

Fig. 11a, (a) and (b) are current waveform diagrams showing a data writing operation of the semiconductor memory device.

Fig. 11b, (c) and (d) are current waveform diagrams showing a data writing operation of the semiconductor memory device.

Fig. 12 is a cross-sectional view showing the structure of a memory cell of the semiconductor memory device according to embodiment 2.

Fig. 13 is a graph showing current-voltage characteristics of the memory cell.

Fig. 14(a) to (g) are diagrams showing the relationship between the data stored in the memory cell and the current-voltage characteristics.

Fig. 15 is a circuit diagram showing a TCAM (Ternary content addressable Memory) cell of the semiconductor Memory device according to embodiment 3.

Fig. 16 is a graph showing current-voltage characteristics of a memory cell of the semiconductor memory device.

Fig. 17 is a diagram showing data stored in the memory cell.

Fig. 18 is a diagram showing an operation of the TCAM unit.

Fig. 19 is a circuit diagram of the semiconductor memory device.

Embodiments relate to a semiconductor memory device and a data reading method thereof.