阅读说明：本技术 存储装置及其操作方法 (Storage device and operation method thereof ) 是由 黄智训 于 2021-02-09 设计创作，主要内容包括：本技术涉及一种电子装置。根据本技术的存储装置包括多个存储器装置和存储器控制器。多个存储器装置中的每一个包括多个存储块。存储器控制器检测多个存储器装置之中的缺陷存储器装置,并且将该缺陷存储器装置中包括的正常块分配到用于对多个存储器装置执行后台操作的超量配置区域。(The present technology relates to an electronic device. A memory device according to the present technology includes a plurality of memory devices and a memory controller. Each of the plurality of memory devices includes a plurality of memory blocks. The memory controller detects a defective memory device among the plurality of memory devices and allocates a normal block included in the defective memory device to an over-provisioning area for performing a background operation on the plurality of memory devices.)

1. A memory device, comprising:

a plurality of memory devices, each of the plurality of memory devices comprising a plurality of memory blocks; and

a memory controller detecting a defective memory device among the plurality of memory devices and allocating a normal block included in the defective memory device to an over-provisioning area for performing a background operation on the plurality of memory devices.

2. The storage device of claim 1, wherein the memory controller comprises:

a storage area manager that allocates a normal block included in each of the plurality of memory devices to a user area storing user data or the over-provisioning area, and detects the defective memory device satisfying a defect condition among the plurality of memory devices; and

a background controller to perform the background operation on the plurality of memory devices using the normal block included in the defective memory device.

3. The storage device of claim 2, wherein the storage area manager comprises:

a block information storage device that stores block information on the plurality of storage blocks included in each of the plurality of memory devices;

a bad block detector that detects a bad block among the plurality of memory blocks included in each of the plurality of memory devices and updates the block information based on a result of detecting the bad block; and

a storage area setting component that detects the defective memory device among the plurality of memory devices based on the block information.

4. The storage device of claim 3, wherein the block information includes status information indicating whether a storage block is a normal block or a bad block and allocation information indicating whether the storage block is allocated to the user area or the over-allocated area.

5. The storage device according to claim 4, wherein when the defective memory device is detected, the storage area setting component updates allocation information corresponding to the normal block included in the defective memory device so that the normal block included in the defective memory device is allocated to the over-provisioning area.

6. The storage device according to claim 3, wherein the bad block detector detects an error uncorrectable block as the bad block when the error uncorrectable block occurs while various operations are performed on the plurality of storage blocks.

7. The storage device of claim 2, wherein the background controller performs a backup operation of storing user data stored in the normal block included in the defective memory device in a normal memory device other than the defective memory device among the plurality of memory devices.

8. The storage device of claim 2, wherein the defect condition is that a number of bad blocks included in the memory device is equal to or greater than a reference number.

9. The memory device of claim 2, wherein each of the plurality of memory devices comprises at least one plane, and

The defect condition is that the number of bad blocks included in any one of the at least one plane included in the memory device is equal to or greater than a reference number.

10. The storage device of claim 2, wherein each of the plurality of memory devices comprises at least one super block and a plurality of planes, and

the defect condition is that a number of bad blocks in any one of the at least one super block in the memory device is equal to or greater than a reference number, the super block including a plurality of memory blocks arranged in different planes of the memory device.

11. The memory device of claim 2, wherein the defect condition is determined based on a reference number, and the reference number is preset in a manufacturing stage of the memory device.

12. The storage device according to claim 11, wherein the reference number is updated according to a request of a host or a degree to which a lifetime of the storage device elapses.

13. A method of operating a storage device, the storage device comprising a plurality of memory devices, each of the plurality of memory devices comprising a plurality of memory blocks, the method comprising:

Detecting a defective memory device satisfying a defect condition among the plurality of memory devices, and

allocating normal blocks included in the defective memory device to an over-provisioning region for performing background operations on the plurality of memory devices.

14. The method of claim 13, wherein detecting the defective memory device comprises:

detecting a bad block among the plurality of memory blocks included in each of the plurality of memory devices;

updating block information on the plurality of memory blocks included in each of the plurality of memory devices based on a result of detecting the bad block; and is

Detecting the defective memory device among the plurality of memory devices based on the block information about the plurality of memory blocks.

15. The method of claim 14, wherein the block information includes status information indicating whether a memory block is a normal block or a bad block and allocation information indicating whether the memory block is allocated to a user area or the over-provisioned area, the user area storing user data.

16. The method of claim 15, wherein the allocating comprises updating allocation information corresponding to the normal blocks included in the defective memory device.

17. The method of claim 13, further comprising:

performing a backup operation of storing user data stored in the normal block included in the defective memory device in a normal memory device other than the defective memory device among the plurality of memory devices.

18. The method of claim 13, wherein the defect condition is a number of bad blocks included in a memory device equal to or greater than a reference number.

19. The method of claim 13, wherein each of the plurality of memory devices comprises at least one plane, and

the defect condition is that the number of bad blocks included in any one of the at least one plane included in the memory device is equal to or greater than a reference number.

20. The method of claim 13, wherein the defect condition is determined based on a reference number, and the reference number is preset at a manufacturing stage of the storage device and updated according to a request of a host or a degree to which a life span of the storage device elapses.

Technical Field

Embodiments of the present disclosure relate to an electronic device, and more particularly, to a memory device and a method of operating the same.

Background

A storage device is a device that stores data under the control of a host device such as a computer, smart phone, or the like. The memory device may include a memory device to store data and a memory controller to control the memory device. The memory device may include a volatile memory device or a non-volatile memory device.

A volatile memory device is a device that stores data only when power is supplied and loses the stored data when the power supply is cut off. Volatile memory devices include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.

A nonvolatile memory device is a device that does not lose data even if power supply is cut off. Non-volatile memory devices can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), flash memory, and the like.

Disclosure of Invention

Embodiments of the present disclosure provide a memory device having improved memory region management performance and a method of operating the same.

A memory device according to an embodiment of the present disclosure includes a plurality of memory devices and a memory controller. Each of the plurality of memory devices includes a plurality of memory blocks. The memory controller detects a defective memory device among the plurality of memory devices and allocates a normal block included in the defective memory device to an over-provisioning (over-provisioning) area for performing a background operation on the plurality of memory devices.

A method of operating a storage device according to an embodiment of the present disclosure, the storage device including a plurality of memory devices, each of the plurality of memory devices including a plurality of memory blocks, the method including: a defective memory device satisfying a defect condition among the plurality of memory devices is detected, and a normal block included in the defective memory device is allocated to an over-provisioning area for performing a background operation on the plurality of memory devices.

In accordance with the present technique, a storage device having improved storage region management performance and a method of operating the same are provided.

Drawings

Fig. 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

Fig. 2 is a diagram illustrating the memory device of fig. 1.

Fig. 3 is a diagram illustrating the memory cell array of fig. 2.

Fig. 4 is a diagram illustrating a method of one memory controller controlling a plurality of memory devices.

FIG. 5 is a diagram illustrating a superblock, according to an embodiment.

Fig. 6 is a diagram illustrating a normal block of a defective memory device according to an embodiment.

FIG. 7 is a diagram illustrating the memory controller of FIG. 1, according to an embodiment.

Fig. 8 is a diagram illustrating the block information storage device of fig. 7.

Fig. 9 is a flowchart for describing an operation of a memory device according to an embodiment.

Fig. 10 is a flowchart for describing an operation of detecting a defective memory device according to the first embodiment.

Fig. 11 is a flowchart for describing an operation of detecting a defective memory device according to the second embodiment.

Fig. 12 is a flowchart showing an operation of detecting a defective memory device according to the third embodiment.

FIG. 13 is a diagram illustrating the memory controller of FIG. 1 according to another embodiment.

Fig. 14 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 15 is a block diagram illustrating a Solid State Drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 16 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

Detailed Description

The specific structural and functional descriptions of the embodiments according to the concepts disclosed in the present specification or application are presented only to describe the embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be embodied in various forms, and the description is not limited to the embodiments described in the specification or the application.

Fig. 1 is a diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

Referring to fig. 1, a memory device 50 may include a memory device 100 and a memory controller 200 for controlling operations of the memory device 100. The storage device 50 may be a device that stores data under the control of a host 300 such as: mobile phones, smart phones, MP3 players, laptop computers, desktop computers, game consoles, TVs, tablet PCs, or in-vehicle infotainment systems, etc.

The storage device 50 may be one of various types of storage devices according to a host interface as a communication method with the host 300. For example, the storage device 50 may be configured as any of various types of storage devices such as: SSD, multimedia cards in the form of MMC, eMMC, RS-MMC, micro MMC and the like, secure digital cards in the form of SD, mini SD, micro SD and the like, Universal Serial Bus (USB) storage devices, universal flash memory (UFS) devices, Personal Computer Memory Card International Association (PCMCIA) card type storage devices, Peripheral Component Interconnect (PCI) card type storage devices, PCI express (PCI-E) card type storage devices, Compact Flash (CF) cards, smart media cards, memory sticks and the like.

The storage device 50 may be manufactured as any of various types of packages such as: package On Package (POP), System In Package (SIP), System On Chip (SOC), multi-chip package (MCP), Chip On Board (COB), wafer level manufacturing package (WFP), wafer level package on stack (WSP), etc.

The memory device 100 may store data. The memory device 100 may operate under the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells storing data.

Each of the memory cells may be configured as a single-layer cell (SLC) storing 1-bit data, a multi-layer cell (MLC) storing 2-bit data, a triple-layer cell (TLC) storing 3-bit data, or a four-layer cell (QLC) storing 4-bit data.

The memory cell array may include a plurality of memory blocks. Each of the memory blocks may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading out data stored in the memory device 100.

The memory block may be a unit for erasing data stored in the memory device 100. In an embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4(LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, a low power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), phase change random access memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), spin transfer torque random access memory (STT-RAM), or the like. In this specification, for convenience of description, it is assumed that the memory device 100 is a NAND flash memory.

The memory device 100 is configured to receive a command and an address from the memory controller 200 and access a target area in the memory cell array selected by the address. That is, the memory device 100 may perform the operation indicated by the command on the target area selected by the address. For example, the memory device 100 may perform a write operation (or program operation), a read operation, and an erase operation under the control of the memory controller 200. During a programming operation, the memory device 100 may program data to a target area selected by an address. During a read operation, the memory device 100 may read data from a target area selected by an address. During an erase operation, the memory device 100 may erase data stored in a target area selected by an address.

In an embodiment, the memory device 100 may include a user area and an over-provisioning area. The user area stores user data. The over-allocated area is a spare area for maintaining the performance of the storage device 50. The user area may be used as a space for storing user data received from the host pc 300. The over-provisioning region may be used as spare space for temporarily storing data to perform background operations such as wear leveling, garbage collection, read reclamation, and the like.

In an embodiment, a plurality of memory blocks included in the memory device 100 may be classified into normal blocks capable of storing data and unusable bad blocks. The normal blocks may be allocated to a user area or an over-provisioning area.

In an embodiment, a normal block included in a memory device detected as a defective memory device among the plurality of memory devices 100 controlled by the memory controller 200 may be allocated to the over-provisioning area.

The memory controller 200 controls the overall operation of the memory device 50.

When power is supplied to the storage device 50, the memory controller 200 may run the firmware FW. When the memory device 100 is a flash memory device, the memory controller 200 may operate firmware such as a Flash Translation Layer (FTL) to control communication between the host 300 and the memory device 100.

In an embodiment, the memory controller 200 may receive data and Logical Block Addresses (LBAs) from the host 300 and convert the Logical Block Addresses (LBAs) to Physical Block Addresses (PBAs) indicating memory units in the memory device 100 where the data is to be stored.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host 300. During a programming operation, the memory controller 200 may provide a write command, a physical block address, and write data to the memory device 100 in response to a write request received from the host 300. During a read operation, the memory controller 200 may provide a read command and a physical block address to the memory device 100 in response to a read request received from the host 300. During an erase operation, the memory controller 200 may provide an erase command and a physical block address to the memory device 100 in response to an erase request received from the host 300.

In an embodiment, the memory controller 200 may generate and transmit commands, addresses, and data to the memory device 100 regardless of whether there is a request received from the host 300. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as programming operations for wear leveling, programming operations for garbage collection, and so on.

In an embodiment, memory controller 200 may control multiple memory devices 100. In this case, the memory controller 200 may control the plurality of memory devices 100 according to the interleaving method to improve the operation performance. The interleaving method may be an operation method for overlapping operation periods of the plurality of memory devices 100.

In an embodiment, memory controller 200 may include a storage area manager 210 and a background controller 220. In an embodiment, memory or registers and one or more processors may be used to implement storage area manager 210 and background controller 220.

The memory area manager 210 may detect a defective memory device satisfying a defect condition among the plurality of memory devices 100. Whether the defect condition is satisfied may be determined based on a comparison result of the number of bad blocks included in the memory device and a reference number. The reference number may be preset at the manufacturing stage. The reference number may be updated or changed according to the request of the host 300 or the degree to which the life span of the storage device 50 has elapsed in the use stage.

In an embodiment, the memory region manager 210 may detect a defective memory device among the plurality of memory devices 100 in a test phase. At this time, the bad block may be determined based on a Manufactured Bad Block (MBB) manufactured in the manufacturing process.

In an embodiment, the memory region manager 210 may detect defective memory devices during a use phase of the plurality of memory devices 100. At this time, the bad block may be determined based on a Grown Bad Block (GBB) generated as the usage time of each of the plurality of memory devices 100 becomes longer and longer.

The storage area manager 210 may allocate normal blocks included in the plurality of memory devices 100 to a user area or an over-provisioning area. The ratio of allocating the normal block to the user area and the over-provisioning area may be determined differently.

In an embodiment, the memory area manager 210 may allocate a normal block included in the defective memory device to the over-provisioning area.

The background controller 220 may control the plurality of memory devices 100 to perform background operations. In an embodiment, the background controller 220 may perform a background operation on the plurality of memory devices 100 using normal blocks included in the defective memory device. For example, a normal block in a defective memory device is used to temporarily store data received from a normal memory device. The temporarily stored data is returned to the normal memory device.

In embodiments, background operations may include wear leveling, garbage collection, read reclamation, and the like.

In an embodiment, the background controller 220 may control a backup operation of storing user data stored in a normal block included in a defective memory device in a normal memory device other than the defective memory device among the plurality of memory devices 100. In an embodiment, after backing up user data stored in a normal block included in a defective memory device to the normal memory device, the normal block included in the defective memory device may be allocated to an over-provisioning area.

The host 300 may communicate with the storage device 50 using at least one of various communication methods such as: universal Serial Bus (USB), serial AT attachment (SATA), serial SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (pcie), non-volatile memory express (NVMe), universal flash memory (UFS), Secure Digital (SD), multimedia card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered DIMM (rdimm), low-load DIMM (lrdimm), and the like.

Fig. 2 is a diagram illustrating the memory device 100 of fig. 1 according to an embodiment of the present disclosure.

Referring to fig. 2, the memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

Memory cell array 110 includes a plurality of memory blocks BLK1 through BLKz. A plurality of memory blocks BLK1 through BLKz are connected to address decoder 121 through row lines RL. The plurality of memory blocks BLK1 through BLKz are connected to the read and write circuit 123 through bit lines BL1 through BLm. Each of the plurality of memory blocks BLK1 through BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells. A memory cell connected to the same word line among a plurality of memory cells is defined as one physical page. That is, the memory cell array 110 is configured by a plurality of physical pages.

According to an embodiment of the present disclosure, each of the plurality of memory blocks BLK1 through BLKz included in the memory cell array 110 may further include a plurality of dummy cells. In the cell string connected to the bit line, at least one dummy cell may be connected in series between the drain select transistor and the memory cell and between the source select transistor and the memory cell.

Each of the memory cells of the memory device 100 may be configured as a Single Layer Cell (SLC) storing one bit of data, a multi-layer cell (MLC) storing two bits of data, a Triple Layer Cell (TLC) storing three bits of data, or a Quadruple Layer Cell (QLC) storing four bits of data.

The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input/output circuit 124, and a sensing circuit 125.

The peripheral circuit 120 drives the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

Address decoder 121 is connected to memory cell array 110 by row lines RL. The row lines RL may include drain select lines, word lines, source select lines, and a common source line. According to an embodiment of the present disclosure, the word lines may include a normal word line coupled to the memory cell and a dummy word line coupled to the dummy cell. According to an embodiment of the present disclosure, the row line RL may further include a pipe select line.

Address decoder 121 is configured to operate under the control of control logic 130. The address decoder 121 receives a row address RADD from the control logic 130.

The address decoder 121 is configured to decode a block address of the received row address RADD. The address decoder 121 selects at least one memory block from among the memory blocks BLK1 through BLKz according to the decoded block address. The address decoder 121 may select at least one word line from among the word lines of the selected memory block according to a row address RADD. The address decoder 121 may apply the operating voltage Vop received from the voltage generator 122 to the selected word line.

During a program operation, the address decoder 121 may apply a program voltage to a selected word line and apply a pass voltage having a level less than that of the program voltage to unselected word lines among the word lines of the selected memory block. During a program verify operation, the address decoder 121 may apply a verify voltage to a selected word line and a verify pass voltage having a level greater than that of the verify voltage to unselected word lines.

During a read operation, the address decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage having a level greater than that of the read voltage to unselected word lines.

According to an embodiment of the present disclosure, the erase operation of the memory device 100 is performed in units of memory blocks. The address ADDR input to the memory device 100 during the erase operation includes a block address. The address decoder 121 may decode the block address and select at least one memory block according to the decoded block address. During an erase operation, the address decoder 121 may apply a ground voltage to word lines coupled to the selected memory block to delete data stored in the selected memory block.

According to an embodiment of the present disclosure, the address decoder 121 may be configured to further decode a column address of the address ADDR. The decoded column address may be transferred to the read and write circuit 123. For example, the address decoder 121 may include components such as a row decoder, a column decoder, an address buffer, or a combination thereof.

The voltage generator 122 is configured to generate a plurality of operating voltages Vop by using an external power supply voltage supplied to the memory device 100. The voltage generator 122 operates under the control of the control logic 130.

In an embodiment, the voltage generator 122 may generate the internal supply voltage by adjusting the external supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operation voltage of the memory device 100.

In an embodiment, the voltage generator 122 may generate the plurality of operating voltages using an external power supply voltage or an internal power supply voltage. The voltage generator 122 may be configured to generate various voltages required to perform various operations on the memory device 100. For example, the voltage generator 122 may generate one or more of a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, a plurality of non-select read voltages, and the like.

To generate the plurality of operating voltages Vop having various voltage levels, the voltage generator 122 may include a plurality of pumping capacitors receiving an external voltage or an internal voltage, and selectively enable the plurality of pumping capacitors under the control of the control logic 130 to generate the plurality of operating voltages Vop.

A plurality of operating voltages Vop may be supplied to the memory cell array 110 through the address decoder 121.

The read and write circuit 123 includes first to mth page buffers PB1 to PBm. The first to mth page buffers PB1 to PBm are connected to the memory cell array 110 through first to mth bit lines BL1 to BLm, respectively. The first to mth page buffers PB1 to PBm operate under the control of the control logic 130.

The first to mth page buffers PB1 to PBm communicate DATA with the DATA input/output circuit 124. During a program operation, the first to mth page buffers PB1 to PBm receive write DATA to be stored through the DATA input/output circuit 124 and the DATA lines DL.

During a program operation, when a program voltage is applied to a selected wordline, the first to mth page buffers PB1 to PBm may transfer write DATA received through the DATA input/output circuit 124 to a selected memory cell coupled to the selected wordline through the bit lines BL1 to BLm. The memory cells coupled to the selected word line, i.e., the memory cells of the selected page, are programmed according to the transferred write DATA. A memory cell connected to a bit line to which a program enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cell connected to the bit line to which the program-inhibit voltage (e.g., power supply voltage) is applied may be maintained without increasing. During a program verify operation, the first to mth page buffers PB1 to PBm read write DATA stored in the memory cells from the selected memory cells through the bit lines BL1 to BLm.

During a read operation, the read and write circuit 123 may read DATA from the memory cells of the selected page through the bit lines BL1 to BLm and store the read DATA in the first to mth page buffers PB1 to PBm.

During an erase operation, the read and write circuit 123 may float the bit lines BL1 through BLm. In an embodiment, the read and write circuits 123 may include column select circuits.

The data input/output circuit 124 is connected to the first to mth page buffers PB1 to PBm through the data lines DL. The data input/output circuit 124 operates under the control of control logic 130.

The DATA input/output circuit 124 may include a plurality of input/output buffers (not shown) that receive the DATA. During a programming operation, the DATA input/output circuit 124 receives write DATA to be stored from an external controller (not shown). During a read operation, the DATA input/output circuit 124 outputs read DATA transferred from the first to mth page buffers PB1 to PBm included in the read and write circuit 123 to an external controller.

During a read operation or a program verify operation, the sensing circuit 125 may generate a reference current in response to a signal of the enable bit VRYBIT generated by the control logic 130, and may compare the sensing voltage VPB received from the read and write circuit 123 with a reference voltage generated by the reference current and output a pass signal or a fail signal to the control logic 130 based on the comparison result.

The control logic 130 may be connected to the address decoder 121, the voltage generator 122, the read and write circuit 123, the data input/output circuit 124, and the sensing circuit 125. Control logic 130 may be configured to control the overall operation of memory device 100. The control logic 130 may operate in response to a command CMD transmitted from an external device.

Control logic 130 may generate various signals to control peripheral circuits 120 in response to commands CMD and addresses ADDR. For example, the control logic 130 may generate an operation signal OPSIG, a row address RADD, a read and write circuit control signal PBSIGNALS, and an enable bit VRYBIT in response to the command CMD and the address ADDR. The control logic 130 may output an operation signal OPSIG to the voltage generator 122, a row address RADD to the address decoder 121, read and write control signals PBSIGNALS to the read and write circuit 123, and an enable bit VRYBIT to the sense circuit 125. In addition, control logic 130 may determine whether the program verify operation passed or failed in response to PASS or FAIL signals PASS/FAIL output by sensing circuit 125.

Fig. 3 is a diagram illustrating the memory cell array 110 of fig. 2 according to an embodiment of the present disclosure.

Referring to fig. 3, the first to z-th memory blocks BLK1 to BLKz are commonly connected to the first to m-th bit lines BL1 to BLm. For convenience of description, fig. 3 illustrates a configuration of a first memory block BLK1 among a plurality of memory blocks BLK1 through BLKz. Each of the remaining memory blocks BLK2 through BLKz is configured similarly to the first memory block BLK 1.

The memory block BLK1 may include a plurality of cell strings CS1_1 to CS1_ m (m is a positive integer). The first to mth cell strings CS1_1 to CS1_ m are connected to the first to mth bit lines BL1 to BLm, respectively. Each of the first to mth cell strings CS1_1 to CS1_ m includes a drain select transistor DST, a plurality of memory cells MC1 to MCn (n is a positive integer) connected in series, and a source select transistor SST.

The gate terminals of the drain select transistors DST included in the first to mth cell strings CS1_1 to CS1_ m are commonly connected to the drain select line DSL 1. The gate terminals of the first to nth memory cells MC1 to MCn included in each of the first to mth cell strings CS1_1 to CS1_ m are connected to the first to nth word lines WL1 to WLn, respectively. The gate terminals of the source selection transistors SST included in the first to mth cell strings CS1_1 to CS1_ m are commonly connected to a source selection line SSL 1.

For convenience of description, the structure of the cell string will be described with reference to the first cell string CS1_1 of the plurality of cell strings CS1_1 to CS1_ m. However, it will be understood that each of the remaining cell strings CS1_2 to CS1_ m is configured similarly to the first cell string CS1_ 1.

In the first cell string CS1_1, the drain terminal of the drain select transistor DST is connected to the first bit line BL1, and the source terminal of the drain select transistor DST is connected to the drain terminal of the first memory cell MC 1. The first to nth memory cells MC1 to MCn are connected in series with each other. The drain terminal of the source selection transistor SST is connected to the source terminal of the nth memory cell MCn. The source terminal of the source selection transistor SST is connected to a common source line CSL. In an embodiment, the common source line CSL may be commonly connected to the first to z-th memory blocks BLK1 to BLKz.

The drain select line DSL1, the first to nth word lines WL1 to WLn, and the source select line SSL1 are included in the row line RL of fig. 2. The drain select line DSL1, the first to nth word lines WL1 to WLn, and the source select line SSL1 are controlled by the address decoder 121. The common source line CSL is controlled by control logic 130. The first to mth bit lines BL1 to BLm are controlled by the read and write circuit 123.

Fig. 4 is a diagram illustrating a method of one memory controller controlling a plurality of memory devices.

Referring to fig. 4, the memory controller 200 may be connected to a plurality of memory devices Die _11 to Die _14 through a first channel CH1, and to a plurality of memory devices Die _21 to Die _24 through a second channel CH 2. The number of channels or the number of memory devices connected to each channel is not limited to the present embodiment.

The memory devices Die _11 to Die _14 may be commonly connected to the first channel CH 1. The memory devices Die _11 to Die _14 can communicate with the memory controller 200 through the first channel CH 1.

Because the memory devices Die _11 through Die _14 are commonly connected to the first channel CH1, only one of the memory devices Die _11 through Die _14 may communicate with the memory controller 200 at a time. However, the internal operation of each of the memory devices Die _11 to Die _14 may be performed simultaneously.

The memory devices Die _21 to Die _24 may be commonly connected to the second channel CH 2. The memory devices Die _21 to Die _24 can communicate with the memory controller 200 through the second channel CH 2.

Because the memory devices Die _21 through Die _24 are commonly connected to the second channel CH2, only one of the memory devices Die _21 through Die _24 may communicate with the memory controller 200 at a time. However, the internal operation of each of the memory devices Die _21 to Die _24 may be performed simultaneously.

A memory device including a plurality of memory devices may improve performance by using a data interleaving method. The data interleaving method may include performing a data read operation or a data write operation by changing a lane on which the data read operation or the data write operation is performed in a structure in which two or more lanes share one channel. For the data interleaving method, the memory device may be managed in units of channels and ways. To maximize the parallelism of the memory devices connected to each channel, memory controller 200 may distribute contiguous logical memory regions discretely among the channels and ways.

In fig. 4, a plurality of memory devices may be configured by four WAYs WAY1 through WAY 4. The first path WAY1 may include memory devices Die _11 and Die _ 21. Second WAY2 may include memory devices Die _12 and Die _ 22. The third WAY3 may include memory devices Die _13 and Die _ 23. The fourth WAY4 may include memory devices Die _14 and Die _ 24.

Accordingly, the memory controller 200 may transmit a command, a control signal including an address, and data to the memory device Die _11 through the first channel CH 1. While memory device Die _11 programs the transferred data to the memory cells that memory device Die _11 includes, memory controller 200 may transfer commands, control signals including addresses, and data to memory device Die _12 because memory device Die _11 does not use CH1 during internal operations such as programming operations.

Each of the channels CH1 and CH2 may be signal buses shared and used by memory devices connected thereto.

Fig. 4 shows a two-lane/four-lane structure, and the data interleaving method has been described with reference to the two-lane/four-lane structure. However, as the number of channels and the number of lanes increase, data interleaving may be more efficient.

FIG. 5 is a diagram illustrating a superblock, according to an embodiment. The super block will be described with reference to the memory device Die _11 of fig. 4.

Referring to fig. 5, the memory device Die _11 may include first to fourth planes Plane 1 to Plane 4. The number of planes included in one memory device is not limited to the present embodiment. One plane may include a plurality of memory blocks BLK1 through BLKi (i is a positive integer).

The plane may be a unit in which a program operation, a read operation, or an erase operation is independently performed. Thus, for each plane, the memory device Die _11 may include the address decoder 121 and the read and write circuit 123 that have been described with reference to fig. 2.

In an embodiment, the super block may include at least two or more memory blocks included in different planes among the memory blocks included in the memory device.

Referring to fig. 5, the first super block SB1 may include a first memory block BLK1 of first to fourth planes Plane 1 to Plane 4. The second super block SB2 may include a second memory block BLK2 of the first to fourth planes Plane 1 to Plane 4. In the same manner, the ith super block SBi may include the ith memory block BLKi of the first to fourth planes Plane 1 to Plane 4. Accordingly, the memory device Die _11 may include the first to ith superblocks SB1 to SBi.

Each superblock may include multiple stripes (or superpages). A memory controller such as the memory controller 200 of fig. 4 may store data in the first to fourth planes Plane 1 to Plane 4 in units of stripes or in units of superpages and read the stored data.

Fig. 6 is a diagram illustrating a normal block of a defective memory device according to an embodiment.

Referring to fig. 6, the memory controller 200 described with reference to fig. 1 may control the plurality of memory devices Die _11 to Die _24 shown in fig. 4. The number of memory devices controlled by the memory controller 200 is not limited to the present embodiment.

In fig. 6, the memory device Die _14 may be a defective memory device satisfying a defective condition. The memory device Die _14 may include first to fourth planes Plane 1 to Plane 4. The number of planes included in the memory device Die _14 and the number of memory blocks included in one plane are not limited to the present embodiment.

In an embodiment, the defect condition may be satisfied when the number of bad blocks included in the memory device is equal to or greater than a reference number. In an embodiment, the reference number may be determined based on a reference ratio of the bad blocks to all the memory blocks in the reference area.

For example, referring to fig. 6, the memory device Die _14 may include (18 × 4 ═ 72) memory blocks, each plane including 18 memory blocks. The memory device Die _14 may include eight bad blocks B1 through B8.

Description will be made under the assumption that the reference ratio is 1/9 when the reference area is 1 memory device. The reference number may be 8, 1/9 of 72 memory blocks. Therefore, since the total number of bad blocks, i.e., 8, included in the memory device Die _14 is equal to the reference number, i.e., 8, the memory device Die _14 can be detected as a defective memory device.

In an embodiment, the defect condition may be satisfied when the number of bad blocks included in any one of one or more planes included in one memory device is equal to or greater than a reference number.

For example, as shown in fig. 6, each of the plurality of planes Plane 1 to Plane 4 may include 18 memory blocks. The first planar plate 1 may include two bad blocks B1 and B2. The second planar Plane 2 may include two bad blocks B3 and B4. The fourth Plane 4 may include four bad blocks B5, B6, B7, and B8.

Description will be made under the assumption that the reference ratio is 1/6 when the reference area is one plane. The reference number may be 3, 1/6 of a total of 18 memory blocks included in one plane. Accordingly, since the total number of bad blocks, i.e., 4, included in the fourth Plane 4 is greater than the reference number, i.e., 3, the memory device Die _14 can be detected as a defective memory device.

In an embodiment, the defect condition may be satisfied when the number of bad blocks included in any one of one or more super blocks included in one memory device is equal to or greater than a reference number.

As described with reference to fig. 5, one super block may include memory blocks disposed at the same position in each plane in the memory device. Thus, a super block may include four memory blocks. The description will be made under the assumption that the reference ratio is 1/2. The reference number may be 2, 1/2 for all 4 memory blocks included in a super block.

In fig. 6, each super block may include four memory blocks respectively included in the first to fourth planes Plane 1 to Plane 4. Memory device Die _14 includes a super block with two bad blocks B2 and B8 located at the same location in plane 1 and plane 4. Therefore, since the number of bad blocks, i.e., 2, is equal to the reference number, i.e., 2, the memory device Die _14 including the super block having the two bad blocks B2 and B8 can be detected as a defective memory device.

In an embodiment, the reference number or the reference ratio of the defect condition may be determined at a manufacturing stage of the memory device 50. In various embodiments, in the use phase described with reference to fig. 1, the reference number or the reference ratio of the defect condition may be updated according to the request of the host 300 or the degree to which the life span of the storage device 50 has elapsed. For example, since the probability of occurrence of bad blocks increases as the life span of the storage device 50 elapses, the reference number or the reference ratio may be increased accordingly.

Fig. 7 is a diagram illustrating the memory controller 200 of fig. 1, according to an embodiment. As shown in fig. 1, memory controller 200 includes a storage area manager 210 and a background controller 220.

Referring to fig. 7, a memory controller 200 may control a plurality of memory devices 100.

Each of the memory devices 100 may include a user area and an over-provisioning area. The user area stores user data, and the over-provisioning area is a spare area for maintaining the performance of the storage device 50. The user area may be used as a storage space for storing user data received from the host pc 300. The over-provisioned area may be used as spare storage space to temporarily store data to perform background operations such as wear leveling, garbage collection, or read reclamation.

A plurality of memory blocks included in the memory device 100 may be classified into normal blocks capable of storing data and unusable bad blocks. The normal blocks may be allocated to a user area or an over-provisioning area.

In an embodiment, the storage area manager 210 may include a block information storage 211, a bad block detector 212, and a storage area setting component 213.

The block information storage 211 may store block information regarding a plurality of memory blocks included in each of the plurality of memory devices 100.

The block information may include state information indicating whether each memory block is a normal block or a bad block, and allocation information indicating whether the normal block is allocated to the user area or the over-allocated area. In an embodiment, an initial value of the state information of each memory block may be set to indicate a normal block.

When an error uncorrectable block is detected while performing a full operation on each of a plurality of memory blocks included in each of the plurality of memory devices 100, the bad block detector 212 may determine the error uncorrectable block as a bad block. The full operation may include a read operation, a program operation, or an erase operation.

When an error uncorrectable block is detected, the bad block detector 212 may update block information corresponding to the error uncorrectable block among block information on a plurality of storage blocks stored in the block information storage 211. For example, the bad block detector 212 may update the block information such that the state information included in the block information corresponding to the error uncorrectable block is changed from an initial value to a value indicating a bad block.

The storage area setting component 213 may detect a defective memory device satisfying a defect condition from among the plurality of memory devices 100 based on the block information stored in the block information storage 211. When the number of bad blocks included in the reference area is equal to or greater than the reference number, a defect condition may be satisfied. For example, the reference area may be a memory device, a plane, or a super block. The reference region is not limited to the present embodiment and may be set differently.

In an embodiment, the reference number may be preset at a manufacturing stage. The reference number may be updated or changed according to the request of the host 300 or the degree to which the life span of the storage device 50 has elapsed at the use stage.

In an embodiment, the storage area setting component 213 may detect a defective memory device based on a result of comparing the number of bad blocks included in one memory device 100 with a first reference number. In another embodiment, the storage area setting component 213 may detect a defective memory device based on a result of comparing the number of bad blocks in any one of one or more planes included in one memory device 100 with a second reference number. In yet another embodiment, the storage area setting component 213 may detect a defective memory device based on a result of comparing the number of bad blocks in any one of one or more super blocks included in one memory device 100 with a third reference number.

As described with reference to fig. 6, the reference number may vary according to the range of the reference area for counting the number of bad blocks. In an embodiment, the reference number may be determined based on a reference ratio of the bad blocks included in the reference area to all the memory blocks. In an embodiment, the bad block may be determined based on at least one of a Manufactured Bad Block (MBB) and a Grown Bad Block (GBB).

In an embodiment, the storage area setting component 213 can detect defective memory devices at a testing stage of multiple memory devices 100. In another embodiment, the storage area setting component 213 can detect defective memory devices at the stage of use of the plurality of memory devices 100.

The storage area setting component 213 may allocate normal blocks included in the plurality of memory devices 100 to a user area or an over-provisioning area. For example, the storage area setting component 213 may update the allocation information corresponding to the normal block stored in the block information storage 211 according to whether the normal block is allocated to the user area or the over-allocated area.

In an embodiment, the storage area setting component 213 may allocate a normal block included in the defective memory device to the over-allocated area. For example, the storage area setting component 213 may update block information corresponding to a normal block included in the defective memory device among the block information on the plurality of storage blocks stored in the block information storage 211. The storage area setting component 213 may update the block information such that allocation information included in the block information corresponding to the normal block included in the defective memory device indicates the over-allocated area.

The background controller 220 may control the plurality of memory devices 100 to perform background operations to preserve the performance of the storage device 50. In an embodiment, the background controller 220 may control the defective memory device to perform a background operation using normal blocks included in the defective memory device. For example, background operations may include wear leveling, garbage collection, read reclamation, and the like.

In an embodiment, the background controller 220 may control a backup operation for storing user data stored in a normal block included in a defective memory device in a normal memory device other than the defective memory device among the plurality of memory devices 100. In an embodiment, after backing up user data stored in a normal block included in a defective memory device to the normal memory device, the normal block included in the defective memory device may be allocated to an over-provisioning area.

Fig. 8 is a diagram illustrating the block information storage 211 of fig. 7 according to an embodiment.

Referring to fig. 8, the block information storage 211 may store block information about a plurality of memory devices 100.

The block information may include state information indicating whether each memory block is a normal block or a bad block, and allocation information indicating whether the normal block is allocated to the user area or the over-allocated area. In an embodiment, an initial value of the state information may be set to indicate a normal block.

In an embodiment, the block information may be managed in units of memory devices. In another embodiment, the block information may be managed in units of planes in one memory device. In yet another embodiment, the block information may be managed in units of super blocks in one memory device.

In fig. 8, the state information of the first memory block BLK1 may indicate a bad block. The state information of the second storage block BLK2 may indicate a normal block, and the allocation information of the second storage block BLK2 may indicate a user area. The state information of the third memory block BLK3 may indicate a normal block, and the allocation information of the third memory block BLK3 may indicate an over-allocated area.

In various embodiments, the block information may include one or more of address information, program/erase count information, read count information, capacity information, etc. of the memory block, in addition to the state information and allocation information.

Fig. 9 is a flowchart for describing an operation of a memory device according to an embodiment. The memory device of fig. 9 may correspond to the memory device 50 shown in fig. 1 and 7. The operation shown in fig. 9 will be described with reference to the memory device 50 shown in fig. 7.

Referring to fig. 9, in step S901, the storage device 50 may detect a bad block. Specifically, the bad block detector 212 of the memory device 50 may detect a bad block among a plurality of memory blocks included in each of the plurality of memory devices 100. The bad block may be a memory block in which an uncorrectable error occurs while performing a full operation on each of the plurality of memory blocks. The full operation may include a read operation, a program operation, or an erase operation.

In step S903, the storage area setting component 213 of the storage device 50 may determine whether the memory device including the bad block satisfies a defect condition to determine whether the memory device is a defective memory device. As a result of the determination, when the memory device satisfies the defect condition, that is, when it is determined that the memory device is a defective memory device, the operation proceeds to step S905, and when the memory device does not satisfy the defect condition, the operation ends.

As described with reference to fig. 6, in an embodiment, the defect condition may be satisfied when the number of bad blocks included in the memory device is equal to or greater than the first reference number. In another embodiment, the defect condition may be satisfied when the number of bad blocks in any one of the one or more planes included in the memory device is equal to or greater than a second reference number. In still another embodiment, the defect condition may be satisfied when the number of bad blocks in any one of the one or more super blocks included in the memory device is equal to or greater than a third reference number.

In an embodiment, each of the first to third reference numbers may be determined based on a reference ratio of the bad blocks included in the reference area to all the memory blocks.

In an embodiment, the first to third reference numbers may be preset in a manufacturing stage. The first to third reference numbers may be updated or changed according to a request of the host 300 or a degree of the life span of the storage device 50 in the use stage.

In an embodiment, the bad block may be determined based on at least one of a Manufactured Bad Block (MBB) and a Grown Bad Block (GBB).

In step S905, the background controller 220 of the storage device 50 may perform a backup operation for storing data stored in a normal block included in the defective memory device in another normal memory device. The memory device 50 may not perform a backup operation when a defective memory device is detected in a test phase of the memory device 100.

In step S907, the storage area setting component 213 of the storage device 50 may allocate the normal blocks included in the defective memory device to the over-allocated area.

Fig. 10 is a flowchart for describing an operation of detecting a defective memory device according to the first embodiment.

Referring to fig. 10, in step S1001, the storage device 50 may determine whether the number of bad blocks included in the memory device is equal to or greater than a first reference number. As a result of the determination, when the number of bad blocks is equal to or greater than the first reference number, the operation proceeds to step S1003, and when the number of bad blocks is less than the first reference number, the operation ends.

In step S1003, the memory device 50 may determine the memory device as a defective memory device.

Fig. 11 is a flowchart for describing an operation of detecting a defective memory device according to the second embodiment.

Referring to fig. 11, in step S1101, the storage device 50 may determine whether the number of bad blocks in any one of one or more planes included in the memory device is equal to or greater than a second reference number. As a result of the determination, when the number of bad blocks is equal to or greater than the second reference number, the operation proceeds to step S1103, and when the number of bad blocks is less than the second reference number, the operation ends.

In step S1103, the memory device may determine a memory device including the corresponding plane as a defective memory device.

Fig. 12 is a flowchart showing an operation of detecting a defective memory device according to the third embodiment.

Referring to fig. 12, the storage device 50 may determine whether the number of bad blocks included in any one of one or more super blocks included in the memory device is equal to or greater than a third reference number in step S1201. As a result of the determination, when the number of bad blocks is equal to or larger than the third reference number, the operation proceeds to step S1203, and when the number of bad blocks is smaller than the third reference number, the operation ends.

In step S1203, the storage device 50 may determine a memory device including the corresponding super block as a defective memory device.

Fig. 13 is a diagram illustrating the memory controller 200 of fig. 1 according to another embodiment.

Referring to fig. 13, a memory controller 1000 is connected to the host 300 of fig. 1 and the plurality of memory devices 100 of fig. 1. The memory controller 1000 is configured to access the memory device 100 in response to a request from the host 300. For example, the memory controller 1000 is configured to control write operations, read operations, erase operations, and background operations of the memory device 100. Memory controller 1000 is configured to provide an interface between memory device 100 and host 300. Memory controller 1000 is configured to drive firmware to control memory device 100.

Memory controller 1000 may include a processor 1010, a memory buffer 1020, an Error Correction Component (ECC)1030, a host interface 1040, a buffer controller 1050, a memory interface 1060, and a bus 1070.

Bus 1070 may be configured to provide a channel between components of memory controller 1000.

The processor 1010 may control the overall operation of the memory controller 1000 and may perform logical operations. The processor 1010 may communicate with the host 300 through a host interface 1040 and with the memory device 100 through a memory interface 1060. Additionally, processor 1010 may communicate with memory buffer 1020 through buffer controller 1050. Processor 1010 may use memory buffer 1020 as an operating memory, cache memory, or buffer memory to control the operation of storage 50.

Processor 1010 may perform the functions of a Flash Translation Layer (FTL). Processor 1010 may convert Logical Block Addresses (LBAs) provided by host 300 to Physical Block Addresses (PBAs) through a Flash Translation Layer (FTL). A Flash Translation Layer (FTL) may receive a Logical Block Address (LBA) and translate the Logical Block Address (LBA) to a Physical Block Address (PBA) using a mapping table. The address mapping method of the Flash Translation Layer (FTL) may include various methods according to a mapping unit. Representative address mapping methods include any one of a page mapping method, a block mapping method, and a hybrid mapping method.

Processor 1010 is configured to randomize data received from host 300. For example, processor 1010 may randomize data received from host 300 using a randomization seed. The randomized data is provided to the memory device 100 as data to be stored and programmed into an array of memory cells in the memory device 100.

The processor 1010 is configured to derandomize data received from the memory device 100 during a read operation. For example, the processor 1010 may de-randomize data received from the memory device 100 using a de-randomization seed. The derandomized data can be output to the host 300.

In an embodiment, the processor 1010 may perform randomization and derandomization by driving software or firmware.

Memory buffer 1020 may serve as an operating memory, cache memory, or buffer memory for processor 1010. Memory buffer 1020 may store codes and commands that are executed by processor 1010. Memory buffer 1020 may store data processed by processor 1010. Memory buffer 1020 may include static ram (sram) or dynamic ram (dram).

ECC 1030 may perform error correction. ECC 1030 may perform error correction coding (ECC coding) based on data to be written to memory device 100 through memory interface 1060. Error correction coded data may be transferred to memory device 100 through memory interface 1060. ECC 1030 may perform error correction decoding (ECC decoding) on data received from memory device 100 through memory interface 1060. For example, ECC 1030 may be included in memory interface 1060 as a component of memory interface 1060.

Host interface 1040 is configured to communicate with host 300 under the control of processor 1010. Host interface 1040 may be configured to perform communications using at least one of various communication methods such as: universal Serial Bus (USB), serial AT attachment (SATA), serial SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI) express, non-volatile memory express (NVMe), universal flash memory (UFS), Secure Digital (SD), multimedia card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered DIMM (rdimm), and low-load DIMM (lrdimm).

The buffer controller 1050 is configured to control the memory buffer 1020 under the control of the processor 1010.

The memory interface 1060 is configured to communicate with the memory device 100 under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory device 100 through the channels.

In an embodiment, memory buffer 1020 and buffer controller 1050 may not be provided inside memory controller 1000.

In an embodiment, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a non-volatile memory device (e.g., read only memory) disposed within the memory controller 1000. In another embodiment, the processor 1010 may load code from the memory device 100 through the memory interface 1060.

The bus 1070 of the memory controller 1000 may include a control bus and a data bus. The data bus may be configured to transmit data within the memory controller 1000, and the control bus may be configured to transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus may be separated from each other so that they do not interfere or interact with each other. The data bus may be connected to a host interface 1040, a buffer controller 1050, an ECC 1030, and a memory interface 1060. The control bus may be connected to a host interface 1040, processor 1010, buffer controller 1050, memory buffer 1020, and memory interface 1060.

Fig. 14 is a block diagram showing a memory card system 2000 to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 14, the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 is configured to drive firmware to control the memory device 2200. The memory controller 2100 may correspond to the memory controller 200 described with reference to fig. 1.

The memory controller 2100 may include components such as a Random Access Memory (RAM), a processor, a host interface, a memory interface, and ECC.

The memory controller 2100 may communicate with an external device such as a host through the connector 2300. The memory controller 2100 may communicate with external devices according to a particular communication standard. For example, the memory controller 2100 may be configured to communicate with external devices using at least one of various communication standards such as: universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-E), Advanced Technology Attachment (ATA), serial ATA, parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and NVMe. For example, the connector 2300 may be defined by at least one of the various communication standards described above.

The memory device 2200 may be configured by various non-volatile memory devices such as: electrically erasable programmable rom (eeprom), NAND flash memory, NOR flash memory, phase change RAM (pram), resistive RAM (reram), ferroelectric RAM (fram), spin torque magnetic RAM (STT-MRAM), and the like.

The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to form a memory card as follows: PC cards (personal computer memory card international association (PCMCIA)), compact flash Cards (CF), smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC or micro MMC or eMMC), SD cards (SD, mini SD, micro SD and SDHC), universal flash memory (UFS), and the like.

Fig. 15 is a block diagram illustrating a Solid State Drive (SSD) system 3000 to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 15, the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through the signal connector 3001, and receives power PWR through the power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

According to an embodiment of the present disclosure, the SSD controller 3210 may perform the functions of the memory controller 200 described with reference to fig. 1.

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, signal SIG may be a signal based on an interface between host 3100 and SSD 3200. For example, the signal SIG may be a signal defined by at least one of the interfaces such as: universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-E), Advanced Technology Attachment (ATA), serial ATA, parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and NVMe.

The auxiliary power supply device 3230 is connected to the host 3100 through a power supply connector 3002. The auxiliary power supply device 3230 may receive power PWR from the host 3100 and may be charged. When the power supply from the host 3100 is not smooth, the auxiliary power supply device 3230 may supply the power of the SSD 3200. For example, the auxiliary power supply device 3230 may be located in the SSD 3200 or may be located outside the SSD 3200. For example, the auxiliary power supply device 3230 may be located on a motherboard, and may supply auxiliary power to the SSD 3200.

The buffer memory 3240 serves as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322 n. The buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

Fig. 16 is a block diagram illustrating a user system 4000 to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 16, the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may drive components, an Operating System (OS), user programs, and the like included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphic engine, and the like that control components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

The memory module 4200 may operate as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a Package On Package (POP) and provided as one semiconductor package.

The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communications such as: code Division Multiple Access (CDMA), Global System for Mobile communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long term evolution, Wimax, WLAN, UWB, Bluetooth and Wi-Fi. For example, the network module 4300 may be included in the application processor 4100.

The memory module 4400 may store data. For example, the memory module 4400 may store data received from the application processor 4100. Alternatively, the memory module 4400 may transmit data stored in the memory module 4400 to the application processor 4100. For example, the memory module 4400 may be implemented as a nonvolatile semiconductor memory element such as a phase change ram (pram), a magnetic ram (mram), a resistive ram (rram), a NAND flash memory, a NOR flash memory, and a three-dimensional structured NAND flash memory. For example, the memory module 4400 may be provided as a removable storage device (i.e., a removable drive) such as a memory card or an external drive of the user system 4000.

For example, the memory module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may operate the same as the memory device 100 described with reference to fig. 1. The memory module 4400 may operate the same as the memory device 50 described with reference to fig. 1.

The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 may include a user input interface such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. The user interface 4500 may include a user output interface such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display device, an active matrix OLED (amoled) display device, an LED, a speaker, and a monitor.

While various embodiments have been described above, it will be understood by those skilled in the art that the described embodiments are merely exemplary. Thus, the storage and memory devices described herein should not be limited based on the described embodiments.