阅读说明：本技术 一种非易失存储器处理方法及装置 (Nonvolatile memory processing method and device ) 是由 李琪 林子曾 于 2018-07-13 设计创作，主要内容包括：本发明实施例提供了一种非易失存储器处理方法及装置,该方法包括：确定第一寄存器的第一数据；其中所述第一寄存器用于存储对待检测存储单元进行写操作时的结果数据；若所述第一数据为第一状态,对待检测存储单元对应的位线BL进行放电操作。本发明实施例中,首先确定第一寄存器中的第一数据,若第一数据为第一状态,则说明是不需要进行编程的数据,此时若保持BL的电压,则会持续为第一待检测单元提供电流,造成无用的功耗,因此本发明实施例若第一数据为第一状态,对第一待检测单元对应的位线BL进行放电操作,使得BL不为待检测存储单元提供电流,从而有效减少了功耗。(The embodiment of the invention provides a nonvolatile memory processing method and a nonvolatile memory processing device, wherein the method comprises the following steps: determining first data of a first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation; and if the first data is in the first state, performing discharge operation on the bit line BL corresponding to the memory cell to be detected. In the embodiment of the invention, first data in the first register is determined, if the first data is in a first state, the data is data which does not need programming, and at this time, if the voltage of the BL is maintained, current is continuously supplied to the first to-be-detected cell, so that useless power consumption is caused.)

1. A non-volatile memory processing method, the method comprising:

determining first data in a first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation;

and if the first data is in the first state, performing discharge operation on the bit line BL corresponding to the memory cell to be detected.

2. The method of claim 1, further comprising:

and if the first data is in a second state, carrying out charging operation on the bit line BL corresponding to the memory cell to be detected.

3. The method of claim 2, wherein the step of determining the first data of the first register is preceded by the step of:

copying data in the second register to the first register through the BUS; the second register is used for storing data input by a user or data after programming verification;

the BUS is charged.

4. The method of claim 3, further comprising:

establishing a current loop between the BUS and the memory cell to be detected;

if the voltage of the BUS is maintained at a high level, performing programming verification operation on the memory cell to be detected;

if the voltage value of the BUS decreases, the BUS is discharged to 0.

5. The method of claim 4, further comprising:

if the voltage of the BUS is high level, writing the level state of the BUS into the first register, and enabling the first register to store second data;

storing the second data in the second register via an OR operation.

6. A non-volatile memory processing apparatus, the apparatus comprising:

the first data determining module is used for determining first data of the first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation;

and the first discharging module is used for performing discharging operation on the bit line BL corresponding to the memory cell to be detected if the first data is in the first state.

7. The apparatus of claim 6, further comprising:

and the first charging module is used for charging the bit line BL corresponding to the memory cell to be detected if the first data is in the second state.

8. The apparatus of claim 7, further comprising:

the copying module is used for copying the data in the second register to the first register through the BUS BUS; the second register is used for storing data input by a user or result data after programming verification;

and the second charging module is used for charging the BUS BUS.

9. The apparatus of claim 8, further comprising:

the current loop establishing module is used for establishing a current loop between the BUS and the storage unit to be detected;

the verification module is used for performing programming verification operation on the memory cell to be detected if the voltage of the BUS is maintained at a high level;

and the second discharging module is used for discharging the BUS to be 0 if the voltage value of the BUS is reduced.

10. The apparatus of claim 9, further comprising:

the write-in module is used for writing the level state of the BUS into the first register if the voltage of the BUS is high level, so that second data are stored in the first register;

and the OR operation module is used for storing the second data in the second register through OR operation.

Technical Field

The present invention relates to the field of memory processing technologies, and in particular, to a method and an apparatus for processing a nonvolatile memory.

Background

With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices are widely used in electronic products. Taking a non-volatile Memory NAND Flash Memory (NAND Flash Memory) as an example, the NAND Memory is composed of a plurality of Memory cells (cells), and the NAND Memory stores data by performing read-write erasing operations on the cells.

Disclosure of Invention

In view of the foregoing problems, embodiments of the present invention provide a nonvolatile memory processing method and apparatus to reduce power consumption of a detection unit when writing to a memory cell.

According to a first aspect of the present invention, there is provided a non-volatile memory processing method, the method comprising:

determining first data of a first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation;

and if the first data is in the first state, performing discharge operation on the bit line BL corresponding to the memory cell to be detected.

Preferably, the method further comprises:

and if the first data is in a second state, carrying out charging operation on the bit line BL corresponding to the memory cell to be detected.

Copying data in the second register to the first register through the BUS; the second register is used for storing data input by a user or result data after programming verification;

the BUS is charged.

Establishing a current loop between the BUS and the memory cell to be detected;

if the voltage of the BUS is maintained at a high level, performing programming verification operation on the memory cell to be detected;

if the voltage value of the BUS decreases, the BUS is discharged to 0.

If the voltage of the BUS is high level, writing the level state of the BUS into the first register, and enabling the first register to store second data;

storing the second data in the second register via an OR operation.

According to a second aspect of the present invention, there is provided a non-volatile memory processing apparatus, the apparatus comprising:

the first data determining module is used for determining first data of the first register; the first register is used for storing result data when the memory unit to be detected is subjected to write operation;

and the first discharging module is used for performing discharging operation on the bit line BL corresponding to the memory cell to be detected if the first data is in the first state.

Preferably, the apparatus further comprises:

and the first charging module is used for charging the bit line BL corresponding to the memory cell to be detected if the first data is in the second state.

The copying module is used for copying the data in the second register to the first register through the BUS BUS; the second register is used for storing data input by a user or result data after programming verification;

and the second charging module is used for charging the BUS BUS.

The current loop establishing module is used for establishing a current loop between the BUS and the storage unit to be detected;

the verification module is used for performing programming verification operation on the memory cell to be detected if the voltage of the BUS is maintained at a high level;

and the second discharging module is used for discharging the BUS to be 0 if the voltage value of the BUS is reduced.

The write-in module is used for writing the level state of the BUS into the first register if the voltage of the BUS is high level, so that second data are stored in the first register;

and the OR operation module is used for storing the second data in the second register through OR operation.

In the embodiment of the present invention, it is found that the reason that the power consumption is large when the nonvolatile memory performs the write operation in the prior art is as follows: since the cells in the first state "1" are mostly inside one page of the initial PV, since the "1" cells have current flowing through the bit line BL of the nonvolatile memory during the reading process of the PV, assuming that the capacity of the page is 16KB, about 16 × 1024 × 8 × i _ string current flows from the power supply VDD of the SA, even if the current i _ string of one cell is 1uA (or less), the power consumption of hundreds of milliamperes level will exist during the initial PV, and the power consumption is very large. Therefore, in the embodiment of the present invention, first data in the first register is determined, and if the first data is in the first state, it indicates that the data does not need to be programmed, and at this time, if the voltage of the BL is maintained, current is continuously supplied to the first to-be-detected cell, which causes useless power consumption.

The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a flow chart of a method for processing a non-volatile memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a detection unit circuit according to the present invention;

FIG. 3 is a flowchart illustrating a method for processing a non-volatile memory according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a detection unit circuit applied in a nonvolatile memory processing method according to an embodiment of the present invention;

FIG. 5 is a block diagram of a non-volatile memory processing apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.