阅读说明：本技术 一种非易失存储器处理电路及方法 (Nonvolatile memory processing circuit and method ) 是由 马思博 贾少旭 舒清明 于 2018-07-13 设计创作，主要内容包括：本发明实施例提供一种非易失存储器处理电路及方法,该方法包括：充电电路与存储单元选择电路连接,用于对第一存储单元串的位线进行充电；及,对源线进行充电；当第一存储单元串的位线充电稳定后,通过源线对第二存储单元串的位线进行充电；充电电路与比较电路连接,用于当第二存储单元串的位线充电稳定后,对比较电路进行充电,且,当比较电路充电稳定后,结束对比较电路和存储单元选择电路的充电；存储单元选择电路与比较电路构成电流回路,以使比较电路根据电流回路输出高电平或低电平。本发明实施例屏蔽了第一存储单元串与第二存储单元串之间电容的串扰,因此在对非易失存储器中的存储单元进行读取操作时,可以准确的读取各存储单元的数据。(The embodiment of the invention provides a nonvolatile memory processing circuit and a method, wherein the method comprises the following steps: the charging circuit is connected with the storage unit selection circuit and used for charging a bit line of the first storage unit string; and, charging the source line; when the charging of the bit line of the first memory cell string is stable, the bit line of the second memory cell string is charged through the source line; the charging circuit is connected with the comparison circuit and used for charging the comparison circuit after the bit line of the second storage unit string is stably charged, and finishing charging the comparison circuit and the storage unit selection circuit after the comparison circuit is stably charged; the memory cell selection circuit and the comparison circuit form a current loop, so that the comparison circuit outputs a high level or a low level according to the current loop. According to the embodiment of the invention, the crosstalk of the capacitor between the first storage cell string and the second storage cell string is shielded, so that the data of each storage cell can be accurately read when the storage cell in the nonvolatile memory is read.)

1. A non-volatile memory processing circuit, the circuit comprising:

the device comprises a charging circuit, a comparison circuit and a storage unit selection circuit;

the memory cell selection circuit comprises at least one pair of memory cell strings; each pair of memory cell strings comprises a first memory cell string and a second memory cell string, and a capacitor CBL is connected between a bit line BLO of the first memory cell string and a bit line BLE of the second memory cell string; each memory cell string is connected with a source line SL;

the charging circuit is connected with the storage unit selection circuit and used for initially charging a bit line BLO of a first storage unit string in the storage unit selection circuit; and charging the source line SL; when charging of a bit line BLO of the first memory cell string is stable, charging of a bit line BLE of the second memory cell string is performed through the source line SL;

the charging circuit is connected with the comparison circuit and used for charging the comparison circuit after the charging of the bit line BLE of the second memory cell string is stable, and finishing the charging of the comparison circuit and the memory cell selection circuit after the charging of the comparison circuit is stable;

a second storage unit string in the storage unit selection circuit and the comparison circuit form a current loop through the charging circuit, so that the comparison circuit outputs a high level or a low level according to the current loop;

the output end of the comparison circuit is used as the output end of the nonvolatile memory processing circuit.

2. The circuit of claim 1, wherein the charging circuit comprises:

NMOS transistors M1, M2, M3, a first power supply VDD;

the drain of the M1 is connected with the first power supply VDD;

the source of the M1 is connected with the drain of the M3 to serve as a connection end of the charging circuit and the comparison circuit for charging the comparison circuit;

the drain of the M2 is connected with the first power supply VDD;

the source of the M2 is connected to the source of the M3 to act as a connection for the charging circuit to the memory cell selection circuit to charge the memory cell selection circuit.

3. The circuit of claim 2, wherein the comparison circuit comprises:

a comparator, a first input terminal of which is provided with a comparison voltage VTH, and a second input terminal of which is connected with the source of the M1 to receive the charging voltage of the charging circuit;

a second input terminal of the comparator is connected with the drain of the M3 to form a current loop with the memory cell selection circuit through the M3;

and the first end of the capacitor C is connected with the second input end of the comparator, and the second end of the capacitor C is grounded.

4. The circuit of claim 3, wherein the memory cell selection circuit comprises:

a bit line selection field effect cell M4, a memory cell determination module;

the drain of the M4 is connected with the source of the M3;

the source of the M4 is connected to the bit line of each of the memory cell determination modules.

5. The circuit of claim 4, wherein the memory location determination module comprises: a bit line switch SGD and a source line switch SGS;

the bit line switch SGD is configured to control on/off between the bit lines of the memory cell determination module and the memory cell determination module;

the source line switch SGS is configured to control on or off between the memory cell determination module and a source line of the memory cell determination module.

6. A nonvolatile memory processing method applied to the nonvolatile memory processing circuit according to any one of claims 1 to 5, the method comprising:

determining a memory cell to be detected in the memory cell selection circuit; the storage unit string where the storage unit to be detected is located is a second storage unit string;

charging a bit line BLO of a first memory cell string in the memory cell selection circuit; and charging the source line SL; when charging of a bit line BLO of the first memory cell string is stable, charging of a bit line BLE of the second memory cell string is performed through the source line SL;

when the charging of the bit line BLE of the second memory cell string is stable, the second input end of the comparison circuit is charged through the charging circuit; a first input end of the comparison circuit is provided with a comparison voltage VTH;

when the charging of the second input end of the comparison circuit is stable, the charging of the storage unit selection circuit and the comparison circuit is finished, and the storage unit selection circuit and the comparison circuit form a current loop by controlling the charging circuit;

and determining the data state of the memory cell to be detected according to the current loop.

7. The method of claim 6, wherein the charging circuit comprises: an NMOS transistor M2;

the step of charging the memory cell selection circuit by the charging circuit includes:

and controlling M2 of the charging circuit to be conducted to charge the storage unit selection circuit.

8. The method of claim 6, wherein the charging circuit comprises: an NMOS transistor M1;

the step of charging the second input terminal of the comparison circuit through the charging circuit after the charging of the memory cell selection circuit is stable comprises:

and when the charging of the storage unit selection circuit is stable, controlling the M1 of the charging circuit to be conducted, and charging the second input end of the comparison circuit.

9. The method of claim 6, wherein the charging circuit comprises: an NMOS transistor M3;

the step of making the memory cell selection circuit and the comparison circuit constitute a current loop by controlling the charging circuit includes:

and controlling M3 of the charging circuit to be conducted, so that the storage unit selection circuit and the comparison circuit form a current loop.

10. The method of claim 9, wherein the memory cells to be tested are negative threshold memory cells.

Technical Field

The present invention relates to the field of memory processing technologies, and in particular, to a nonvolatile memory processing circuit and method.

Background

With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices are widely used in electronic products. Taking a non-volatile Memory NAND Flash Memory (NAND Flash Memory) as an example, the NAND Memory is composed of a plurality of Memory cells (cells), and the Memory cells can be negative threshold Memory cells, that is, Memory cells with negative turn-on threshold voltage; or a positive threshold memory cell, i.e., a memory cell in which the turn-on threshold voltage is a positive value; the data state of the memory cell, such as an erased state, a programmed state, etc., can be read according to the on-current of the memory cell when it is operated.

Disclosure of Invention

In view of the foregoing problems, a nonvolatile memory processing circuit and method according to embodiments of the present invention are provided to improve the accuracy of reading data from a memory cell.

According to a first aspect of the present invention, there is provided a non-volatile memory processing circuit comprising:

the device comprises a charging circuit, a comparison circuit and a storage unit selection circuit;

the memory cell selection circuit comprises at least one pair of memory cell strings; each pair of memory cell strings comprises a first memory cell string and a second memory cell string, and a capacitor CBL is connected between a bit line BLO of the first memory cell string and a bit line BLE of the second memory cell string; each memory cell string is connected with a source line SL;

the charging circuit is connected with the storage unit selection circuit and used for initially charging a bit line BLO of a first storage unit string in the storage unit selection circuit; and charging the source line SL; when charging of a bit line BLO of the first memory cell string is stable, charging of a bit line BLE of the second memory cell string is performed through the source line SL;

the charging circuit is connected with the comparison circuit and used for charging the comparison circuit after the charging of the bit line BLE of the second memory cell string is stable, and finishing the charging of the comparison circuit and the memory cell selection circuit after the charging of the comparison circuit is stable;

a second storage unit string in the storage unit selection circuit and the comparison circuit form a current loop through the charging circuit, so that the comparison circuit outputs a high level or a low level according to the current loop;

the output end of the comparison circuit is used as the output end of the nonvolatile memory processing circuit.

Preferably, the charging circuit includes:

NMOS transistors M1, M2, M3, a first power supply VDD;

the drain of the M1 is connected with the first power supply VDD;

the source of the M1 is connected with the drain of the M3 to serve as a connection end of the charging circuit and the comparison circuit for charging the comparison circuit;

the drain of the M2 is connected with the first power supply VDD;

the source of the M2 is connected to the source of the M3 to act as a connection for the charging circuit to the memory cell selection circuit to charge the memory cell selection circuit.

Preferably, the comparison circuit includes:

a comparator, a first input terminal of which is provided with a comparison voltage VTH, and a second input terminal of which is connected with the source of the M1 to receive the charging voltage of the charging circuit;

a second input terminal of the comparator is connected with the drain of the M3 to form a current loop with the memory cell selection circuit through the M3;

and the first end of the capacitor C is connected with the second input end of the comparator, and the second end of the capacitor C is grounded.

Preferably, the memory cell selection circuit includes:

a bit line selection field effect cell M4, a memory cell determination module;

the drain of the M4 is connected with the source of the M3;

the source of the M4 is connected to the bit line of each of the memory cell determination modules.

Preferably, the storage unit determination module includes: a bit line switch SGD and a source line switch SGS;

the bit line switch SGD is configured to control on/off between the bit lines of the memory cell determination module and the memory cell determination module;

the source line switch SGS is configured to control on or off between the memory cell determination module and a source line of the memory cell determination module.

According to a second aspect of the present invention, there is provided a non-volatile memory processing method applied in the non-volatile memory processing circuit as described in any one of the above, the method comprising:

determining a memory cell to be detected in the memory cell selection circuit; the storage unit string where the storage unit to be detected is located is a second storage unit string;

charging a bit line BLO of a first memory cell string in the memory cell selection circuit; and charging the source line SL; when charging of a bit line BLO of the first memory cell string is stable, charging of a bit line BLE of the second memory cell string is performed through the source line SL;

when the charging of the bit line BLE of the second memory cell string is stable, the second input end of the comparison circuit is charged through the charging circuit; a first input end of the comparison circuit is provided with a comparison voltage VTH;

when the charging of the second input end of the comparison circuit is stable, the charging of the storage unit selection circuit and the comparison circuit is finished, and the storage unit selection circuit and the comparison circuit form a current loop by controlling the charging circuit;

and determining the data state of the memory cell to be detected according to the current loop.

Preferably, the charging circuit includes: an NMOS transistor M2;

the step of charging the memory cell selection circuit by the charging circuit includes:

and controlling M2 of the charging circuit to be conducted to charge the storage unit selection circuit.

Preferably, the charging circuit includes: an NMOS transistor M1;

the step of charging the second input terminal of the comparison circuit through the charging circuit after the charging of the memory cell selection circuit is stable comprises:

and when the charging of the storage unit selection circuit is stable, controlling the M1 of the charging circuit to be conducted, and charging the second input end of the comparison circuit.

Preferably, the charging circuit includes: an NMOS transistor M3;

the step of making the memory cell selection circuit and the comparison circuit constitute a current loop by controlling the charging circuit includes:

and controlling M3 of the charging circuit to be conducted, so that the storage unit selection circuit and the comparison circuit form a current loop.

Preferably, the memory cell to be detected is a negative threshold memory cell.

In the embodiment of the invention, when data reading operation is performed on the memory cells in the second memory cell string of the nonvolatile memory, the bit line BLO of the first memory cell string paired with the second memory cell string can be set to a fixed voltage, so that crosstalk of the capacitor CBL between the first memory cell string and the second memory cell string is shielded, and therefore, data of each memory cell can be accurately read when the data reading operation is performed on the memory cells in the nonvolatile memory.

The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic diagram of a nonvolatile memory processing circuit according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a memory cell determination module according to an embodiment of the present invention;

FIG. 3 is a timing diagram of a processing circuit of a non-volatile memory according to an embodiment of the present invention;

FIG. 4 is a flowchart of a processing method of a non-volatile memory according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.